alpha.md revision 1.1.1.10
1 ;; Machine description for DEC Alpha for GNU C compiler 2 ;; Copyright (C) 1992-2022 Free Software Foundation, Inc. 3 ;; Contributed by Richard Kenner (kenner (a] vlsi1.ultra.nyu.edu) 4 ;; 5 ;; This file is part of GCC. 6 ;; 7 ;; GCC is free software; you can redistribute it and/or modify 8 ;; it under the terms of the GNU General Public License as published by 9 ;; the Free Software Foundation; either version 3, or (at your option) 10 ;; any later version. 11 ;; 12 ;; GCC is distributed in the hope that it will be useful, 13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 ;; GNU General Public License for more details. 16 ;; 17 ;; You should have received a copy of the GNU General Public License 18 ;; along with GCC; see the file COPYING3. If not see 19 ;; <http://www.gnu.org/licenses/>. 20 21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 23 ;; Uses of UNSPEC in this file: 24 25 (define_c_enum "unspec" [ 26 UNSPEC_XFLT_COMPARE 27 UNSPEC_ARG_HOME 28 UNSPEC_LDGP1 29 UNSPEC_INSXH 30 UNSPEC_MSKXH 31 UNSPEC_CVTQL 32 UNSPEC_CVTLQ 33 UNSPEC_LDGP2 34 UNSPEC_LITERAL 35 UNSPEC_LITUSE 36 UNSPEC_SIBCALL 37 UNSPEC_SYMBOL 38 39 ;; TLS Support 40 UNSPEC_TLSGD_CALL 41 UNSPEC_TLSLDM_CALL 42 UNSPEC_TLSGD 43 UNSPEC_TLSLDM 44 UNSPEC_DTPREL 45 UNSPEC_TPREL 46 UNSPEC_TP 47 48 ;; Builtins 49 UNSPEC_CMPBGE 50 UNSPEC_ZAP 51 UNSPEC_AMASK 52 UNSPEC_IMPLVER 53 UNSPEC_PERR 54 UNSPEC_COPYSIGN 55 56 ;; Atomic operations 57 UNSPEC_MB 58 UNSPEC_ATOMIC 59 UNSPEC_CMPXCHG 60 UNSPEC_XCHG 61 ]) 62 63 ;; UNSPEC_VOLATILE: 64 65 (define_c_enum "unspecv" [ 66 UNSPECV_IMB 67 UNSPECV_BLOCKAGE 68 UNSPECV_SETJMPR ; builtin_setjmp_receiver 69 UNSPECV_LONGJMP ; builtin_longjmp 70 UNSPECV_TRAPB 71 UNSPECV_PSPL ; prologue_stack_probe_loop 72 UNSPECV_REALIGN 73 UNSPECV_EHR ; exception_receiver 74 UNSPECV_MCOUNT 75 UNSPECV_FORCE_MOV 76 UNSPECV_LDGP1 77 UNSPECV_PLDGP2 ; prologue ldgp 78 UNSPECV_SET_TP 79 UNSPECV_RPCC 80 UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 81 UNSPECV_LL ; load-locked 82 UNSPECV_SC ; store-conditional 83 UNSPECV_CMPXCHG 84 ]) 85 86 ;; On non-BWX targets, CQImode must be handled the similarly to HImode 87 ;; when generating reloads. 88 (define_mode_iterator RELOAD12 [QI HI CQI]) 89 (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 90 91 ;; Other mode iterators 92 (define_mode_iterator IMODE [QI HI SI DI]) 93 (define_mode_iterator I12MODE [QI HI]) 94 (define_mode_iterator I124MODE [QI HI SI]) 95 (define_mode_iterator I24MODE [HI SI]) 96 (define_mode_iterator I248MODE [HI SI DI]) 97 (define_mode_iterator I48MODE [SI DI]) 98 99 (define_mode_attr DWI [(SI "DI") (DI "TI")]) 100 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 101 (V8QI "b8") (V4HI "w4") 102 (SF "%,") (DF "%-")]) 103 (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 104 105 (define_code_iterator any_maxmin [smax smin umax umin]) 106 107 (define_code_attr maxmin [(smax "maxs") (smin "mins") 108 (umax "maxu") (umin "minu")]) 109 110 ;; Where necessary, the suffixes _le and _be are used to distinguish between 111 ;; little-endian and big-endian patterns. 112 ;; 113 ;; Note that the Unicos/Mk assembler does not support the following 114 ;; opcodes: mov, fmov, nop, fnop, unop. 115 117 ;; Processor type -- this attribute must exactly match the processor_type 118 ;; enumeration in alpha.h. 119 120 (define_attr "tune" "ev4,ev5,ev6" 121 (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 122 123 ;; Define an insn type attribute. This is used in function unit delay 124 ;; computations, among other purposes. For the most part, we use the names 125 ;; defined in the EV4 documentation, but add a few that we have to know about 126 ;; separately. 127 128 (define_attr "type" 129 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 130 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 131 multi,none" 132 (const_string "iadd")) 133 134 ;; Describe a user's asm statement. 135 (define_asm_attributes 136 [(set_attr "type" "multi")]) 137 138 ;; Define the operand size an insn operates on. Used primarily by mul 139 ;; and div operations that have size dependent timings. 140 141 (define_attr "opsize" "si,di,udi" 142 (const_string "di")) 143 144 ;; The TRAP attribute marks instructions that may generate traps 145 ;; (which are imprecise and may need a trapb if software completion 146 ;; is desired). 147 148 (define_attr "trap" "no,yes" 149 (const_string "no")) 150 151 ;; The ROUND_SUFFIX attribute marks which instructions require a 152 ;; rounding-mode suffix. The value NONE indicates no suffix, 153 ;; the value NORMAL indicates a suffix controlled by alpha_fprm. 154 155 (define_attr "round_suffix" "none,normal,c" 156 (const_string "none")) 157 158 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 159 ;; NONE no suffix 160 ;; SU accepts only /su (cmpt et al) 161 ;; SUI accepts only /sui (cvtqt and cvtqs) 162 ;; V_SV accepts /v and /sv (cvtql only) 163 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 164 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 165 ;; 166 ;; The actual suffix emitted is controlled by alpha_fptm. 167 168 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 169 (const_string "none")) 170 171 ;; The length of an instruction sequence in bytes. 172 173 (define_attr "length" "" 174 (const_int 4)) 175 176 ;; The USEGP attribute marks instructions that have relocations that use 177 ;; the GP. 178 179 (define_attr "usegp" "no,yes" 180 (cond [(eq_attr "type" "ldsym,jsr") 181 (const_string "yes") 182 (eq_attr "type" "ild,fld,ist,fst") 183 (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 184 ] 185 (const_string "no"))) 186 187 ;; The CANNOT_COPY attribute marks instructions with relocations that 188 ;; cannot easily be duplicated. This includes insns with gpdisp relocs 189 ;; since they have to stay in 1-1 correspondence with one another. This 190 ;; also includes jsr insns, since they must stay in correspondence with 191 ;; the immediately following gpdisp instructions. 192 193 (define_attr "cannot_copy" "false,true" 194 (const_string "false")) 195 196 ;; Used to control the "enabled" attribute on a per-instruction basis. 197 ;; For convenience, conflate ABI issues re loading of addresses with 198 ;; an "isa". 199 (define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 200 (const_string "base")) 201 202 (define_attr "enabled" "" 203 (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 204 (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 205 (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 206 (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 207 (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 208 (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 209 (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 210 ] 211 (const_int 1))) 212 214 ;; Include scheduling descriptions. 215 216 (include "ev4.md") 217 (include "ev5.md") 218 (include "ev6.md") 219 220 222 ;; Operand and operator predicates and constraints 223 224 (include "predicates.md") 225 (include "constraints.md") 226 227 229 ;; First define the arithmetic insns. Note that the 32-bit forms also 230 ;; sign-extend. 231 232 ;; Handle 32-64 bit extension from memory to a floating point register 233 ;; specially, since this occurs frequently in int->double conversions. 234 ;; 235 ;; Note that while we must retain the =f case in the insn for reload's 236 ;; benefit, it should be eliminated after reload, so we should never emit 237 ;; code for that case. But we don't reject the possibility. 238 239 (define_expand "extendsidi2" 240 [(set (match_operand:DI 0 "register_operand") 241 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 242 243 (define_insn "*cvtlq" 244 [(set (match_operand:DI 0 "register_operand" "=f") 245 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 246 UNSPEC_CVTLQ))] 247 "" 248 "cvtlq %1,%0" 249 [(set_attr "type" "fadd")]) 250 251 (define_insn "*extendsidi2_1" 252 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 253 (sign_extend:DI 254 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 255 "" 256 "@ 257 addl $31,%1,%0 258 ldl %0,%1 259 lds %0,%1\;cvtlq %0,%0" 260 [(set_attr "type" "iadd,ild,fld") 261 (set_attr "length" "*,*,8")]) 262 263 (define_split 264 [(set (match_operand:DI 0 "hard_fp_register_operand") 265 (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 266 "reload_completed" 267 [(set (match_dup 2) (match_dup 1)) 268 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 269 { 270 operands[1] = adjust_address (operands[1], SFmode, 0); 271 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 272 }) 273 274 ;; Optimize sign-extension of SImode loads. This shows up in the wake of 275 ;; reload when converting fp->int. 276 277 (define_peephole2 278 [(set (match_operand:SI 0 "hard_int_register_operand") 279 (match_operand:SI 1 "memory_operand")) 280 (set (match_operand:DI 2 "hard_int_register_operand") 281 (sign_extend:DI (match_dup 0)))] 282 "true_regnum (operands[0]) == true_regnum (operands[2]) 283 || peep2_reg_dead_p (2, operands[0])" 284 [(set (match_dup 2) 285 (sign_extend:DI (match_dup 1)))]) 286 287 (define_insn "addsi3" 288 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 289 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 290 (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 291 "" 292 "@ 293 addl %r1,%2,%0 294 subl %r1,%n2,%0 295 lda %0,%2(%r1) 296 ldah %0,%h2(%r1)") 297 298 (define_split 299 [(set (match_operand:SI 0 "register_operand") 300 (plus:SI (match_operand:SI 1 "register_operand") 301 (match_operand:SI 2 "const_int_operand")))] 302 "! add_operand (operands[2], SImode)" 303 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 304 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 305 { 306 HOST_WIDE_INT val = INTVAL (operands[2]); 307 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 308 HOST_WIDE_INT rest = val - low; 309 310 operands[3] = GEN_INT (rest); 311 operands[4] = GEN_INT (low); 312 }) 313 314 (define_insn "*addsi_se" 315 [(set (match_operand:DI 0 "register_operand" "=r,r") 316 (sign_extend:DI 317 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 318 (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 319 "" 320 "@ 321 addl %r1,%2,%0 322 subl %r1,%n2,%0") 323 324 (define_insn "*addsi_se2" 325 [(set (match_operand:DI 0 "register_operand" "=r,r") 326 (sign_extend:DI 327 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 328 (match_operand:DI 2 "sext_add_operand" "rI,O")) 329 0)))] 330 "" 331 "@ 332 addl %r1,%2,%0 333 subl %r1,%n2,%0") 334 335 (define_split 336 [(set (match_operand:DI 0 "register_operand") 337 (sign_extend:DI 338 (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 339 (match_operand:SI 2 "const_int_operand")))) 340 (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 341 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 342 && INTVAL (operands[2]) % 4 == 0" 343 [(set (match_dup 3) (match_dup 4)) 344 (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3) 345 (match_dup 5)) 346 (match_dup 1))))] 347 { 348 HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 349 int mult = 4; 350 351 if (val % 2 == 0) 352 val /= 2, mult = 8; 353 354 operands[4] = GEN_INT (val); 355 operands[5] = GEN_INT (exact_log2 (mult)); 356 }) 357 358 (define_split 359 [(set (match_operand:DI 0 "register_operand") 360 (sign_extend:DI 361 (plus:SI (match_operator:SI 1 "comparison_operator" 362 [(match_operand 2) 363 (match_operand 3)]) 364 (match_operand:SI 4 "add_operand")))) 365 (clobber (match_operand:DI 5 "register_operand"))] 366 "" 367 [(set (match_dup 5) (match_dup 6)) 368 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 369 { 370 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 371 operands[2], operands[3]); 372 operands[7] = gen_lowpart (SImode, operands[5]); 373 }) 374 375 (define_expand "adddi3" 376 [(set (match_operand:DI 0 "register_operand") 377 (plus:DI (match_operand:DI 1 "register_operand") 378 (match_operand:DI 2 "add_operand")))]) 379 380 (define_insn "*adddi_er_lo16_dtp" 381 [(set (match_operand:DI 0 "register_operand" "=r") 382 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 383 (match_operand:DI 2 "dtp16_symbolic_operand")))] 384 "HAVE_AS_TLS" 385 "lda %0,%2(%1)\t\t!dtprel") 386 387 (define_insn "*adddi_er_hi32_dtp" 388 [(set (match_operand:DI 0 "register_operand" "=r") 389 (plus:DI (match_operand:DI 1 "register_operand" "r") 390 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 391 "HAVE_AS_TLS" 392 "ldah %0,%2(%1)\t\t!dtprelhi") 393 394 (define_insn "*adddi_er_lo32_dtp" 395 [(set (match_operand:DI 0 "register_operand" "=r") 396 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 397 (match_operand:DI 2 "dtp32_symbolic_operand")))] 398 "HAVE_AS_TLS" 399 "lda %0,%2(%1)\t\t!dtprello") 400 401 (define_insn "*adddi_er_lo16_tp" 402 [(set (match_operand:DI 0 "register_operand" "=r") 403 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 404 (match_operand:DI 2 "tp16_symbolic_operand")))] 405 "HAVE_AS_TLS" 406 "lda %0,%2(%1)\t\t!tprel") 407 408 (define_insn "*adddi_er_hi32_tp" 409 [(set (match_operand:DI 0 "register_operand" "=r") 410 (plus:DI (match_operand:DI 1 "register_operand" "r") 411 (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 412 "HAVE_AS_TLS" 413 "ldah %0,%2(%1)\t\t!tprelhi") 414 415 (define_insn "*adddi_er_lo32_tp" 416 [(set (match_operand:DI 0 "register_operand" "=r") 417 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 418 (match_operand:DI 2 "tp32_symbolic_operand")))] 419 "HAVE_AS_TLS" 420 "lda %0,%2(%1)\t\t!tprello") 421 422 (define_insn "*adddi_er_high_l" 423 [(set (match_operand:DI 0 "register_operand" "=r") 424 (plus:DI (match_operand:DI 1 "register_operand" "r") 425 (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 426 "TARGET_EXPLICIT_RELOCS && reload_completed" 427 "ldah %0,%2(%1)\t\t!gprelhigh" 428 [(set_attr "usegp" "yes")]) 429 430 (define_split 431 [(set (match_operand:DI 0 "register_operand") 432 (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 433 "TARGET_EXPLICIT_RELOCS && reload_completed" 434 [(set (match_dup 0) 435 (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 436 "operands[2] = pic_offset_table_rtx;") 437 438 ;; We used to expend quite a lot of effort choosing addq/subq/lda. 439 ;; With complications like 440 ;; 441 ;; The NT stack unwind code can't handle a subq to adjust the stack 442 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 443 ;; the exception handling code will loop if a subq is used and an 444 ;; exception occurs. 445 ;; 446 ;; The 19980616 change to emit prologues as RTL also confused some 447 ;; versions of GDB, which also interprets prologues. This has been 448 ;; fixed as of GDB 4.18, but it does not harm to unconditionally 449 ;; use lda here. 450 ;; 451 ;; and the fact that the three insns schedule exactly the same, it's 452 ;; just not worth the effort. 453 454 (define_insn "*adddi_internal" 455 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 456 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 457 (match_operand:DI 2 "add_operand" "r,K,L")))] 458 "" 459 "@ 460 addq %1,%2,%0 461 lda %0,%2(%1) 462 ldah %0,%h2(%1)") 463 464 ;; ??? Allow large constants when basing off the frame pointer or some 465 ;; virtual register that may eliminate to the frame pointer. This is 466 ;; done because register elimination offsets will change the hi/lo split, 467 ;; and if we split before reload, we will require additional instructions. 468 469 (define_insn "*adddi_fp_hack" 470 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 471 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 472 (match_operand:DI 2 "const_int_operand" "K,L,n")))] 473 "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 474 && INTVAL (operands[2]) >= 0 475 /* This is the largest constant an lda+ldah pair can add, minus 476 an upper bound on the displacement between SP and AP during 477 register elimination. See INITIAL_ELIMINATION_OFFSET. */ 478 && INTVAL (operands[2]) 479 < (0x7fff8000 480 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 481 - ALPHA_ROUND(crtl->outgoing_args_size) 482 - (ALPHA_ROUND (get_frame_size () 483 + max_reg_num () * UNITS_PER_WORD 484 + crtl->args.pretend_args_size) 485 - crtl->args.pretend_args_size))" 486 "@ 487 lda %0,%2(%1) 488 ldah %0,%h2(%1) 489 #") 490 491 ;; Don't do this if we are adjusting SP since we don't want to do it 492 ;; in two steps. Don't split FP sources for the reason listed above. 493 (define_split 494 [(set (match_operand:DI 0 "register_operand") 495 (plus:DI (match_operand:DI 1 "register_operand") 496 (match_operand:DI 2 "const_int_operand")))] 497 "! add_operand (operands[2], DImode) 498 && operands[0] != stack_pointer_rtx 499 && operands[1] != frame_pointer_rtx 500 && operands[1] != arg_pointer_rtx" 501 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 502 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 503 { 504 HOST_WIDE_INT val = INTVAL (operands[2]); 505 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 506 HOST_WIDE_INT rest = val - low; 507 rtx rest_rtx = GEN_INT (rest); 508 509 operands[4] = GEN_INT (low); 510 if (satisfies_constraint_L (rest_rtx)) 511 operands[3] = rest_rtx; 512 else if (can_create_pseudo_p ()) 513 { 514 operands[3] = gen_reg_rtx (DImode); 515 emit_move_insn (operands[3], operands[2]); 516 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 517 DONE; 518 } 519 else 520 FAIL; 521 }) 522 523 (define_insn "*sadd<modesuffix>" 524 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 525 (plus:I48MODE 526 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 527 (match_operand:I48MODE 2 "const23_operand" "I,I")) 528 (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 529 "" 530 "@ 531 s%P2add<modesuffix> %1,%3,%0 532 s%P2sub<modesuffix> %1,%n3,%0") 533 534 (define_insn "*saddl_se" 535 [(set (match_operand:DI 0 "register_operand" "=r,r") 536 (sign_extend:DI 537 (plus:SI 538 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 539 (match_operand:SI 2 "const23_operand" "I,I")) 540 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 541 "" 542 "@ 543 s%P2addl %1,%3,%0 544 s%P2subl %1,%n3,%0") 545 546 (define_split 547 [(set (match_operand:DI 0 "register_operand") 548 (sign_extend:DI 549 (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator" 550 [(match_operand 2) 551 (match_operand 3)]) 552 (match_operand:SI 4 "const23_operand")) 553 (match_operand:SI 5 "sext_add_operand")))) 554 (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 555 "" 556 [(set (match_dup 6) (match_dup 7)) 557 (set (match_dup 0) 558 (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4)) 559 (match_dup 5))))] 560 { 561 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 562 operands[2], operands[3]); 563 operands[8] = gen_lowpart (SImode, operands[6]); 564 }) 565 566 (define_insn "addv<mode>3" 567 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 568 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 569 (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 570 (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 571 (sign_extend:<DWI> (match_dup 2))) 572 (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 573 (match_dup 2)))) 574 (const_int 0))] 575 "" 576 "@ 577 add<modesuffix>v %r1,%2,%0 578 sub<modesuffix>v %r1,%n2,%0") 579 580 (define_insn "neg<mode>2" 581 [(set (match_operand:I48MODE 0 "register_operand" "=r") 582 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 583 "" 584 "sub<modesuffix> $31,%1,%0") 585 586 (define_insn "*negsi_se" 587 [(set (match_operand:DI 0 "register_operand" "=r") 588 (sign_extend:DI (neg:SI 589 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 590 "" 591 "subl $31,%1,%0") 592 593 (define_insn "negv<mode>2" 594 [(set (match_operand:I48MODE 0 "register_operand" "=r") 595 (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 596 (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 597 (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 598 (const_int 0))] 599 "" 600 "sub<modesuffix>v $31,%1,%0") 601 602 (define_insn "sub<mode>3" 603 [(set (match_operand:I48MODE 0 "register_operand" "=r") 604 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 605 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 606 "" 607 "sub<modesuffix> %r1,%2,%0") 608 609 (define_insn "*subsi_se" 610 [(set (match_operand:DI 0 "register_operand" "=r") 611 (sign_extend:DI 612 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 613 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 614 "" 615 "subl %r1,%2,%0") 616 617 (define_insn "*subsi_se2" 618 [(set (match_operand:DI 0 "register_operand" "=r") 619 (sign_extend:DI 620 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 621 (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 622 0)))] 623 "" 624 "subl %r1,%2,%0") 625 626 (define_insn "*ssub<modesuffix>" 627 [(set (match_operand:I48MODE 0 "register_operand" "=r") 628 (minus:I48MODE 629 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 630 (match_operand:I48MODE 2 "const23_operand" "I")) 631 (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 632 "" 633 "s%P2sub<modesuffix> %1,%3,%0") 634 635 (define_insn "*ssubl_se" 636 [(set (match_operand:DI 0 "register_operand" "=r") 637 (sign_extend:DI 638 (minus:SI 639 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 640 (match_operand:SI 2 "const23_operand" "I")) 641 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 642 "" 643 "s%P2subl %1,%3,%0") 644 645 (define_insn "subv<mode>3" 646 [(set (match_operand:I48MODE 0 "register_operand" "=r") 647 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 648 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 649 (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 650 (sign_extend:<DWI> (match_dup 2))) 651 (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 652 (match_dup 2)))) 653 (const_int 0))] 654 "" 655 "sub<modesuffix>v %r1,%2,%0") 656 657 (define_insn "mul<mode>3" 658 [(set (match_operand:I48MODE 0 "register_operand" "=r") 659 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 660 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 661 "" 662 "mul<modesuffix> %r1,%2,%0" 663 [(set_attr "type" "imul") 664 (set_attr "opsize" "<mode>")]) 665 666 (define_insn "*mulsi_se" 667 [(set (match_operand:DI 0 "register_operand" "=r") 668 (sign_extend:DI 669 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 670 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 671 "" 672 "mull %r1,%2,%0" 673 [(set_attr "type" "imul") 674 (set_attr "opsize" "si")]) 675 676 (define_insn "mulv<mode>3" 677 [(set (match_operand:I48MODE 0 "register_operand" "=r") 678 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 679 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 680 (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 681 (sign_extend:<DWI> (match_dup 2))) 682 (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 683 (match_dup 2)))) 684 (const_int 0))] 685 "" 686 "mul<modesuffix>v %r1,%2,%0" 687 [(set_attr "type" "imul") 688 (set_attr "opsize" "<mode>")]) 689 690 (define_expand "umuldi3_highpart" 691 [(set (match_operand:DI 0 "register_operand") 692 (truncate:DI 693 (lshiftrt:TI 694 (mult:TI (zero_extend:TI 695 (match_operand:DI 1 "register_operand")) 696 (match_operand:DI 2 "reg_or_8bit_operand")) 697 (const_int 64))))] 698 "" 699 { 700 if (REG_P (operands[2])) 701 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 702 }) 703 704 (define_insn "*umuldi3_highpart_reg" 705 [(set (match_operand:DI 0 "register_operand" "=r") 706 (truncate:DI 707 (lshiftrt:TI 708 (mult:TI (zero_extend:TI 709 (match_operand:DI 1 "register_operand" "r")) 710 (zero_extend:TI 711 (match_operand:DI 2 "register_operand" "r"))) 712 (const_int 64))))] 713 "" 714 "umulh %1,%2,%0" 715 [(set_attr "type" "imul") 716 (set_attr "opsize" "udi")]) 717 718 (define_insn "*umuldi3_highpart_const" 719 [(set (match_operand:DI 0 "register_operand" "=r") 720 (truncate:DI 721 (lshiftrt:TI 722 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 723 (match_operand:TI 2 "cint8_operand" "I")) 724 (const_int 64))))] 725 "" 726 "umulh %1,%2,%0" 727 [(set_attr "type" "imul") 728 (set_attr "opsize" "udi")]) 729 730 (define_expand "umulditi3" 731 [(set (match_operand:TI 0 "register_operand") 732 (mult:TI 733 (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 734 (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 735 "" 736 { 737 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 738 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 739 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 740 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 741 emit_move_insn (gen_highpart (DImode, operands[0]), h); 742 DONE; 743 }) 744 746 ;; The divide and remainder operations take their inputs from r24 and 747 ;; r25, put their output in r27, and clobber r23 and r28 on all systems. 748 ;; 749 ;; ??? Force sign-extension here because some versions of OSF/1 and 750 ;; Interix/NT don't do the right thing if the inputs are not properly 751 ;; sign-extended. But Linux, for instance, does not have this 752 ;; problem. Is it worth the complication here to eliminate the sign 753 ;; extension? 754 755 (define_code_iterator any_divmod [div mod udiv umod]) 756 757 (define_expand "<code>si3" 758 [(set (match_dup 3) 759 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 760 (set (match_dup 4) 761 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 762 (parallel [(set (match_dup 5) 763 (sign_extend:DI 764 (any_divmod:SI (truncate:SI (match_dup 3)) 765 (truncate:SI (match_dup 4))))) 766 (clobber (reg:DI 23)) 767 (clobber (reg:DI 28))]) 768 (set (match_operand:SI 0 "nonimmediate_operand") 769 (subreg:SI (match_dup 5) 0))] 770 "TARGET_ABI_OSF" 771 { 772 operands[3] = gen_reg_rtx (DImode); 773 operands[4] = gen_reg_rtx (DImode); 774 operands[5] = gen_reg_rtx (DImode); 775 }) 776 777 (define_expand "<code>di3" 778 [(parallel [(set (match_operand:DI 0 "register_operand") 779 (any_divmod:DI 780 (match_operand:DI 1 "register_operand") 781 (match_operand:DI 2 "register_operand"))) 782 (clobber (reg:DI 23)) 783 (clobber (reg:DI 28))])] 784 "TARGET_ABI_OSF") 785 786 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 787 ;; expanded by the assembler. 788 789 (define_insn_and_split "*divmodsi_internal_er" 790 [(set (match_operand:DI 0 "register_operand" "=c") 791 (sign_extend:DI 792 (match_operator:SI 3 "divmod_operator" 793 [(truncate:SI (match_operand:DI 1 "register_operand" "a")) 794 (truncate:SI (match_operand:DI 2 "register_operand" "b"))]))) 795 (clobber (reg:DI 23)) 796 (clobber (reg:DI 28))] 797 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 798 "#" 799 "&& reload_completed" 800 [(parallel [(set (match_dup 0) 801 (sign_extend:DI (match_dup 3))) 802 (use (match_dup 0)) 803 (use (match_dup 4)) 804 (clobber (reg:DI 23)) 805 (clobber (reg:DI 28))])] 806 { 807 const char *str; 808 switch (GET_CODE (operands[3])) 809 { 810 case DIV: 811 str = "__divl"; 812 break; 813 case UDIV: 814 str = "__divlu"; 815 break; 816 case MOD: 817 str = "__reml"; 818 break; 819 case UMOD: 820 str = "__remlu"; 821 break; 822 default: 823 gcc_unreachable (); 824 } 825 operands[4] = GEN_INT (alpha_next_sequence_number++); 826 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 827 gen_rtx_SYMBOL_REF (DImode, str), 828 operands[4])); 829 } 830 [(set_attr "type" "jsr") 831 (set_attr "length" "8")]) 832 833 (define_insn "*divmodsi_internal_er_1" 834 [(set (match_operand:DI 0 "register_operand" "=c") 835 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 836 [(truncate:SI (match_operand:DI 1 "register_operand" "a")) 837 (truncate:SI (match_operand:DI 2 "register_operand" "b"))]))) 838 (use (match_operand:DI 4 "register_operand" "c")) 839 (use (match_operand 5 "const_int_operand")) 840 (clobber (reg:DI 23)) 841 (clobber (reg:DI 28))] 842 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 843 "jsr $23,($27),__%E3%j5" 844 [(set_attr "type" "jsr") 845 (set_attr "length" "4")]) 846 847 (define_insn "*divmodsi_internal" 848 [(set (match_operand:DI 0 "register_operand" "=c") 849 (sign_extend:DI 850 (match_operator:SI 3 "divmod_operator" 851 [(truncate:SI (match_operand:DI 1 "register_operand" "a")) 852 (truncate:SI (match_operand:DI 2 "register_operand" "b"))]))) 853 (clobber (reg:DI 23)) 854 (clobber (reg:DI 28))] 855 "TARGET_ABI_OSF" 856 "%E3 %1,%2,%0" 857 [(set_attr "type" "jsr") 858 (set_attr "length" "8")]) 859 860 (define_insn_and_split "*divmoddi_internal_er" 861 [(set (match_operand:DI 0 "register_operand" "=c") 862 (match_operator:DI 3 "divmod_operator" 863 [(match_operand:DI 1 "register_operand" "a") 864 (match_operand:DI 2 "register_operand" "b")])) 865 (clobber (reg:DI 23)) 866 (clobber (reg:DI 28))] 867 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 868 "#" 869 "&& reload_completed" 870 [(parallel [(set (match_dup 0) (match_dup 3)) 871 (use (match_dup 0)) 872 (use (match_dup 4)) 873 (clobber (reg:DI 23)) 874 (clobber (reg:DI 28))])] 875 { 876 const char *str; 877 switch (GET_CODE (operands[3])) 878 { 879 case DIV: 880 str = "__divq"; 881 break; 882 case UDIV: 883 str = "__divqu"; 884 break; 885 case MOD: 886 str = "__remq"; 887 break; 888 case UMOD: 889 str = "__remqu"; 890 break; 891 default: 892 gcc_unreachable (); 893 } 894 operands[4] = GEN_INT (alpha_next_sequence_number++); 895 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 896 gen_rtx_SYMBOL_REF (DImode, str), 897 operands[4])); 898 } 899 [(set_attr "type" "jsr") 900 (set_attr "length" "8")]) 901 902 (define_insn "*divmoddi_internal_er_1" 903 [(set (match_operand:DI 0 "register_operand" "=c") 904 (match_operator:DI 3 "divmod_operator" 905 [(match_operand:DI 1 "register_operand" "a") 906 (match_operand:DI 2 "register_operand" "b")])) 907 (use (match_operand:DI 4 "register_operand" "c")) 908 (use (match_operand 5 "const_int_operand")) 909 (clobber (reg:DI 23)) 910 (clobber (reg:DI 28))] 911 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 912 "jsr $23,($27),__%E3%j5" 913 [(set_attr "type" "jsr") 914 (set_attr "length" "4")]) 915 916 (define_insn "*divmoddi_internal" 917 [(set (match_operand:DI 0 "register_operand" "=c") 918 (match_operator:DI 3 "divmod_operator" 919 [(match_operand:DI 1 "register_operand" "a") 920 (match_operand:DI 2 "register_operand" "b")])) 921 (clobber (reg:DI 23)) 922 (clobber (reg:DI 28))] 923 "TARGET_ABI_OSF" 924 "%E3 %1,%2,%0" 925 [(set_attr "type" "jsr") 926 (set_attr "length" "8")]) 927 929 ;; Next are the basic logical operations. We only expose the DImode operations 930 ;; to the rtl expanders, but SImode versions exist for combine as well as for 931 ;; the atomic operation splitters. 932 933 (define_insn "*andsi_internal" 934 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 935 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 936 (match_operand:SI 2 "and_operand" "rI,N,M")))] 937 "" 938 "@ 939 and %r1,%2,%0 940 bic %r1,%N2,%0 941 zapnot %r1,%m2,%0" 942 [(set_attr "type" "ilog,ilog,shift")]) 943 944 (define_insn "anddi3" 945 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 946 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 947 (match_operand:DI 2 "and_operand" "rI,N,M")))] 948 "" 949 "@ 950 and %r1,%2,%0 951 bic %r1,%N2,%0 952 zapnot %r1,%m2,%0" 953 [(set_attr "type" "ilog,ilog,shift")]) 954 955 ;; There are times when we can split an AND into two AND insns. This occurs 956 ;; when we can first clear any bytes and then clear anything else. For 957 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 958 ;; Only do this when running on 64-bit host since the computations are 959 ;; too messy otherwise. 960 961 (define_split 962 [(set (match_operand:DI 0 "register_operand") 963 (and:DI (match_operand:DI 1 "register_operand") 964 (match_operand:DI 2 "const_int_operand")))] 965 "! and_operand (operands[2], DImode)" 966 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 967 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 968 { 969 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 970 unsigned HOST_WIDE_INT mask2 = mask1; 971 int i; 972 973 /* For each byte that isn't all zeros, make it all ones. */ 974 for (i = 0; i < 64; i += 8) 975 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 976 mask1 |= (HOST_WIDE_INT) 0xff << i; 977 978 /* Now turn on any bits we've just turned off. */ 979 mask2 |= ~ mask1; 980 981 operands[3] = GEN_INT (mask1); 982 operands[4] = GEN_INT (mask2); 983 }) 984 985 (define_insn "zero_extendqi<mode>2" 986 [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 987 (zero_extend:I248MODE 988 (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 989 "" 990 "@ 991 and %1,0xff,%0 992 ldbu %0,%1" 993 [(set_attr "type" "ilog,ild") 994 (set_attr "isa" "*,bwx")]) 995 996 (define_insn "zero_extendhi<mode>2" 997 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 998 (zero_extend:I48MODE 999 (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 1000 "" 1001 "@ 1002 zapnot %1,3,%0 1003 ldwu %0,%1" 1004 [(set_attr "type" "shift,ild") 1005 (set_attr "isa" "*,bwx")]) 1006 1007 (define_insn "zero_extendsidi2" 1008 [(set (match_operand:DI 0 "register_operand" "=r") 1009 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1010 "" 1011 "zapnot %1,15,%0" 1012 [(set_attr "type" "shift")]) 1013 1014 (define_insn "andnot<mode>3" 1015 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1016 (and:I48MODE 1017 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1018 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1019 "" 1020 "bic %r2,%1,%0" 1021 [(set_attr "type" "ilog")]) 1022 1023 (define_insn "*iorsi_internal" 1024 [(set (match_operand:SI 0 "register_operand" "=r,r") 1025 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1026 (match_operand:SI 2 "or_operand" "rI,N")))] 1027 "" 1028 "@ 1029 bis %r1,%2,%0 1030 ornot %r1,%N2,%0" 1031 [(set_attr "type" "ilog")]) 1032 1033 (define_insn "iordi3" 1034 [(set (match_operand:DI 0 "register_operand" "=r,r") 1035 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1036 (match_operand:DI 2 "or_operand" "rI,N")))] 1037 "" 1038 "@ 1039 bis %r1,%2,%0 1040 ornot %r1,%N2,%0" 1041 [(set_attr "type" "ilog")]) 1042 1043 (define_insn "*one_cmplsi_internal" 1044 [(set (match_operand:SI 0 "register_operand" "=r") 1045 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1046 "" 1047 "ornot $31,%1,%0" 1048 [(set_attr "type" "ilog")]) 1049 1050 (define_insn "one_cmpldi2" 1051 [(set (match_operand:DI 0 "register_operand" "=r") 1052 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1053 "" 1054 "ornot $31,%1,%0" 1055 [(set_attr "type" "ilog")]) 1056 1057 (define_insn "*iornot<mode>3" 1058 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1059 (ior:I48MODE 1060 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1061 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1062 "" 1063 "ornot %r2,%1,%0" 1064 [(set_attr "type" "ilog")]) 1065 1066 (define_insn "*xorsi_internal" 1067 [(set (match_operand:SI 0 "register_operand" "=r,r") 1068 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1069 (match_operand:SI 2 "or_operand" "rI,N")))] 1070 "" 1071 "@ 1072 xor %r1,%2,%0 1073 eqv %r1,%N2,%0" 1074 [(set_attr "type" "ilog")]) 1075 1076 (define_insn "xordi3" 1077 [(set (match_operand:DI 0 "register_operand" "=r,r") 1078 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1079 (match_operand:DI 2 "or_operand" "rI,N")))] 1080 "" 1081 "@ 1082 xor %r1,%2,%0 1083 eqv %r1,%N2,%0" 1084 [(set_attr "type" "ilog")]) 1085 1086 (define_insn "*xornot<mode>3" 1087 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1088 (not:I48MODE (xor:I48MODE 1089 (match_operand:I48MODE 1 "register_operand" "%rJ") 1090 (match_operand:I48MODE 2 "register_operand" "rI"))))] 1091 "" 1092 "eqv %r1,%2,%0" 1093 [(set_attr "type" "ilog")]) 1094 1096 ;; Handle FFS and related insns iff we support CIX. 1097 1098 (define_expand "ffsdi2" 1099 [(set (match_dup 2) 1100 (ctz:DI (match_operand:DI 1 "register_operand"))) 1101 (set (match_dup 3) 1102 (plus:DI (match_dup 2) (const_int 1))) 1103 (set (match_operand:DI 0 "register_operand") 1104 (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1105 (const_int 0) (match_dup 3)))] 1106 "TARGET_CIX" 1107 { 1108 operands[2] = gen_reg_rtx (DImode); 1109 operands[3] = gen_reg_rtx (DImode); 1110 }) 1111 1112 (define_insn "clzdi2" 1113 [(set (match_operand:DI 0 "register_operand" "=r") 1114 (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1115 "TARGET_CIX" 1116 "ctlz %1,%0" 1117 [(set_attr "type" "mvi")]) 1118 1119 (define_insn "ctzdi2" 1120 [(set (match_operand:DI 0 "register_operand" "=r") 1121 (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1122 "TARGET_CIX" 1123 "cttz %1,%0" 1124 [(set_attr "type" "mvi")]) 1125 1126 (define_insn "popcountdi2" 1127 [(set (match_operand:DI 0 "register_operand" "=r") 1128 (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1129 "TARGET_CIX" 1130 "ctpop %1,%0" 1131 [(set_attr "type" "mvi")]) 1132 1133 (define_expand "bswapsi2" 1134 [(set (match_operand:SI 0 "register_operand") 1135 (bswap:SI (match_operand:SI 1 "register_operand")))] 1136 "!optimize_size" 1137 { 1138 rtx t0, t1; 1139 1140 t0 = gen_reg_rtx (DImode); 1141 t1 = gen_reg_rtx (DImode); 1142 1143 emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1144 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1145 GEN_INT (24))); 1146 emit_insn (gen_iordi3 (t1, t0, t1)); 1147 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1148 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1149 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1150 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1151 gen_lowpart (SImode, t1))); 1152 DONE; 1153 }) 1154 1155 (define_expand "bswapdi2" 1156 [(set (match_operand:DI 0 "register_operand") 1157 (bswap:DI (match_operand:DI 1 "register_operand")))] 1158 "!optimize_size" 1159 { 1160 rtx t0, t1; 1161 1162 t0 = gen_reg_rtx (DImode); 1163 t1 = gen_reg_rtx (DImode); 1164 1165 /* This method of shifting and masking is not specific to Alpha, but 1166 is only profitable on Alpha because of our handy byte zap insn. */ 1167 1168 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1169 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1170 emit_insn (gen_iordi3 (t1, t0, t1)); 1171 1172 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1173 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1174 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1175 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1176 emit_insn (gen_iordi3 (t1, t0, t1)); 1177 1178 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1179 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1180 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1181 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1182 emit_insn (gen_iordi3 (operands[0], t0, t1)); 1183 DONE; 1184 }) 1185 1187 ;; Next come the shifts and the various extract and insert operations. 1188 1189 (define_insn "ashldi3" 1190 [(set (match_operand:DI 0 "register_operand" "=r,r") 1191 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1192 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1193 "" 1194 { 1195 switch (which_alternative) 1196 { 1197 case 0: 1198 if (operands[2] == const1_rtx) 1199 return "addq %r1,%r1,%0"; 1200 else 1201 return "s%P2addq %r1,0,%0"; 1202 case 1: 1203 return "sll %r1,%2,%0"; 1204 default: 1205 gcc_unreachable (); 1206 } 1207 } 1208 [(set_attr "type" "iadd,shift")]) 1209 1210 (define_insn "ashlsi3" 1211 [(set (match_operand:SI 0 "register_operand" "=r") 1212 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1213 (match_operand:SI 2 "const123_operand" "P")))] 1214 "" 1215 { 1216 if (operands[2] == const1_rtx) 1217 return "addl %r1,%r1,%0"; 1218 else 1219 return "s%P2addl %r1,0,%0"; 1220 } 1221 [(set_attr "type" "iadd")]) 1222 1223 (define_insn "*ashlsi_se" 1224 [(set (match_operand:DI 0 "register_operand" "=r") 1225 (sign_extend:DI 1226 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1227 (match_operand:SI 2 "const123_operand" "P"))))] 1228 "" 1229 { 1230 if (operands[2] == const1_rtx) 1231 return "addl %r1,%r1,%0"; 1232 else 1233 return "s%P2addl %r1,0,%0"; 1234 } 1235 [(set_attr "type" "iadd")]) 1236 1237 (define_insn "lshrdi3" 1238 [(set (match_operand:DI 0 "register_operand" "=r") 1239 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1240 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1241 "" 1242 "srl %r1,%2,%0" 1243 [(set_attr "type" "shift")]) 1244 1245 (define_insn "ashrdi3" 1246 [(set (match_operand:DI 0 "register_operand" "=r") 1247 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1248 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1249 "" 1250 "sra %r1,%2,%0" 1251 [(set_attr "type" "shift")]) 1252 1253 (define_insn "extendqi<mode>2" 1254 [(set (match_operand:I24MODE 0 "register_operand" "=r") 1255 (sign_extend:I24MODE 1256 (match_operand:QI 1 "register_operand" "r")))] 1257 "TARGET_BWX" 1258 "sextb %1,%0" 1259 [(set_attr "type" "shift")]) 1260 1261 (define_expand "extendqidi2" 1262 [(set (match_operand:DI 0 "register_operand") 1263 (sign_extend:DI (match_operand:QI 1 "general_operand")))] 1264 "" 1265 { 1266 if (TARGET_BWX) 1267 operands[1] = force_reg (QImode, operands[1]); 1268 else 1269 { 1270 rtx x, t1, t2, i56; 1271 1272 if (unaligned_memory_operand (operands[1], QImode)) 1273 { 1274 x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1275 alpha_set_memflags (x, operands[1]); 1276 emit_insn (x); 1277 DONE; 1278 } 1279 1280 t1 = gen_reg_rtx (DImode); 1281 t2 = gen_reg_rtx (DImode); 1282 i56 = GEN_INT (56); 1283 1284 x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1285 emit_move_insn (t1, x); 1286 emit_insn (gen_ashldi3 (t2, t1, i56)); 1287 emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1288 DONE; 1289 } 1290 }) 1291 1292 (define_insn "*extendqidi2_bwx" 1293 [(set (match_operand:DI 0 "register_operand" "=r") 1294 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1295 "TARGET_BWX" 1296 "sextb %1,%0" 1297 [(set_attr "type" "shift")]) 1298 1299 (define_insn "extendhisi2" 1300 [(set (match_operand:SI 0 "register_operand" "=r") 1301 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1302 "TARGET_BWX" 1303 "sextw %1,%0" 1304 [(set_attr "type" "shift")]) 1305 1306 (define_expand "extendhidi2" 1307 [(set (match_operand:DI 0 "register_operand") 1308 (sign_extend:DI (match_operand:HI 1 "general_operand")))] 1309 "" 1310 { 1311 if (TARGET_BWX) 1312 operands[1] = force_reg (HImode, operands[1]); 1313 else 1314 { 1315 rtx x, t1, t2, i48; 1316 1317 if (unaligned_memory_operand (operands[1], HImode)) 1318 { 1319 x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1320 alpha_set_memflags (x, operands[1]); 1321 emit_insn (x); 1322 DONE; 1323 } 1324 1325 t1 = gen_reg_rtx (DImode); 1326 t2 = gen_reg_rtx (DImode); 1327 i48 = GEN_INT (48); 1328 1329 x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1330 emit_move_insn (t1, x); 1331 emit_insn (gen_ashldi3 (t2, t1, i48)); 1332 emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1333 DONE; 1334 } 1335 }) 1336 1337 (define_insn "*extendhidi2_bwx" 1338 [(set (match_operand:DI 0 "register_operand" "=r") 1339 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1340 "TARGET_BWX" 1341 "sextw %1,%0" 1342 [(set_attr "type" "shift")]) 1343 1344 ;; Here's how we sign extend an unaligned byte and halfword. Doing this 1345 ;; as a pattern saves one instruction. The code is similar to that for 1346 ;; the unaligned loads (see below). 1347 ;; 1348 ;; Operand 1 is the address, operand 0 is the result. 1349 1350 (define_expand "unaligned_extendqidi" 1351 [(set (match_dup 3) 1352 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1353 (set (match_dup 4) 1354 (ashift:DI (match_dup 3) 1355 (minus:DI (const_int 64) 1356 (ashift:DI 1357 (and:DI (match_dup 2) (const_int 7)) 1358 (const_int 3))))) 1359 (set (match_operand:QI 0 "register_operand") 1360 (ashiftrt:DI (match_dup 4) (const_int 56)))] 1361 "" 1362 { 1363 operands[0] = gen_lowpart (DImode, operands[0]); 1364 operands[2] = get_unaligned_offset (operands[1], 1); 1365 operands[3] = gen_reg_rtx (DImode); 1366 operands[4] = gen_reg_rtx (DImode); 1367 }) 1368 1369 (define_expand "unaligned_extendhidi" 1370 [(set (match_dup 3) 1371 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1372 (set (match_dup 4) 1373 (ashift:DI (match_dup 3) 1374 (minus:DI (const_int 64) 1375 (ashift:DI 1376 (and:DI (match_dup 2) (const_int 7)) 1377 (const_int 3))))) 1378 (set (match_operand:HI 0 "register_operand") 1379 (ashiftrt:DI (match_dup 4) (const_int 48)))] 1380 "" 1381 { 1382 operands[0] = gen_lowpart (DImode, operands[0]); 1383 operands[2] = get_unaligned_offset (operands[1], 2); 1384 operands[3] = gen_reg_rtx (DImode); 1385 operands[4] = gen_reg_rtx (DImode); 1386 }) 1387 1388 (define_insn "*extxl_const" 1389 [(set (match_operand:DI 0 "register_operand" "=r") 1390 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1391 (match_operand:DI 2 "mode_width_operand" "n") 1392 (match_operand:DI 3 "mul8_operand" "I")))] 1393 "" 1394 "ext%M2l %r1,%s3,%0" 1395 [(set_attr "type" "shift")]) 1396 1397 (define_insn "extxl" 1398 [(set (match_operand:DI 0 "register_operand" "=r") 1399 (zero_extract:DI 1400 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1401 (match_operand:DI 2 "mode_width_operand" "n") 1402 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1403 (const_int 3))))] 1404 "" 1405 "ext%M2l %r1,%3,%0" 1406 [(set_attr "type" "shift")]) 1407 1408 ;; Combine has some strange notion of preserving existing undefined behavior 1409 ;; in shifts larger than a word size. So capture these patterns that it 1410 ;; should have turned into zero_extracts. 1411 1412 (define_insn "*extxl_1" 1413 [(set (match_operand:DI 0 "register_operand" "=r") 1414 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1415 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1416 (const_int 3))) 1417 (match_operand:DI 3 "mode_mask_operand" "n")))] 1418 "" 1419 "ext%U3l %1,%2,%0" 1420 [(set_attr "type" "shift")]) 1421 1422 (define_insn "*extql_2" 1423 [(set (match_operand:DI 0 "register_operand" "=r") 1424 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1425 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1426 (const_int 3))))] 1427 "" 1428 "extql %1,%2,%0" 1429 [(set_attr "type" "shift")]) 1430 1431 (define_insn "extqh" 1432 [(set (match_operand:DI 0 "register_operand" "=r") 1433 (ashift:DI 1434 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1435 (minus:DI (const_int 64) 1436 (ashift:DI 1437 (and:DI 1438 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1439 (const_int 7)) 1440 (const_int 3)))))] 1441 "" 1442 "extqh %r1,%2,%0" 1443 [(set_attr "type" "shift")]) 1444 1445 (define_insn "extwh" 1446 [(set (match_operand:DI 0 "register_operand" "=r") 1447 (ashift:DI 1448 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1449 (const_int 65535)) 1450 (minus:DI (const_int 64) 1451 (ashift:DI 1452 (and:DI 1453 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1454 (const_int 7)) 1455 (const_int 3)))))] 1456 "" 1457 "extwh %r1,%2,%0" 1458 [(set_attr "type" "shift")]) 1459 1460 (define_insn "extlh" 1461 [(set (match_operand:DI 0 "register_operand" "=r") 1462 (ashift:DI 1463 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1464 (const_int 2147483647)) 1465 (minus:DI (const_int 64) 1466 (ashift:DI 1467 (and:DI 1468 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1469 (const_int 7)) 1470 (const_int 3)))))] 1471 "" 1472 "extlh %r1,%2,%0" 1473 [(set_attr "type" "shift")]) 1474 1475 ;; This converts an extXl into an extXh with an appropriate adjustment 1476 ;; to the address calculation. 1477 1478 ;;(define_split 1479 ;; [(set (match_operand:DI 0 "register_operand") 1480 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1481 ;; (match_operand:DI 2 "mode_width_operand") 1482 ;; (ashift:DI (match_operand:DI 3) 1483 ;; (const_int 3))) 1484 ;; (match_operand:DI 4 "const_int_operand"))) 1485 ;; (clobber (match_operand:DI 5 "register_operand"))] 1486 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1487 ;; [(set (match_dup 5) (match_dup 6)) 1488 ;; (set (match_dup 0) 1489 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1490 ;; (ashift:DI (plus:DI (match_dup 5) 1491 ;; (match_dup 7)) 1492 ;; (const_int 3))) 1493 ;; (match_dup 4)))] 1494 ;; " 1495 ;;{ 1496 ;; operands[6] = plus_constant (DImode, operands[3], 1497 ;; INTVAL (operands[2]) / BITS_PER_UNIT); 1498 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1499 ;;}") 1500 1501 (define_insn "ins<modesuffix>l_const" 1502 [(set (match_operand:DI 0 "register_operand" "=r") 1503 (ashift:DI (zero_extend:DI 1504 (match_operand:I124MODE 1 "register_operand" "r")) 1505 (match_operand:DI 2 "mul8_operand" "I")))] 1506 "" 1507 "ins<modesuffix>l %1,%s2,%0" 1508 [(set_attr "type" "shift")]) 1509 1510 (define_insn "ins<modesuffix>l" 1511 [(set (match_operand:DI 0 "register_operand" "=r") 1512 (ashift:DI (zero_extend:DI 1513 (match_operand:I124MODE 1 "register_operand" "r")) 1514 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1515 (const_int 3))))] 1516 "" 1517 "ins<modesuffix>l %1,%2,%0" 1518 [(set_attr "type" "shift")]) 1519 1520 (define_insn "insql" 1521 [(set (match_operand:DI 0 "register_operand" "=r") 1522 (ashift:DI (match_operand:DI 1 "register_operand" "r") 1523 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1524 (const_int 3))))] 1525 "" 1526 "insql %1,%2,%0" 1527 [(set_attr "type" "shift")]) 1528 1529 ;; Combine has this sometimes habit of moving the and outside of the 1530 ;; shift, making life more interesting. 1531 1532 (define_insn "*insxl" 1533 [(set (match_operand:DI 0 "register_operand" "=r") 1534 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1535 (match_operand:DI 2 "mul8_operand" "I")) 1536 (match_operand:DI 3 "const_int_operand" "i")))] 1537 "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1538 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1539 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1540 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1541 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1542 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))" 1543 { 1544 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1545 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1546 return "insbl %1,%s2,%0"; 1547 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1548 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1549 return "inswl %1,%s2,%0"; 1550 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1551 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1552 return "insll %1,%s2,%0"; 1553 1554 gcc_unreachable (); 1555 } 1556 [(set_attr "type" "shift")]) 1557 1558 ;; We do not include the insXh insns because they are complex to express 1559 ;; and it does not appear that we would ever want to generate them. 1560 ;; 1561 ;; Since we need them for block moves, though, cop out and use unspec. 1562 1563 (define_insn "insxh" 1564 [(set (match_operand:DI 0 "register_operand" "=r") 1565 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1566 (match_operand:DI 2 "mode_width_operand" "n") 1567 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1568 UNSPEC_INSXH))] 1569 "" 1570 "ins%M2h %1,%3,%0" 1571 [(set_attr "type" "shift")]) 1572 1573 (define_insn "mskxl" 1574 [(set (match_operand:DI 0 "register_operand" "=r") 1575 (and:DI (not:DI (ashift:DI 1576 (match_operand:DI 2 "mode_mask_operand" "n") 1577 (ashift:DI 1578 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1579 (const_int 3)))) 1580 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1581 "" 1582 "msk%U2l %r1,%3,%0" 1583 [(set_attr "type" "shift")]) 1584 1585 ;; We do not include the mskXh insns because it does not appear we would 1586 ;; ever generate one. 1587 ;; 1588 ;; Again, we do for block moves and we use unspec again. 1589 1590 (define_insn "mskxh" 1591 [(set (match_operand:DI 0 "register_operand" "=r") 1592 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1593 (match_operand:DI 2 "mode_width_operand" "n") 1594 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1595 UNSPEC_MSKXH))] 1596 "" 1597 "msk%M2h %1,%3,%0" 1598 [(set_attr "type" "shift")]) 1599 1600 ;; Prefer AND + NE over LSHIFTRT + AND. 1601 1602 (define_insn_and_split "*ze_and_ne" 1603 [(set (match_operand:DI 0 "register_operand" "=r") 1604 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1605 (const_int 1) 1606 (match_operand 2 "const_int_operand" "I")))] 1607 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1608 "#" 1609 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1610 [(set (match_dup 0) 1611 (and:DI (match_dup 1) (match_dup 3))) 1612 (set (match_dup 0) 1613 (ne:DI (match_dup 0) (const_int 0)))] 1614 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1615 1617 ;; Floating-point operations. All the double-precision insns can extend 1618 ;; from single, so indicate that. The exception are the ones that simply 1619 ;; play with the sign bits; it's not clear what to do there. 1620 1621 (define_mode_iterator FMODE [SF DF]) 1622 1623 (define_mode_attr opmode [(SF "si") (DF "di")]) 1624 1625 (define_insn "abs<mode>2" 1626 [(set (match_operand:FMODE 0 "register_operand" "=f") 1627 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1628 "TARGET_FP" 1629 "cpys $f31,%R1,%0" 1630 [(set_attr "type" "fcpys")]) 1631 1632 (define_insn "*nabs<mode>2" 1633 [(set (match_operand:FMODE 0 "register_operand" "=f") 1634 (neg:FMODE 1635 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1636 "TARGET_FP" 1637 "cpysn $f31,%R1,%0" 1638 [(set_attr "type" "fadd")]) 1639 1640 (define_expand "abstf2" 1641 [(parallel [(set (match_operand:TF 0 "register_operand") 1642 (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1643 (use (match_dup 2))])] 1644 "TARGET_HAS_XFLOATING_LIBS" 1645 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1646 1647 (define_insn_and_split "*abstf_internal" 1648 [(set (match_operand:TF 0 "register_operand" "=r") 1649 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1650 (use (match_operand:DI 2 "register_operand" "r"))] 1651 "TARGET_HAS_XFLOATING_LIBS" 1652 "#" 1653 "&& reload_completed" 1654 [(const_int 0)] 1655 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1656 1657 (define_insn "neg<mode>2" 1658 [(set (match_operand:FMODE 0 "register_operand" "=f") 1659 (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1660 "TARGET_FP" 1661 "cpysn %R1,%R1,%0" 1662 [(set_attr "type" "fadd")]) 1663 1664 (define_expand "negtf2" 1665 [(parallel [(set (match_operand:TF 0 "register_operand") 1666 (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1667 (use (match_dup 2))])] 1668 "TARGET_HAS_XFLOATING_LIBS" 1669 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1670 1671 (define_insn_and_split "*negtf_internal" 1672 [(set (match_operand:TF 0 "register_operand" "=r") 1673 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1674 (use (match_operand:DI 2 "register_operand" "r"))] 1675 "TARGET_HAS_XFLOATING_LIBS" 1676 "#" 1677 "&& reload_completed" 1678 [(const_int 0)] 1679 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1680 1681 (define_insn "copysign<mode>3" 1682 [(set (match_operand:FMODE 0 "register_operand" "=f") 1683 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1684 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1685 UNSPEC_COPYSIGN))] 1686 "TARGET_FP" 1687 "cpys %R2,%R1,%0" 1688 [(set_attr "type" "fadd")]) 1689 1690 (define_insn "*ncopysign<mode>3" 1691 [(set (match_operand:FMODE 0 "register_operand" "=f") 1692 (neg:FMODE 1693 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1694 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1695 UNSPEC_COPYSIGN)))] 1696 "TARGET_FP" 1697 "cpysn %R2,%R1,%0" 1698 [(set_attr "type" "fadd")]) 1699 1700 (define_insn "add<mode>3" 1701 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1702 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1703 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1704 "TARGET_FP" 1705 "add<modesuffix>%/ %R1,%R2,%0" 1706 [(set_attr "type" "fadd") 1707 (set_attr "trap" "yes") 1708 (set_attr "round_suffix" "normal") 1709 (set_attr "trap_suffix" "u_su_sui") 1710 (set (attr "enabled") 1711 (cond [(eq_attr "alternative" "0") 1712 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1713 ] 1714 (symbol_ref "true")))]) 1715 1716 (define_insn "*adddf_ext1" 1717 [(set (match_operand:DF 0 "register_operand" "=f") 1718 (plus:DF (float_extend:DF 1719 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1720 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1721 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1722 "add%-%/ %R1,%R2,%0" 1723 [(set_attr "type" "fadd") 1724 (set_attr "trap" "yes") 1725 (set_attr "round_suffix" "normal") 1726 (set_attr "trap_suffix" "u_su_sui")]) 1727 1728 (define_insn "*adddf_ext2" 1729 [(set (match_operand:DF 0 "register_operand" "=f") 1730 (plus:DF (float_extend:DF 1731 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1732 (float_extend:DF 1733 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1734 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1735 "add%-%/ %R1,%R2,%0" 1736 [(set_attr "type" "fadd") 1737 (set_attr "trap" "yes") 1738 (set_attr "round_suffix" "normal") 1739 (set_attr "trap_suffix" "u_su_sui")]) 1740 1741 (define_expand "addtf3" 1742 [(use (match_operand:TF 0 "register_operand")) 1743 (use (match_operand:TF 1 "general_operand")) 1744 (use (match_operand:TF 2 "general_operand"))] 1745 "TARGET_HAS_XFLOATING_LIBS" 1746 "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1747 1748 (define_insn "sub<mode>3" 1749 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1750 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1751 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1752 "TARGET_FP" 1753 "sub<modesuffix>%/ %R1,%R2,%0" 1754 [(set_attr "type" "fadd") 1755 (set_attr "trap" "yes") 1756 (set_attr "round_suffix" "normal") 1757 (set_attr "trap_suffix" "u_su_sui") 1758 (set (attr "enabled") 1759 (cond [(eq_attr "alternative" "0") 1760 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1761 ] 1762 (symbol_ref "true")))]) 1763 1764 (define_insn "*subdf_ext1" 1765 [(set (match_operand:DF 0 "register_operand" "=f") 1766 (minus:DF (float_extend:DF 1767 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1768 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1769 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1770 "sub%-%/ %R1,%R2,%0" 1771 [(set_attr "type" "fadd") 1772 (set_attr "trap" "yes") 1773 (set_attr "round_suffix" "normal") 1774 (set_attr "trap_suffix" "u_su_sui")]) 1775 1776 (define_insn "*subdf_ext2" 1777 [(set (match_operand:DF 0 "register_operand" "=f") 1778 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1779 (float_extend:DF 1780 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1781 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1782 "sub%-%/ %R1,%R2,%0" 1783 [(set_attr "type" "fadd") 1784 (set_attr "trap" "yes") 1785 (set_attr "round_suffix" "normal") 1786 (set_attr "trap_suffix" "u_su_sui")]) 1787 1788 (define_insn "*subdf_ext3" 1789 [(set (match_operand:DF 0 "register_operand" "=f") 1790 (minus:DF (float_extend:DF 1791 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1792 (float_extend:DF 1793 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1794 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1795 "sub%-%/ %R1,%R2,%0" 1796 [(set_attr "type" "fadd") 1797 (set_attr "trap" "yes") 1798 (set_attr "round_suffix" "normal") 1799 (set_attr "trap_suffix" "u_su_sui")]) 1800 1801 (define_expand "subtf3" 1802 [(use (match_operand:TF 0 "register_operand")) 1803 (use (match_operand:TF 1 "general_operand")) 1804 (use (match_operand:TF 2 "general_operand"))] 1805 "TARGET_HAS_XFLOATING_LIBS" 1806 "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1807 1808 (define_insn "mul<mode>3" 1809 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1810 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1811 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1812 "TARGET_FP" 1813 "mul<modesuffix>%/ %R1,%R2,%0" 1814 [(set_attr "type" "fmul") 1815 (set_attr "trap" "yes") 1816 (set_attr "round_suffix" "normal") 1817 (set_attr "trap_suffix" "u_su_sui") 1818 (set (attr "enabled") 1819 (cond [(eq_attr "alternative" "0") 1820 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1821 ] 1822 (symbol_ref "true")))]) 1823 1824 (define_insn "*muldf_ext1" 1825 [(set (match_operand:DF 0 "register_operand" "=f") 1826 (mult:DF (float_extend:DF 1827 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1828 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1829 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1830 "mul%-%/ %R1,%R2,%0" 1831 [(set_attr "type" "fmul") 1832 (set_attr "trap" "yes") 1833 (set_attr "round_suffix" "normal") 1834 (set_attr "trap_suffix" "u_su_sui")]) 1835 1836 (define_insn "*muldf_ext2" 1837 [(set (match_operand:DF 0 "register_operand" "=f") 1838 (mult:DF (float_extend:DF 1839 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1840 (float_extend:DF 1841 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1842 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1843 "mul%-%/ %R1,%R2,%0" 1844 [(set_attr "type" "fmul") 1845 (set_attr "trap" "yes") 1846 (set_attr "round_suffix" "normal") 1847 (set_attr "trap_suffix" "u_su_sui")]) 1848 1849 (define_expand "multf3" 1850 [(use (match_operand:TF 0 "register_operand")) 1851 (use (match_operand:TF 1 "general_operand")) 1852 (use (match_operand:TF 2 "general_operand"))] 1853 "TARGET_HAS_XFLOATING_LIBS" 1854 "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1855 1856 (define_insn "div<mode>3" 1857 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1858 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1859 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1860 "TARGET_FP" 1861 "div<modesuffix>%/ %R1,%R2,%0" 1862 [(set_attr "type" "fdiv") 1863 (set_attr "opsize" "<opmode>") 1864 (set_attr "trap" "yes") 1865 (set_attr "round_suffix" "normal") 1866 (set_attr "trap_suffix" "u_su_sui") 1867 (set (attr "enabled") 1868 (cond [(eq_attr "alternative" "0") 1869 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1870 ] 1871 (symbol_ref "true")))]) 1872 1873 (define_insn "*divdf_ext1" 1874 [(set (match_operand:DF 0 "register_operand" "=f") 1875 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1876 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1877 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1878 "div%-%/ %R1,%R2,%0" 1879 [(set_attr "type" "fdiv") 1880 (set_attr "trap" "yes") 1881 (set_attr "round_suffix" "normal") 1882 (set_attr "trap_suffix" "u_su_sui")]) 1883 1884 (define_insn "*divdf_ext2" 1885 [(set (match_operand:DF 0 "register_operand" "=f") 1886 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1887 (float_extend:DF 1888 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1889 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1890 "div%-%/ %R1,%R2,%0" 1891 [(set_attr "type" "fdiv") 1892 (set_attr "trap" "yes") 1893 (set_attr "round_suffix" "normal") 1894 (set_attr "trap_suffix" "u_su_sui")]) 1895 1896 (define_insn "*divdf_ext3" 1897 [(set (match_operand:DF 0 "register_operand" "=f") 1898 (div:DF (float_extend:DF 1899 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1900 (float_extend:DF 1901 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1902 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1903 "div%-%/ %R1,%R2,%0" 1904 [(set_attr "type" "fdiv") 1905 (set_attr "trap" "yes") 1906 (set_attr "round_suffix" "normal") 1907 (set_attr "trap_suffix" "u_su_sui")]) 1908 1909 (define_expand "divtf3" 1910 [(use (match_operand:TF 0 "register_operand")) 1911 (use (match_operand:TF 1 "general_operand")) 1912 (use (match_operand:TF 2 "general_operand"))] 1913 "TARGET_HAS_XFLOATING_LIBS" 1914 "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1915 1916 (define_insn "sqrt<mode>2" 1917 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1918 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))] 1919 "TARGET_FP && TARGET_FIX" 1920 "sqrt<modesuffix>%/ %R1,%0" 1921 [(set_attr "type" "fsqrt") 1922 (set_attr "opsize" "<opmode>") 1923 (set_attr "trap" "yes") 1924 (set_attr "round_suffix" "normal") 1925 (set_attr "trap_suffix" "u_su_sui") 1926 (set (attr "enabled") 1927 (cond [(eq_attr "alternative" "0") 1928 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1929 ] 1930 (symbol_ref "true")))]) 1931 1932 ;; Define conversion operators between DFmode and SImode, using the cvtql 1933 ;; instruction. To allow combine et al to do useful things, we keep the 1934 ;; operation as a unit until after reload, at which point we split the 1935 ;; instructions. 1936 ;; 1937 ;; Note that we (attempt to) only consider this optimization when the 1938 ;; ultimate destination is memory. If we will be doing further integer 1939 ;; processing, it is cheaper to do the truncation in the int regs. 1940 1941 (define_insn "*cvtql" 1942 [(set (match_operand:SF 0 "register_operand" "=f") 1943 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1944 UNSPEC_CVTQL))] 1945 "TARGET_FP" 1946 "cvtql%/ %R1,%0" 1947 [(set_attr "type" "fadd") 1948 (set_attr "trap" "yes") 1949 (set_attr "trap_suffix" "v_sv")]) 1950 1951 (define_insn_and_split "*fix_truncdfsi_ieee" 1952 [(set (match_operand:SI 0 "memory_operand" "=m") 1953 (subreg:SI 1954 (match_operator:DI 4 "fix_operator" 1955 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1956 (clobber (match_scratch:DI 2 "=&f")) 1957 (clobber (match_scratch:SF 3 "=&f"))] 1958 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1959 "#" 1960 "&& reload_completed" 1961 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 1962 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1963 (set (match_dup 5) (match_dup 3))] 1964 { 1965 operands[5] = adjust_address (operands[0], SFmode, 0); 1966 } 1967 [(set_attr "type" "fadd") 1968 (set_attr "trap" "yes")]) 1969 1970 (define_insn_and_split "*fix_truncdfsi_internal" 1971 [(set (match_operand:SI 0 "memory_operand" "=m") 1972 (subreg:SI 1973 (match_operator:DI 3 "fix_operator" 1974 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1975 (clobber (match_scratch:DI 2 "=f"))] 1976 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1977 "#" 1978 "&& reload_completed" 1979 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 1980 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1981 (set (match_dup 5) (match_dup 4))] 1982 { 1983 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 1984 operands[5] = adjust_address (operands[0], SFmode, 0); 1985 } 1986 [(set_attr "type" "fadd") 1987 (set_attr "trap" "yes")]) 1988 1989 (define_insn "*fix_truncdfdi2" 1990 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 1991 (match_operator:DI 2 "fix_operator" 1992 [(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))] 1993 "TARGET_FP" 1994 "cvt%-q%/ %R1,%0" 1995 [(set_attr "type" "fadd") 1996 (set_attr "trap" "yes") 1997 (set_attr "round_suffix" "c") 1998 (set_attr "trap_suffix" "v_sv_svi") 1999 (set (attr "enabled") 2000 (cond [(eq_attr "alternative" "0") 2001 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2002 ] 2003 (symbol_ref "true")))]) 2004 2005 (define_expand "fix_truncdfdi2" 2006 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2007 (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2008 "TARGET_FP") 2009 2010 (define_expand "fixuns_truncdfdi2" 2011 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2012 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2013 "TARGET_FP") 2014 2015 ;; Likewise between SFmode and SImode. 2016 2017 (define_insn_and_split "*fix_truncsfsi_ieee" 2018 [(set (match_operand:SI 0 "memory_operand" "=m") 2019 (subreg:SI 2020 (match_operator:DI 4 "fix_operator" 2021 [(float_extend:DF 2022 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2023 (clobber (match_scratch:DI 2 "=&f")) 2024 (clobber (match_scratch:SF 3 "=&f"))] 2025 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2026 "#" 2027 "&& reload_completed" 2028 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2029 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2030 (set (match_dup 5) (match_dup 3))] 2031 "operands[5] = adjust_address (operands[0], SFmode, 0);" 2032 [(set_attr "type" "fadd") 2033 (set_attr "trap" "yes")]) 2034 2035 (define_insn_and_split "*fix_truncsfsi_internal" 2036 [(set (match_operand:SI 0 "memory_operand" "=m") 2037 (subreg:SI 2038 (match_operator:DI 3 "fix_operator" 2039 [(float_extend:DF 2040 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2041 (clobber (match_scratch:DI 2 "=f"))] 2042 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2043 "#" 2044 "&& reload_completed" 2045 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2046 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2047 (set (match_dup 5) (match_dup 4))] 2048 { 2049 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2050 operands[5] = adjust_address (operands[0], SFmode, 0); 2051 } 2052 [(set_attr "type" "fadd") 2053 (set_attr "trap" "yes")]) 2054 2055 (define_insn "*fix_truncsfdi2" 2056 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 2057 (match_operator:DI 2 "fix_operator" 2058 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))] 2059 "TARGET_FP" 2060 "cvt%-q%/ %R1,%0" 2061 [(set_attr "type" "fadd") 2062 (set_attr "trap" "yes") 2063 (set_attr "round_suffix" "c") 2064 (set_attr "trap_suffix" "v_sv_svi") 2065 (set (attr "enabled") 2066 (cond [(eq_attr "alternative" "0") 2067 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2068 ] 2069 (symbol_ref "true")))]) 2070 2071 (define_expand "fix_truncsfdi2" 2072 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2073 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2074 "TARGET_FP") 2075 2076 (define_expand "fixuns_truncsfdi2" 2077 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2078 (unsigned_fix:DI 2079 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2080 "TARGET_FP") 2081 2082 (define_expand "fix_trunctfdi2" 2083 [(use (match_operand:DI 0 "register_operand")) 2084 (use (match_operand:TF 1 "general_operand"))] 2085 "TARGET_HAS_XFLOATING_LIBS" 2086 "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2087 2088 (define_expand "fixuns_trunctfdi2" 2089 [(use (match_operand:DI 0 "register_operand")) 2090 (use (match_operand:TF 1 "general_operand"))] 2091 "TARGET_HAS_XFLOATING_LIBS" 2092 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2093 2094 (define_insn "floatdisf2" 2095 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2096 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2097 "TARGET_FP" 2098 "cvtq%,%/ %1,%0" 2099 [(set_attr "type" "fadd") 2100 (set_attr "trap" "yes") 2101 (set_attr "round_suffix" "normal") 2102 (set_attr "trap_suffix" "sui") 2103 (set (attr "enabled") 2104 (cond [(eq_attr "alternative" "0") 2105 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2106 ] 2107 (symbol_ref "true")))]) 2108 2109 (define_insn_and_split "*floatsisf2_ieee" 2110 [(set (match_operand:SF 0 "register_operand" "=&f") 2111 (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2112 (clobber (match_scratch:DI 2 "=&f")) 2113 (clobber (match_scratch:SF 3 "=&f"))] 2114 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2115 "#" 2116 "&& reload_completed" 2117 [(set (match_dup 3) (match_dup 1)) 2118 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2119 (set (match_dup 0) (float:SF (match_dup 2)))] 2120 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2121 2122 (define_insn_and_split "*floatsisf2" 2123 [(set (match_operand:SF 0 "register_operand" "=f") 2124 (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2125 "TARGET_FP" 2126 "#" 2127 "&& reload_completed" 2128 [(set (match_dup 0) (match_dup 1)) 2129 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2130 (set (match_dup 0) (float:SF (match_dup 2)))] 2131 { 2132 operands[1] = adjust_address (operands[1], SFmode, 0); 2133 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2134 }) 2135 2136 (define_insn "floatdidf2" 2137 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2138 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2139 "TARGET_FP" 2140 "cvtq%-%/ %1,%0" 2141 [(set_attr "type" "fadd") 2142 (set_attr "trap" "yes") 2143 (set_attr "round_suffix" "normal") 2144 (set_attr "trap_suffix" "sui") 2145 (set (attr "enabled") 2146 (cond [(eq_attr "alternative" "0") 2147 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2148 ] 2149 (symbol_ref "true")))]) 2150 2151 (define_insn_and_split "*floatsidf2_ieee" 2152 [(set (match_operand:DF 0 "register_operand" "=&f") 2153 (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2154 (clobber (match_scratch:DI 2 "=&f")) 2155 (clobber (match_scratch:SF 3 "=&f"))] 2156 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2157 "#" 2158 "&& reload_completed" 2159 [(set (match_dup 3) (match_dup 1)) 2160 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2161 (set (match_dup 0) (float:DF (match_dup 2)))] 2162 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2163 2164 (define_insn_and_split "*floatsidf2" 2165 [(set (match_operand:DF 0 "register_operand" "=f") 2166 (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2167 "TARGET_FP" 2168 "#" 2169 "&& reload_completed" 2170 [(set (match_dup 3) (match_dup 1)) 2171 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2172 (set (match_dup 0) (float:DF (match_dup 2)))] 2173 { 2174 operands[1] = adjust_address (operands[1], SFmode, 0); 2175 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2176 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2177 }) 2178 2179 (define_expand "floatditf2" 2180 [(use (match_operand:TF 0 "register_operand")) 2181 (use (match_operand:DI 1 "general_operand"))] 2182 "TARGET_HAS_XFLOATING_LIBS" 2183 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2184 2185 (define_expand "floatunsdisf2" 2186 [(use (match_operand:SF 0 "register_operand")) 2187 (use (match_operand:DI 1 "register_operand"))] 2188 "TARGET_FP" 2189 "alpha_emit_floatuns (operands); DONE;") 2190 2191 (define_expand "floatunsdidf2" 2192 [(use (match_operand:DF 0 "register_operand")) 2193 (use (match_operand:DI 1 "register_operand"))] 2194 "TARGET_FP" 2195 "alpha_emit_floatuns (operands); DONE;") 2196 2197 (define_expand "floatunsditf2" 2198 [(use (match_operand:TF 0 "register_operand")) 2199 (use (match_operand:DI 1 "general_operand"))] 2200 "TARGET_HAS_XFLOATING_LIBS" 2201 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2202 2203 (define_expand "extendsfdf2" 2204 [(set (match_operand:DF 0 "register_operand") 2205 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2206 "TARGET_FP" 2207 { 2208 if (alpha_fptm >= ALPHA_FPTM_SU) 2209 operands[1] = force_reg (SFmode, operands[1]); 2210 }) 2211 2212 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2213 ;; asserted that alpha_fptm == ALPHA_FPTM_N. 2214 2215 (define_insn "*extendsfdf2_ieee" 2216 [(set (match_operand:DF 0 "register_operand" "=&f") 2217 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2218 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2219 "cvtsts %1,%0" 2220 [(set_attr "type" "fadd") 2221 (set_attr "trap" "yes")]) 2222 2223 (define_insn "*extendsfdf2_internal" 2224 [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2225 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2226 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2227 "@ 2228 cpys %1,%1,%0 2229 ld%, %0,%1 2230 st%- %1,%0" 2231 [(set_attr "type" "fcpys,fld,fst")]) 2232 2233 ;; Use register_operand for operand 1 to prevent compress_float_constant 2234 ;; from doing something silly. When optimizing we'll put things back 2235 ;; together anyway. 2236 (define_expand "extendsftf2" 2237 [(use (match_operand:TF 0 "register_operand")) 2238 (use (match_operand:SF 1 "register_operand"))] 2239 "TARGET_HAS_XFLOATING_LIBS" 2240 { 2241 rtx tmp = gen_reg_rtx (DFmode); 2242 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2243 emit_insn (gen_extenddftf2 (operands[0], tmp)); 2244 DONE; 2245 }) 2246 2247 (define_expand "extenddftf2" 2248 [(use (match_operand:TF 0 "register_operand")) 2249 (use (match_operand:DF 1 "register_operand"))] 2250 "TARGET_HAS_XFLOATING_LIBS" 2251 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2252 2253 (define_insn "truncdfsf2" 2254 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2255 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))] 2256 "TARGET_FP" 2257 "cvt%-%,%/ %R1,%0" 2258 [(set_attr "type" "fadd") 2259 (set_attr "trap" "yes") 2260 (set_attr "round_suffix" "normal") 2261 (set_attr "trap_suffix" "u_su_sui") 2262 (set (attr "enabled") 2263 (cond [(eq_attr "alternative" "0") 2264 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2265 ] 2266 (symbol_ref "true")))]) 2267 2268 (define_expand "trunctfdf2" 2269 [(use (match_operand:DF 0 "register_operand")) 2270 (use (match_operand:TF 1 "general_operand"))] 2271 "TARGET_HAS_XFLOATING_LIBS" 2272 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2273 2274 (define_expand "trunctfsf2" 2275 [(use (match_operand:SF 0 "register_operand")) 2276 (use (match_operand:TF 1 "general_operand"))] 2277 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2278 { 2279 rtx tmpf, sticky, arg, lo, hi; 2280 2281 tmpf = gen_reg_rtx (DFmode); 2282 sticky = gen_reg_rtx (DImode); 2283 arg = copy_to_mode_reg (TFmode, operands[1]); 2284 lo = gen_lowpart (DImode, arg); 2285 hi = gen_highpart (DImode, arg); 2286 2287 /* Convert the low word of the TFmode value into a sticky rounding bit, 2288 then or it into the low bit of the high word. This leaves the sticky 2289 bit at bit 48 of the fraction, which is representable in DFmode, 2290 which prevents rounding error in the final conversion to SFmode. */ 2291 2292 emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx))); 2293 emit_insn (gen_iordi3 (hi, hi, sticky)); 2294 emit_insn (gen_trunctfdf2 (tmpf, arg)); 2295 emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2296 DONE; 2297 }) 2298 2300 ;; Next are all the integer comparisons, and conditional moves and branches 2301 ;; and some of the related define_expand's and define_split's. 2302 2303 (define_insn "*setcc_internal" 2304 [(set (match_operand 0 "register_operand" "=r") 2305 (match_operator 1 "alpha_comparison_operator" 2306 [(match_operand:DI 2 "register_operand" "r") 2307 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2308 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2309 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2310 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2311 "cmp%C1 %2,%3,%0" 2312 [(set_attr "type" "icmp")]) 2313 2314 ;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2315 ;; but that's non-canonical rtl and allowing that causes inefficiencies 2316 ;; from cse on. 2317 (define_insn "*setcc_swapped_internal" 2318 [(set (match_operand 0 "register_operand" "=r") 2319 (match_operator 1 "alpha_swapped_comparison_operator" 2320 [(match_operand:DI 2 "register_operand" "r") 2321 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2322 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2323 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2324 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2325 "cmp%c1 %r3,%2,%0" 2326 [(set_attr "type" "icmp")]) 2327 2328 ;; Use match_operator rather than ne directly so that we can match 2329 ;; multiple integer modes. 2330 (define_insn "*setne_internal" 2331 [(set (match_operand 0 "register_operand" "=r") 2332 (match_operator 1 "signed_comparison_operator" 2333 [(match_operand:DI 2 "register_operand" "r") 2334 (const_int 0)]))] 2335 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2336 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2337 && GET_CODE (operands[1]) == NE 2338 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2339 "cmpult $31,%2,%0" 2340 [(set_attr "type" "icmp")]) 2341 2342 ;; The mode folding trick can't be used with const_int operands, since 2343 ;; reload needs to know the proper mode. 2344 ;; 2345 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2346 ;; in order to create more pairs of constants. As long as we're allowing 2347 ;; two constants at the same time, and will have to reload one of them... 2348 2349 (define_insn "*mov<mode>cc_internal" 2350 [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2351 (if_then_else:IMODE 2352 (match_operator 2 "signed_comparison_operator" 2353 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2354 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2355 (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2356 (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2357 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2358 "@ 2359 cmov%C2 %r3,%1,%0 2360 cmov%D2 %r3,%5,%0 2361 cmov%c2 %r4,%1,%0 2362 cmov%d2 %r4,%5,%0" 2363 [(set_attr "type" "icmov")]) 2364 2365 (define_insn "*mov<mode>cc_lbc" 2366 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2367 (if_then_else:IMODE 2368 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2369 (const_int 1) 2370 (const_int 0)) 2371 (const_int 0)) 2372 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2373 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2374 "" 2375 "@ 2376 cmovlbc %r2,%1,%0 2377 cmovlbs %r2,%3,%0" 2378 [(set_attr "type" "icmov")]) 2379 2380 (define_insn "*mov<mode>cc_lbs" 2381 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2382 (if_then_else:IMODE 2383 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2384 (const_int 1) 2385 (const_int 0)) 2386 (const_int 0)) 2387 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2388 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2389 "" 2390 "@ 2391 cmovlbs %r2,%1,%0 2392 cmovlbc %r2,%3,%0" 2393 [(set_attr "type" "icmov")]) 2394 2395 ;; For ABS, we have two choices, depending on whether the input and output 2396 ;; registers are the same or not. 2397 (define_expand "absdi2" 2398 [(set (match_operand:DI 0 "register_operand") 2399 (abs:DI (match_operand:DI 1 "register_operand")))] 2400 "" 2401 { 2402 if (rtx_equal_p (operands[0], operands[1])) 2403 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2404 else 2405 emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2406 DONE; 2407 }) 2408 2409 (define_expand "absdi2_same" 2410 [(set (match_operand:DI 1 "register_operand") 2411 (neg:DI (match_operand:DI 0 "register_operand"))) 2412 (set (match_dup 0) 2413 (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2414 (match_dup 0) 2415 (match_dup 1)))]) 2416 2417 (define_expand "absdi2_diff" 2418 [(set (match_operand:DI 0 "register_operand") 2419 (neg:DI (match_operand:DI 1 "register_operand"))) 2420 (set (match_dup 0) 2421 (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2422 (match_dup 0) 2423 (match_dup 1)))]) 2424 2425 (define_split 2426 [(set (match_operand:DI 0 "register_operand") 2427 (abs:DI (match_dup 0))) 2428 (clobber (match_operand:DI 1 "register_operand"))] 2429 "" 2430 [(set (match_dup 1) (neg:DI (match_dup 0))) 2431 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2432 (match_dup 0) (match_dup 1)))]) 2433 2434 (define_split 2435 [(set (match_operand:DI 0 "register_operand") 2436 (abs:DI (match_operand:DI 1 "register_operand")))] 2437 "! rtx_equal_p (operands[0], operands[1])" 2438 [(set (match_dup 0) (neg:DI (match_dup 1))) 2439 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2440 (match_dup 0) (match_dup 1)))]) 2441 2442 (define_split 2443 [(set (match_operand:DI 0 "register_operand") 2444 (neg:DI (abs:DI (match_dup 0)))) 2445 (clobber (match_operand:DI 1 "register_operand"))] 2446 "" 2447 [(set (match_dup 1) (neg:DI (match_dup 0))) 2448 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2449 (match_dup 0) (match_dup 1)))]) 2450 2451 (define_split 2452 [(set (match_operand:DI 0 "register_operand") 2453 (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2454 "! rtx_equal_p (operands[0], operands[1])" 2455 [(set (match_dup 0) (neg:DI (match_dup 1))) 2456 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2457 (match_dup 0) (match_dup 1)))]) 2458 2459 (define_insn "<code><mode>3" 2460 [(set (match_operand:I12MODE 0 "register_operand" "=r") 2461 (any_maxmin:I12MODE 2462 (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2463 (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2464 "TARGET_MAX" 2465 "<maxmin><vecmodesuffix> %r1,%2,%0" 2466 [(set_attr "type" "mvi")]) 2467 2468 (define_expand "smaxdi3" 2469 [(set (match_dup 3) 2470 (le:DI (match_operand:DI 1 "reg_or_0_operand") 2471 (match_operand:DI 2 "reg_or_8bit_operand"))) 2472 (set (match_operand:DI 0 "register_operand") 2473 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2474 (match_dup 1) (match_dup 2)))] 2475 "" 2476 "operands[3] = gen_reg_rtx (DImode);") 2477 2478 (define_split 2479 [(set (match_operand:DI 0 "register_operand") 2480 (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2481 (match_operand:DI 2 "reg_or_8bit_operand"))) 2482 (clobber (match_operand:DI 3 "register_operand"))] 2483 "operands[2] != const0_rtx" 2484 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2485 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2486 (match_dup 1) (match_dup 2)))]) 2487 2488 (define_insn "*smax_const0" 2489 [(set (match_operand:DI 0 "register_operand" "=r") 2490 (smax:DI (match_operand:DI 1 "register_operand" "0") 2491 (const_int 0)))] 2492 "" 2493 "cmovlt %0,0,%0" 2494 [(set_attr "type" "icmov")]) 2495 2496 (define_expand "smindi3" 2497 [(set (match_dup 3) 2498 (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2499 (match_operand:DI 2 "reg_or_8bit_operand"))) 2500 (set (match_operand:DI 0 "register_operand") 2501 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2502 (match_dup 1) (match_dup 2)))] 2503 "" 2504 "operands[3] = gen_reg_rtx (DImode);") 2505 2506 (define_split 2507 [(set (match_operand:DI 0 "register_operand") 2508 (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2509 (match_operand:DI 2 "reg_or_8bit_operand"))) 2510 (clobber (match_operand:DI 3 "register_operand"))] 2511 "operands[2] != const0_rtx" 2512 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2513 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2514 (match_dup 1) (match_dup 2)))]) 2515 2516 (define_insn "*smin_const0" 2517 [(set (match_operand:DI 0 "register_operand" "=r") 2518 (smin:DI (match_operand:DI 1 "register_operand" "0") 2519 (const_int 0)))] 2520 "" 2521 "cmovgt %0,0,%0" 2522 [(set_attr "type" "icmov")]) 2523 2524 (define_expand "umaxdi3" 2525 [(set (match_dup 3) 2526 (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2527 (match_operand:DI 2 "reg_or_8bit_operand"))) 2528 (set (match_operand:DI 0 "register_operand") 2529 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2530 (match_dup 1) (match_dup 2)))] 2531 "" 2532 "operands[3] = gen_reg_rtx (DImode);") 2533 2534 (define_split 2535 [(set (match_operand:DI 0 "register_operand") 2536 (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2537 (match_operand:DI 2 "reg_or_8bit_operand"))) 2538 (clobber (match_operand:DI 3 "register_operand"))] 2539 "operands[2] != const0_rtx" 2540 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2541 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2542 (match_dup 1) (match_dup 2)))]) 2543 2544 (define_expand "umindi3" 2545 [(set (match_dup 3) 2546 (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2547 (match_operand:DI 2 "reg_or_8bit_operand"))) 2548 (set (match_operand:DI 0 "register_operand") 2549 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2550 (match_dup 1) (match_dup 2)))] 2551 "" 2552 "operands[3] = gen_reg_rtx (DImode);") 2553 2554 (define_split 2555 [(set (match_operand:DI 0 "register_operand") 2556 (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2557 (match_operand:DI 2 "reg_or_8bit_operand"))) 2558 (clobber (match_operand:DI 3 "register_operand"))] 2559 "operands[2] != const0_rtx" 2560 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2561 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2562 (match_dup 1) (match_dup 2)))]) 2563 2564 (define_insn "*bcc_normal" 2565 [(set (pc) 2566 (if_then_else 2567 (match_operator 1 "signed_comparison_operator" 2568 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2569 (const_int 0)]) 2570 (label_ref (match_operand 0)) 2571 (pc)))] 2572 "" 2573 "b%C1 %r2,%0" 2574 [(set_attr "type" "ibr")]) 2575 2576 (define_insn "*bcc_reverse" 2577 [(set (pc) 2578 (if_then_else 2579 (match_operator 1 "signed_comparison_operator" 2580 [(match_operand:DI 2 "register_operand" "r") 2581 (const_int 0)]) 2582 2583 (pc) 2584 (label_ref (match_operand 0))))] 2585 "" 2586 "b%c1 %2,%0" 2587 [(set_attr "type" "ibr")]) 2588 2589 (define_insn "*blbs_normal" 2590 [(set (pc) 2591 (if_then_else 2592 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2593 (const_int 1) 2594 (const_int 0)) 2595 (const_int 0)) 2596 (label_ref (match_operand 0)) 2597 (pc)))] 2598 "" 2599 "blbs %r1,%0" 2600 [(set_attr "type" "ibr")]) 2601 2602 (define_insn "*blbc_normal" 2603 [(set (pc) 2604 (if_then_else 2605 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2606 (const_int 1) 2607 (const_int 0)) 2608 (const_int 0)) 2609 (label_ref (match_operand 0)) 2610 (pc)))] 2611 "" 2612 "blbc %r1,%0" 2613 [(set_attr "type" "ibr")]) 2614 2615 (define_split 2616 [(parallel 2617 [(set (pc) 2618 (if_then_else 2619 (match_operator 1 "comparison_operator" 2620 [(zero_extract:DI (match_operand:DI 2 "register_operand") 2621 (const_int 1) 2622 (match_operand:DI 3 "const_int_operand")) 2623 (const_int 0)]) 2624 (label_ref (match_operand 0)) 2625 (pc))) 2626 (clobber (match_operand:DI 4 "register_operand"))])] 2627 "INTVAL (operands[3]) != 0" 2628 [(set (match_dup 4) 2629 (lshiftrt:DI (match_dup 2) (match_dup 3))) 2630 (set (pc) 2631 (if_then_else (match_op_dup 1 2632 [(zero_extract:DI (match_dup 4) 2633 (const_int 1) 2634 (const_int 0)) 2635 (const_int 0)]) 2636 (label_ref (match_dup 0)) 2637 (pc)))] 2638 ) 2639 2641 ;; The following are the corresponding floating-point insns. Recall 2642 ;; we need to have variants that expand the arguments from SFmode 2643 ;; to DFmode. 2644 2645 (define_insn "*cmpdf_internal" 2646 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2647 (match_operator:DF 1 "alpha_fp_comparison_operator" 2648 [(match_operand:DF 2 "reg_or_0_operand" "fG,fG") 2649 (match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))] 2650 "TARGET_FP" 2651 "cmp%-%C1%/ %R2,%R3,%0" 2652 [(set_attr "type" "fadd") 2653 (set_attr "trap" "yes") 2654 (set_attr "trap_suffix" "su") 2655 (set (attr "enabled") 2656 (cond [(eq_attr "alternative" "0") 2657 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2658 ] 2659 (symbol_ref "true")))]) 2660 2661 (define_insn "*cmpdf_ext1" 2662 [(set (match_operand:DF 0 "register_operand" "=f") 2663 (match_operator:DF 1 "alpha_fp_comparison_operator" 2664 [(float_extend:DF 2665 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2666 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2667 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2668 "cmp%-%C1%/ %R2,%R3,%0" 2669 [(set_attr "type" "fadd") 2670 (set_attr "trap" "yes") 2671 (set_attr "trap_suffix" "su")]) 2672 2673 (define_insn "*cmpdf_ext2" 2674 [(set (match_operand:DF 0 "register_operand" "=f") 2675 (match_operator:DF 1 "alpha_fp_comparison_operator" 2676 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2677 (float_extend:DF 2678 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2679 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2680 "cmp%-%C1%/ %R2,%R3,%0" 2681 [(set_attr "type" "fadd") 2682 (set_attr "trap" "yes") 2683 (set_attr "trap_suffix" "su")]) 2684 2685 (define_insn "*cmpdf_ext3" 2686 [(set (match_operand:DF 0 "register_operand" "=f") 2687 (match_operator:DF 1 "alpha_fp_comparison_operator" 2688 [(float_extend:DF 2689 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2690 (float_extend:DF 2691 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2692 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2693 "cmp%-%C1%/ %R2,%R3,%0" 2694 [(set_attr "type" "fadd") 2695 (set_attr "trap" "yes") 2696 (set_attr "trap_suffix" "su")]) 2697 2698 (define_insn "*mov<mode>cc_internal" 2699 [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2700 (if_then_else:FMODE 2701 (match_operator 3 "signed_comparison_operator" 2702 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2703 (match_operand:DF 2 "const0_operand" "G,G")]) 2704 (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2705 (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2706 "TARGET_FP" 2707 "@ 2708 fcmov%C3 %R4,%R1,%0 2709 fcmov%D3 %R4,%R5,%0" 2710 [(set_attr "type" "fcmov")]) 2711 2712 (define_insn "*movdfcc_ext1" 2713 [(set (match_operand:DF 0 "register_operand" "=f,f") 2714 (if_then_else:DF 2715 (match_operator 3 "signed_comparison_operator" 2716 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2717 (match_operand:DF 2 "const0_operand" "G,G")]) 2718 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2719 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2720 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2721 "@ 2722 fcmov%C3 %R4,%R1,%0 2723 fcmov%D3 %R4,%R5,%0" 2724 [(set_attr "type" "fcmov")]) 2725 2726 (define_insn "*movdfcc_ext2" 2727 [(set (match_operand:DF 0 "register_operand" "=f,f") 2728 (if_then_else:DF 2729 (match_operator 3 "signed_comparison_operator" 2730 [(float_extend:DF 2731 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2732 (match_operand:DF 2 "const0_operand" "G,G")]) 2733 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2734 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2735 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2736 "@ 2737 fcmov%C3 %R4,%R1,%0 2738 fcmov%D3 %R4,%R5,%0" 2739 [(set_attr "type" "fcmov")]) 2740 2741 (define_insn "*movdfcc_ext3" 2742 [(set (match_operand:SF 0 "register_operand" "=f,f") 2743 (if_then_else:SF 2744 (match_operator 3 "signed_comparison_operator" 2745 [(float_extend:DF 2746 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2747 (match_operand:DF 2 "const0_operand" "G,G")]) 2748 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2749 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2750 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2751 "@ 2752 fcmov%C3 %R4,%R1,%0 2753 fcmov%D3 %R4,%R5,%0" 2754 [(set_attr "type" "fcmov")]) 2755 2756 (define_insn "*movdfcc_ext4" 2757 [(set (match_operand:DF 0 "register_operand" "=f,f") 2758 (if_then_else:DF 2759 (match_operator 3 "signed_comparison_operator" 2760 [(float_extend:DF 2761 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2762 (match_operand:DF 2 "const0_operand" "G,G")]) 2763 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2764 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2765 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2766 "@ 2767 fcmov%C3 %R4,%R1,%0 2768 fcmov%D3 %R4,%R5,%0" 2769 [(set_attr "type" "fcmov")]) 2770 2771 (define_expand "smaxdf3" 2772 [(set (match_dup 3) 2773 (le:DF (match_operand:DF 1 "reg_or_0_operand") 2774 (match_operand:DF 2 "reg_or_0_operand"))) 2775 (set (match_operand:DF 0 "register_operand") 2776 (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2777 (match_dup 1) (match_dup 2)))] 2778 "TARGET_FP" 2779 { 2780 operands[3] = gen_reg_rtx (DFmode); 2781 operands[4] = CONST0_RTX (DFmode); 2782 }) 2783 2784 (define_expand "smindf3" 2785 [(set (match_dup 3) 2786 (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2787 (match_operand:DF 2 "reg_or_0_operand"))) 2788 (set (match_operand:DF 0 "register_operand") 2789 (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2790 (match_dup 1) (match_dup 2)))] 2791 "TARGET_FP" 2792 { 2793 operands[3] = gen_reg_rtx (DFmode); 2794 operands[4] = CONST0_RTX (DFmode); 2795 }) 2796 2797 (define_expand "smaxsf3" 2798 [(set (match_dup 3) 2799 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2800 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2801 (set (match_operand:SF 0 "register_operand") 2802 (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2803 (match_dup 1) (match_dup 2)))] 2804 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2805 { 2806 operands[3] = gen_reg_rtx (DFmode); 2807 operands[4] = CONST0_RTX (DFmode); 2808 }) 2809 2810 (define_expand "sminsf3" 2811 [(set (match_dup 3) 2812 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2813 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2814 (set (match_operand:SF 0 "register_operand") 2815 (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2816 (match_dup 1) (match_dup 2)))] 2817 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2818 { 2819 operands[3] = gen_reg_rtx (DFmode); 2820 operands[4] = CONST0_RTX (DFmode); 2821 }) 2822 2823 (define_insn "*fbcc_normal" 2824 [(set (pc) 2825 (if_then_else 2826 (match_operator 1 "signed_comparison_operator" 2827 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2828 (match_operand:DF 3 "const0_operand" "G")]) 2829 (label_ref (match_operand 0)) 2830 (pc)))] 2831 "TARGET_FP" 2832 "fb%C1 %R2,%0" 2833 [(set_attr "type" "fbr")]) 2834 2835 (define_insn "*fbcc_ext_normal" 2836 [(set (pc) 2837 (if_then_else 2838 (match_operator 1 "signed_comparison_operator" 2839 [(float_extend:DF 2840 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2841 (match_operand:DF 3 "const0_operand" "G")]) 2842 (label_ref (match_operand 0)) 2843 (pc)))] 2844 "TARGET_FP" 2845 "fb%C1 %R2,%0" 2846 [(set_attr "type" "fbr")]) 2847 2849 ;; These are the main define_expand's used to make conditional branches 2850 ;; and compares. 2851 2852 (define_expand "cbranchdf4" 2853 [(use (match_operator 0 "alpha_cbranch_operator" 2854 [(match_operand:DF 1 "reg_or_0_operand") 2855 (match_operand:DF 2 "reg_or_0_operand")])) 2856 (use (match_operand 3))] 2857 "TARGET_FP" 2858 "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2859 2860 (define_expand "cbranchtf4" 2861 [(use (match_operator 0 "alpha_cbranch_operator" 2862 [(match_operand:TF 1 "general_operand") 2863 (match_operand:TF 2 "general_operand")])) 2864 (use (match_operand 3))] 2865 "TARGET_HAS_XFLOATING_LIBS" 2866 "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2867 2868 (define_expand "cbranchdi4" 2869 [(use (match_operator 0 "alpha_cbranch_operator" 2870 [(match_operand:DI 1 "general_operand") 2871 (match_operand:DI 2 "general_operand")])) 2872 (use (match_operand 3))] 2873 "" 2874 "alpha_emit_conditional_branch (operands, DImode); DONE;") 2875 2876 (define_expand "cstoredf4" 2877 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2878 [(match_operand:DF 2 "reg_or_0_operand") 2879 (match_operand:DF 3 "reg_or_0_operand")])) 2880 (clobber (match_operand:DI 0 "register_operand"))] 2881 "TARGET_FP" 2882 { 2883 if (alpha_emit_setcc (operands, DFmode)) 2884 DONE; 2885 else 2886 FAIL; 2887 }) 2888 2889 (define_expand "cstoretf4" 2890 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2891 [(match_operand:TF 2 "general_operand") 2892 (match_operand:TF 3 "general_operand")])) 2893 (clobber (match_operand:DI 0 "register_operand"))] 2894 "TARGET_HAS_XFLOATING_LIBS" 2895 { 2896 if (alpha_emit_setcc (operands, TFmode)) 2897 DONE; 2898 else 2899 FAIL; 2900 }) 2901 2902 (define_expand "cstoredi4" 2903 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2904 [(match_operand:DI 2 "general_operand") 2905 (match_operand:DI 3 "general_operand")])) 2906 (clobber (match_operand:DI 0 "register_operand"))] 2907 "" 2908 { 2909 if (alpha_emit_setcc (operands, DImode)) 2910 DONE; 2911 else 2912 FAIL; 2913 }) 2914 2916 ;; These are the main define_expand's used to make conditional moves. 2917 2918 (define_expand "mov<mode>cc" 2919 [(set (match_operand:I48MODE 0 "register_operand") 2920 (if_then_else:I48MODE 2921 (match_operand 1 "comparison_operator") 2922 (match_operand:I48MODE 2 "reg_or_8bit_operand") 2923 (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2924 "" 2925 { 2926 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2927 if (operands[1] == 0) 2928 FAIL; 2929 }) 2930 2931 (define_expand "mov<mode>cc" 2932 [(set (match_operand:FMODE 0 "register_operand") 2933 (if_then_else:FMODE 2934 (match_operand 1 "comparison_operator") 2935 (match_operand:FMODE 2 "reg_or_8bit_operand") 2936 (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2937 "" 2938 { 2939 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2940 if (operands[1] == 0) 2941 FAIL; 2942 }) 2943 2945 ;; These define_split definitions are used in cases when comparisons have 2946 ;; not be stated in the correct way and we need to reverse the second 2947 ;; comparison. For example, x >= 7 has to be done as x < 6 with the 2948 ;; comparison that tests the result being reversed. We have one define_split 2949 ;; for each use of a comparison. They do not match valid insns and need 2950 ;; not generate valid insns. 2951 ;; 2952 ;; We can also handle equality comparisons (and inequality comparisons in 2953 ;; cases where the resulting add cannot overflow) by doing an add followed by 2954 ;; a comparison with zero. This is faster since the addition takes one 2955 ;; less cycle than a compare when feeding into a conditional move. 2956 ;; For this case, we also have an SImode pattern since we can merge the add 2957 ;; and sign extend and the order doesn't matter. 2958 ;; 2959 ;; We do not do this for floating-point, since it isn't clear how the "wrong" 2960 ;; operation could have been generated. 2961 2962 (define_split 2963 [(set (match_operand:DI 0 "register_operand") 2964 (if_then_else:DI 2965 (match_operator 1 "comparison_operator" 2966 [(match_operand:DI 2 "reg_or_0_operand") 2967 (match_operand:DI 3 "reg_or_cint_operand")]) 2968 (match_operand:DI 4 "reg_or_cint_operand") 2969 (match_operand:DI 5 "reg_or_cint_operand"))) 2970 (clobber (match_operand:DI 6 "register_operand"))] 2971 "operands[3] != const0_rtx" 2972 [(set (match_dup 6) (match_dup 7)) 2973 (set (match_dup 0) 2974 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 2975 { 2976 enum rtx_code code = GET_CODE (operands[1]); 2977 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2978 2979 /* If we are comparing for equality with a constant and that constant 2980 appears in the arm when the register equals the constant, use the 2981 register since that is more likely to match (and to produce better code 2982 if both would). */ 2983 2984 if (code == EQ && CONST_INT_P (operands[3]) 2985 && rtx_equal_p (operands[4], operands[3])) 2986 operands[4] = operands[2]; 2987 2988 else if (code == NE && CONST_INT_P (operands[3]) 2989 && rtx_equal_p (operands[5], operands[3])) 2990 operands[5] = operands[2]; 2991 2992 if (code == NE || code == EQ 2993 || (extended_count (operands[2], DImode, unsignedp) >= 1 2994 && extended_count (operands[3], DImode, unsignedp) >= 1)) 2995 { 2996 if (CONST_INT_P (operands[3])) 2997 operands[7] = gen_rtx_PLUS (DImode, operands[2], 2998 GEN_INT (- INTVAL (operands[3]))); 2999 else 3000 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 3001 3002 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 3003 } 3004 3005 else if (code == EQ || code == LE || code == LT 3006 || code == LEU || code == LTU) 3007 { 3008 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 3009 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 3010 } 3011 else 3012 { 3013 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 3014 operands[2], operands[3]); 3015 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 3016 } 3017 }) 3018 3019 (define_split 3020 [(set (match_operand:DI 0 "register_operand") 3021 (if_then_else:DI 3022 (match_operator 1 "comparison_operator" 3023 [(match_operand:SI 2 "reg_or_0_operand") 3024 (match_operand:SI 3 "reg_or_cint_operand")]) 3025 (match_operand:DI 4 "reg_or_8bit_operand") 3026 (match_operand:DI 5 "reg_or_8bit_operand"))) 3027 (clobber (match_operand:DI 6 "register_operand"))] 3028 "operands[3] != const0_rtx 3029 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3030 [(set (match_dup 6) (match_dup 7)) 3031 (set (match_dup 0) 3032 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3033 { 3034 enum rtx_code code = GET_CODE (operands[1]); 3035 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3036 rtx tem; 3037 3038 if ((code != NE && code != EQ 3039 && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3040 && extended_count (operands[3], DImode, unsignedp) >= 1))) 3041 FAIL; 3042 3043 if (CONST_INT_P (operands[3])) 3044 tem = gen_rtx_PLUS (SImode, operands[2], 3045 GEN_INT (- INTVAL (operands[3]))); 3046 else 3047 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3048 3049 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3050 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3051 operands[6], const0_rtx); 3052 }) 3053 3054 ;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3055 3056 (define_split 3057 [(set (match_operand 0 "register_operand") 3058 (if_then_else (match_operator 1 "signed_comparison_operator" 3059 [(match_operand:DI 2 "reg_or_0_operand") 3060 (const_int 0)]) 3061 (match_operand 3 "const_int_operand") 3062 (match_operand 4 "const_int_operand")))] 3063 "" 3064 [(const_int 0)] 3065 { 3066 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3067 operands[2], operands[3], operands[4])) 3068 DONE; 3069 else 3070 FAIL; 3071 }) 3072 3073 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3074 ;; Oh well, we match it in movcc, so it must be partially our fault. 3075 (define_split 3076 [(set (match_operand 0 "register_operand") 3077 (if_then_else (match_operator 1 "signed_comparison_operator" 3078 [(const_int 0) 3079 (match_operand:DI 2 "reg_or_0_operand")]) 3080 (match_operand 3 "const_int_operand") 3081 (match_operand 4 "const_int_operand")))] 3082 "" 3083 [(const_int 0)] 3084 { 3085 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3086 operands[0], operands[2], operands[3], 3087 operands[4])) 3088 DONE; 3089 else 3090 FAIL; 3091 }) 3092 3093 (define_insn_and_split "*cmp_sadd_di" 3094 [(set (match_operand:DI 0 "register_operand" "=r") 3095 (plus:DI (if_then_else:DI 3096 (match_operator 1 "alpha_zero_comparison_operator" 3097 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3098 (const_int 0)]) 3099 (match_operand:DI 3 "const48_operand" "I") 3100 (const_int 0)) 3101 (match_operand:DI 4 "sext_add_operand" "rIO"))) 3102 (clobber (match_scratch:DI 5 "=r"))] 3103 "" 3104 "#" 3105 "" 3106 [(set (match_dup 5) 3107 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3108 (set (match_dup 0) 3109 (plus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3110 (match_dup 4)))] 3111 { 3112 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3113 if (can_create_pseudo_p ()) 3114 operands[5] = gen_reg_rtx (DImode); 3115 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3116 operands[5] = operands[0]; 3117 }) 3118 3119 (define_insn_and_split "*cmp_sadd_si" 3120 [(set (match_operand:SI 0 "register_operand" "=r") 3121 (plus:SI (if_then_else:SI 3122 (match_operator 1 "alpha_zero_comparison_operator" 3123 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3124 (const_int 0)]) 3125 (match_operand:SI 3 "const48_operand" "I") 3126 (const_int 0)) 3127 (match_operand:SI 4 "sext_add_operand" "rIO"))) 3128 (clobber (match_scratch:DI 5 "=r"))] 3129 "" 3130 "#" 3131 "" 3132 [(set (match_dup 5) 3133 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3134 (set (match_dup 0) 3135 (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3136 (match_dup 4)))] 3137 { 3138 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3139 if (can_create_pseudo_p ()) 3140 operands[5] = gen_reg_rtx (DImode); 3141 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3142 operands[5] = gen_lowpart (DImode, operands[0]); 3143 3144 operands[6] = gen_lowpart (SImode, operands[5]); 3145 }) 3146 3147 (define_insn_and_split "*cmp_sadd_sidi" 3148 [(set (match_operand:DI 0 "register_operand" "=r") 3149 (sign_extend:DI 3150 (plus:SI (if_then_else:SI 3151 (match_operator 1 "alpha_zero_comparison_operator" 3152 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3153 (const_int 0)]) 3154 (match_operand:SI 3 "const48_operand" "I") 3155 (const_int 0)) 3156 (match_operand:SI 4 "sext_add_operand" "rIO")))) 3157 (clobber (match_scratch:DI 5 "=r"))] 3158 "" 3159 "#" 3160 "" 3161 [(set (match_dup 5) 3162 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3163 (set (match_dup 0) 3164 (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3165 (match_dup 4))))] 3166 { 3167 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3168 if (can_create_pseudo_p ()) 3169 operands[5] = gen_reg_rtx (DImode); 3170 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3171 operands[5] = operands[0]; 3172 3173 operands[6] = gen_lowpart (SImode, operands[5]); 3174 }) 3175 3176 (define_insn_and_split "*cmp_ssub_di" 3177 [(set (match_operand:DI 0 "register_operand" "=r") 3178 (minus:DI (if_then_else:DI 3179 (match_operator 1 "alpha_zero_comparison_operator" 3180 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3181 (const_int 0)]) 3182 (match_operand:DI 3 "const48_operand" "I") 3183 (const_int 0)) 3184 (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3185 (clobber (match_scratch:DI 5 "=r"))] 3186 "" 3187 "#" 3188 "" 3189 [(set (match_dup 5) 3190 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3191 (set (match_dup 0) 3192 (minus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3193 (match_dup 4)))] 3194 { 3195 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3196 if (can_create_pseudo_p ()) 3197 operands[5] = gen_reg_rtx (DImode); 3198 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3199 operands[5] = operands[0]; 3200 }) 3201 3202 (define_insn_and_split "*cmp_ssub_si" 3203 [(set (match_operand:SI 0 "register_operand" "=r") 3204 (minus:SI (if_then_else:SI 3205 (match_operator 1 "alpha_zero_comparison_operator" 3206 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3207 (const_int 0)]) 3208 (match_operand:SI 3 "const48_operand" "I") 3209 (const_int 0)) 3210 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3211 (clobber (match_scratch:DI 5 "=r"))] 3212 "" 3213 "#" 3214 "" 3215 [(set (match_dup 5) 3216 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3217 (set (match_dup 0) 3218 (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3219 (match_dup 4)))] 3220 { 3221 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3222 if (can_create_pseudo_p ()) 3223 operands[5] = gen_reg_rtx (DImode); 3224 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3225 operands[5] = gen_lowpart (DImode, operands[0]); 3226 3227 operands[6] = gen_lowpart (SImode, operands[5]); 3228 }) 3229 3230 (define_insn_and_split "*cmp_ssub_sidi" 3231 [(set (match_operand:DI 0 "register_operand" "=r") 3232 (sign_extend:DI 3233 (minus:SI (if_then_else:SI 3234 (match_operator 1 "alpha_zero_comparison_operator" 3235 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3236 (const_int 0)]) 3237 (match_operand:SI 3 "const48_operand" "I") 3238 (const_int 0)) 3239 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3240 (clobber (match_scratch:DI 5 "=r"))] 3241 "" 3242 "#" 3243 "" 3244 [(set (match_dup 5) 3245 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3246 (set (match_dup 0) 3247 (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3248 (match_dup 4))))] 3249 { 3250 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3251 if (can_create_pseudo_p ()) 3252 operands[5] = gen_reg_rtx (DImode); 3253 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3254 operands[5] = operands[0]; 3255 3256 operands[6] = gen_lowpart (SImode, operands[5]); 3257 }) 3258 3260 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3261 ;; work differently, so we have different patterns for each. 3262 3263 (define_expand "call" 3264 [(use (match_operand:DI 0)) 3265 (use (match_operand 1)) 3266 (use (match_operand 2)) 3267 (use (match_operand 3))] 3268 "" 3269 { 3270 if (TARGET_ABI_OPEN_VMS) 3271 emit_call_insn (gen_call_vms (operands[0], operands[2])); 3272 else 3273 emit_call_insn (gen_call_osf (operands[0], operands[1])); 3274 DONE; 3275 }) 3276 3277 (define_expand "sibcall" 3278 [(parallel [(call (mem:DI (match_operand 0)) 3279 (match_operand 1)) 3280 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3281 "TARGET_ABI_OSF" 3282 { 3283 gcc_assert (MEM_P (operands[0])); 3284 operands[0] = XEXP (operands[0], 0); 3285 }) 3286 3287 (define_expand "call_osf" 3288 [(parallel [(call (mem:DI (match_operand 0)) 3289 (match_operand 1)) 3290 (use (reg:DI 29)) 3291 (clobber (reg:DI 26))])] 3292 "" 3293 { 3294 gcc_assert (MEM_P (operands[0])); 3295 3296 operands[0] = XEXP (operands[0], 0); 3297 if (! call_operand (operands[0], Pmode)) 3298 operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3299 }) 3300 3301 ;; 3302 ;; call openvms/alpha 3303 ;; op 0: symbol ref for called function 3304 ;; op 1: next_arg_reg (argument information value for R25) 3305 ;; 3306 (define_expand "call_vms" 3307 [(parallel [(call (mem:DI (match_operand 0)) 3308 (match_operand 1)) 3309 (use (match_dup 2)) 3310 (use (reg:DI 25)) 3311 (use (reg:DI 26)) 3312 (clobber (reg:DI 27))])] 3313 "" 3314 { 3315 gcc_assert (MEM_P (operands[0])); 3316 3317 operands[0] = XEXP (operands[0], 0); 3318 3319 /* Always load AI with argument information, then handle symbolic and 3320 indirect call differently. Load RA and set operands[2] to PV in 3321 both cases. */ 3322 3323 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3324 if (GET_CODE (operands[0]) == SYMBOL_REF) 3325 { 3326 operands[2] = const0_rtx; 3327 } 3328 else 3329 { 3330 emit_move_insn (gen_rtx_REG (Pmode, 26), 3331 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3332 operands[0], 8))); 3333 operands[2] = operands[0]; 3334 } 3335 }) 3336 3337 (define_expand "call_value" 3338 [(use (match_operand 0)) 3339 (use (match_operand:DI 1)) 3340 (use (match_operand 2)) 3341 (use (match_operand 3)) 3342 (use (match_operand 4))] 3343 "" 3344 { 3345 if (TARGET_ABI_OPEN_VMS) 3346 emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3347 operands[3])); 3348 else 3349 emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3350 operands[2])); 3351 DONE; 3352 }) 3353 3354 (define_expand "sibcall_value" 3355 [(parallel [(set (match_operand 0) 3356 (call (mem:DI (match_operand 1)) 3357 (match_operand 2))) 3358 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3359 "TARGET_ABI_OSF" 3360 { 3361 gcc_assert (MEM_P (operands[1])); 3362 operands[1] = XEXP (operands[1], 0); 3363 }) 3364 3365 (define_expand "call_value_osf" 3366 [(parallel [(set (match_operand 0) 3367 (call (mem:DI (match_operand 1)) 3368 (match_operand 2))) 3369 (use (reg:DI 29)) 3370 (clobber (reg:DI 26))])] 3371 "" 3372 { 3373 gcc_assert (MEM_P (operands[1])); 3374 3375 operands[1] = XEXP (operands[1], 0); 3376 if (! call_operand (operands[1], Pmode)) 3377 operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3378 }) 3379 3380 (define_expand "call_value_vms" 3381 [(parallel [(set (match_operand 0) 3382 (call (mem:DI (match_operand:DI 1)) 3383 (match_operand 2))) 3384 (use (match_dup 3)) 3385 (use (reg:DI 25)) 3386 (use (reg:DI 26)) 3387 (clobber (reg:DI 27))])] 3388 "" 3389 { 3390 gcc_assert (MEM_P (operands[1])); 3391 3392 operands[1] = XEXP (operands[1], 0); 3393 3394 /* Always load AI with argument information, then handle symbolic and 3395 indirect call differently. Load RA and set operands[3] to PV in 3396 both cases. */ 3397 3398 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3399 if (GET_CODE (operands[1]) == SYMBOL_REF) 3400 { 3401 operands[3] = const0_rtx; 3402 } 3403 else 3404 { 3405 emit_move_insn (gen_rtx_REG (Pmode, 26), 3406 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3407 operands[1], 8))); 3408 operands[3] = operands[1]; 3409 } 3410 }) 3411 3412 (define_insn "*call_osf_1_er_noreturn" 3413 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3414 (match_operand 1)) 3415 (use (reg:DI 29)) 3416 (clobber (reg:DI 26))] 3417 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3418 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3419 "@ 3420 jsr $26,($27),0 3421 bsr $26,%0\t\t!samegp 3422 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3423 [(set_attr "type" "jsr") 3424 (set_attr "length" "*,*,8")]) 3425 3426 (define_insn "*call_osf_1_er" 3427 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3428 (match_operand 1)) 3429 (use (reg:DI 29)) 3430 (clobber (reg:DI 26))] 3431 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3432 "@ 3433 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3434 bsr $26,%0\t\t!samegp 3435 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3436 [(set_attr "type" "jsr") 3437 (set_attr "length" "12,*,16")]) 3438 3439 ;; We must use peep2 instead of a split because we need accurate life 3440 ;; information for $gp. Consider the case of { bar(); while (1); }. 3441 (define_peephole2 3442 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3443 (match_operand 1)) 3444 (use (reg:DI 29)) 3445 (clobber (reg:DI 26))])] 3446 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3447 && ! samegp_function_operand (operands[0], Pmode) 3448 && (peep2_regno_dead_p (1, 29) 3449 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3450 [(parallel [(call (mem:DI (match_dup 2)) 3451 (match_dup 1)) 3452 (use (reg:DI 29)) 3453 (use (match_dup 0)) 3454 (use (match_dup 3)) 3455 (clobber (reg:DI 26))])] 3456 { 3457 if (CONSTANT_P (operands[0])) 3458 { 3459 operands[2] = gen_rtx_REG (Pmode, 27); 3460 operands[3] = GEN_INT (alpha_next_sequence_number++); 3461 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3462 operands[0], operands[3])); 3463 } 3464 else 3465 { 3466 operands[2] = operands[0]; 3467 operands[0] = const0_rtx; 3468 operands[3] = const0_rtx; 3469 } 3470 }) 3471 3472 (define_peephole2 3473 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3474 (match_operand 1)) 3475 (use (reg:DI 29)) 3476 (clobber (reg:DI 26))])] 3477 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3478 && ! samegp_function_operand (operands[0], Pmode) 3479 && ! (peep2_regno_dead_p (1, 29) 3480 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3481 [(parallel [(call (mem:DI (match_dup 2)) 3482 (match_dup 1)) 3483 (set (match_dup 5) 3484 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3485 (use (match_dup 0)) 3486 (use (match_dup 4)) 3487 (clobber (reg:DI 26))]) 3488 (set (match_dup 5) 3489 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3490 { 3491 if (CONSTANT_P (operands[0])) 3492 { 3493 operands[2] = gen_rtx_REG (Pmode, 27); 3494 operands[4] = GEN_INT (alpha_next_sequence_number++); 3495 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3496 operands[0], operands[4])); 3497 } 3498 else 3499 { 3500 operands[2] = operands[0]; 3501 operands[0] = const0_rtx; 3502 operands[4] = const0_rtx; 3503 } 3504 operands[3] = GEN_INT (alpha_next_sequence_number++); 3505 operands[5] = pic_offset_table_rtx; 3506 }) 3507 3508 (define_insn "*call_osf_2_er_nogp" 3509 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3510 (match_operand 1)) 3511 (use (reg:DI 29)) 3512 (use (match_operand 2)) 3513 (use (match_operand 3 "const_int_operand")) 3514 (clobber (reg:DI 26))] 3515 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3516 "jsr $26,(%0),%2%J3" 3517 [(set_attr "type" "jsr")]) 3518 3519 (define_insn "*call_osf_2_er" 3520 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3521 (match_operand 1)) 3522 (set (reg:DI 29) 3523 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3524 UNSPEC_LDGP1)) 3525 (use (match_operand 2)) 3526 (use (match_operand 3 "const_int_operand")) 3527 (clobber (reg:DI 26))] 3528 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3529 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3530 [(set_attr "type" "jsr") 3531 (set_attr "cannot_copy" "true") 3532 (set_attr "length" "8")]) 3533 3534 (define_insn "*call_osf_1_noreturn" 3535 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3536 (match_operand 1)) 3537 (use (reg:DI 29)) 3538 (clobber (reg:DI 26))] 3539 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3540 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3541 "@ 3542 jsr $26,($27),0 3543 bsr $26,$%0..ng 3544 jsr $26,%0" 3545 [(set_attr "type" "jsr") 3546 (set_attr "length" "*,*,8")]) 3547 3548 (define_insn "*call_osf_1" 3549 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3550 (match_operand 1)) 3551 (use (reg:DI 29)) 3552 (clobber (reg:DI 26))] 3553 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3554 "@ 3555 jsr $26,($27),0\;ldgp $29,0($26) 3556 bsr $26,$%0..ng 3557 jsr $26,%0\;ldgp $29,0($26)" 3558 [(set_attr "type" "jsr") 3559 (set_attr "length" "12,*,16")]) 3560 3561 (define_insn "*sibcall_osf_1_er" 3562 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3563 (match_operand 1)) 3564 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3565 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3566 "@ 3567 br $31,%0\t\t!samegp 3568 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3569 [(set_attr "type" "jsr") 3570 (set_attr "length" "*,8")]) 3571 3572 ;; Note that the DEC assembler expands "jmp foo" with $at, which 3573 ;; doesn't do what we want. 3574 (define_insn "*sibcall_osf_1" 3575 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3576 (match_operand 1)) 3577 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3578 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3579 "@ 3580 br $31,$%0..ng 3581 lda $27,%0\;jmp $31,($27),%0" 3582 [(set_attr "type" "jsr") 3583 (set_attr "length" "*,8")]) 3584 3585 ; GAS relies on the order and position of instructions output below in order 3586 ; to generate relocs for VMS link to potentially optimize the call. 3587 ; Please do not molest. 3588 (define_insn "*call_vms_1" 3589 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3590 (match_operand 1)) 3591 (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3592 (use (reg:DI 25)) 3593 (use (reg:DI 26)) 3594 (clobber (reg:DI 27))] 3595 "TARGET_ABI_OPEN_VMS" 3596 { 3597 switch (which_alternative) 3598 { 3599 case 0: 3600 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3601 case 1: 3602 operands [2] = alpha_use_linkage (operands [0], true, false); 3603 operands [3] = alpha_use_linkage (operands [0], false, false); 3604 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3605 default: 3606 gcc_unreachable (); 3607 } 3608 } 3609 [(set_attr "type" "jsr") 3610 (set_attr "length" "12,16")]) 3611 3612 ;; Call subroutine returning any type. 3613 3614 (define_expand "untyped_call" 3615 [(parallel [(call (match_operand 0) 3616 (const_int 0)) 3617 (match_operand 1) 3618 (match_operand 2)])] 3619 "" 3620 { 3621 int i; 3622 3623 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3624 3625 for (i = 0; i < XVECLEN (operands[2], 0); i++) 3626 { 3627 rtx set = XVECEXP (operands[2], 0, i); 3628 emit_move_insn (SET_DEST (set), SET_SRC (set)); 3629 } 3630 3631 /* The optimizer does not know that the call sets the function value 3632 registers we stored in the result block. We avoid problems by 3633 claiming that all hard registers are used and clobbered at this 3634 point. */ 3635 emit_insn (gen_blockage ()); 3636 3637 DONE; 3638 }) 3639 3640 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3641 ;; all of memory. This blocks insns from being moved across this point. 3642 3643 (define_insn "blockage" 3644 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3645 "" 3646 "" 3647 [(set_attr "length" "0") 3648 (set_attr "type" "none")]) 3649 3650 (define_insn "jump" 3651 [(set (pc) 3652 (label_ref (match_operand 0)))] 3653 "" 3654 "br $31,%l0" 3655 [(set_attr "type" "ibr")]) 3656 3657 (define_expand "return" 3658 [(return)] 3659 "direct_return ()") 3660 3661 (define_insn "*return_internal" 3662 [(return)] 3663 "reload_completed" 3664 "ret $31,($26),1" 3665 [(set_attr "type" "ibr")]) 3666 3667 (define_insn "indirect_jump" 3668 [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3669 "" 3670 "jmp $31,(%0),0" 3671 [(set_attr "type" "ibr")]) 3672 3673 (define_expand "tablejump" 3674 [(parallel [(set (pc) 3675 (match_operand 0 "register_operand")) 3676 (use (label_ref:DI (match_operand 1)))])] 3677 "" 3678 { 3679 if (TARGET_ABI_OSF) 3680 { 3681 rtx dest = gen_reg_rtx (DImode); 3682 emit_insn (gen_extendsidi2 (dest, operands[0])); 3683 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3684 operands[0] = dest; 3685 } 3686 }) 3687 3688 (define_insn "*tablejump_internal" 3689 [(set (pc) 3690 (match_operand:DI 0 "register_operand" "r")) 3691 (use (label_ref (match_operand 1)))] 3692 "" 3693 "jmp $31,(%0),0" 3694 [(set_attr "type" "ibr")]) 3695 3696 ;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3697 ;; want to have to include pal.h in our .s file. 3698 (define_insn "imb" 3699 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3700 "" 3701 "call_pal 0x86" 3702 [(set_attr "type" "callpal")]) 3703 3704 (define_expand "clear_cache" 3705 [(match_operand:DI 0) ; region start 3706 (match_operand:DI 1)] ; region end 3707 "" 3708 { 3709 emit_insn (gen_imb ()); 3710 DONE; 3711 }) 3712 3713 ;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3714 (define_insn "trap" 3715 [(trap_if (const_int 1) (const_int 0)) 3716 (use (reg:DI 29))] 3717 "" 3718 "call_pal 0x81" 3719 [(set_attr "type" "callpal")]) 3720 3721 ;; For userland, we load the thread pointer from the TCB. 3722 ;; For the kernel, we load the per-cpu private value. 3723 3724 (define_insn "get_thread_pointerdi" 3725 [(set (match_operand:DI 0 "register_operand" "=v") 3726 (unspec:DI [(const_int 0)] UNSPEC_TP))] 3727 "TARGET_ABI_OSF" 3728 { 3729 if (TARGET_TLS_KERNEL) 3730 return "call_pal 0x32"; 3731 else 3732 return "call_pal 0x9e"; 3733 } 3734 [(set_attr "type" "callpal")]) 3735 3736 ;; For completeness, and possibly a __builtin function, here's how to 3737 ;; set the thread pointer. Since we don't describe enough of this 3738 ;; quantity for CSE, we have to use a volatile unspec, and then there's 3739 ;; not much point in creating an R16_REG register class. 3740 3741 (define_expand "set_thread_pointerdi" 3742 [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3743 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3744 "TARGET_ABI_OSF") 3745 3746 (define_insn "*set_tp" 3747 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3748 "TARGET_ABI_OSF" 3749 { 3750 if (TARGET_TLS_KERNEL) 3751 return "call_pal 0x31"; 3752 else 3753 return "call_pal 0x9f"; 3754 } 3755 [(set_attr "type" "callpal")]) 3756 3757 ;; Special builtins for establishing and reverting VMS condition handlers. 3758 3759 (define_expand "builtin_establish_vms_condition_handler" 3760 [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3761 (use (match_operand:DI 1 "address_operand"))] 3762 "TARGET_ABI_OPEN_VMS" 3763 { 3764 alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3765 operands[1]); 3766 }) 3767 3768 (define_expand "builtin_revert_vms_condition_handler" 3769 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3770 "TARGET_ABI_OPEN_VMS" 3771 "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3772 3774 ;; Finally, we have the basic data motion insns. The byte and word insns 3775 ;; are done via define_expand. Start with the floating-point insns, since 3776 ;; they are simpler. 3777 3778 (define_expand "movsf" 3779 [(set (match_operand:SF 0 "nonimmediate_operand") 3780 (match_operand:SF 1 "general_operand"))] 3781 "" 3782 { 3783 if (MEM_P (operands[0]) 3784 && ! reg_or_0_operand (operands[1], SFmode)) 3785 operands[1] = force_reg (SFmode, operands[1]); 3786 }) 3787 3788 (define_insn "*movsf" 3789 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3790 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3791 "register_operand (operands[0], SFmode) 3792 || reg_or_0_operand (operands[1], SFmode)" 3793 "@ 3794 cpys %R1,%R1,%0 3795 ld%, %0,%1 3796 bis $31,%r1,%0 3797 ldl %0,%1 3798 st%, %R1,%0 3799 stl %r1,%0 3800 itofs %1,%0 3801 ftois %1,%0" 3802 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3803 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3804 3805 (define_expand "movdf" 3806 [(set (match_operand:DF 0 "nonimmediate_operand") 3807 (match_operand:DF 1 "general_operand"))] 3808 "" 3809 { 3810 if (MEM_P (operands[0]) 3811 && ! reg_or_0_operand (operands[1], DFmode)) 3812 operands[1] = force_reg (DFmode, operands[1]); 3813 }) 3814 3815 (define_insn "*movdf" 3816 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3817 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3818 "register_operand (operands[0], DFmode) 3819 || reg_or_0_operand (operands[1], DFmode)" 3820 "@ 3821 cpys %R1,%R1,%0 3822 ld%- %0,%1 3823 bis $31,%r1,%0 3824 ldq %0,%1 3825 st%- %R1,%0 3826 stq %r1,%0 3827 itoft %1,%0 3828 ftoit %1,%0" 3829 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3830 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3831 3832 ;; Subregs suck for register allocation. Pretend we can move TFmode 3833 ;; data between general registers until after reload. 3834 ;; ??? Is this still true now that we have the lower-subreg pass? 3835 3836 (define_expand "movtf" 3837 [(set (match_operand:TF 0 "nonimmediate_operand") 3838 (match_operand:TF 1 "general_operand"))] 3839 "" 3840 { 3841 if (MEM_P (operands[0]) 3842 && ! reg_or_0_operand (operands[1], TFmode)) 3843 operands[1] = force_reg (TFmode, operands[1]); 3844 }) 3845 3846 (define_insn_and_split "*movtf_internal" 3847 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3848 (match_operand:TF 1 "input_operand" "roG,rG"))] 3849 "register_operand (operands[0], TFmode) 3850 || reg_or_0_operand (operands[1], TFmode)" 3851 "#" 3852 "reload_completed" 3853 [(set (match_dup 0) (match_dup 2)) 3854 (set (match_dup 1) (match_dup 3))] 3855 "alpha_split_tmode_pair (operands, TFmode, true);") 3856 3857 ;; We do two major things here: handle mem->mem and construct long 3858 ;; constants. 3859 3860 (define_expand "movsi" 3861 [(set (match_operand:SI 0 "nonimmediate_operand") 3862 (match_operand:SI 1 "general_operand"))] 3863 "" 3864 { 3865 if (alpha_expand_mov (SImode, operands)) 3866 DONE; 3867 }) 3868 3869 (define_insn "*movsi" 3870 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3871 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3872 "register_operand (operands[0], SImode) 3873 || reg_or_0_operand (operands[1], SImode)" 3874 "@ 3875 bis $31,%r1,%0 3876 lda %0,%1($31) 3877 ldah %0,%h1($31) 3878 # 3879 ldl %0,%1 3880 stl %r1,%0 3881 lda %0,%1" 3882 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3883 (set_attr "isa" "*,*,*,*,*,*,vms")]) 3884 3885 ;; Split a load of a large constant into the appropriate two-insn 3886 ;; sequence. 3887 3888 (define_split 3889 [(set (match_operand:SI 0 "register_operand") 3890 (match_operand:SI 1 "non_add_const_operand"))] 3891 "" 3892 [(const_int 0)] 3893 { 3894 if (alpha_split_const_mov (SImode, operands)) 3895 DONE; 3896 else 3897 FAIL; 3898 }) 3899 3900 (define_insn "*movdi_er_low_l" 3901 [(set (match_operand:DI 0 "register_operand" "=r") 3902 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3903 (match_operand:DI 2 "local_symbolic_operand")))] 3904 "TARGET_EXPLICIT_RELOCS" 3905 { 3906 if (true_regnum (operands[1]) == 29) 3907 return "lda %0,%2(%1)\t\t!gprel"; 3908 else 3909 return "lda %0,%2(%1)\t\t!gprellow"; 3910 } 3911 [(set_attr "usegp" "yes")]) 3912 3913 (define_split 3914 [(set (match_operand:DI 0 "register_operand") 3915 (match_operand:DI 1 "small_symbolic_operand"))] 3916 "TARGET_EXPLICIT_RELOCS && reload_completed" 3917 [(set (match_dup 0) 3918 (lo_sum:DI (match_dup 2) (match_dup 1)))] 3919 "operands[2] = pic_offset_table_rtx;") 3920 3921 (define_split 3922 [(set (match_operand:DI 0 "register_operand") 3923 (match_operand:DI 1 "local_symbolic_operand"))] 3924 "TARGET_EXPLICIT_RELOCS && reload_completed" 3925 [(set (match_dup 0) 3926 (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3927 (set (match_dup 0) 3928 (lo_sum:DI (match_dup 0) (match_dup 1)))] 3929 "operands[2] = pic_offset_table_rtx;") 3930 3931 (define_split 3932 [(match_operand 0 "some_small_symbolic_operand")] 3933 "" 3934 [(match_dup 0)] 3935 "operands[0] = split_small_symbolic_operand (operands[0]);") 3936 3937 ;; Accepts any symbolic, not just global, since function calls that 3938 ;; don't go via bsr still use !literal in hopes of linker relaxation. 3939 (define_insn "movdi_er_high_g" 3940 [(set (match_operand:DI 0 "register_operand" "=r") 3941 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3942 (match_operand:DI 2 "symbolic_operand") 3943 (match_operand 3 "const_int_operand")] 3944 UNSPEC_LITERAL))] 3945 "TARGET_EXPLICIT_RELOCS" 3946 { 3947 if (INTVAL (operands[3]) == 0) 3948 return "ldq %0,%2(%1)\t\t!literal"; 3949 else 3950 return "ldq %0,%2(%1)\t\t!literal!%3"; 3951 } 3952 [(set_attr "type" "ldsym") 3953 (set_attr "cannot_copy" "true")]) 3954 3955 (define_split 3956 [(set (match_operand:DI 0 "register_operand") 3957 (match_operand:DI 1 "global_symbolic_operand"))] 3958 "TARGET_EXPLICIT_RELOCS && reload_completed" 3959 [(set (match_dup 0) 3960 (unspec:DI [(match_dup 2) 3961 (match_dup 1) 3962 (const_int 0)] UNSPEC_LITERAL))] 3963 "operands[2] = pic_offset_table_rtx;") 3964 3965 (define_insn "movdi_er_tlsgd" 3966 [(set (match_operand:DI 0 "register_operand" "=r") 3967 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3968 (match_operand:DI 2 "symbolic_operand") 3969 (match_operand 3 "const_int_operand")] 3970 UNSPEC_TLSGD))] 3971 "HAVE_AS_TLS" 3972 { 3973 if (INTVAL (operands[3]) == 0) 3974 return "lda %0,%2(%1)\t\t!tlsgd"; 3975 else 3976 return "lda %0,%2(%1)\t\t!tlsgd!%3"; 3977 } 3978 [(set_attr "cannot_copy" "true")]) 3979 3980 (define_insn "movdi_er_tlsldm" 3981 [(set (match_operand:DI 0 "register_operand" "=r") 3982 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3983 (match_operand 2 "const_int_operand")] 3984 UNSPEC_TLSLDM))] 3985 "HAVE_AS_TLS" 3986 { 3987 if (INTVAL (operands[2]) == 0) 3988 return "lda %0,%&(%1)\t\t!tlsldm"; 3989 else 3990 return "lda %0,%&(%1)\t\t!tlsldm!%2"; 3991 } 3992 [(set_attr "cannot_copy" "true")]) 3993 3994 (define_insn "*movdi_er_gotdtp" 3995 [(set (match_operand:DI 0 "register_operand" "=r") 3996 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3997 (match_operand:DI 2 "symbolic_operand")] 3998 UNSPEC_DTPREL))] 3999 "HAVE_AS_TLS" 4000 "ldq %0,%2(%1)\t\t!gotdtprel" 4001 [(set_attr "type" "ild") 4002 (set_attr "usegp" "yes")]) 4003 4004 (define_split 4005 [(set (match_operand:DI 0 "register_operand") 4006 (match_operand:DI 1 "gotdtp_symbolic_operand"))] 4007 "HAVE_AS_TLS && reload_completed" 4008 [(set (match_dup 0) 4009 (unspec:DI [(match_dup 2) 4010 (match_dup 1)] UNSPEC_DTPREL))] 4011 { 4012 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4013 operands[2] = pic_offset_table_rtx; 4014 }) 4015 4016 (define_insn "*movdi_er_gottp" 4017 [(set (match_operand:DI 0 "register_operand" "=r") 4018 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4019 (match_operand:DI 2 "symbolic_operand")] 4020 UNSPEC_TPREL))] 4021 "HAVE_AS_TLS" 4022 "ldq %0,%2(%1)\t\t!gottprel" 4023 [(set_attr "type" "ild") 4024 (set_attr "usegp" "yes")]) 4025 4026 (define_split 4027 [(set (match_operand:DI 0 "register_operand") 4028 (match_operand:DI 1 "gottp_symbolic_operand"))] 4029 "HAVE_AS_TLS && reload_completed" 4030 [(set (match_dup 0) 4031 (unspec:DI [(match_dup 2) 4032 (match_dup 1)] UNSPEC_TPREL))] 4033 { 4034 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4035 operands[2] = pic_offset_table_rtx; 4036 }) 4037 4038 (define_insn "*movdi" 4039 [(set (match_operand:DI 0 "nonimmediate_operand" 4040 "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4041 (match_operand:DI 1 "input_operand" 4042 "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4043 "register_operand (operands[0], DImode) 4044 || reg_or_0_operand (operands[1], DImode)" 4045 "@ 4046 mov %r1,%0 4047 lda %0,%1($31) 4048 ldah %0,%h1($31) 4049 # 4050 # 4051 # 4052 lda %0,%1 4053 ldq%A1 %0,%1 4054 stq%A0 %r1,%0 4055 fmov %R1,%0 4056 ldt %0,%1 4057 stt %R1,%0 4058 ftoit %1,%0 4059 itoft %1,%0" 4060 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4061 (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4062 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4063 4064 ;; VMS needs to set up "vms_base_regno" for unwinding. This move 4065 ;; often appears dead to the life analysis code, at which point we 4066 ;; die for emitting dead prologue instructions. Force this live. 4067 4068 (define_insn "force_movdi" 4069 [(set (match_operand:DI 0 "register_operand" "=r") 4070 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4071 UNSPECV_FORCE_MOV))] 4072 "" 4073 "mov %1,%0" 4074 [(set_attr "type" "ilog")]) 4075 4076 ;; We do three major things here: handle mem->mem, put 64-bit constants in 4077 ;; memory, and construct long 32-bit constants. 4078 4079 (define_expand "movdi" 4080 [(set (match_operand:DI 0 "nonimmediate_operand") 4081 (match_operand:DI 1 "general_operand"))] 4082 "" 4083 { 4084 if (alpha_expand_mov (DImode, operands)) 4085 DONE; 4086 }) 4087 4088 ;; Split a load of a large constant into the appropriate two-insn 4089 ;; sequence. 4090 4091 (define_split 4092 [(set (match_operand:DI 0 "register_operand") 4093 (match_operand:DI 1 "non_add_const_operand"))] 4094 "" 4095 [(const_int 0)] 4096 { 4097 if (alpha_split_const_mov (DImode, operands)) 4098 DONE; 4099 else 4100 FAIL; 4101 }) 4102 4103 ;; We need to prevent reload from splitting TImode moves, because it 4104 ;; might decide to overwrite a pointer with the value it points to. 4105 ;; In that case we have to do the loads in the appropriate order so 4106 ;; that the pointer is not destroyed too early. 4107 4108 (define_insn_and_split "*movti_internal" 4109 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4110 (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4111 "(register_operand (operands[0], TImode) 4112 /* Prevent rematerialization of constants. */ 4113 && ! CONSTANT_P (operands[1])) 4114 || reg_or_0_operand (operands[1], TImode)" 4115 "#" 4116 "reload_completed" 4117 [(set (match_dup 0) (match_dup 2)) 4118 (set (match_dup 1) (match_dup 3))] 4119 "alpha_split_tmode_pair (operands, TImode, true);") 4120 4121 (define_expand "movti" 4122 [(set (match_operand:TI 0 "nonimmediate_operand") 4123 (match_operand:TI 1 "general_operand"))] 4124 "" 4125 { 4126 if (MEM_P (operands[0]) 4127 && ! reg_or_0_operand (operands[1], TImode)) 4128 operands[1] = force_reg (TImode, operands[1]); 4129 4130 if (operands[1] == const0_rtx) 4131 ; 4132 /* We must put 64-bit constants in memory. We could keep the 4133 32-bit constants in TImode and rely on the splitter, but 4134 this doesn't seem to be worth the pain. */ 4135 else if (CONST_SCALAR_INT_P (operands[1])) 4136 { 4137 rtx in[2], out[2], target; 4138 4139 gcc_assert (can_create_pseudo_p ()); 4140 4141 split_double (operands[1], &in[0], &in[1]); 4142 4143 if (in[0] == const0_rtx) 4144 out[0] = const0_rtx; 4145 else 4146 { 4147 out[0] = gen_reg_rtx (DImode); 4148 emit_insn (gen_movdi (out[0], in[0])); 4149 } 4150 4151 if (in[1] == const0_rtx) 4152 out[1] = const0_rtx; 4153 else 4154 { 4155 out[1] = gen_reg_rtx (DImode); 4156 emit_insn (gen_movdi (out[1], in[1])); 4157 } 4158 4159 if (!REG_P (operands[0])) 4160 target = gen_reg_rtx (TImode); 4161 else 4162 target = operands[0]; 4163 4164 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4165 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4166 4167 if (target != operands[0]) 4168 emit_insn (gen_rtx_SET (operands[0], target)); 4169 4170 DONE; 4171 } 4172 }) 4173 4174 ;; These are the partial-word cases. 4175 ;; 4176 ;; First we have the code to load an aligned word. Operand 0 is the register 4177 ;; in which to place the result. It's mode is QImode or HImode. Operand 1 4178 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4179 ;; number of bits within the word that the value is. Operand 3 is an SImode 4180 ;; scratch register. If operand 0 is a hard register, operand 3 may be the 4181 ;; same register. It is allowed to conflict with operand 1 as well. 4182 4183 (define_expand "aligned_loadqi" 4184 [(set (match_operand:SI 3 "register_operand") 4185 (match_operand:SI 1 "memory_operand")) 4186 (set (match_operand:DI 0 "register_operand") 4187 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4188 (const_int 8) 4189 (match_operand:DI 2 "const_int_operand")))]) 4190 4191 (define_expand "aligned_loadhi" 4192 [(set (match_operand:SI 3 "register_operand") 4193 (match_operand:SI 1 "memory_operand")) 4194 (set (match_operand:DI 0 "register_operand") 4195 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4196 (const_int 16) 4197 (match_operand:DI 2 "const_int_operand")))]) 4198 4199 ;; Similar for unaligned loads, where we use the sequence from the 4200 ;; Alpha Architecture manual. We have to distinguish between little-endian 4201 ;; and big-endian systems as the sequences are different. 4202 ;; 4203 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4204 ;; operand 3 can overlap the input and output registers. 4205 4206 (define_expand "unaligned_loadqi" 4207 [(set (match_operand:DI 2 "register_operand") 4208 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4209 (const_int -8)))) 4210 (set (match_operand:DI 3 "register_operand") 4211 (match_dup 1)) 4212 (set (match_operand:DI 0 "register_operand") 4213 (zero_extract:DI (match_dup 2) 4214 (const_int 8) 4215 (ashift:DI (match_dup 3) (const_int 3))))]) 4216 4217 (define_expand "unaligned_loadhi" 4218 [(set (match_operand:DI 2 "register_operand") 4219 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4220 (const_int -8)))) 4221 (set (match_operand:DI 3 "register_operand") 4222 (match_dup 1)) 4223 (set (match_operand:DI 0 "register_operand") 4224 (zero_extract:DI (match_dup 2) 4225 (const_int 16) 4226 (ashift:DI (match_dup 3) (const_int 3))))]) 4227 4228 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4229 ;; aligned SImode MEM. Operand 1 is the register containing the 4230 ;; byte or word to store. Operand 2 is the number of bits within the word that 4231 ;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4232 4233 (define_expand "aligned_store" 4234 [(set (match_operand:SI 3 "register_operand") 4235 (match_operand:SI 0 "memory_operand")) 4236 (set (subreg:DI (match_dup 3) 0) 4237 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4238 (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4239 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4240 (match_operand:DI 2 "const_int_operand"))) 4241 (set (subreg:DI (match_dup 4) 0) 4242 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4243 (set (match_dup 0) (match_dup 4))] 4244 "" 4245 { 4246 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4247 << INTVAL (operands[2]))); 4248 }) 4249 4250 ;; For the unaligned byte and halfword cases, we use code similar to that 4251 ;; in the ;; Architecture book, but reordered to lower the number of registers 4252 ;; required. Operand 0 is the address. Operand 1 is the data to store. 4253 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4254 ;; be the same temporary, if desired. If the address is in a register, 4255 ;; operand 2 can be that register. 4256 4257 (define_expand "@unaligned_store<mode>" 4258 [(set (match_operand:DI 3 "register_operand") 4259 (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4260 (const_int -8)))) 4261 (set (match_operand:DI 2 "register_operand") 4262 (match_dup 0)) 4263 (set (match_dup 3) 4264 (and:DI (not:DI (ashift:DI (match_dup 5) 4265 (ashift:DI (match_dup 2) (const_int 3)))) 4266 (match_dup 3))) 4267 (set (match_operand:DI 4 "register_operand") 4268 (ashift:DI (zero_extend:DI 4269 (match_operand:I12MODE 1 "register_operand")) 4270 (ashift:DI (match_dup 2) (const_int 3)))) 4271 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4272 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4273 (match_dup 4))] 4274 "" 4275 "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4276 4277 ;; Here are the define_expand's for QI and HI moves that use the above 4278 ;; patterns. We have the normal sets, plus the ones that need scratch 4279 ;; registers for reload. 4280 4281 (define_expand "mov<mode>" 4282 [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4283 (match_operand:I12MODE 1 "general_operand"))] 4284 "" 4285 { 4286 if (TARGET_BWX 4287 ? alpha_expand_mov (<MODE>mode, operands) 4288 : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4289 DONE; 4290 }) 4291 4292 (define_insn "*movqi" 4293 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4294 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4295 "register_operand (operands[0], QImode) 4296 || reg_or_0_operand (operands[1], QImode)" 4297 "@ 4298 bis $31,%r1,%0 4299 lda %0,%L1($31) 4300 ldbu %0,%1 4301 stb %r1,%0" 4302 [(set_attr "type" "ilog,iadd,ild,ist") 4303 (set_attr "isa" "*,*,bwx,bwx")]) 4304 4305 (define_insn "*movhi" 4306 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4307 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4308 "register_operand (operands[0], HImode) 4309 || reg_or_0_operand (operands[1], HImode)" 4310 "@ 4311 bis $31,%r1,%0 4312 lda %0,%L1($31) 4313 ldwu %0,%1 4314 stw %r1,%0" 4315 [(set_attr "type" "ilog,iadd,ild,ist") 4316 (set_attr "isa" "*,*,bwx,bwx")]) 4317 4318 ;; We need to hook into the extra support that we have for HImode 4319 ;; reloads when BWX insns are not available. 4320 (define_expand "movcqi" 4321 [(set (match_operand:CQI 0 "nonimmediate_operand") 4322 (match_operand:CQI 1 "general_operand"))] 4323 "!TARGET_BWX" 4324 { 4325 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4326 ; 4327 else if (!any_memory_operand (operands[0], CQImode)) 4328 { 4329 if (!any_memory_operand (operands[1], CQImode)) 4330 { 4331 emit_move_insn (gen_lowpart (HImode, operands[0]), 4332 gen_lowpart (HImode, operands[1])); 4333 DONE; 4334 } 4335 if (aligned_memory_operand (operands[1], CQImode)) 4336 { 4337 bool done; 4338 do_aligned1: 4339 operands[1] = gen_lowpart (HImode, operands[1]); 4340 do_aligned2: 4341 operands[0] = gen_lowpart (HImode, operands[0]); 4342 done = alpha_expand_mov_nobwx (HImode, operands); 4343 gcc_assert (done); 4344 DONE; 4345 } 4346 } 4347 else if (aligned_memory_operand (operands[0], CQImode)) 4348 { 4349 if (MEM_P (operands[1])) 4350 { 4351 rtx x = gen_reg_rtx (HImode); 4352 emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4353 operands[1] = x; 4354 goto do_aligned2; 4355 } 4356 goto do_aligned1; 4357 } 4358 4359 gcc_assert (!reload_in_progress); 4360 emit_move_complex_parts (operands[0], operands[1]); 4361 DONE; 4362 }) 4363 4364 ;; Here are the versions for reload. 4365 ;; 4366 ;; The aligned input case is recognized early in alpha_secondary_reload 4367 ;; in order to avoid allocating an unnecessary scratch register. 4368 ;; 4369 ;; Note that in the unaligned cases we know that the operand must not be 4370 ;; a pseudo-register because stack slots are always aligned references. 4371 4372 (define_expand "reload_in<mode>" 4373 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4374 (match_operand:RELOAD12 1 "any_memory_operand" "m") 4375 (match_operand:TI 2 "register_operand" "=&r")])] 4376 "!TARGET_BWX" 4377 { 4378 rtx scratch, seq, addr; 4379 unsigned regno = REGNO (operands[2]); 4380 4381 /* It is possible that one of the registers we got for operands[2] 4382 might coincide with that of operands[0] (which is why we made 4383 it TImode). Pick the other one to use as our scratch. */ 4384 if (regno == REGNO (operands[0])) 4385 regno++; 4386 scratch = gen_rtx_REG (DImode, regno); 4387 4388 addr = get_unaligned_address (operands[1]); 4389 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4390 seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4391 scratch, operands[0]); 4392 alpha_set_memflags (seq, operands[1]); 4393 4394 emit_insn (seq); 4395 DONE; 4396 }) 4397 4398 (define_expand "reload_out<mode>" 4399 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4400 (match_operand:RELOAD12 1 "register_operand" "r") 4401 (match_operand:TI 2 "register_operand" "=&r")])] 4402 "!TARGET_BWX" 4403 { 4404 unsigned regno = REGNO (operands[2]); 4405 4406 if (<MODE>mode == CQImode) 4407 { 4408 operands[0] = gen_lowpart (HImode, operands[0]); 4409 operands[1] = gen_lowpart (HImode, operands[1]); 4410 } 4411 4412 if (aligned_memory_operand (operands[0], <MODE>mode)) 4413 { 4414 emit_insn (gen_reload_out<reloadmode>_aligned 4415 (operands[0], operands[1], 4416 gen_rtx_REG (SImode, regno), 4417 gen_rtx_REG (SImode, regno + 1))); 4418 } 4419 else 4420 { 4421 rtx addr = get_unaligned_address (operands[0]); 4422 rtx scratch1 = gen_rtx_REG (DImode, regno); 4423 rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4424 rtx scratch3 = scratch1; 4425 rtx seq; 4426 4427 if (REG_P (addr)) 4428 scratch1 = addr; 4429 4430 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4431 scratch2, scratch3); 4432 alpha_set_memflags (seq, operands[0]); 4433 emit_insn (seq); 4434 } 4435 DONE; 4436 }) 4437 4438 ;; Helpers for the above. The way reload is structured, we can't 4439 ;; always get a proper address for a stack slot during reload_foo 4440 ;; expansion, so we must delay our address manipulations until after. 4441 4442 (define_insn_and_split "@reload_in<mode>_aligned" 4443 [(set (match_operand:I12MODE 0 "register_operand" "=r") 4444 (match_operand:I12MODE 1 "memory_operand" "m"))] 4445 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4446 "#" 4447 "!TARGET_BWX && reload_completed" 4448 [(const_int 0)] 4449 { 4450 rtx aligned_mem, bitnum; 4451 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4452 emit_insn (gen_aligned_load<reloadmode> 4453 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4454 gen_rtx_REG (SImode, REGNO (operands[0])))); 4455 DONE; 4456 }) 4457 4458 (define_insn_and_split "reload_out<mode>_aligned" 4459 [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4460 (match_operand:I12MODE 1 "register_operand" "r")) 4461 (clobber (match_operand:SI 2 "register_operand" "=&r")) 4462 (clobber (match_operand:SI 3 "register_operand" "=&r"))] 4463 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4464 "#" 4465 "!TARGET_BWX && reload_completed" 4466 [(const_int 0)] 4467 { 4468 rtx aligned_mem, bitnum; 4469 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4470 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4471 operands[2], operands[3])); 4472 DONE; 4473 }) 4474 4476 ;; Vector operations 4477 4478 (define_mode_iterator VEC [V8QI V4HI V2SI]) 4479 (define_mode_iterator VEC12 [V8QI V4HI]) 4480 4481 (define_expand "mov<mode>" 4482 [(set (match_operand:VEC 0 "nonimmediate_operand") 4483 (match_operand:VEC 1 "general_operand"))] 4484 "" 4485 { 4486 if (alpha_expand_mov (<MODE>mode, operands)) 4487 DONE; 4488 }) 4489 4490 (define_split 4491 [(set (match_operand:VEC 0 "register_operand") 4492 (match_operand:VEC 1 "non_zero_const_operand"))] 4493 "" 4494 [(const_int 0)] 4495 { 4496 if (alpha_split_const_mov (<MODE>mode, operands)) 4497 DONE; 4498 else 4499 FAIL; 4500 }) 4501 4502 4503 (define_expand "movmisalign<mode>" 4504 [(set (match_operand:VEC 0 "nonimmediate_operand") 4505 (match_operand:VEC 1 "general_operand"))] 4506 "" 4507 { 4508 alpha_expand_movmisalign (<MODE>mode, operands); 4509 DONE; 4510 }) 4511 4512 (define_insn "*mov<mode>_fix" 4513 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4514 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4515 "register_operand (operands[0], <MODE>mode) 4516 || reg_or_0_operand (operands[1], <MODE>mode)" 4517 "@ 4518 bis $31,%r1,%0 4519 # 4520 ldq %0,%1 4521 stq %r1,%0 4522 cpys %R1,%R1,%0 4523 ldt %0,%1 4524 stt %R1,%0 4525 ftoit %1,%0 4526 itoft %1,%0" 4527 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4528 (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4529 4530 (define_insn "<code><mode>3" 4531 [(set (match_operand:VEC12 0 "register_operand" "=r") 4532 (any_maxmin:VEC12 4533 (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4534 (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4535 "TARGET_MAX" 4536 "<maxmin><modesuffix> %r1,%r2,%0" 4537 [(set_attr "type" "mvi")]) 4538 4539 (define_insn "one_cmpl<mode>2" 4540 [(set (match_operand:VEC 0 "register_operand" "=r") 4541 (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4542 "" 4543 "ornot $31,%1,%0" 4544 [(set_attr "type" "ilog")]) 4545 4546 (define_insn "and<mode>3" 4547 [(set (match_operand:VEC 0 "register_operand" "=r") 4548 (and:VEC (match_operand:VEC 1 "register_operand" "r") 4549 (match_operand:VEC 2 "register_operand" "r")))] 4550 "" 4551 "and %1,%2,%0" 4552 [(set_attr "type" "ilog")]) 4553 4554 (define_insn "*andnot<mode>3" 4555 [(set (match_operand:VEC 0 "register_operand" "=r") 4556 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4557 (match_operand:VEC 2 "register_operand" "r")))] 4558 "" 4559 "bic %2,%1,%0" 4560 [(set_attr "type" "ilog")]) 4561 4562 (define_insn "ior<mode>3" 4563 [(set (match_operand:VEC 0 "register_operand" "=r") 4564 (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4565 (match_operand:VEC 2 "register_operand" "r")))] 4566 "" 4567 "bis %1,%2,%0" 4568 [(set_attr "type" "ilog")]) 4569 4570 (define_insn "*iornot<mode>3" 4571 [(set (match_operand:VEC 0 "register_operand" "=r") 4572 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4573 (match_operand:VEC 2 "register_operand" "r")))] 4574 "" 4575 "ornot %2,%1,%0" 4576 [(set_attr "type" "ilog")]) 4577 4578 (define_insn "xor<mode>3" 4579 [(set (match_operand:VEC 0 "register_operand" "=r") 4580 (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4581 (match_operand:VEC 2 "register_operand" "r")))] 4582 "" 4583 "xor %1,%2,%0" 4584 [(set_attr "type" "ilog")]) 4585 4586 (define_insn "*xornot<mode>3" 4587 [(set (match_operand:VEC 0 "register_operand" "=r") 4588 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4589 (match_operand:VEC 2 "register_operand" "r"))))] 4590 "" 4591 "eqv %1,%2,%0" 4592 [(set_attr "type" "ilog")]) 4593 4594 (define_expand "vec_shl_<mode>" 4595 [(set (match_operand:VEC 0 "register_operand") 4596 (ashift:DI (match_operand:VEC 1 "register_operand") 4597 (match_operand:DI 2 "reg_or_6bit_operand")))] 4598 "" 4599 { 4600 operands[0] = gen_lowpart (DImode, operands[0]); 4601 operands[1] = gen_lowpart (DImode, operands[1]); 4602 }) 4603 4604 (define_expand "vec_shr_<mode>" 4605 [(set (match_operand:VEC 0 "register_operand") 4606 (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4607 (match_operand:DI 2 "reg_or_6bit_operand")))] 4608 "" 4609 { 4610 operands[0] = gen_lowpart (DImode, operands[0]); 4611 operands[1] = gen_lowpart (DImode, operands[1]); 4612 }) 4613 4615 ;; Bit field extract patterns which use ext[wlq][lh] 4616 4617 (define_expand "extvmisaligndi" 4618 [(set (match_operand:DI 0 "register_operand") 4619 (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4620 (match_operand:DI 2 "const_int_operand") 4621 (match_operand:DI 3 "const_int_operand")))] 4622 "" 4623 { 4624 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4625 if (INTVAL (operands[3]) % 8 != 0 4626 || (INTVAL (operands[2]) != 16 4627 && INTVAL (operands[2]) != 32 4628 && INTVAL (operands[2]) != 64)) 4629 FAIL; 4630 4631 alpha_expand_unaligned_load (operands[0], operands[1], 4632 INTVAL (operands[2]) / 8, 4633 INTVAL (operands[3]) / 8, 1); 4634 DONE; 4635 }) 4636 4637 (define_expand "extzvdi" 4638 [(set (match_operand:DI 0 "register_operand") 4639 (zero_extract:DI (match_operand:DI 1 "register_operand") 4640 (match_operand:DI 2 "const_int_operand") 4641 (match_operand:DI 3 "const_int_operand")))] 4642 "" 4643 { 4644 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4645 if (INTVAL (operands[3]) % 8 != 0 4646 || (INTVAL (operands[2]) != 8 4647 && INTVAL (operands[2]) != 16 4648 && INTVAL (operands[2]) != 32 4649 && INTVAL (operands[2]) != 64)) 4650 FAIL; 4651 }) 4652 4653 (define_expand "extzvmisaligndi" 4654 [(set (match_operand:DI 0 "register_operand") 4655 (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4656 (match_operand:DI 2 "const_int_operand") 4657 (match_operand:DI 3 "const_int_operand")))] 4658 "" 4659 { 4660 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4661 We fail 8-bit fields, falling back on a simple byte load. */ 4662 if (INTVAL (operands[3]) % 8 != 0 4663 || (INTVAL (operands[2]) != 16 4664 && INTVAL (operands[2]) != 32 4665 && INTVAL (operands[2]) != 64)) 4666 FAIL; 4667 4668 alpha_expand_unaligned_load (operands[0], operands[1], 4669 INTVAL (operands[2]) / 8, 4670 INTVAL (operands[3]) / 8, 0); 4671 DONE; 4672 }) 4673 4674 (define_expand "insvmisaligndi" 4675 [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4676 (match_operand:DI 1 "const_int_operand") 4677 (match_operand:DI 2 "const_int_operand")) 4678 (match_operand:DI 3 "register_operand"))] 4679 "" 4680 { 4681 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4682 if (INTVAL (operands[2]) % 8 != 0 4683 || (INTVAL (operands[1]) != 16 4684 && INTVAL (operands[1]) != 32 4685 && INTVAL (operands[1]) != 64)) 4686 FAIL; 4687 4688 alpha_expand_unaligned_store (operands[0], operands[3], 4689 INTVAL (operands[1]) / 8, 4690 INTVAL (operands[2]) / 8); 4691 DONE; 4692 }) 4693 4694 ;; Block move/clear, see alpha.cc for more details. 4695 ;; Argument 0 is the destination 4696 ;; Argument 1 is the source 4697 ;; Argument 2 is the length 4698 ;; Argument 3 is the alignment 4699 4700 (define_expand "cpymemqi" 4701 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4702 (match_operand:BLK 1 "memory_operand")) 4703 (use (match_operand:DI 2 "immediate_operand")) 4704 (use (match_operand:DI 3 "immediate_operand"))])] 4705 "" 4706 { 4707 if (alpha_expand_block_move (operands)) 4708 DONE; 4709 else 4710 FAIL; 4711 }) 4712 4713 (define_expand "cpymemdi" 4714 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4715 (match_operand:BLK 1 "memory_operand")) 4716 (use (match_operand:DI 2 "immediate_operand")) 4717 (use (match_operand:DI 3 "immediate_operand")) 4718 (use (match_dup 4)) 4719 (clobber (reg:DI 25)) 4720 (clobber (reg:DI 16)) 4721 (clobber (reg:DI 17)) 4722 (clobber (reg:DI 18)) 4723 (clobber (reg:DI 19)) 4724 (clobber (reg:DI 20)) 4725 (clobber (reg:DI 26)) 4726 (clobber (reg:DI 27))])] 4727 "TARGET_ABI_OPEN_VMS" 4728 "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4729 4730 (define_insn "*cpymemdi_1" 4731 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4732 (match_operand:BLK 1 "memory_operand" "m,m")) 4733 (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4734 (use (match_operand:DI 3 "immediate_operand")) 4735 (use (match_operand:DI 4 "call_operand" "i,i")) 4736 (clobber (reg:DI 25)) 4737 (clobber (reg:DI 16)) 4738 (clobber (reg:DI 17)) 4739 (clobber (reg:DI 18)) 4740 (clobber (reg:DI 19)) 4741 (clobber (reg:DI 20)) 4742 (clobber (reg:DI 26)) 4743 (clobber (reg:DI 27))] 4744 "TARGET_ABI_OPEN_VMS" 4745 { 4746 operands [5] = alpha_use_linkage (operands [4], false, true); 4747 switch (which_alternative) 4748 { 4749 case 0: 4750 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4751 case 1: 4752 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4753 default: 4754 gcc_unreachable (); 4755 } 4756 } 4757 [(set_attr "type" "multi") 4758 (set_attr "length" "28")]) 4759 4760 (define_expand "setmemqi" 4761 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4762 (match_operand 2 "const_int_operand")) 4763 (use (match_operand:DI 1 "immediate_operand")) 4764 (use (match_operand:DI 3 "immediate_operand"))])] 4765 "" 4766 { 4767 /* If value to set is not zero, use the library routine. */ 4768 if (operands[2] != const0_rtx) 4769 FAIL; 4770 4771 if (alpha_expand_block_clear (operands)) 4772 DONE; 4773 else 4774 FAIL; 4775 }) 4776 4777 (define_expand "setmemdi" 4778 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4779 (match_operand 2 "const_int_operand")) 4780 (use (match_operand:DI 1 "immediate_operand")) 4781 (use (match_operand:DI 3 "immediate_operand")) 4782 (use (match_dup 4)) 4783 (clobber (reg:DI 25)) 4784 (clobber (reg:DI 16)) 4785 (clobber (reg:DI 17)) 4786 (clobber (reg:DI 26)) 4787 (clobber (reg:DI 27))])] 4788 "TARGET_ABI_OPEN_VMS" 4789 { 4790 /* If value to set is not zero, use the library routine. */ 4791 if (operands[2] != const0_rtx) 4792 FAIL; 4793 4794 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4795 }) 4796 4797 (define_insn "*clrmemdi_1" 4798 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4799 (const_int 0)) 4800 (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4801 (use (match_operand:DI 2 "immediate_operand")) 4802 (use (match_operand:DI 3 "call_operand" "i,i")) 4803 (clobber (reg:DI 25)) 4804 (clobber (reg:DI 16)) 4805 (clobber (reg:DI 17)) 4806 (clobber (reg:DI 26)) 4807 (clobber (reg:DI 27))] 4808 "TARGET_ABI_OPEN_VMS" 4809 { 4810 operands [4] = alpha_use_linkage (operands [3], false, true); 4811 switch (which_alternative) 4812 { 4813 case 0: 4814 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4815 case 1: 4816 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4817 default: 4818 gcc_unreachable (); 4819 } 4820 } 4821 [(set_attr "type" "multi") 4822 (set_attr "length" "24")]) 4823 4824 4826 ;; Subroutine of stack space allocation. Perform a stack probe. 4827 (define_expand "stack_probe_internal" 4828 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4829 "" 4830 { 4831 operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4832 INTVAL (operands[0]))); 4833 MEM_VOLATILE_P (operands[1]) = 1; 4834 4835 operands[0] = const0_rtx; 4836 }) 4837 4838 ;; This is how we allocate stack space. If we are allocating a 4839 ;; constant amount of space and we know it is less than 4096 4840 ;; bytes, we need do nothing. 4841 ;; 4842 ;; If it is more than 4096 bytes, we need to probe the stack 4843 ;; periodically. 4844 (define_expand "allocate_stack" 4845 [(set (reg:DI 30) 4846 (plus:DI (reg:DI 30) 4847 (match_operand:DI 1 "reg_or_cint_operand"))) 4848 (set (match_operand:DI 0 "register_operand" "=r") 4849 (match_dup 2))] 4850 "" 4851 { 4852 if (CONST_INT_P (operands[1]) 4853 && INTVAL (operands[1]) < 32768) 4854 { 4855 if (INTVAL (operands[1]) >= 4096) 4856 { 4857 /* We do this the same way as in the prologue and generate explicit 4858 probes. Then we update the stack by the constant. */ 4859 4860 int probed = 4096; 4861 4862 emit_insn (gen_stack_probe_internal (GEN_INT (- probed))); 4863 while (probed + 8192 < INTVAL (operands[1])) 4864 emit_insn (gen_stack_probe_internal 4865 (GEN_INT (- (probed += 8192)))); 4866 4867 if (probed + 4096 < INTVAL (operands[1])) 4868 emit_insn (gen_stack_probe_internal 4869 (GEN_INT (- INTVAL(operands[1])))); 4870 } 4871 4872 operands[1] = GEN_INT (- INTVAL (operands[1])); 4873 operands[2] = virtual_stack_dynamic_rtx; 4874 } 4875 else 4876 { 4877 rtx_code_label *out_label = 0; 4878 rtx_code_label *loop_label = gen_label_rtx (); 4879 rtx want = gen_reg_rtx (Pmode); 4880 rtx tmp = gen_reg_rtx (Pmode); 4881 rtx memref, test; 4882 4883 emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4884 force_reg (Pmode, operands[1]))); 4885 4886 if (!CONST_INT_P (operands[1])) 4887 { 4888 rtx limit = GEN_INT (4096); 4889 out_label = gen_label_rtx (); 4890 test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4891 emit_jump_insn 4892 (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4893 } 4894 4895 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4896 emit_label (loop_label); 4897 memref = gen_rtx_MEM (DImode, tmp); 4898 MEM_VOLATILE_P (memref) = 1; 4899 emit_move_insn (memref, const0_rtx); 4900 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4901 test = gen_rtx_GTU (VOIDmode, tmp, want); 4902 emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4903 4904 memref = gen_rtx_MEM (DImode, want); 4905 MEM_VOLATILE_P (memref) = 1; 4906 emit_move_insn (memref, const0_rtx); 4907 4908 if (out_label) 4909 emit_label (out_label); 4910 4911 emit_move_insn (stack_pointer_rtx, want); 4912 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4913 DONE; 4914 } 4915 }) 4916 4917 ;; This is used by alpha_expand_prolog to do the same thing as above, 4918 ;; except we cannot at that time generate new basic blocks, so we hide 4919 ;; the loop in this one insn. 4920 4921 (define_insn "prologue_stack_probe_loop" 4922 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4923 (match_operand:DI 1 "register_operand" "r")] 4924 UNSPECV_PSPL)] 4925 "" 4926 { 4927 operands[2] = gen_label_rtx (); 4928 (*targetm.asm_out.internal_label) (asm_out_file, "L", 4929 CODE_LABEL_NUMBER (operands[2])); 4930 4931 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4932 } 4933 [(set_attr "length" "16") 4934 (set_attr "type" "multi")]) 4935 4936 (define_expand "prologue" 4937 [(const_int 0)] 4938 "" 4939 { 4940 alpha_expand_prologue (); 4941 DONE; 4942 }) 4943 4944 ;; These take care of emitting the ldgp insn in the prologue. This will be 4945 ;; an lda/ldah pair and we want to align them properly. So we have two 4946 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4947 ;; and the second of which emits nothing. However, both are marked as type 4948 ;; IADD (the default) so the alignment code in alpha.cc does the right thing 4949 ;; with them. 4950 4951 (define_expand "prologue_ldgp" 4952 [(set (match_dup 0) 4953 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4954 (set (match_dup 0) 4955 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4956 "" 4957 { 4958 operands[0] = pic_offset_table_rtx; 4959 operands[1] = gen_rtx_REG (Pmode, 27); 4960 operands[2] = (TARGET_EXPLICIT_RELOCS 4961 ? GEN_INT (alpha_next_sequence_number++) 4962 : const0_rtx); 4963 }) 4964 4965 (define_insn "*ldgp_er_1" 4966 [(set (match_operand:DI 0 "register_operand" "=r") 4967 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4968 (match_operand 2 "const_int_operand")] 4969 UNSPECV_LDGP1))] 4970 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4971 "ldah %0,0(%1)\t\t!gpdisp!%2" 4972 [(set_attr "cannot_copy" "true")]) 4973 4974 (define_insn "*ldgp_er_2" 4975 [(set (match_operand:DI 0 "register_operand" "=r") 4976 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4977 (match_operand 2 "const_int_operand")] 4978 UNSPEC_LDGP2))] 4979 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4980 "lda %0,0(%1)\t\t!gpdisp!%2" 4981 [(set_attr "cannot_copy" "true")]) 4982 4983 (define_insn "*prologue_ldgp_er_2" 4984 [(set (match_operand:DI 0 "register_operand" "=r") 4985 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4986 (match_operand 2 "const_int_operand")] 4987 UNSPECV_PLDGP2))] 4988 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4989 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 4990 [(set_attr "cannot_copy" "true")]) 4991 4992 (define_insn "*prologue_ldgp_1" 4993 [(set (match_operand:DI 0 "register_operand" "=r") 4994 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4995 (match_operand 2 "const_int_operand")] 4996 UNSPECV_LDGP1))] 4997 "" 4998 "ldgp %0,0(%1)\n$%~..ng:" 4999 [(set_attr "cannot_copy" "true")]) 5000 5001 (define_insn "*prologue_ldgp_2" 5002 [(set (match_operand:DI 0 "register_operand" "=r") 5003 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 5004 (match_operand 2 "const_int_operand")] 5005 UNSPECV_PLDGP2))] 5006 "" 5007 ) 5008 5009 ;; The _mcount profiling hook has special calling conventions, and 5010 ;; does not clobber all the registers that a normal call would. So 5011 ;; hide the fact this is a call at all. 5012 5013 (define_insn "prologue_mcount" 5014 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 5015 "" 5016 { 5017 if (TARGET_EXPLICIT_RELOCS) 5018 /* Note that we cannot use a lituse_jsr reloc, since _mcount 5019 cannot be called via the PLT. */ 5020 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 5021 else 5022 return "lda $28,_mcount\;jsr $28,($28),_mcount"; 5023 } 5024 [(set_attr "type" "multi") 5025 (set_attr "length" "8")]) 5026 5027 (define_insn "init_fp" 5028 [(set (match_operand:DI 0 "register_operand" "=r") 5029 (match_operand:DI 1 "register_operand" "r")) 5030 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5031 "" 5032 "bis $31,%1,%0") 5033 5034 (define_expand "epilogue" 5035 [(return)] 5036 "" 5037 "alpha_expand_epilogue ();") 5038 5039 (define_expand "sibcall_epilogue" 5040 [(return)] 5041 "TARGET_ABI_OSF" 5042 { 5043 alpha_expand_epilogue (); 5044 DONE; 5045 }) 5046 5047 (define_expand "builtin_longjmp" 5048 [(use (match_operand:DI 0 "register_operand" "r"))] 5049 "TARGET_ABI_OSF" 5050 { 5051 /* The elements of the buffer are, in order: */ 5052 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5053 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5054 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5055 rtx pv = gen_rtx_REG (Pmode, 27); 5056 5057 /* This bit is the same as expand_builtin_longjmp. */ 5058 emit_move_insn (hard_frame_pointer_rtx, fp); 5059 emit_move_insn (pv, lab); 5060 emit_stack_restore (SAVE_NONLOCAL, stack); 5061 emit_use (hard_frame_pointer_rtx); 5062 emit_use (stack_pointer_rtx); 5063 5064 /* Load the label we are jumping through into $27 so that we know 5065 where to look for it when we get back to setjmp's function for 5066 restoring the gp. */ 5067 emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5068 emit_barrier (); 5069 DONE; 5070 }) 5071 5072 ;; This is effectively a copy of indirect_jump, but constrained such 5073 ;; that register renaming cannot foil our cunning plan with $27. 5074 (define_insn "builtin_longjmp_internal" 5075 [(set (pc) 5076 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5077 UNSPECV_LONGJMP))] 5078 "" 5079 "jmp $31,(%0),0" 5080 [(set_attr "type" "ibr")]) 5081 5082 (define_expand "builtin_setjmp_receiver" 5083 [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5084 "TARGET_ABI_OSF") 5085 5086 (define_insn_and_split "*builtin_setjmp_receiver_1" 5087 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5088 "TARGET_ABI_OSF" 5089 { 5090 if (TARGET_EXPLICIT_RELOCS) 5091 return "#"; 5092 else 5093 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5094 } 5095 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5096 [(set (match_dup 1) 5097 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5098 (set (match_dup 1) 5099 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5100 { 5101 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5102 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5103 UNSPECV_SETJMPR_ER)); 5104 operands[1] = pic_offset_table_rtx; 5105 operands[2] = gen_rtx_REG (Pmode, 27); 5106 operands[3] = GEN_INT (alpha_next_sequence_number++); 5107 } 5108 [(set_attr "length" "12") 5109 (set_attr "type" "multi")]) 5110 5111 (define_insn "*builtin_setjmp_receiver_er_sl_1" 5112 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5113 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5114 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5115 5116 ;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5117 ;; exception landing pads in a cold section. To prevent inter-section offset 5118 ;; calculation, a jump to original landing pad is emitted in the place of the 5119 ;; original landing pad. Since landing pad is moved, RA-relative GP 5120 ;; calculation in the prologue of landing pad breaks. To solve this problem, 5121 ;; we use alternative GP load approach. 5122 5123 (define_expand "exception_receiver" 5124 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5125 "TARGET_ABI_OSF" 5126 { 5127 if (flag_reorder_blocks_and_partition) 5128 operands[0] = copy_rtx (alpha_gp_save_rtx ()); 5129 else 5130 operands[0] = const0_rtx; 5131 }) 5132 5133 (define_insn "*exception_receiver_2" 5134 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5135 "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5136 "ldq $29,%0" 5137 [(set_attr "type" "ild")]) 5138 5139 (define_insn_and_split "*exception_receiver_1" 5140 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5141 "TARGET_ABI_OSF" 5142 { 5143 if (TARGET_EXPLICIT_RELOCS) 5144 return "#"; 5145 else 5146 return "ldgp $29,0($26)"; 5147 } 5148 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5149 [(set (match_dup 0) 5150 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5151 (set (match_dup 0) 5152 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5153 { 5154 operands[0] = pic_offset_table_rtx; 5155 operands[1] = gen_rtx_REG (Pmode, 26); 5156 operands[2] = GEN_INT (alpha_next_sequence_number++); 5157 } 5158 [(set_attr "length" "8") 5159 (set_attr "type" "multi")]) 5160 5161 (define_expand "nonlocal_goto_receiver" 5162 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5163 (set (reg:DI 27) (mem:DI (reg:DI 29))) 5164 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5165 (use (reg:DI 27))] 5166 "TARGET_ABI_OPEN_VMS") 5167 5168 (define_insn "arg_home" 5169 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5170 (use (reg:DI 1)) 5171 (use (reg:DI 25)) 5172 (use (reg:DI 16)) 5173 (use (reg:DI 17)) 5174 (use (reg:DI 18)) 5175 (use (reg:DI 19)) 5176 (use (reg:DI 20)) 5177 (use (reg:DI 21)) 5178 (use (reg:DI 48)) 5179 (use (reg:DI 49)) 5180 (use (reg:DI 50)) 5181 (use (reg:DI 51)) 5182 (use (reg:DI 52)) 5183 (use (reg:DI 53)) 5184 (clobber (mem:BLK (const_int 0))) 5185 (clobber (reg:DI 24)) 5186 (clobber (reg:DI 25)) 5187 (clobber (reg:DI 0))] 5188 "TARGET_ABI_OPEN_VMS" 5189 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5190 [(set_attr "length" "16") 5191 (set_attr "type" "multi")]) 5192 5193 ;; Prefetch data. 5194 ;; 5195 ;; On EV4, these instructions are nops -- no load occurs. 5196 ;; 5197 ;; On EV5, these instructions act as a normal load, and thus can trap 5198 ;; if the address is invalid. The OS may (or may not) handle this in 5199 ;; the entMM fault handler and suppress the fault. If so, then this 5200 ;; has the effect of a read prefetch instruction. 5201 ;; 5202 ;; On EV6, these become official prefetch instructions. 5203 5204 (define_insn "prefetch" 5205 [(prefetch (match_operand:DI 0 "address_operand" "p") 5206 (match_operand:DI 1 "const_int_operand" "n") 5207 (match_operand:DI 2 "const_int_operand" "n"))] 5208 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5209 { 5210 /* Interpret "no temporal locality" as this data should be evicted once 5211 it is used. The "evict next" alternatives load the data into the cache 5212 and leave the LRU eviction counter pointing to that block. */ 5213 static const char * const alt[2][2] = { 5214 { 5215 "ldq $31,%a0", /* read, evict next */ 5216 "ldl $31,%a0", /* read, evict last */ 5217 }, 5218 { 5219 "ldt $f31,%a0", /* write, evict next */ 5220 "lds $f31,%a0", /* write, evict last */ 5221 } 5222 }; 5223 5224 bool write = INTVAL (operands[1]) != 0; 5225 bool lru = INTVAL (operands[2]) != 0; 5226 5227 return alt[write][lru]; 5228 } 5229 [(set_attr "type" "ild")]) 5230 5231 ;; Close the trap shadow of preceding instructions. This is generated 5232 ;; by alpha_reorg. 5233 5234 (define_insn "trapb" 5235 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5236 "" 5237 "trapb" 5238 [(set_attr "type" "misc")]) 5239 5240 ;; No-op instructions used by machine-dependent reorg to preserve 5241 ;; alignment for instruction issue. 5242 ;; The Unicos/Mk assembler does not support these opcodes. 5243 5244 (define_insn "nop" 5245 [(const_int 0)] 5246 "" 5247 "bis $31,$31,$31" 5248 [(set_attr "type" "ilog")]) 5249 5250 (define_insn "fnop" 5251 [(const_int 1)] 5252 "TARGET_FP" 5253 "cpys $f31,$f31,$f31" 5254 [(set_attr "type" "fcpys")]) 5255 5256 (define_insn "unop" 5257 [(const_int 2)] 5258 "" 5259 "ldq_u $31,0($30)") 5260 5261 (define_insn "realign" 5262 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5263 UNSPECV_REALIGN)] 5264 "" 5265 ".align %0 #realign") 5266 5268 ;; Instructions to be emitted from __builtins. 5269 5270 (define_insn "builtin_cmpbge" 5271 [(set (match_operand:DI 0 "register_operand" "=r") 5272 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5273 (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5274 UNSPEC_CMPBGE))] 5275 "" 5276 "cmpbge %r1,%2,%0" 5277 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5278 ;; actually differentiate between ILOG and ICMP in the schedule. 5279 [(set_attr "type" "icmp")]) 5280 5281 (define_expand "extbl" 5282 [(match_operand:DI 0 "register_operand") 5283 (match_operand:DI 1 "reg_or_0_operand") 5284 (match_operand:DI 2 "reg_or_8bit_operand")] 5285 "" 5286 { 5287 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5288 DONE; 5289 }) 5290 5291 (define_expand "extwl" 5292 [(match_operand:DI 0 "register_operand") 5293 (match_operand:DI 1 "reg_or_0_operand") 5294 (match_operand:DI 2 "reg_or_8bit_operand")] 5295 "" 5296 { 5297 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5298 DONE; 5299 }) 5300 5301 (define_expand "extll" 5302 [(match_operand:DI 0 "register_operand") 5303 (match_operand:DI 1 "reg_or_0_operand") 5304 (match_operand:DI 2 "reg_or_8bit_operand")] 5305 "" 5306 { 5307 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5308 DONE; 5309 }) 5310 5311 (define_expand "extql" 5312 [(match_operand:DI 0 "register_operand") 5313 (match_operand:DI 1 "reg_or_0_operand") 5314 (match_operand:DI 2 "reg_or_8bit_operand")] 5315 "" 5316 { 5317 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5318 DONE; 5319 }) 5320 5321 (define_expand "builtin_insbl" 5322 [(match_operand:DI 0 "register_operand") 5323 (match_operand:DI 1 "register_operand") 5324 (match_operand:DI 2 "reg_or_8bit_operand")] 5325 "" 5326 { 5327 operands[1] = gen_lowpart (QImode, operands[1]); 5328 emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5329 DONE; 5330 }) 5331 5332 (define_expand "builtin_inswl" 5333 [(match_operand:DI 0 "register_operand") 5334 (match_operand:DI 1 "register_operand") 5335 (match_operand:DI 2 "reg_or_8bit_operand")] 5336 "" 5337 { 5338 operands[1] = gen_lowpart (HImode, operands[1]); 5339 emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5340 DONE; 5341 }) 5342 5343 (define_expand "builtin_insll" 5344 [(match_operand:DI 0 "register_operand") 5345 (match_operand:DI 1 "register_operand") 5346 (match_operand:DI 2 "reg_or_8bit_operand")] 5347 "" 5348 { 5349 operands[1] = gen_lowpart (SImode, operands[1]); 5350 emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5351 DONE; 5352 }) 5353 5354 (define_expand "inswh" 5355 [(match_operand:DI 0 "register_operand") 5356 (match_operand:DI 1 "register_operand") 5357 (match_operand:DI 2 "reg_or_8bit_operand")] 5358 "" 5359 { 5360 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5361 DONE; 5362 }) 5363 5364 (define_expand "inslh" 5365 [(match_operand:DI 0 "register_operand") 5366 (match_operand:DI 1 "register_operand") 5367 (match_operand:DI 2 "reg_or_8bit_operand")] 5368 "" 5369 { 5370 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5371 DONE; 5372 }) 5373 5374 (define_expand "insqh" 5375 [(match_operand:DI 0 "register_operand") 5376 (match_operand:DI 1 "register_operand") 5377 (match_operand:DI 2 "reg_or_8bit_operand")] 5378 "" 5379 { 5380 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5381 DONE; 5382 }) 5383 5384 (define_expand "mskbl" 5385 [(match_operand:DI 0 "register_operand") 5386 (match_operand:DI 1 "reg_or_0_operand") 5387 (match_operand:DI 2 "reg_or_8bit_operand")] 5388 "" 5389 { 5390 rtx mask = GEN_INT (0xff); 5391 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5392 DONE; 5393 }) 5394 5395 (define_expand "mskwl" 5396 [(match_operand:DI 0 "register_operand") 5397 (match_operand:DI 1 "reg_or_0_operand") 5398 (match_operand:DI 2 "reg_or_8bit_operand")] 5399 "" 5400 { 5401 rtx mask = GEN_INT (0xffff); 5402 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5403 DONE; 5404 }) 5405 5406 (define_expand "mskll" 5407 [(match_operand:DI 0 "register_operand") 5408 (match_operand:DI 1 "reg_or_0_operand") 5409 (match_operand:DI 2 "reg_or_8bit_operand")] 5410 "" 5411 { 5412 rtx mask = gen_int_mode (0xffffffff, DImode); 5413 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5414 DONE; 5415 }) 5416 5417 (define_expand "mskql" 5418 [(match_operand:DI 0 "register_operand") 5419 (match_operand:DI 1 "reg_or_0_operand") 5420 (match_operand:DI 2 "reg_or_8bit_operand")] 5421 "" 5422 { 5423 rtx mask = constm1_rtx; 5424 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5425 DONE; 5426 }) 5427 5428 (define_expand "mskwh" 5429 [(match_operand:DI 0 "register_operand") 5430 (match_operand:DI 1 "register_operand") 5431 (match_operand:DI 2 "reg_or_8bit_operand")] 5432 "" 5433 { 5434 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5435 DONE; 5436 }) 5437 5438 (define_expand "msklh" 5439 [(match_operand:DI 0 "register_operand") 5440 (match_operand:DI 1 "register_operand") 5441 (match_operand:DI 2 "reg_or_8bit_operand")] 5442 "" 5443 { 5444 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5445 DONE; 5446 }) 5447 5448 (define_expand "mskqh" 5449 [(match_operand:DI 0 "register_operand") 5450 (match_operand:DI 1 "register_operand") 5451 (match_operand:DI 2 "reg_or_8bit_operand")] 5452 "" 5453 { 5454 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5455 DONE; 5456 }) 5457 5458 (define_expand "builtin_zap" 5459 [(set (match_operand:DI 0 "register_operand") 5460 (and:DI (unspec:DI 5461 [(match_operand:DI 2 "reg_or_cint_operand")] 5462 UNSPEC_ZAP) 5463 (match_operand:DI 1 "reg_or_cint_operand")))] 5464 "" 5465 { 5466 if (CONST_INT_P (operands[2])) 5467 { 5468 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5469 5470 if (mask == const0_rtx) 5471 { 5472 emit_move_insn (operands[0], const0_rtx); 5473 DONE; 5474 } 5475 if (mask == constm1_rtx) 5476 { 5477 emit_move_insn (operands[0], operands[1]); 5478 DONE; 5479 } 5480 5481 operands[1] = force_reg (DImode, operands[1]); 5482 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5483 DONE; 5484 } 5485 5486 operands[1] = force_reg (DImode, operands[1]); 5487 operands[2] = gen_lowpart (QImode, operands[2]); 5488 }) 5489 5490 (define_insn "*builtin_zap_1" 5491 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5492 (and:DI (unspec:DI 5493 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5494 UNSPEC_ZAP) 5495 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5496 "" 5497 "@ 5498 # 5499 # 5500 bis $31,$31,%0 5501 zap %r1,%2,%0" 5502 [(set_attr "type" "shift,shift,ilog,shift")]) 5503 5504 (define_split 5505 [(set (match_operand:DI 0 "register_operand") 5506 (and:DI (unspec:DI 5507 [(match_operand:QI 2 "const_int_operand")] 5508 UNSPEC_ZAP) 5509 (match_operand:DI 1 "const_int_operand")))] 5510 "" 5511 [(const_int 0)] 5512 { 5513 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5514 5515 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5516 emit_move_insn (operands[0], operands[1]); 5517 DONE; 5518 }) 5519 5520 (define_split 5521 [(set (match_operand:DI 0 "register_operand") 5522 (and:DI (unspec:DI 5523 [(match_operand:QI 2 "const_int_operand")] 5524 UNSPEC_ZAP) 5525 (match_operand:DI 1 "register_operand")))] 5526 "" 5527 [(set (match_dup 0) 5528 (and:DI (match_dup 1) (match_dup 2)))] 5529 { 5530 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5531 if (operands[2] == const0_rtx) 5532 { 5533 emit_move_insn (operands[0], const0_rtx); 5534 DONE; 5535 } 5536 if (operands[2] == constm1_rtx) 5537 { 5538 emit_move_insn (operands[0], operands[1]); 5539 DONE; 5540 } 5541 }) 5542 5543 (define_expand "builtin_zapnot" 5544 [(set (match_operand:DI 0 "register_operand") 5545 (and:DI (unspec:DI 5546 [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5547 UNSPEC_ZAP) 5548 (match_operand:DI 1 "reg_or_cint_operand")))] 5549 "" 5550 { 5551 if (CONST_INT_P (operands[2])) 5552 { 5553 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5554 5555 if (mask == const0_rtx) 5556 { 5557 emit_move_insn (operands[0], const0_rtx); 5558 DONE; 5559 } 5560 if (mask == constm1_rtx) 5561 { 5562 emit_move_insn (operands[0], operands[1]); 5563 DONE; 5564 } 5565 5566 operands[1] = force_reg (DImode, operands[1]); 5567 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5568 DONE; 5569 } 5570 5571 operands[1] = force_reg (DImode, operands[1]); 5572 operands[2] = gen_lowpart (QImode, operands[2]); 5573 }) 5574 5575 (define_insn "*builtin_zapnot_1" 5576 [(set (match_operand:DI 0 "register_operand" "=r") 5577 (and:DI (unspec:DI 5578 [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5579 UNSPEC_ZAP) 5580 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5581 "" 5582 "zapnot %r1,%2,%0" 5583 [(set_attr "type" "shift")]) 5584 5585 (define_insn "builtin_amask" 5586 [(set (match_operand:DI 0 "register_operand" "=r") 5587 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5588 UNSPEC_AMASK))] 5589 "" 5590 "amask %1,%0" 5591 [(set_attr "type" "ilog")]) 5592 5593 (define_insn "builtin_implver" 5594 [(set (match_operand:DI 0 "register_operand" "=r") 5595 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5596 "" 5597 "implver %0" 5598 [(set_attr "type" "ilog")]) 5599 5600 (define_insn "builtin_rpcc" 5601 [(set (match_operand:DI 0 "register_operand" "=r") 5602 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5603 "" 5604 "rpcc %0" 5605 [(set_attr "type" "ilog")]) 5606 5607 (define_expand "builtin_minub8" 5608 [(match_operand:DI 0 "register_operand") 5609 (match_operand:DI 1 "reg_or_0_operand") 5610 (match_operand:DI 2 "reg_or_0_operand")] 5611 "TARGET_MAX" 5612 { 5613 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5614 operands[1], operands[2]); 5615 DONE; 5616 }) 5617 5618 (define_expand "builtin_minsb8" 5619 [(match_operand:DI 0 "register_operand") 5620 (match_operand:DI 1 "reg_or_0_operand") 5621 (match_operand:DI 2 "reg_or_0_operand")] 5622 "TARGET_MAX" 5623 { 5624 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5625 operands[1], operands[2]); 5626 DONE; 5627 }) 5628 5629 (define_expand "builtin_minuw4" 5630 [(match_operand:DI 0 "register_operand") 5631 (match_operand:DI 1 "reg_or_0_operand") 5632 (match_operand:DI 2 "reg_or_0_operand")] 5633 "TARGET_MAX" 5634 { 5635 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5636 operands[1], operands[2]); 5637 DONE; 5638 }) 5639 5640 (define_expand "builtin_minsw4" 5641 [(match_operand:DI 0 "register_operand") 5642 (match_operand:DI 1 "reg_or_0_operand") 5643 (match_operand:DI 2 "reg_or_0_operand")] 5644 "TARGET_MAX" 5645 { 5646 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5647 operands[1], operands[2]); 5648 DONE; 5649 }) 5650 5651 (define_expand "builtin_maxub8" 5652 [(match_operand:DI 0 "register_operand") 5653 (match_operand:DI 1 "reg_or_0_operand") 5654 (match_operand:DI 2 "reg_or_0_operand")] 5655 "TARGET_MAX" 5656 { 5657 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5658 operands[1], operands[2]); 5659 DONE; 5660 }) 5661 5662 (define_expand "builtin_maxsb8" 5663 [(match_operand:DI 0 "register_operand") 5664 (match_operand:DI 1 "reg_or_0_operand") 5665 (match_operand:DI 2 "reg_or_0_operand")] 5666 "TARGET_MAX" 5667 { 5668 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5669 operands[1], operands[2]); 5670 DONE; 5671 }) 5672 5673 (define_expand "builtin_maxuw4" 5674 [(match_operand:DI 0 "register_operand") 5675 (match_operand:DI 1 "reg_or_0_operand") 5676 (match_operand:DI 2 "reg_or_0_operand")] 5677 "TARGET_MAX" 5678 { 5679 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5680 operands[1], operands[2]); 5681 DONE; 5682 }) 5683 5684 (define_expand "builtin_maxsw4" 5685 [(match_operand:DI 0 "register_operand") 5686 (match_operand:DI 1 "reg_or_0_operand") 5687 (match_operand:DI 2 "reg_or_0_operand")] 5688 "TARGET_MAX" 5689 { 5690 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5691 operands[1], operands[2]); 5692 DONE; 5693 }) 5694 5695 (define_insn "builtin_perr" 5696 [(set (match_operand:DI 0 "register_operand" "=r") 5697 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5698 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5699 UNSPEC_PERR))] 5700 "TARGET_MAX" 5701 "perr %r1,%r2,%0" 5702 [(set_attr "type" "mvi")]) 5703 5704 (define_expand "builtin_pklb" 5705 [(set (match_operand:DI 0 "register_operand") 5706 (vec_concat:V8QI 5707 (vec_concat:V4QI 5708 (truncate:V2QI (match_operand:DI 1 "register_operand")) 5709 (match_dup 2)) 5710 (match_dup 3)))] 5711 "TARGET_MAX" 5712 { 5713 operands[0] = gen_lowpart (V8QImode, operands[0]); 5714 operands[1] = gen_lowpart (V2SImode, operands[1]); 5715 operands[2] = CONST0_RTX (V2QImode); 5716 operands[3] = CONST0_RTX (V4QImode); 5717 }) 5718 5719 (define_insn "*pklb" 5720 [(set (match_operand:V8QI 0 "register_operand" "=r") 5721 (vec_concat:V8QI 5722 (vec_concat:V4QI 5723 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5724 (match_operand:V2QI 2 "const0_operand")) 5725 (match_operand:V4QI 3 "const0_operand")))] 5726 "TARGET_MAX" 5727 "pklb %r1,%0" 5728 [(set_attr "type" "mvi")]) 5729 5730 (define_expand "builtin_pkwb" 5731 [(set (match_operand:DI 0 "register_operand") 5732 (vec_concat:V8QI 5733 (truncate:V4QI (match_operand:DI 1 "register_operand")) 5734 (match_dup 2)))] 5735 "TARGET_MAX" 5736 { 5737 operands[0] = gen_lowpart (V8QImode, operands[0]); 5738 operands[1] = gen_lowpart (V4HImode, operands[1]); 5739 operands[2] = CONST0_RTX (V4QImode); 5740 }) 5741 5742 (define_insn "*pkwb" 5743 [(set (match_operand:V8QI 0 "register_operand" "=r") 5744 (vec_concat:V8QI 5745 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5746 (match_operand:V4QI 2 "const0_operand")))] 5747 "TARGET_MAX" 5748 "pkwb %r1,%0" 5749 [(set_attr "type" "mvi")]) 5750 5751 (define_expand "builtin_unpkbl" 5752 [(set (match_operand:DI 0 "register_operand") 5753 (zero_extend:V2SI 5754 (vec_select:V2QI (match_operand:DI 1 "register_operand") 5755 (parallel [(const_int 0) (const_int 1)]))))] 5756 "TARGET_MAX" 5757 { 5758 operands[0] = gen_lowpart (V2SImode, operands[0]); 5759 operands[1] = gen_lowpart (V8QImode, operands[1]); 5760 }) 5761 5762 (define_insn "*unpkbl" 5763 [(set (match_operand:V2SI 0 "register_operand" "=r") 5764 (zero_extend:V2SI 5765 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5766 (parallel [(const_int 0) (const_int 1)]))))] 5767 "TARGET_MAX" 5768 "unpkbl %r1,%0" 5769 [(set_attr "type" "mvi")]) 5770 5771 (define_expand "builtin_unpkbw" 5772 [(set (match_operand:DI 0 "register_operand") 5773 (zero_extend:V4HI 5774 (vec_select:V4QI (match_operand:DI 1 "register_operand") 5775 (parallel [(const_int 0) 5776 (const_int 1) 5777 (const_int 2) 5778 (const_int 3)]))))] 5779 "TARGET_MAX" 5780 { 5781 operands[0] = gen_lowpart (V4HImode, operands[0]); 5782 operands[1] = gen_lowpart (V8QImode, operands[1]); 5783 }) 5784 5785 (define_insn "*unpkbw" 5786 [(set (match_operand:V4HI 0 "register_operand" "=r") 5787 (zero_extend:V4HI 5788 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5789 (parallel [(const_int 0) 5790 (const_int 1) 5791 (const_int 2) 5792 (const_int 3)]))))] 5793 "TARGET_MAX" 5794 "unpkbw %r1,%0" 5795 [(set_attr "type" "mvi")]) 5796 5798 (include "sync.md") 5799 5801 ;; The call patterns are at the end of the file because their 5802 ;; wildcard operand0 interferes with nice recognition. 5803 5804 (define_insn "*call_value_osf_1_er_noreturn" 5805 [(set (match_operand 0) 5806 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5807 (match_operand 2))) 5808 (use (reg:DI 29)) 5809 (clobber (reg:DI 26))] 5810 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5811 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5812 "@ 5813 jsr $26,($27),0 5814 bsr $26,%1\t\t!samegp 5815 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5816 [(set_attr "type" "jsr") 5817 (set_attr "length" "*,*,8")]) 5818 5819 (define_insn "*call_value_osf_1_er" 5820 [(set (match_operand 0) 5821 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5822 (match_operand 2))) 5823 (use (reg:DI 29)) 5824 (clobber (reg:DI 26))] 5825 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5826 "@ 5827 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5828 bsr $26,%1\t\t!samegp 5829 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5830 [(set_attr "type" "jsr") 5831 (set_attr "length" "12,*,16")]) 5832 5833 ;; We must use peep2 instead of a split because we need accurate life 5834 ;; information for $gp. Consider the case of { bar(); while (1); }. 5835 (define_peephole2 5836 [(parallel [(set (match_operand 0) 5837 (call (mem:DI (match_operand:DI 1 "call_operand")) 5838 (match_operand 2))) 5839 (use (reg:DI 29)) 5840 (clobber (reg:DI 26))])] 5841 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5842 && ! samegp_function_operand (operands[1], Pmode) 5843 && (peep2_regno_dead_p (1, 29) 5844 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5845 [(parallel [(set (match_dup 0) 5846 (call (mem:DI (match_dup 3)) 5847 (match_dup 2))) 5848 (use (reg:DI 29)) 5849 (use (match_dup 1)) 5850 (use (match_dup 4)) 5851 (clobber (reg:DI 26))])] 5852 { 5853 if (CONSTANT_P (operands[1])) 5854 { 5855 operands[3] = gen_rtx_REG (Pmode, 27); 5856 operands[4] = GEN_INT (alpha_next_sequence_number++); 5857 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5858 operands[1], operands[4])); 5859 } 5860 else 5861 { 5862 operands[3] = operands[1]; 5863 operands[1] = const0_rtx; 5864 operands[4] = const0_rtx; 5865 } 5866 }) 5867 5868 (define_peephole2 5869 [(parallel [(set (match_operand 0) 5870 (call (mem:DI (match_operand:DI 1 "call_operand")) 5871 (match_operand 2))) 5872 (use (reg:DI 29)) 5873 (clobber (reg:DI 26))])] 5874 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5875 && ! samegp_function_operand (operands[1], Pmode) 5876 && ! (peep2_regno_dead_p (1, 29) 5877 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5878 [(parallel [(set (match_dup 0) 5879 (call (mem:DI (match_dup 3)) 5880 (match_dup 2))) 5881 (set (match_dup 6) 5882 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5883 (use (match_dup 1)) 5884 (use (match_dup 5)) 5885 (clobber (reg:DI 26))]) 5886 (set (match_dup 6) 5887 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5888 { 5889 if (CONSTANT_P (operands[1])) 5890 { 5891 operands[3] = gen_rtx_REG (Pmode, 27); 5892 operands[5] = GEN_INT (alpha_next_sequence_number++); 5893 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5894 operands[1], operands[5])); 5895 } 5896 else 5897 { 5898 operands[3] = operands[1]; 5899 operands[1] = const0_rtx; 5900 operands[5] = const0_rtx; 5901 } 5902 operands[4] = GEN_INT (alpha_next_sequence_number++); 5903 operands[6] = pic_offset_table_rtx; 5904 }) 5905 5906 (define_insn "*call_value_osf_2_er_nogp" 5907 [(set (match_operand 0) 5908 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5909 (match_operand 2))) 5910 (use (reg:DI 29)) 5911 (use (match_operand 3)) 5912 (use (match_operand 4)) 5913 (clobber (reg:DI 26))] 5914 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5915 "jsr $26,(%1),%3%J4" 5916 [(set_attr "type" "jsr")]) 5917 5918 (define_insn "*call_value_osf_2_er" 5919 [(set (match_operand 0) 5920 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5921 (match_operand 2))) 5922 (set (reg:DI 29) 5923 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5924 UNSPEC_LDGP1)) 5925 (use (match_operand 3)) 5926 (use (match_operand 4)) 5927 (clobber (reg:DI 26))] 5928 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5929 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5930 [(set_attr "type" "jsr") 5931 (set_attr "cannot_copy" "true") 5932 (set_attr "length" "8")]) 5933 5934 (define_insn "*call_value_osf_1_noreturn" 5935 [(set (match_operand 0) 5936 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5937 (match_operand 2))) 5938 (use (reg:DI 29)) 5939 (clobber (reg:DI 26))] 5940 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5941 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5942 "@ 5943 jsr $26,($27),0 5944 bsr $26,$%1..ng 5945 jsr $26,%1" 5946 [(set_attr "type" "jsr") 5947 (set_attr "length" "*,*,8")]) 5948 5949 (define_int_iterator TLS_CALL 5950 [UNSPEC_TLSGD_CALL 5951 UNSPEC_TLSLDM_CALL]) 5952 5953 (define_int_attr tls 5954 [(UNSPEC_TLSGD_CALL "tlsgd") 5955 (UNSPEC_TLSLDM_CALL "tlsldm")]) 5956 5957 (define_insn "call_value_osf_<tls>" 5958 [(set (match_operand 0) 5959 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5960 (const_int 0))) 5961 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5962 (use (reg:DI 29)) 5963 (clobber (reg:DI 26))] 5964 "HAVE_AS_TLS" 5965 "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5966 [(set_attr "type" "jsr") 5967 (set_attr "cannot_copy" "true") 5968 (set_attr "length" "16")]) 5969 5970 ;; We must use peep2 instead of a split because we need accurate life 5971 ;; information for $gp. 5972 (define_peephole2 5973 [(parallel 5974 [(set (match_operand 0) 5975 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5976 (const_int 0))) 5977 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5978 (use (reg:DI 29)) 5979 (clobber (reg:DI 26))])] 5980 "HAVE_AS_TLS && reload_completed 5981 && peep2_regno_dead_p (1, 29)" 5982 [(set (match_dup 3) 5983 (unspec:DI [(match_dup 5) 5984 (match_dup 1) 5985 (match_dup 2)] UNSPEC_LITERAL)) 5986 (parallel [(set (match_dup 0) 5987 (call (mem:DI (match_dup 3)) 5988 (const_int 0))) 5989 (use (match_dup 5)) 5990 (use (match_dup 1)) 5991 (use (unspec [(match_dup 2)] TLS_CALL)) 5992 (clobber (reg:DI 26))]) 5993 (set (match_dup 5) 5994 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 5995 { 5996 operands[3] = gen_rtx_REG (Pmode, 27); 5997 operands[4] = GEN_INT (alpha_next_sequence_number++); 5998 operands[5] = pic_offset_table_rtx; 5999 }) 6000 6001 (define_peephole2 6002 [(parallel 6003 [(set (match_operand 0) 6004 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 6005 (const_int 0))) 6006 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6007 (use (reg:DI 29)) 6008 (clobber (reg:DI 26))])] 6009 "HAVE_AS_TLS && reload_completed 6010 && !peep2_regno_dead_p (1, 29)" 6011 [(set (match_dup 3) 6012 (unspec:DI [(match_dup 5) 6013 (match_dup 1) 6014 (match_dup 2)] UNSPEC_LITERAL)) 6015 (parallel [(set (match_dup 0) 6016 (call (mem:DI (match_dup 3)) 6017 (const_int 0))) 6018 (set (match_dup 5) 6019 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6020 (use (match_dup 1)) 6021 (use (unspec [(match_dup 2)] TLS_CALL)) 6022 (clobber (reg:DI 26))]) 6023 (set (match_dup 5) 6024 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6025 { 6026 operands[3] = gen_rtx_REG (Pmode, 27); 6027 operands[4] = GEN_INT (alpha_next_sequence_number++); 6028 operands[5] = pic_offset_table_rtx; 6029 }) 6030 6031 (define_insn "*call_value_osf_1" 6032 [(set (match_operand 0) 6033 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6034 (match_operand 2))) 6035 (use (reg:DI 29)) 6036 (clobber (reg:DI 26))] 6037 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6038 "@ 6039 jsr $26,($27),0\;ldgp $29,0($26) 6040 bsr $26,$%1..ng 6041 jsr $26,%1\;ldgp $29,0($26)" 6042 [(set_attr "type" "jsr") 6043 (set_attr "length" "12,*,16")]) 6044 6045 (define_insn "*sibcall_value_osf_1_er" 6046 [(set (match_operand 0) 6047 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6048 (match_operand 2))) 6049 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6050 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6051 "@ 6052 br $31,%1\t\t!samegp 6053 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6054 [(set_attr "type" "jsr") 6055 (set_attr "length" "*,8")]) 6056 6057 (define_insn "*sibcall_value_osf_1" 6058 [(set (match_operand 0) 6059 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6060 (match_operand 2))) 6061 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6062 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6063 "@ 6064 br $31,$%1..ng 6065 lda $27,%1\;jmp $31,($27),%1" 6066 [(set_attr "type" "jsr") 6067 (set_attr "length" "*,8")]) 6068 6069 ; GAS relies on the order and position of instructions output below in order 6070 ; to generate relocs for VMS link to potentially optimize the call. 6071 ; Please do not molest. 6072 (define_insn "*call_value_vms_1" 6073 [(set (match_operand 0) 6074 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6075 (match_operand 2))) 6076 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6077 (use (reg:DI 25)) 6078 (use (reg:DI 26)) 6079 (clobber (reg:DI 27))] 6080 "TARGET_ABI_OPEN_VMS" 6081 { 6082 switch (which_alternative) 6083 { 6084 case 0: 6085 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6086 case 1: 6087 operands [3] = alpha_use_linkage (operands [1], true, false); 6088 operands [4] = alpha_use_linkage (operands [1], false, false); 6089 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6090 default: 6091 gcc_unreachable (); 6092 } 6093 } 6094 [(set_attr "type" "jsr") 6095 (set_attr "length" "12,16")]) 6096
Indexes created Thu Sep 10 00:26:39 UTC 2026