alpha.md revision 1.1.1.8
1 ;; Machine description for DEC Alpha for GNU C compiler 2 ;; Copyright (C) 1992-2019 Free Software Foundation, Inc. 3 ;; Contributed by Richard Kenner (kenner (a] vlsi1.ultra.nyu.edu) 4 ;; 5 ;; This file is part of GCC. 6 ;; 7 ;; GCC is free software; you can redistribute it and/or modify 8 ;; it under the terms of the GNU General Public License as published by 9 ;; the Free Software Foundation; either version 3, or (at your option) 10 ;; any later version. 11 ;; 12 ;; GCC is distributed in the hope that it will be useful, 13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 ;; GNU General Public License for more details. 16 ;; 17 ;; You should have received a copy of the GNU General Public License 18 ;; along with GCC; see the file COPYING3. If not see 19 ;; <http://www.gnu.org/licenses/>. 20 21 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 23 ;; Uses of UNSPEC in this file: 24 25 (define_c_enum "unspec" [ 26 UNSPEC_XFLT_COMPARE 27 UNSPEC_ARG_HOME 28 UNSPEC_LDGP1 29 UNSPEC_INSXH 30 UNSPEC_MSKXH 31 UNSPEC_CVTQL 32 UNSPEC_CVTLQ 33 UNSPEC_LDGP2 34 UNSPEC_LITERAL 35 UNSPEC_LITUSE 36 UNSPEC_SIBCALL 37 UNSPEC_SYMBOL 38 39 ;; TLS Support 40 UNSPEC_TLSGD_CALL 41 UNSPEC_TLSLDM_CALL 42 UNSPEC_TLSGD 43 UNSPEC_TLSLDM 44 UNSPEC_DTPREL 45 UNSPEC_TPREL 46 UNSPEC_TP 47 48 ;; Builtins 49 UNSPEC_CMPBGE 50 UNSPEC_ZAP 51 UNSPEC_AMASK 52 UNSPEC_IMPLVER 53 UNSPEC_PERR 54 UNSPEC_COPYSIGN 55 56 ;; Atomic operations 57 UNSPEC_MB 58 UNSPEC_ATOMIC 59 UNSPEC_CMPXCHG 60 UNSPEC_XCHG 61 ]) 62 63 ;; UNSPEC_VOLATILE: 64 65 (define_c_enum "unspecv" [ 66 UNSPECV_IMB 67 UNSPECV_BLOCKAGE 68 UNSPECV_SETJMPR ; builtin_setjmp_receiver 69 UNSPECV_LONGJMP ; builtin_longjmp 70 UNSPECV_TRAPB 71 UNSPECV_PSPL ; prologue_stack_probe_loop 72 UNSPECV_REALIGN 73 UNSPECV_EHR ; exception_receiver 74 UNSPECV_MCOUNT 75 UNSPECV_FORCE_MOV 76 UNSPECV_LDGP1 77 UNSPECV_PLDGP2 ; prologue ldgp 78 UNSPECV_SET_TP 79 UNSPECV_RPCC 80 UNSPECV_SETJMPR_ER ; builtin_setjmp_receiver fragment 81 UNSPECV_LL ; load-locked 82 UNSPECV_SC ; store-conditional 83 UNSPECV_CMPXCHG 84 ]) 85 86 ;; On non-BWX targets, CQImode must be handled the similarly to HImode 87 ;; when generating reloads. 88 (define_mode_iterator RELOAD12 [QI HI CQI]) 89 (define_mode_attr reloadmode [(QI "qi") (HI "hi") (CQI "hi")]) 90 91 ;; Other mode iterators 92 (define_mode_iterator IMODE [QI HI SI DI]) 93 (define_mode_iterator I12MODE [QI HI]) 94 (define_mode_iterator I124MODE [QI HI SI]) 95 (define_mode_iterator I24MODE [HI SI]) 96 (define_mode_iterator I248MODE [HI SI DI]) 97 (define_mode_iterator I48MODE [SI DI]) 98 99 (define_mode_attr DWI [(SI "DI") (DI "TI")]) 100 (define_mode_attr modesuffix [(QI "b") (HI "w") (SI "l") (DI "q") 101 (V8QI "b8") (V4HI "w4") 102 (SF "%,") (DF "%-")]) 103 (define_mode_attr vecmodesuffix [(QI "b8") (HI "w4")]) 104 105 (define_code_iterator any_maxmin [smax smin umax umin]) 106 107 (define_code_attr maxmin [(smax "maxs") (smin "mins") 108 (umax "maxu") (umin "minu")]) 109 110 ;; Where necessary, the suffixes _le and _be are used to distinguish between 111 ;; little-endian and big-endian patterns. 112 ;; 113 ;; Note that the Unicos/Mk assembler does not support the following 114 ;; opcodes: mov, fmov, nop, fnop, unop. 115 117 ;; Processor type -- this attribute must exactly match the processor_type 118 ;; enumeration in alpha.h. 119 120 (define_attr "tune" "ev4,ev5,ev6" 121 (const (symbol_ref "((enum attr_tune) alpha_tune)"))) 122 123 ;; Define an insn type attribute. This is used in function unit delay 124 ;; computations, among other purposes. For the most part, we use the names 125 ;; defined in the EV4 documentation, but add a few that we have to know about 126 ;; separately. 127 128 (define_attr "type" 129 "ild,fld,ldsym,ist,fst,ibr,callpal,fbr,jsr,iadd,ilog,shift,icmov,fcmov, 130 icmp,imul,fadd,fmul,fcpys,fdiv,fsqrt,misc,mvi,ftoi,itof,mb,ld_l,st_c, 131 multi,none" 132 (const_string "iadd")) 133 134 ;; Describe a user's asm statement. 135 (define_asm_attributes 136 [(set_attr "type" "multi")]) 137 138 ;; Define the operand size an insn operates on. Used primarily by mul 139 ;; and div operations that have size dependent timings. 140 141 (define_attr "opsize" "si,di,udi" 142 (const_string "di")) 143 144 ;; The TRAP attribute marks instructions that may generate traps 145 ;; (which are imprecise and may need a trapb if software completion 146 ;; is desired). 147 148 (define_attr "trap" "no,yes" 149 (const_string "no")) 150 151 ;; The ROUND_SUFFIX attribute marks which instructions require a 152 ;; rounding-mode suffix. The value NONE indicates no suffix, 153 ;; the value NORMAL indicates a suffix controlled by alpha_fprm. 154 155 (define_attr "round_suffix" "none,normal,c" 156 (const_string "none")) 157 158 ;; The TRAP_SUFFIX attribute marks instructions requiring a trap-mode suffix: 159 ;; NONE no suffix 160 ;; SU accepts only /su (cmpt et al) 161 ;; SUI accepts only /sui (cvtqt and cvtqs) 162 ;; V_SV accepts /v and /sv (cvtql only) 163 ;; V_SV_SVI accepts /v, /sv and /svi (cvttq only) 164 ;; U_SU_SUI accepts /u, /su and /sui (most fp instructions) 165 ;; 166 ;; The actual suffix emitted is controlled by alpha_fptm. 167 168 (define_attr "trap_suffix" "none,su,sui,v_sv,v_sv_svi,u_su_sui" 169 (const_string "none")) 170 171 ;; The length of an instruction sequence in bytes. 172 173 (define_attr "length" "" 174 (const_int 4)) 175 176 ;; The USEGP attribute marks instructions that have relocations that use 177 ;; the GP. 178 179 (define_attr "usegp" "no,yes" 180 (cond [(eq_attr "type" "ldsym,jsr") 181 (const_string "yes") 182 (eq_attr "type" "ild,fld,ist,fst") 183 (symbol_ref "((enum attr_usegp) alpha_find_lo_sum_using_gp (insn))") 184 ] 185 (const_string "no"))) 186 187 ;; The CANNOT_COPY attribute marks instructions with relocations that 188 ;; cannot easily be duplicated. This includes insns with gpdisp relocs 189 ;; since they have to stay in 1-1 correspondence with one another. This 190 ;; also includes jsr insns, since they must stay in correspondence with 191 ;; the immediately following gpdisp instructions. 192 193 (define_attr "cannot_copy" "false,true" 194 (const_string "false")) 195 196 ;; Used to control the "enabled" attribute on a per-instruction basis. 197 ;; For convenience, conflate ABI issues re loading of addresses with 198 ;; an "isa". 199 (define_attr "isa" "base,bwx,max,fix,cix,vms,ner,er" 200 (const_string "base")) 201 202 (define_attr "enabled" "" 203 (cond [(eq_attr "isa" "bwx") (symbol_ref "TARGET_BWX") 204 (eq_attr "isa" "max") (symbol_ref "TARGET_MAX") 205 (eq_attr "isa" "fix") (symbol_ref "TARGET_FIX") 206 (eq_attr "isa" "cix") (symbol_ref "TARGET_CIX") 207 (eq_attr "isa" "vms") (symbol_ref "TARGET_ABI_OPEN_VMS") 208 (eq_attr "isa" "ner") (symbol_ref "!TARGET_EXPLICIT_RELOCS") 209 (eq_attr "isa" "er") (symbol_ref "TARGET_EXPLICIT_RELOCS") 210 ] 211 (const_int 1))) 212 214 ;; Include scheduling descriptions. 215 216 (include "ev4.md") 217 (include "ev5.md") 218 (include "ev6.md") 219 220 222 ;; Operand and operator predicates and constraints 223 224 (include "predicates.md") 225 (include "constraints.md") 226 227 229 ;; First define the arithmetic insns. Note that the 32-bit forms also 230 ;; sign-extend. 231 232 ;; Handle 32-64 bit extension from memory to a floating point register 233 ;; specially, since this occurs frequently in int->double conversions. 234 ;; 235 ;; Note that while we must retain the =f case in the insn for reload's 236 ;; benefit, it should be eliminated after reload, so we should never emit 237 ;; code for that case. But we don't reject the possibility. 238 239 (define_expand "extendsidi2" 240 [(set (match_operand:DI 0 "register_operand") 241 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand")))]) 242 243 (define_insn "*cvtlq" 244 [(set (match_operand:DI 0 "register_operand" "=f") 245 (unspec:DI [(match_operand:SF 1 "reg_or_0_operand" "fG")] 246 UNSPEC_CVTLQ))] 247 "" 248 "cvtlq %1,%0" 249 [(set_attr "type" "fadd")]) 250 251 (define_insn "*extendsidi2_1" 252 [(set (match_operand:DI 0 "register_operand" "=r,r,!*f") 253 (sign_extend:DI 254 (match_operand:SI 1 "nonimmediate_operand" "r,m,m")))] 255 "" 256 "@ 257 addl $31,%1,%0 258 ldl %0,%1 259 lds %0,%1\;cvtlq %0,%0" 260 [(set_attr "type" "iadd,ild,fld") 261 (set_attr "length" "*,*,8")]) 262 263 (define_split 264 [(set (match_operand:DI 0 "hard_fp_register_operand") 265 (sign_extend:DI (match_operand:SI 1 "memory_operand")))] 266 "reload_completed" 267 [(set (match_dup 2) (match_dup 1)) 268 (set (match_dup 0) (unspec:DI [(match_dup 2)] UNSPEC_CVTLQ))] 269 { 270 operands[1] = adjust_address (operands[1], SFmode, 0); 271 operands[2] = gen_rtx_REG (SFmode, REGNO (operands[0])); 272 }) 273 274 ;; Optimize sign-extension of SImode loads. This shows up in the wake of 275 ;; reload when converting fp->int. 276 277 (define_peephole2 278 [(set (match_operand:SI 0 "hard_int_register_operand") 279 (match_operand:SI 1 "memory_operand")) 280 (set (match_operand:DI 2 "hard_int_register_operand") 281 (sign_extend:DI (match_dup 0)))] 282 "true_regnum (operands[0]) == true_regnum (operands[2]) 283 || peep2_reg_dead_p (2, operands[0])" 284 [(set (match_dup 2) 285 (sign_extend:DI (match_dup 1)))]) 286 287 (define_insn "addsi3" 288 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 289 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ,rJ") 290 (match_operand:SI 2 "add_operand" "rI,O,K,L")))] 291 "" 292 "@ 293 addl %r1,%2,%0 294 subl %r1,%n2,%0 295 lda %0,%2(%r1) 296 ldah %0,%h2(%r1)") 297 298 (define_split 299 [(set (match_operand:SI 0 "register_operand") 300 (plus:SI (match_operand:SI 1 "register_operand") 301 (match_operand:SI 2 "const_int_operand")))] 302 "! add_operand (operands[2], SImode)" 303 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) 304 (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] 305 { 306 HOST_WIDE_INT val = INTVAL (operands[2]); 307 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 308 HOST_WIDE_INT rest = val - low; 309 310 operands[3] = GEN_INT (rest); 311 operands[4] = GEN_INT (low); 312 }) 313 314 (define_insn "*addsi_se" 315 [(set (match_operand:DI 0 "register_operand" "=r,r") 316 (sign_extend:DI 317 (plus:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 318 (match_operand:SI 2 "sext_add_operand" "rI,O"))))] 319 "" 320 "@ 321 addl %r1,%2,%0 322 subl %r1,%n2,%0") 323 324 (define_insn "*addsi_se2" 325 [(set (match_operand:DI 0 "register_operand" "=r,r") 326 (sign_extend:DI 327 (subreg:SI (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 328 (match_operand:DI 2 "sext_add_operand" "rI,O")) 329 0)))] 330 "" 331 "@ 332 addl %r1,%2,%0 333 subl %r1,%n2,%0") 334 335 (define_split 336 [(set (match_operand:DI 0 "register_operand") 337 (sign_extend:DI 338 (plus:SI (match_operand:SI 1 "reg_not_elim_operand") 339 (match_operand:SI 2 "const_int_operand")))) 340 (clobber (match_operand:SI 3 "reg_not_elim_operand"))] 341 "! sext_add_operand (operands[2], SImode) && INTVAL (operands[2]) > 0 342 && INTVAL (operands[2]) % 4 == 0" 343 [(set (match_dup 3) (match_dup 4)) 344 (set (match_dup 0) (sign_extend:DI (plus:SI (ashift:SI (match_dup 3) 345 (match_dup 5)) 346 (match_dup 1))))] 347 { 348 HOST_WIDE_INT val = INTVAL (operands[2]) / 4; 349 int mult = 4; 350 351 if (val % 2 == 0) 352 val /= 2, mult = 8; 353 354 operands[4] = GEN_INT (val); 355 operands[5] = GEN_INT (exact_log2 (mult)); 356 }) 357 358 (define_split 359 [(set (match_operand:DI 0 "register_operand") 360 (sign_extend:DI 361 (plus:SI (match_operator:SI 1 "comparison_operator" 362 [(match_operand 2) 363 (match_operand 3)]) 364 (match_operand:SI 4 "add_operand")))) 365 (clobber (match_operand:DI 5 "register_operand"))] 366 "" 367 [(set (match_dup 5) (match_dup 6)) 368 (set (match_dup 0) (sign_extend:DI (plus:SI (match_dup 7) (match_dup 4))))] 369 { 370 operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 371 operands[2], operands[3]); 372 operands[7] = gen_lowpart (SImode, operands[5]); 373 }) 374 375 (define_expand "adddi3" 376 [(set (match_operand:DI 0 "register_operand") 377 (plus:DI (match_operand:DI 1 "register_operand") 378 (match_operand:DI 2 "add_operand")))]) 379 380 (define_insn "*adddi_er_lo16_dtp" 381 [(set (match_operand:DI 0 "register_operand" "=r") 382 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 383 (match_operand:DI 2 "dtp16_symbolic_operand")))] 384 "HAVE_AS_TLS" 385 "lda %0,%2(%1)\t\t!dtprel") 386 387 (define_insn "*adddi_er_hi32_dtp" 388 [(set (match_operand:DI 0 "register_operand" "=r") 389 (plus:DI (match_operand:DI 1 "register_operand" "r") 390 (high:DI (match_operand:DI 2 "dtp32_symbolic_operand"))))] 391 "HAVE_AS_TLS" 392 "ldah %0,%2(%1)\t\t!dtprelhi") 393 394 (define_insn "*adddi_er_lo32_dtp" 395 [(set (match_operand:DI 0 "register_operand" "=r") 396 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 397 (match_operand:DI 2 "dtp32_symbolic_operand")))] 398 "HAVE_AS_TLS" 399 "lda %0,%2(%1)\t\t!dtprello") 400 401 (define_insn "*adddi_er_lo16_tp" 402 [(set (match_operand:DI 0 "register_operand" "=r") 403 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 404 (match_operand:DI 2 "tp16_symbolic_operand")))] 405 "HAVE_AS_TLS" 406 "lda %0,%2(%1)\t\t!tprel") 407 408 (define_insn "*adddi_er_hi32_tp" 409 [(set (match_operand:DI 0 "register_operand" "=r") 410 (plus:DI (match_operand:DI 1 "register_operand" "r") 411 (high:DI (match_operand:DI 2 "tp32_symbolic_operand"))))] 412 "HAVE_AS_TLS" 413 "ldah %0,%2(%1)\t\t!tprelhi") 414 415 (define_insn "*adddi_er_lo32_tp" 416 [(set (match_operand:DI 0 "register_operand" "=r") 417 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 418 (match_operand:DI 2 "tp32_symbolic_operand")))] 419 "HAVE_AS_TLS" 420 "lda %0,%2(%1)\t\t!tprello") 421 422 (define_insn "*adddi_er_high_l" 423 [(set (match_operand:DI 0 "register_operand" "=r") 424 (plus:DI (match_operand:DI 1 "register_operand" "r") 425 (high:DI (match_operand:DI 2 "local_symbolic_operand"))))] 426 "TARGET_EXPLICIT_RELOCS && reload_completed" 427 "ldah %0,%2(%1)\t\t!gprelhigh" 428 [(set_attr "usegp" "yes")]) 429 430 (define_split 431 [(set (match_operand:DI 0 "register_operand") 432 (high:DI (match_operand:DI 1 "local_symbolic_operand")))] 433 "TARGET_EXPLICIT_RELOCS && reload_completed" 434 [(set (match_dup 0) 435 (plus:DI (match_dup 2) (high:DI (match_dup 1))))] 436 "operands[2] = pic_offset_table_rtx;") 437 438 ;; We used to expend quite a lot of effort choosing addq/subq/lda. 439 ;; With complications like 440 ;; 441 ;; The NT stack unwind code can't handle a subq to adjust the stack 442 ;; (that's a bug, but not one we can do anything about). As of NT4.0 SP3, 443 ;; the exception handling code will loop if a subq is used and an 444 ;; exception occurs. 445 ;; 446 ;; The 19980616 change to emit prologues as RTL also confused some 447 ;; versions of GDB, which also interprets prologues. This has been 448 ;; fixed as of GDB 4.18, but it does not harm to unconditionally 449 ;; use lda here. 450 ;; 451 ;; and the fact that the three insns schedule exactly the same, it's 452 ;; just not worth the effort. 453 454 (define_insn "*adddi_internal" 455 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 456 (plus:DI (match_operand:DI 1 "register_operand" "%r,r,r") 457 (match_operand:DI 2 "add_operand" "r,K,L")))] 458 "" 459 "@ 460 addq %1,%2,%0 461 lda %0,%2(%1) 462 ldah %0,%h2(%1)") 463 464 ;; ??? Allow large constants when basing off the frame pointer or some 465 ;; virtual register that may eliminate to the frame pointer. This is 466 ;; done because register elimination offsets will change the hi/lo split, 467 ;; and if we split before reload, we will require additional instructions. 468 469 (define_insn "*adddi_fp_hack" 470 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 471 (plus:DI (match_operand:DI 1 "reg_no_subreg_operand" "r,r,r") 472 (match_operand:DI 2 "const_int_operand" "K,L,n")))] 473 "NONSTRICT_REG_OK_FP_BASE_P (operands[1]) 474 && INTVAL (operands[2]) >= 0 475 /* This is the largest constant an lda+ldah pair can add, minus 476 an upper bound on the displacement between SP and AP during 477 register elimination. See INITIAL_ELIMINATION_OFFSET. */ 478 && INTVAL (operands[2]) 479 < (0x7fff8000 480 - FIRST_PSEUDO_REGISTER * UNITS_PER_WORD 481 - ALPHA_ROUND(crtl->outgoing_args_size) 482 - (ALPHA_ROUND (get_frame_size () 483 + max_reg_num () * UNITS_PER_WORD 484 + crtl->args.pretend_args_size) 485 - crtl->args.pretend_args_size))" 486 "@ 487 lda %0,%2(%1) 488 ldah %0,%h2(%1) 489 #") 490 491 ;; Don't do this if we are adjusting SP since we don't want to do it 492 ;; in two steps. Don't split FP sources for the reason listed above. 493 (define_split 494 [(set (match_operand:DI 0 "register_operand") 495 (plus:DI (match_operand:DI 1 "register_operand") 496 (match_operand:DI 2 "const_int_operand")))] 497 "! add_operand (operands[2], DImode) 498 && operands[0] != stack_pointer_rtx 499 && operands[1] != frame_pointer_rtx 500 && operands[1] != arg_pointer_rtx" 501 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 3))) 502 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 4)))] 503 { 504 HOST_WIDE_INT val = INTVAL (operands[2]); 505 HOST_WIDE_INT low = (val & 0xffff) - 2 * (val & 0x8000); 506 HOST_WIDE_INT rest = val - low; 507 rtx rest_rtx = GEN_INT (rest); 508 509 operands[4] = GEN_INT (low); 510 if (satisfies_constraint_L (rest_rtx)) 511 operands[3] = rest_rtx; 512 else if (can_create_pseudo_p ()) 513 { 514 operands[3] = gen_reg_rtx (DImode); 515 emit_move_insn (operands[3], operands[2]); 516 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 517 DONE; 518 } 519 else 520 FAIL; 521 }) 522 523 (define_insn "*sadd<modesuffix>" 524 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 525 (plus:I48MODE 526 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r,r") 527 (match_operand:I48MODE 2 "const23_operand" "I,I")) 528 (match_operand:I48MODE 3 "sext_add_operand" "rI,O")))] 529 "" 530 "@ 531 s%P2add<modesuffix> %1,%3,%0 532 s%P2sub<modesuffix> %1,%n3,%0") 533 534 (define_insn "*saddl_se" 535 [(set (match_operand:DI 0 "register_operand" "=r,r") 536 (sign_extend:DI 537 (plus:SI 538 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r,r") 539 (match_operand:SI 2 "const23_operand" "I,I")) 540 (match_operand:SI 3 "sext_add_operand" "rI,O"))))] 541 "" 542 "@ 543 s%P2addl %1,%3,%0 544 s%P2subl %1,%n3,%0") 545 546 (define_split 547 [(set (match_operand:DI 0 "register_operand") 548 (sign_extend:DI 549 (plus:SI (ashift:SI (match_operator:SI 1 "comparison_operator" 550 [(match_operand 2) 551 (match_operand 3)]) 552 (match_operand:SI 4 "const23_operand")) 553 (match_operand:SI 5 "sext_add_operand")))) 554 (clobber (match_operand:DI 6 "reg_not_elim_operand"))] 555 "" 556 [(set (match_dup 6) (match_dup 7)) 557 (set (match_dup 0) 558 (sign_extend:DI (plus:SI (ashift:SI (match_dup 8) (match_dup 4)) 559 (match_dup 5))))] 560 { 561 operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[1]), DImode, 562 operands[2], operands[3]); 563 operands[8] = gen_lowpart (SImode, operands[6]); 564 }) 565 566 (define_insn "addv<mode>3" 567 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 568 (plus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ,rJ") 569 (match_operand:I48MODE 2 "sext_add_operand" "rI,O"))) 570 (trap_if (ne (plus:<DWI> (sign_extend:<DWI> (match_dup 1)) 571 (sign_extend:<DWI> (match_dup 2))) 572 (sign_extend:<DWI> (plus:I48MODE (match_dup 1) 573 (match_dup 2)))) 574 (const_int 0))] 575 "" 576 "@ 577 add<modesuffix>v %r1,%2,%0 578 sub<modesuffix>v %r1,%n2,%0") 579 580 (define_insn "neg<mode>2" 581 [(set (match_operand:I48MODE 0 "register_operand" "=r") 582 (neg:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")))] 583 "" 584 "sub<modesuffix> $31,%1,%0") 585 586 (define_insn "*negsi_se" 587 [(set (match_operand:DI 0 "register_operand" "=r") 588 (sign_extend:DI (neg:SI 589 (match_operand:SI 1 "reg_or_8bit_operand" "rI"))))] 590 "" 591 "subl $31,%1,%0") 592 593 (define_insn "negv<mode>2" 594 [(set (match_operand:I48MODE 0 "register_operand" "=r") 595 (neg:I48MODE (match_operand:I48MODE 1 "register_operand" "r"))) 596 (trap_if (ne (neg:<DWI> (sign_extend:<DWI> (match_dup 1))) 597 (sign_extend:<DWI> (neg:I48MODE (match_dup 1)))) 598 (const_int 0))] 599 "" 600 "sub<modesuffix>v $31,%1,%0") 601 602 (define_insn "sub<mode>3" 603 [(set (match_operand:I48MODE 0 "register_operand" "=r") 604 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 605 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 606 "" 607 "sub<modesuffix> %r1,%2,%0") 608 609 (define_insn "*subsi_se" 610 [(set (match_operand:DI 0 "register_operand" "=r") 611 (sign_extend:DI 612 (minus:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 613 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 614 "" 615 "subl %r1,%2,%0") 616 617 (define_insn "*subsi_se2" 618 [(set (match_operand:DI 0 "register_operand" "=r") 619 (sign_extend:DI 620 (subreg:SI (minus:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 621 (match_operand:DI 2 "reg_or_8bit_operand" "rI")) 622 0)))] 623 "" 624 "subl %r1,%2,%0") 625 626 (define_insn "*ssub<modesuffix>" 627 [(set (match_operand:I48MODE 0 "register_operand" "=r") 628 (minus:I48MODE 629 (ashift:I48MODE (match_operand:I48MODE 1 "reg_not_elim_operand" "r") 630 (match_operand:I48MODE 2 "const23_operand" "I")) 631 (match_operand:I48MODE 3 "reg_or_8bit_operand" "rI")))] 632 "" 633 "s%P2sub<modesuffix> %1,%3,%0") 634 635 (define_insn "*ssubl_se" 636 [(set (match_operand:DI 0 "register_operand" "=r") 637 (sign_extend:DI 638 (minus:SI 639 (ashift:SI (match_operand:SI 1 "reg_not_elim_operand" "r") 640 (match_operand:SI 2 "const23_operand" "I")) 641 (match_operand:SI 3 "reg_or_8bit_operand" "rI"))))] 642 "" 643 "s%P2subl %1,%3,%0") 644 645 (define_insn "subv<mode>3" 646 [(set (match_operand:I48MODE 0 "register_operand" "=r") 647 (minus:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "rJ") 648 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 649 (trap_if (ne (minus:<DWI> (sign_extend:<DWI> (match_dup 1)) 650 (sign_extend:<DWI> (match_dup 2))) 651 (sign_extend:<DWI> (minus:I48MODE (match_dup 1) 652 (match_dup 2)))) 653 (const_int 0))] 654 "" 655 "sub<modesuffix>v %r1,%2,%0") 656 657 (define_insn "mul<mode>3" 658 [(set (match_operand:I48MODE 0 "register_operand" "=r") 659 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 660 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI")))] 661 "" 662 "mul<modesuffix> %r1,%2,%0" 663 [(set_attr "type" "imul") 664 (set_attr "opsize" "<mode>")]) 665 666 (define_insn "*mulsi_se" 667 [(set (match_operand:DI 0 "register_operand" "=r") 668 (sign_extend:DI 669 (mult:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ") 670 (match_operand:SI 2 "reg_or_8bit_operand" "rI"))))] 671 "" 672 "mull %r1,%2,%0" 673 [(set_attr "type" "imul") 674 (set_attr "opsize" "si")]) 675 676 (define_insn "mulv<mode>3" 677 [(set (match_operand:I48MODE 0 "register_operand" "=r") 678 (mult:I48MODE (match_operand:I48MODE 1 "reg_or_0_operand" "%rJ") 679 (match_operand:I48MODE 2 "reg_or_8bit_operand" "rI"))) 680 (trap_if (ne (mult:<DWI> (sign_extend:<DWI> (match_dup 1)) 681 (sign_extend:<DWI> (match_dup 2))) 682 (sign_extend:<DWI> (mult:I48MODE (match_dup 1) 683 (match_dup 2)))) 684 (const_int 0))] 685 "" 686 "mul<modesuffix>v %r1,%2,%0" 687 [(set_attr "type" "imul") 688 (set_attr "opsize" "<mode>")]) 689 690 (define_expand "umuldi3_highpart" 691 [(set (match_operand:DI 0 "register_operand") 692 (truncate:DI 693 (lshiftrt:TI 694 (mult:TI (zero_extend:TI 695 (match_operand:DI 1 "register_operand")) 696 (match_operand:DI 2 "reg_or_8bit_operand")) 697 (const_int 64))))] 698 "" 699 { 700 if (REG_P (operands[2])) 701 operands[2] = gen_rtx_ZERO_EXTEND (TImode, operands[2]); 702 }) 703 704 (define_insn "*umuldi3_highpart_reg" 705 [(set (match_operand:DI 0 "register_operand" "=r") 706 (truncate:DI 707 (lshiftrt:TI 708 (mult:TI (zero_extend:TI 709 (match_operand:DI 1 "register_operand" "r")) 710 (zero_extend:TI 711 (match_operand:DI 2 "register_operand" "r"))) 712 (const_int 64))))] 713 "" 714 "umulh %1,%2,%0" 715 [(set_attr "type" "imul") 716 (set_attr "opsize" "udi")]) 717 718 (define_insn "*umuldi3_highpart_const" 719 [(set (match_operand:DI 0 "register_operand" "=r") 720 (truncate:DI 721 (lshiftrt:TI 722 (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "r")) 723 (match_operand:TI 2 "cint8_operand" "I")) 724 (const_int 64))))] 725 "" 726 "umulh %1,%2,%0" 727 [(set_attr "type" "imul") 728 (set_attr "opsize" "udi")]) 729 730 (define_expand "umulditi3" 731 [(set (match_operand:TI 0 "register_operand") 732 (mult:TI 733 (zero_extend:TI (match_operand:DI 1 "reg_no_subreg_operand")) 734 (zero_extend:TI (match_operand:DI 2 "reg_no_subreg_operand"))))] 735 "" 736 { 737 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 738 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 739 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 740 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 741 emit_move_insn (gen_highpart (DImode, operands[0]), h); 742 DONE; 743 }) 744 746 ;; The divide and remainder operations take their inputs from r24 and 747 ;; r25, put their output in r27, and clobber r23 and r28 on all systems. 748 ;; 749 ;; ??? Force sign-extension here because some versions of OSF/1 and 750 ;; Interix/NT don't do the right thing if the inputs are not properly 751 ;; sign-extended. But Linux, for instance, does not have this 752 ;; problem. Is it worth the complication here to eliminate the sign 753 ;; extension? 754 755 (define_code_iterator any_divmod [div mod udiv umod]) 756 757 (define_expand "<code>si3" 758 [(set (match_dup 3) 759 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand"))) 760 (set (match_dup 4) 761 (sign_extend:DI (match_operand:SI 2 "nonimmediate_operand"))) 762 (parallel [(set (match_dup 5) 763 (sign_extend:DI 764 (any_divmod:SI (match_dup 3) (match_dup 4)))) 765 (clobber (reg:DI 23)) 766 (clobber (reg:DI 28))]) 767 (set (match_operand:SI 0 "nonimmediate_operand") 768 (subreg:SI (match_dup 5) 0))] 769 "TARGET_ABI_OSF" 770 { 771 operands[3] = gen_reg_rtx (DImode); 772 operands[4] = gen_reg_rtx (DImode); 773 operands[5] = gen_reg_rtx (DImode); 774 }) 775 776 (define_expand "<code>di3" 777 [(parallel [(set (match_operand:DI 0 "register_operand") 778 (any_divmod:DI 779 (match_operand:DI 1 "register_operand") 780 (match_operand:DI 2 "register_operand"))) 781 (clobber (reg:DI 23)) 782 (clobber (reg:DI 28))])] 783 "TARGET_ABI_OSF") 784 785 ;; Lengths of 8 for ldq $t12,__divq($gp); jsr $t9,($t12),__divq as 786 ;; expanded by the assembler. 787 788 (define_insn_and_split "*divmodsi_internal_er" 789 [(set (match_operand:DI 0 "register_operand" "=c") 790 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 791 [(match_operand:DI 1 "register_operand" "a") 792 (match_operand:DI 2 "register_operand" "b")]))) 793 (clobber (reg:DI 23)) 794 (clobber (reg:DI 28))] 795 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 796 "#" 797 "&& reload_completed" 798 [(parallel [(set (match_dup 0) 799 (sign_extend:DI (match_dup 3))) 800 (use (match_dup 0)) 801 (use (match_dup 4)) 802 (clobber (reg:DI 23)) 803 (clobber (reg:DI 28))])] 804 { 805 const char *str; 806 switch (GET_CODE (operands[3])) 807 { 808 case DIV: 809 str = "__divl"; 810 break; 811 case UDIV: 812 str = "__divlu"; 813 break; 814 case MOD: 815 str = "__reml"; 816 break; 817 case UMOD: 818 str = "__remlu"; 819 break; 820 default: 821 gcc_unreachable (); 822 } 823 operands[4] = GEN_INT (alpha_next_sequence_number++); 824 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 825 gen_rtx_SYMBOL_REF (DImode, str), 826 operands[4])); 827 } 828 [(set_attr "type" "jsr") 829 (set_attr "length" "8")]) 830 831 (define_insn "*divmodsi_internal_er_1" 832 [(set (match_operand:DI 0 "register_operand" "=c") 833 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 834 [(match_operand:DI 1 "register_operand" "a") 835 (match_operand:DI 2 "register_operand" "b")]))) 836 (use (match_operand:DI 4 "register_operand" "c")) 837 (use (match_operand 5 "const_int_operand")) 838 (clobber (reg:DI 23)) 839 (clobber (reg:DI 28))] 840 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 841 "jsr $23,($27),__%E3%j5" 842 [(set_attr "type" "jsr") 843 (set_attr "length" "4")]) 844 845 (define_insn "*divmodsi_internal" 846 [(set (match_operand:DI 0 "register_operand" "=c") 847 (sign_extend:DI (match_operator:SI 3 "divmod_operator" 848 [(match_operand:DI 1 "register_operand" "a") 849 (match_operand:DI 2 "register_operand" "b")]))) 850 (clobber (reg:DI 23)) 851 (clobber (reg:DI 28))] 852 "TARGET_ABI_OSF" 853 "%E3 %1,%2,%0" 854 [(set_attr "type" "jsr") 855 (set_attr "length" "8")]) 856 857 (define_insn_and_split "*divmoddi_internal_er" 858 [(set (match_operand:DI 0 "register_operand" "=c") 859 (match_operator:DI 3 "divmod_operator" 860 [(match_operand:DI 1 "register_operand" "a") 861 (match_operand:DI 2 "register_operand" "b")])) 862 (clobber (reg:DI 23)) 863 (clobber (reg:DI 28))] 864 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 865 "#" 866 "&& reload_completed" 867 [(parallel [(set (match_dup 0) (match_dup 3)) 868 (use (match_dup 0)) 869 (use (match_dup 4)) 870 (clobber (reg:DI 23)) 871 (clobber (reg:DI 28))])] 872 { 873 const char *str; 874 switch (GET_CODE (operands[3])) 875 { 876 case DIV: 877 str = "__divq"; 878 break; 879 case UDIV: 880 str = "__divqu"; 881 break; 882 case MOD: 883 str = "__remq"; 884 break; 885 case UMOD: 886 str = "__remqu"; 887 break; 888 default: 889 gcc_unreachable (); 890 } 891 operands[4] = GEN_INT (alpha_next_sequence_number++); 892 emit_insn (gen_movdi_er_high_g (operands[0], pic_offset_table_rtx, 893 gen_rtx_SYMBOL_REF (DImode, str), 894 operands[4])); 895 } 896 [(set_attr "type" "jsr") 897 (set_attr "length" "8")]) 898 899 (define_insn "*divmoddi_internal_er_1" 900 [(set (match_operand:DI 0 "register_operand" "=c") 901 (match_operator:DI 3 "divmod_operator" 902 [(match_operand:DI 1 "register_operand" "a") 903 (match_operand:DI 2 "register_operand" "b")])) 904 (use (match_operand:DI 4 "register_operand" "c")) 905 (use (match_operand 5 "const_int_operand")) 906 (clobber (reg:DI 23)) 907 (clobber (reg:DI 28))] 908 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 909 "jsr $23,($27),__%E3%j5" 910 [(set_attr "type" "jsr") 911 (set_attr "length" "4")]) 912 913 (define_insn "*divmoddi_internal" 914 [(set (match_operand:DI 0 "register_operand" "=c") 915 (match_operator:DI 3 "divmod_operator" 916 [(match_operand:DI 1 "register_operand" "a") 917 (match_operand:DI 2 "register_operand" "b")])) 918 (clobber (reg:DI 23)) 919 (clobber (reg:DI 28))] 920 "TARGET_ABI_OSF" 921 "%E3 %1,%2,%0" 922 [(set_attr "type" "jsr") 923 (set_attr "length" "8")]) 924 926 ;; Next are the basic logical operations. We only expose the DImode operations 927 ;; to the rtl expanders, but SImode versions exist for combine as well as for 928 ;; the atomic operation splitters. 929 930 (define_insn "*andsi_internal" 931 [(set (match_operand:SI 0 "register_operand" "=r,r,r") 932 (and:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 933 (match_operand:SI 2 "and_operand" "rI,N,M")))] 934 "" 935 "@ 936 and %r1,%2,%0 937 bic %r1,%N2,%0 938 zapnot %r1,%m2,%0" 939 [(set_attr "type" "ilog,ilog,shift")]) 940 941 (define_insn "anddi3" 942 [(set (match_operand:DI 0 "register_operand" "=r,r,r") 943 (and:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ,rJ") 944 (match_operand:DI 2 "and_operand" "rI,N,M")))] 945 "" 946 "@ 947 and %r1,%2,%0 948 bic %r1,%N2,%0 949 zapnot %r1,%m2,%0" 950 [(set_attr "type" "ilog,ilog,shift")]) 951 952 ;; There are times when we can split an AND into two AND insns. This occurs 953 ;; when we can first clear any bytes and then clear anything else. For 954 ;; example "I & 0xffff07" is "(I & 0xffffff) & 0xffffffffffffff07". 955 ;; Only do this when running on 64-bit host since the computations are 956 ;; too messy otherwise. 957 958 (define_split 959 [(set (match_operand:DI 0 "register_operand") 960 (and:DI (match_operand:DI 1 "register_operand") 961 (match_operand:DI 2 "const_int_operand")))] 962 "! and_operand (operands[2], DImode)" 963 [(set (match_dup 0) (and:DI (match_dup 1) (match_dup 3))) 964 (set (match_dup 0) (and:DI (match_dup 0) (match_dup 4)))] 965 { 966 unsigned HOST_WIDE_INT mask1 = INTVAL (operands[2]); 967 unsigned HOST_WIDE_INT mask2 = mask1; 968 int i; 969 970 /* For each byte that isn't all zeros, make it all ones. */ 971 for (i = 0; i < 64; i += 8) 972 if ((mask1 & ((HOST_WIDE_INT) 0xff << i)) != 0) 973 mask1 |= (HOST_WIDE_INT) 0xff << i; 974 975 /* Now turn on any bits we've just turned off. */ 976 mask2 |= ~ mask1; 977 978 operands[3] = GEN_INT (mask1); 979 operands[4] = GEN_INT (mask2); 980 }) 981 982 (define_insn "zero_extendqi<mode>2" 983 [(set (match_operand:I248MODE 0 "register_operand" "=r,r") 984 (zero_extend:I248MODE 985 (match_operand:QI 1 "reg_or_bwx_memory_operand" "r,m")))] 986 "" 987 "@ 988 and %1,0xff,%0 989 ldbu %0,%1" 990 [(set_attr "type" "ilog,ild") 991 (set_attr "isa" "*,bwx")]) 992 993 (define_insn "zero_extendhi<mode>2" 994 [(set (match_operand:I48MODE 0 "register_operand" "=r,r") 995 (zero_extend:I48MODE 996 (match_operand:HI 1 "reg_or_bwx_memory_operand" "r,m")))] 997 "" 998 "@ 999 zapnot %1,3,%0 1000 ldwu %0,%1" 1001 [(set_attr "type" "shift,ild") 1002 (set_attr "isa" "*,bwx")]) 1003 1004 (define_insn "zero_extendsidi2" 1005 [(set (match_operand:DI 0 "register_operand" "=r") 1006 (zero_extend:DI (match_operand:SI 1 "register_operand" "r")))] 1007 "" 1008 "zapnot %1,15,%0" 1009 [(set_attr "type" "shift")]) 1010 1011 (define_insn "andnot<mode>3" 1012 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1013 (and:I48MODE 1014 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1015 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1016 "" 1017 "bic %r2,%1,%0" 1018 [(set_attr "type" "ilog")]) 1019 1020 (define_insn "*iorsi_internal" 1021 [(set (match_operand:SI 0 "register_operand" "=r,r") 1022 (ior:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1023 (match_operand:SI 2 "or_operand" "rI,N")))] 1024 "" 1025 "@ 1026 bis %r1,%2,%0 1027 ornot %r1,%N2,%0" 1028 [(set_attr "type" "ilog")]) 1029 1030 (define_insn "iordi3" 1031 [(set (match_operand:DI 0 "register_operand" "=r,r") 1032 (ior:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1033 (match_operand:DI 2 "or_operand" "rI,N")))] 1034 "" 1035 "@ 1036 bis %r1,%2,%0 1037 ornot %r1,%N2,%0" 1038 [(set_attr "type" "ilog")]) 1039 1040 (define_insn "*one_cmplsi_internal" 1041 [(set (match_operand:SI 0 "register_operand" "=r") 1042 (not:SI (match_operand:SI 1 "reg_or_8bit_operand" "rI")))] 1043 "" 1044 "ornot $31,%1,%0" 1045 [(set_attr "type" "ilog")]) 1046 1047 (define_insn "one_cmpldi2" 1048 [(set (match_operand:DI 0 "register_operand" "=r") 1049 (not:DI (match_operand:DI 1 "reg_or_8bit_operand" "rI")))] 1050 "" 1051 "ornot $31,%1,%0" 1052 [(set_attr "type" "ilog")]) 1053 1054 (define_insn "*iornot<mode>3" 1055 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1056 (ior:I48MODE 1057 (not:I48MODE (match_operand:I48MODE 1 "reg_or_8bit_operand" "rI")) 1058 (match_operand:I48MODE 2 "reg_or_0_operand" "rJ")))] 1059 "" 1060 "ornot %r2,%1,%0" 1061 [(set_attr "type" "ilog")]) 1062 1063 (define_insn "*xorsi_internal" 1064 [(set (match_operand:SI 0 "register_operand" "=r,r") 1065 (xor:SI (match_operand:SI 1 "reg_or_0_operand" "%rJ,rJ") 1066 (match_operand:SI 2 "or_operand" "rI,N")))] 1067 "" 1068 "@ 1069 xor %r1,%2,%0 1070 eqv %r1,%N2,%0" 1071 [(set_attr "type" "ilog")]) 1072 1073 (define_insn "xordi3" 1074 [(set (match_operand:DI 0 "register_operand" "=r,r") 1075 (xor:DI (match_operand:DI 1 "reg_or_0_operand" "%rJ,rJ") 1076 (match_operand:DI 2 "or_operand" "rI,N")))] 1077 "" 1078 "@ 1079 xor %r1,%2,%0 1080 eqv %r1,%N2,%0" 1081 [(set_attr "type" "ilog")]) 1082 1083 (define_insn "*xornot<mode>3" 1084 [(set (match_operand:I48MODE 0 "register_operand" "=r") 1085 (not:I48MODE (xor:I48MODE 1086 (match_operand:I48MODE 1 "register_operand" "%rJ") 1087 (match_operand:I48MODE 2 "register_operand" "rI"))))] 1088 "" 1089 "eqv %r1,%2,%0" 1090 [(set_attr "type" "ilog")]) 1091 1093 ;; Handle FFS and related insns iff we support CIX. 1094 1095 (define_expand "ffsdi2" 1096 [(set (match_dup 2) 1097 (ctz:DI (match_operand:DI 1 "register_operand"))) 1098 (set (match_dup 3) 1099 (plus:DI (match_dup 2) (const_int 1))) 1100 (set (match_operand:DI 0 "register_operand") 1101 (if_then_else:DI (eq (match_dup 1) (const_int 0)) 1102 (const_int 0) (match_dup 3)))] 1103 "TARGET_CIX" 1104 { 1105 operands[2] = gen_reg_rtx (DImode); 1106 operands[3] = gen_reg_rtx (DImode); 1107 }) 1108 1109 (define_insn "clzdi2" 1110 [(set (match_operand:DI 0 "register_operand" "=r") 1111 (clz:DI (match_operand:DI 1 "register_operand" "r")))] 1112 "TARGET_CIX" 1113 "ctlz %1,%0" 1114 [(set_attr "type" "mvi")]) 1115 1116 (define_insn "ctzdi2" 1117 [(set (match_operand:DI 0 "register_operand" "=r") 1118 (ctz:DI (match_operand:DI 1 "register_operand" "r")))] 1119 "TARGET_CIX" 1120 "cttz %1,%0" 1121 [(set_attr "type" "mvi")]) 1122 1123 (define_insn "popcountdi2" 1124 [(set (match_operand:DI 0 "register_operand" "=r") 1125 (popcount:DI (match_operand:DI 1 "register_operand" "r")))] 1126 "TARGET_CIX" 1127 "ctpop %1,%0" 1128 [(set_attr "type" "mvi")]) 1129 1130 (define_expand "bswapsi2" 1131 [(set (match_operand:SI 0 "register_operand") 1132 (bswap:SI (match_operand:SI 1 "register_operand")))] 1133 "!optimize_size" 1134 { 1135 rtx t0, t1; 1136 1137 t0 = gen_reg_rtx (DImode); 1138 t1 = gen_reg_rtx (DImode); 1139 1140 emit_insn (gen_inslh (t0, gen_lowpart (DImode, operands[1]), GEN_INT (7))); 1141 emit_insn (gen_inswl_const (t1, gen_lowpart (HImode, operands[1]), 1142 GEN_INT (24))); 1143 emit_insn (gen_iordi3 (t1, t0, t1)); 1144 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1145 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x5))); 1146 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xa))); 1147 emit_insn (gen_addsi3 (operands[0], gen_lowpart (SImode, t0), 1148 gen_lowpart (SImode, t1))); 1149 DONE; 1150 }) 1151 1152 (define_expand "bswapdi2" 1153 [(set (match_operand:DI 0 "register_operand") 1154 (bswap:DI (match_operand:DI 1 "register_operand")))] 1155 "!optimize_size" 1156 { 1157 rtx t0, t1; 1158 1159 t0 = gen_reg_rtx (DImode); 1160 t1 = gen_reg_rtx (DImode); 1161 1162 /* This method of shifting and masking is not specific to Alpha, but 1163 is only profitable on Alpha because of our handy byte zap insn. */ 1164 1165 emit_insn (gen_lshrdi3 (t0, operands[1], GEN_INT (32))); 1166 emit_insn (gen_ashldi3 (t1, operands[1], GEN_INT (32))); 1167 emit_insn (gen_iordi3 (t1, t0, t1)); 1168 1169 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (16))); 1170 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (16))); 1171 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xcc))); 1172 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x33))); 1173 emit_insn (gen_iordi3 (t1, t0, t1)); 1174 1175 emit_insn (gen_lshrdi3 (t0, t1, GEN_INT (8))); 1176 emit_insn (gen_ashldi3 (t1, t1, GEN_INT (8))); 1177 emit_insn (gen_anddi3 (t0, t0, alpha_expand_zap_mask (0xaa))); 1178 emit_insn (gen_anddi3 (t1, t1, alpha_expand_zap_mask (0x55))); 1179 emit_insn (gen_iordi3 (operands[0], t0, t1)); 1180 DONE; 1181 }) 1182 1184 ;; Next come the shifts and the various extract and insert operations. 1185 1186 (define_insn "ashldi3" 1187 [(set (match_operand:DI 0 "register_operand" "=r,r") 1188 (ashift:DI (match_operand:DI 1 "reg_or_0_operand" "rJ,rJ") 1189 (match_operand:DI 2 "reg_or_6bit_operand" "P,rS")))] 1190 "" 1191 { 1192 switch (which_alternative) 1193 { 1194 case 0: 1195 if (operands[2] == const1_rtx) 1196 return "addq %r1,%r1,%0"; 1197 else 1198 return "s%P2addq %r1,0,%0"; 1199 case 1: 1200 return "sll %r1,%2,%0"; 1201 default: 1202 gcc_unreachable (); 1203 } 1204 } 1205 [(set_attr "type" "iadd,shift")]) 1206 1207 (define_insn "ashlsi3" 1208 [(set (match_operand:SI 0 "register_operand" "=r") 1209 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1210 (match_operand:SI 2 "const123_operand" "P")))] 1211 "" 1212 { 1213 if (operands[2] == const1_rtx) 1214 return "addl %r1,%r1,%0"; 1215 else 1216 return "s%P2addl %r1,0,%0"; 1217 } 1218 [(set_attr "type" "iadd")]) 1219 1220 (define_insn "*ashlsi_se" 1221 [(set (match_operand:DI 0 "register_operand" "=r") 1222 (sign_extend:DI 1223 (ashift:SI (match_operand:SI 1 "reg_or_0_operand" "rJ") 1224 (match_operand:SI 2 "const123_operand" "P"))))] 1225 "" 1226 { 1227 if (operands[2] == const1_rtx) 1228 return "addl %r1,%r1,%0"; 1229 else 1230 return "s%P2addl %r1,0,%0"; 1231 } 1232 [(set_attr "type" "iadd")]) 1233 1234 (define_insn "lshrdi3" 1235 [(set (match_operand:DI 0 "register_operand" "=r") 1236 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1237 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1238 "" 1239 "srl %r1,%2,%0" 1240 [(set_attr "type" "shift")]) 1241 1242 (define_insn "ashrdi3" 1243 [(set (match_operand:DI 0 "register_operand" "=r") 1244 (ashiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1245 (match_operand:DI 2 "reg_or_6bit_operand" "rS")))] 1246 "" 1247 "sra %r1,%2,%0" 1248 [(set_attr "type" "shift")]) 1249 1250 (define_insn "extendqi<mode>2" 1251 [(set (match_operand:I24MODE 0 "register_operand" "=r") 1252 (sign_extend:I24MODE 1253 (match_operand:QI 1 "register_operand" "r")))] 1254 "TARGET_BWX" 1255 "sextb %1,%0" 1256 [(set_attr "type" "shift")]) 1257 1258 (define_expand "extendqidi2" 1259 [(set (match_operand:DI 0 "register_operand") 1260 (sign_extend:DI (match_operand:QI 1 "general_operand")))] 1261 "" 1262 { 1263 if (TARGET_BWX) 1264 operands[1] = force_reg (QImode, operands[1]); 1265 else 1266 { 1267 rtx x, t1, t2, i56; 1268 1269 if (unaligned_memory_operand (operands[1], QImode)) 1270 { 1271 x = gen_unaligned_extendqidi (operands[0], XEXP (operands[1], 0)); 1272 alpha_set_memflags (x, operands[1]); 1273 emit_insn (x); 1274 DONE; 1275 } 1276 1277 t1 = gen_reg_rtx (DImode); 1278 t2 = gen_reg_rtx (DImode); 1279 i56 = GEN_INT (56); 1280 1281 x = gen_lowpart (DImode, force_reg (QImode, operands[1])); 1282 emit_move_insn (t1, x); 1283 emit_insn (gen_ashldi3 (t2, t1, i56)); 1284 emit_insn (gen_ashrdi3 (operands[0], t2, i56)); 1285 DONE; 1286 } 1287 }) 1288 1289 (define_insn "*extendqidi2_bwx" 1290 [(set (match_operand:DI 0 "register_operand" "=r") 1291 (sign_extend:DI (match_operand:QI 1 "register_operand" "r")))] 1292 "TARGET_BWX" 1293 "sextb %1,%0" 1294 [(set_attr "type" "shift")]) 1295 1296 (define_insn "extendhisi2" 1297 [(set (match_operand:SI 0 "register_operand" "=r") 1298 (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))] 1299 "TARGET_BWX" 1300 "sextw %1,%0" 1301 [(set_attr "type" "shift")]) 1302 1303 (define_expand "extendhidi2" 1304 [(set (match_operand:DI 0 "register_operand") 1305 (sign_extend:DI (match_operand:HI 1 "general_operand")))] 1306 "" 1307 { 1308 if (TARGET_BWX) 1309 operands[1] = force_reg (HImode, operands[1]); 1310 else 1311 { 1312 rtx x, t1, t2, i48; 1313 1314 if (unaligned_memory_operand (operands[1], HImode)) 1315 { 1316 x = gen_unaligned_extendhidi (operands[0], XEXP (operands[1], 0)); 1317 alpha_set_memflags (x, operands[1]); 1318 emit_insn (x); 1319 DONE; 1320 } 1321 1322 t1 = gen_reg_rtx (DImode); 1323 t2 = gen_reg_rtx (DImode); 1324 i48 = GEN_INT (48); 1325 1326 x = gen_lowpart (DImode, force_reg (HImode, operands[1])); 1327 emit_move_insn (t1, x); 1328 emit_insn (gen_ashldi3 (t2, t1, i48)); 1329 emit_insn (gen_ashrdi3 (operands[0], t2, i48)); 1330 DONE; 1331 } 1332 }) 1333 1334 (define_insn "*extendhidi2_bwx" 1335 [(set (match_operand:DI 0 "register_operand" "=r") 1336 (sign_extend:DI (match_operand:HI 1 "register_operand" "r")))] 1337 "TARGET_BWX" 1338 "sextw %1,%0" 1339 [(set_attr "type" "shift")]) 1340 1341 ;; Here's how we sign extend an unaligned byte and halfword. Doing this 1342 ;; as a pattern saves one instruction. The code is similar to that for 1343 ;; the unaligned loads (see below). 1344 ;; 1345 ;; Operand 1 is the address, operand 0 is the result. 1346 1347 (define_expand "unaligned_extendqidi" 1348 [(set (match_dup 3) 1349 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1350 (set (match_dup 4) 1351 (ashift:DI (match_dup 3) 1352 (minus:DI (const_int 64) 1353 (ashift:DI 1354 (and:DI (match_dup 2) (const_int 7)) 1355 (const_int 3))))) 1356 (set (match_operand:QI 0 "register_operand") 1357 (ashiftrt:DI (match_dup 4) (const_int 56)))] 1358 "" 1359 { 1360 operands[0] = gen_lowpart (DImode, operands[0]); 1361 operands[2] = get_unaligned_offset (operands[1], 1); 1362 operands[3] = gen_reg_rtx (DImode); 1363 operands[4] = gen_reg_rtx (DImode); 1364 }) 1365 1366 (define_expand "unaligned_extendhidi" 1367 [(set (match_dup 3) 1368 (mem:DI (and:DI (match_operand:DI 1 "address_operand") (const_int -8)))) 1369 (set (match_dup 4) 1370 (ashift:DI (match_dup 3) 1371 (minus:DI (const_int 64) 1372 (ashift:DI 1373 (and:DI (match_dup 2) (const_int 7)) 1374 (const_int 3))))) 1375 (set (match_operand:HI 0 "register_operand") 1376 (ashiftrt:DI (match_dup 4) (const_int 48)))] 1377 "" 1378 { 1379 operands[0] = gen_lowpart (DImode, operands[0]); 1380 operands[2] = get_unaligned_offset (operands[1], 2); 1381 operands[3] = gen_reg_rtx (DImode); 1382 operands[4] = gen_reg_rtx (DImode); 1383 }) 1384 1385 (define_insn "*extxl_const" 1386 [(set (match_operand:DI 0 "register_operand" "=r") 1387 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1388 (match_operand:DI 2 "mode_width_operand" "n") 1389 (match_operand:DI 3 "mul8_operand" "I")))] 1390 "" 1391 "ext%M2l %r1,%s3,%0" 1392 [(set_attr "type" "shift")]) 1393 1394 (define_insn "extxl" 1395 [(set (match_operand:DI 0 "register_operand" "=r") 1396 (zero_extract:DI 1397 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1398 (match_operand:DI 2 "mode_width_operand" "n") 1399 (ashift:DI (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1400 (const_int 3))))] 1401 "" 1402 "ext%M2l %r1,%3,%0" 1403 [(set_attr "type" "shift")]) 1404 1405 ;; Combine has some strange notion of preserving existing undefined behavior 1406 ;; in shifts larger than a word size. So capture these patterns that it 1407 ;; should have turned into zero_extracts. 1408 1409 (define_insn "*extxl_1" 1410 [(set (match_operand:DI 0 "register_operand" "=r") 1411 (and:DI (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1412 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1413 (const_int 3))) 1414 (match_operand:DI 3 "mode_mask_operand" "n")))] 1415 "" 1416 "ext%U3l %1,%2,%0" 1417 [(set_attr "type" "shift")]) 1418 1419 (define_insn "*extql_2" 1420 [(set (match_operand:DI 0 "register_operand" "=r") 1421 (lshiftrt:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1422 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1423 (const_int 3))))] 1424 "" 1425 "extql %1,%2,%0" 1426 [(set_attr "type" "shift")]) 1427 1428 (define_insn "extqh" 1429 [(set (match_operand:DI 0 "register_operand" "=r") 1430 (ashift:DI 1431 (match_operand:DI 1 "reg_or_0_operand" "rJ") 1432 (minus:DI (const_int 64) 1433 (ashift:DI 1434 (and:DI 1435 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1436 (const_int 7)) 1437 (const_int 3)))))] 1438 "" 1439 "extqh %r1,%2,%0" 1440 [(set_attr "type" "shift")]) 1441 1442 (define_insn "extwh" 1443 [(set (match_operand:DI 0 "register_operand" "=r") 1444 (ashift:DI 1445 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1446 (const_int 65535)) 1447 (minus:DI (const_int 64) 1448 (ashift:DI 1449 (and:DI 1450 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1451 (const_int 7)) 1452 (const_int 3)))))] 1453 "" 1454 "extwh %r1,%2,%0" 1455 [(set_attr "type" "shift")]) 1456 1457 (define_insn "extlh" 1458 [(set (match_operand:DI 0 "register_operand" "=r") 1459 (ashift:DI 1460 (and:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1461 (const_int 2147483647)) 1462 (minus:DI (const_int 64) 1463 (ashift:DI 1464 (and:DI 1465 (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1466 (const_int 7)) 1467 (const_int 3)))))] 1468 "" 1469 "extlh %r1,%2,%0" 1470 [(set_attr "type" "shift")]) 1471 1472 ;; This converts an extXl into an extXh with an appropriate adjustment 1473 ;; to the address calculation. 1474 1475 ;;(define_split 1476 ;; [(set (match_operand:DI 0 "register_operand") 1477 ;; (ashift:DI (zero_extract:DI (match_operand:DI 1 "register_operand") 1478 ;; (match_operand:DI 2 "mode_width_operand") 1479 ;; (ashift:DI (match_operand:DI 3) 1480 ;; (const_int 3))) 1481 ;; (match_operand:DI 4 "const_int_operand"))) 1482 ;; (clobber (match_operand:DI 5 "register_operand"))] 1483 ;; "INTVAL (operands[4]) == 64 - INTVAL (operands[2])" 1484 ;; [(set (match_dup 5) (match_dup 6)) 1485 ;; (set (match_dup 0) 1486 ;; (ashift:DI (zero_extract:DI (match_dup 1) (match_dup 2) 1487 ;; (ashift:DI (plus:DI (match_dup 5) 1488 ;; (match_dup 7)) 1489 ;; (const_int 3))) 1490 ;; (match_dup 4)))] 1491 ;; " 1492 ;;{ 1493 ;; operands[6] = plus_constant (DImode, operands[3], 1494 ;; INTVAL (operands[2]) / BITS_PER_UNIT); 1495 ;; operands[7] = GEN_INT (- INTVAL (operands[2]) / BITS_PER_UNIT); 1496 ;;}") 1497 1498 (define_insn "ins<modesuffix>l_const" 1499 [(set (match_operand:DI 0 "register_operand" "=r") 1500 (ashift:DI (zero_extend:DI 1501 (match_operand:I124MODE 1 "register_operand" "r")) 1502 (match_operand:DI 2 "mul8_operand" "I")))] 1503 "" 1504 "ins<modesuffix>l %1,%s2,%0" 1505 [(set_attr "type" "shift")]) 1506 1507 (define_insn "ins<modesuffix>l" 1508 [(set (match_operand:DI 0 "register_operand" "=r") 1509 (ashift:DI (zero_extend:DI 1510 (match_operand:I124MODE 1 "register_operand" "r")) 1511 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1512 (const_int 3))))] 1513 "" 1514 "ins<modesuffix>l %1,%2,%0" 1515 [(set_attr "type" "shift")]) 1516 1517 (define_insn "insql" 1518 [(set (match_operand:DI 0 "register_operand" "=r") 1519 (ashift:DI (match_operand:DI 1 "register_operand" "r") 1520 (ashift:DI (match_operand:DI 2 "reg_or_8bit_operand" "rI") 1521 (const_int 3))))] 1522 "" 1523 "insql %1,%2,%0" 1524 [(set_attr "type" "shift")]) 1525 1526 ;; Combine has this sometimes habit of moving the and outside of the 1527 ;; shift, making life more interesting. 1528 1529 (define_insn "*insxl" 1530 [(set (match_operand:DI 0 "register_operand" "=r") 1531 (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") 1532 (match_operand:DI 2 "mul8_operand" "I")) 1533 (match_operand:DI 3 "const_int_operand" "i")))] 1534 "((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1535 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1536 || ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1537 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1538 || ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1539 == (unsigned HOST_WIDE_INT) INTVAL (operands[3]))" 1540 { 1541 if ((unsigned HOST_WIDE_INT) 0xff << INTVAL (operands[2]) 1542 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1543 return "insbl %1,%s2,%0"; 1544 if ((unsigned HOST_WIDE_INT) 0xffff << INTVAL (operands[2]) 1545 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1546 return "inswl %1,%s2,%0"; 1547 if ((unsigned HOST_WIDE_INT) 0xffffffff << INTVAL (operands[2]) 1548 == (unsigned HOST_WIDE_INT) INTVAL (operands[3])) 1549 return "insll %1,%s2,%0"; 1550 1551 gcc_unreachable (); 1552 } 1553 [(set_attr "type" "shift")]) 1554 1555 ;; We do not include the insXh insns because they are complex to express 1556 ;; and it does not appear that we would ever want to generate them. 1557 ;; 1558 ;; Since we need them for block moves, though, cop out and use unspec. 1559 1560 (define_insn "insxh" 1561 [(set (match_operand:DI 0 "register_operand" "=r") 1562 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1563 (match_operand:DI 2 "mode_width_operand" "n") 1564 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1565 UNSPEC_INSXH))] 1566 "" 1567 "ins%M2h %1,%3,%0" 1568 [(set_attr "type" "shift")]) 1569 1570 (define_insn "mskxl" 1571 [(set (match_operand:DI 0 "register_operand" "=r") 1572 (and:DI (not:DI (ashift:DI 1573 (match_operand:DI 2 "mode_mask_operand" "n") 1574 (ashift:DI 1575 (match_operand:DI 3 "reg_or_8bit_operand" "rI") 1576 (const_int 3)))) 1577 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 1578 "" 1579 "msk%U2l %r1,%3,%0" 1580 [(set_attr "type" "shift")]) 1581 1582 ;; We do not include the mskXh insns because it does not appear we would 1583 ;; ever generate one. 1584 ;; 1585 ;; Again, we do for block moves and we use unspec again. 1586 1587 (define_insn "mskxh" 1588 [(set (match_operand:DI 0 "register_operand" "=r") 1589 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 1590 (match_operand:DI 2 "mode_width_operand" "n") 1591 (match_operand:DI 3 "reg_or_8bit_operand" "rI")] 1592 UNSPEC_MSKXH))] 1593 "" 1594 "msk%M2h %1,%3,%0" 1595 [(set_attr "type" "shift")]) 1596 1597 ;; Prefer AND + NE over LSHIFTRT + AND. 1598 1599 (define_insn_and_split "*ze_and_ne" 1600 [(set (match_operand:DI 0 "register_operand" "=r") 1601 (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 1602 (const_int 1) 1603 (match_operand 2 "const_int_operand" "I")))] 1604 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1605 "#" 1606 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 8" 1607 [(set (match_dup 0) 1608 (and:DI (match_dup 1) (match_dup 3))) 1609 (set (match_dup 0) 1610 (ne:DI (match_dup 0) (const_int 0)))] 1611 "operands[3] = GEN_INT (1 << INTVAL (operands[2]));") 1612 1614 ;; Floating-point operations. All the double-precision insns can extend 1615 ;; from single, so indicate that. The exception are the ones that simply 1616 ;; play with the sign bits; it's not clear what to do there. 1617 1618 (define_mode_iterator FMODE [SF DF]) 1619 1620 (define_mode_attr opmode [(SF "si") (DF "di")]) 1621 1622 (define_insn "abs<mode>2" 1623 [(set (match_operand:FMODE 0 "register_operand" "=f") 1624 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1625 "TARGET_FP" 1626 "cpys $f31,%R1,%0" 1627 [(set_attr "type" "fcpys")]) 1628 1629 (define_insn "*nabs<mode>2" 1630 [(set (match_operand:FMODE 0 "register_operand" "=f") 1631 (neg:FMODE 1632 (abs:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG"))))] 1633 "TARGET_FP" 1634 "cpysn $f31,%R1,%0" 1635 [(set_attr "type" "fadd")]) 1636 1637 (define_expand "abstf2" 1638 [(parallel [(set (match_operand:TF 0 "register_operand") 1639 (abs:TF (match_operand:TF 1 "reg_or_0_operand"))) 1640 (use (match_dup 2))])] 1641 "TARGET_HAS_XFLOATING_LIBS" 1642 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1643 1644 (define_insn_and_split "*abstf_internal" 1645 [(set (match_operand:TF 0 "register_operand" "=r") 1646 (abs:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1647 (use (match_operand:DI 2 "register_operand" "r"))] 1648 "TARGET_HAS_XFLOATING_LIBS" 1649 "#" 1650 "&& reload_completed" 1651 [(const_int 0)] 1652 "alpha_split_tfmode_frobsign (operands, gen_andnotdi3); DONE;") 1653 1654 (define_insn "neg<mode>2" 1655 [(set (match_operand:FMODE 0 "register_operand" "=f") 1656 (neg:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG")))] 1657 "TARGET_FP" 1658 "cpysn %R1,%R1,%0" 1659 [(set_attr "type" "fadd")]) 1660 1661 (define_expand "negtf2" 1662 [(parallel [(set (match_operand:TF 0 "register_operand") 1663 (neg:TF (match_operand:TF 1 "reg_or_0_operand"))) 1664 (use (match_dup 2))])] 1665 "TARGET_HAS_XFLOATING_LIBS" 1666 "operands[2] = force_reg (DImode, GEN_INT (HOST_WIDE_INT_1U << 63));") 1667 1668 (define_insn_and_split "*negtf_internal" 1669 [(set (match_operand:TF 0 "register_operand" "=r") 1670 (neg:TF (match_operand:TF 1 "reg_or_0_operand" "rG"))) 1671 (use (match_operand:DI 2 "register_operand" "r"))] 1672 "TARGET_HAS_XFLOATING_LIBS" 1673 "#" 1674 "&& reload_completed" 1675 [(const_int 0)] 1676 "alpha_split_tfmode_frobsign (operands, gen_xordi3); DONE;") 1677 1678 (define_insn "copysign<mode>3" 1679 [(set (match_operand:FMODE 0 "register_operand" "=f") 1680 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1681 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1682 UNSPEC_COPYSIGN))] 1683 "TARGET_FP" 1684 "cpys %R2,%R1,%0" 1685 [(set_attr "type" "fadd")]) 1686 1687 (define_insn "*ncopysign<mode>3" 1688 [(set (match_operand:FMODE 0 "register_operand" "=f") 1689 (neg:FMODE 1690 (unspec:FMODE [(match_operand:FMODE 1 "reg_or_0_operand" "fG") 1691 (match_operand:FMODE 2 "reg_or_0_operand" "fG")] 1692 UNSPEC_COPYSIGN)))] 1693 "TARGET_FP" 1694 "cpysn %R2,%R1,%0" 1695 [(set_attr "type" "fadd")]) 1696 1697 (define_insn "add<mode>3" 1698 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1699 (plus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1700 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1701 "TARGET_FP" 1702 "add<modesuffix>%/ %R1,%R2,%0" 1703 [(set_attr "type" "fadd") 1704 (set_attr "trap" "yes") 1705 (set_attr "round_suffix" "normal") 1706 (set_attr "trap_suffix" "u_su_sui") 1707 (set (attr "enabled") 1708 (cond [(eq_attr "alternative" "0") 1709 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1710 ] 1711 (symbol_ref "true")))]) 1712 1713 (define_insn "*adddf_ext1" 1714 [(set (match_operand:DF 0 "register_operand" "=f") 1715 (plus:DF (float_extend:DF 1716 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1717 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1718 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1719 "add%-%/ %R1,%R2,%0" 1720 [(set_attr "type" "fadd") 1721 (set_attr "trap" "yes") 1722 (set_attr "round_suffix" "normal") 1723 (set_attr "trap_suffix" "u_su_sui")]) 1724 1725 (define_insn "*adddf_ext2" 1726 [(set (match_operand:DF 0 "register_operand" "=f") 1727 (plus:DF (float_extend:DF 1728 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1729 (float_extend:DF 1730 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1731 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1732 "add%-%/ %R1,%R2,%0" 1733 [(set_attr "type" "fadd") 1734 (set_attr "trap" "yes") 1735 (set_attr "round_suffix" "normal") 1736 (set_attr "trap_suffix" "u_su_sui")]) 1737 1738 (define_expand "addtf3" 1739 [(use (match_operand:TF 0 "register_operand")) 1740 (use (match_operand:TF 1 "general_operand")) 1741 (use (match_operand:TF 2 "general_operand"))] 1742 "TARGET_HAS_XFLOATING_LIBS" 1743 "alpha_emit_xfloating_arith (PLUS, operands); DONE;") 1744 1745 (define_insn "sub<mode>3" 1746 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1747 (minus:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1748 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1749 "TARGET_FP" 1750 "sub<modesuffix>%/ %R1,%R2,%0" 1751 [(set_attr "type" "fadd") 1752 (set_attr "trap" "yes") 1753 (set_attr "round_suffix" "normal") 1754 (set_attr "trap_suffix" "u_su_sui") 1755 (set (attr "enabled") 1756 (cond [(eq_attr "alternative" "0") 1757 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1758 ] 1759 (symbol_ref "true")))]) 1760 1761 (define_insn "*subdf_ext1" 1762 [(set (match_operand:DF 0 "register_operand" "=f") 1763 (minus:DF (float_extend:DF 1764 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1765 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1766 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1767 "sub%-%/ %R1,%R2,%0" 1768 [(set_attr "type" "fadd") 1769 (set_attr "trap" "yes") 1770 (set_attr "round_suffix" "normal") 1771 (set_attr "trap_suffix" "u_su_sui")]) 1772 1773 (define_insn "*subdf_ext2" 1774 [(set (match_operand:DF 0 "register_operand" "=f") 1775 (minus:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1776 (float_extend:DF 1777 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1778 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1779 "sub%-%/ %R1,%R2,%0" 1780 [(set_attr "type" "fadd") 1781 (set_attr "trap" "yes") 1782 (set_attr "round_suffix" "normal") 1783 (set_attr "trap_suffix" "u_su_sui")]) 1784 1785 (define_insn "*subdf_ext3" 1786 [(set (match_operand:DF 0 "register_operand" "=f") 1787 (minus:DF (float_extend:DF 1788 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1789 (float_extend:DF 1790 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1791 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1792 "sub%-%/ %R1,%R2,%0" 1793 [(set_attr "type" "fadd") 1794 (set_attr "trap" "yes") 1795 (set_attr "round_suffix" "normal") 1796 (set_attr "trap_suffix" "u_su_sui")]) 1797 1798 (define_expand "subtf3" 1799 [(use (match_operand:TF 0 "register_operand")) 1800 (use (match_operand:TF 1 "general_operand")) 1801 (use (match_operand:TF 2 "general_operand"))] 1802 "TARGET_HAS_XFLOATING_LIBS" 1803 "alpha_emit_xfloating_arith (MINUS, operands); DONE;") 1804 1805 (define_insn "mul<mode>3" 1806 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1807 (mult:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "%fG,fG") 1808 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1809 "TARGET_FP" 1810 "mul<modesuffix>%/ %R1,%R2,%0" 1811 [(set_attr "type" "fmul") 1812 (set_attr "trap" "yes") 1813 (set_attr "round_suffix" "normal") 1814 (set_attr "trap_suffix" "u_su_sui") 1815 (set (attr "enabled") 1816 (cond [(eq_attr "alternative" "0") 1817 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1818 ] 1819 (symbol_ref "true")))]) 1820 1821 (define_insn "*muldf_ext1" 1822 [(set (match_operand:DF 0 "register_operand" "=f") 1823 (mult:DF (float_extend:DF 1824 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1825 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1826 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1827 "mul%-%/ %R1,%R2,%0" 1828 [(set_attr "type" "fmul") 1829 (set_attr "trap" "yes") 1830 (set_attr "round_suffix" "normal") 1831 (set_attr "trap_suffix" "u_su_sui")]) 1832 1833 (define_insn "*muldf_ext2" 1834 [(set (match_operand:DF 0 "register_operand" "=f") 1835 (mult:DF (float_extend:DF 1836 (match_operand:SF 1 "reg_or_0_operand" "%fG")) 1837 (float_extend:DF 1838 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1839 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1840 "mul%-%/ %R1,%R2,%0" 1841 [(set_attr "type" "fmul") 1842 (set_attr "trap" "yes") 1843 (set_attr "round_suffix" "normal") 1844 (set_attr "trap_suffix" "u_su_sui")]) 1845 1846 (define_expand "multf3" 1847 [(use (match_operand:TF 0 "register_operand")) 1848 (use (match_operand:TF 1 "general_operand")) 1849 (use (match_operand:TF 2 "general_operand"))] 1850 "TARGET_HAS_XFLOATING_LIBS" 1851 "alpha_emit_xfloating_arith (MULT, operands); DONE;") 1852 1853 (define_insn "div<mode>3" 1854 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1855 (div:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG") 1856 (match_operand:FMODE 2 "reg_or_0_operand" "fG,fG")))] 1857 "TARGET_FP" 1858 "div<modesuffix>%/ %R1,%R2,%0" 1859 [(set_attr "type" "fdiv") 1860 (set_attr "opsize" "<opmode>") 1861 (set_attr "trap" "yes") 1862 (set_attr "round_suffix" "normal") 1863 (set_attr "trap_suffix" "u_su_sui") 1864 (set (attr "enabled") 1865 (cond [(eq_attr "alternative" "0") 1866 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1867 ] 1868 (symbol_ref "true")))]) 1869 1870 (define_insn "*divdf_ext1" 1871 [(set (match_operand:DF 0 "register_operand" "=f") 1872 (div:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG")) 1873 (match_operand:DF 2 "reg_or_0_operand" "fG")))] 1874 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1875 "div%-%/ %R1,%R2,%0" 1876 [(set_attr "type" "fdiv") 1877 (set_attr "trap" "yes") 1878 (set_attr "round_suffix" "normal") 1879 (set_attr "trap_suffix" "u_su_sui")]) 1880 1881 (define_insn "*divdf_ext2" 1882 [(set (match_operand:DF 0 "register_operand" "=f") 1883 (div:DF (match_operand:DF 1 "reg_or_0_operand" "fG") 1884 (float_extend:DF 1885 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1886 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1887 "div%-%/ %R1,%R2,%0" 1888 [(set_attr "type" "fdiv") 1889 (set_attr "trap" "yes") 1890 (set_attr "round_suffix" "normal") 1891 (set_attr "trap_suffix" "u_su_sui")]) 1892 1893 (define_insn "*divdf_ext3" 1894 [(set (match_operand:DF 0 "register_operand" "=f") 1895 (div:DF (float_extend:DF 1896 (match_operand:SF 1 "reg_or_0_operand" "fG")) 1897 (float_extend:DF 1898 (match_operand:SF 2 "reg_or_0_operand" "fG"))))] 1899 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1900 "div%-%/ %R1,%R2,%0" 1901 [(set_attr "type" "fdiv") 1902 (set_attr "trap" "yes") 1903 (set_attr "round_suffix" "normal") 1904 (set_attr "trap_suffix" "u_su_sui")]) 1905 1906 (define_expand "divtf3" 1907 [(use (match_operand:TF 0 "register_operand")) 1908 (use (match_operand:TF 1 "general_operand")) 1909 (use (match_operand:TF 2 "general_operand"))] 1910 "TARGET_HAS_XFLOATING_LIBS" 1911 "alpha_emit_xfloating_arith (DIV, operands); DONE;") 1912 1913 (define_insn "sqrt<mode>2" 1914 [(set (match_operand:FMODE 0 "register_operand" "=f,&f") 1915 (sqrt:FMODE (match_operand:FMODE 1 "reg_or_0_operand" "fG,fG")))] 1916 "TARGET_FP && TARGET_FIX" 1917 "sqrt<modesuffix>%/ %R1,%0" 1918 [(set_attr "type" "fsqrt") 1919 (set_attr "opsize" "<opmode>") 1920 (set_attr "trap" "yes") 1921 (set_attr "round_suffix" "normal") 1922 (set_attr "trap_suffix" "u_su_sui") 1923 (set (attr "enabled") 1924 (cond [(eq_attr "alternative" "0") 1925 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1926 ] 1927 (symbol_ref "true")))]) 1928 1929 ;; Define conversion operators between DFmode and SImode, using the cvtql 1930 ;; instruction. To allow combine et al to do useful things, we keep the 1931 ;; operation as a unit until after reload, at which point we split the 1932 ;; instructions. 1933 ;; 1934 ;; Note that we (attempt to) only consider this optimization when the 1935 ;; ultimate destination is memory. If we will be doing further integer 1936 ;; processing, it is cheaper to do the truncation in the int regs. 1937 1938 (define_insn "*cvtql" 1939 [(set (match_operand:SF 0 "register_operand" "=f") 1940 (unspec:SF [(match_operand:DI 1 "reg_or_0_operand" "fG")] 1941 UNSPEC_CVTQL))] 1942 "TARGET_FP" 1943 "cvtql%/ %R1,%0" 1944 [(set_attr "type" "fadd") 1945 (set_attr "trap" "yes") 1946 (set_attr "trap_suffix" "v_sv")]) 1947 1948 (define_insn_and_split "*fix_truncdfsi_ieee" 1949 [(set (match_operand:SI 0 "memory_operand" "=m") 1950 (subreg:SI 1951 (match_operator:DI 4 "fix_operator" 1952 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1953 (clobber (match_scratch:DI 2 "=&f")) 1954 (clobber (match_scratch:SF 3 "=&f"))] 1955 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 1956 "#" 1957 "&& reload_completed" 1958 [(set (match_dup 2) (match_op_dup 4 [(match_dup 1)])) 1959 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1960 (set (match_dup 5) (match_dup 3))] 1961 { 1962 operands[5] = adjust_address (operands[0], SFmode, 0); 1963 } 1964 [(set_attr "type" "fadd") 1965 (set_attr "trap" "yes")]) 1966 1967 (define_insn_and_split "*fix_truncdfsi_internal" 1968 [(set (match_operand:SI 0 "memory_operand" "=m") 1969 (subreg:SI 1970 (match_operator:DI 3 "fix_operator" 1971 [(match_operand:DF 1 "reg_or_0_operand" "fG")]) 0)) 1972 (clobber (match_scratch:DI 2 "=f"))] 1973 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 1974 "#" 1975 "&& reload_completed" 1976 [(set (match_dup 2) (match_op_dup 3 [(match_dup 1)])) 1977 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 1978 (set (match_dup 5) (match_dup 4))] 1979 { 1980 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 1981 operands[5] = adjust_address (operands[0], SFmode, 0); 1982 } 1983 [(set_attr "type" "fadd") 1984 (set_attr "trap" "yes")]) 1985 1986 (define_insn "*fix_truncdfdi2" 1987 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 1988 (match_operator:DI 2 "fix_operator" 1989 [(match_operand:DF 1 "reg_or_0_operand" "fG,fG")]))] 1990 "TARGET_FP" 1991 "cvt%-q%/ %R1,%0" 1992 [(set_attr "type" "fadd") 1993 (set_attr "trap" "yes") 1994 (set_attr "round_suffix" "c") 1995 (set_attr "trap_suffix" "v_sv_svi") 1996 (set (attr "enabled") 1997 (cond [(eq_attr "alternative" "0") 1998 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 1999 ] 2000 (symbol_ref "true")))]) 2001 2002 (define_expand "fix_truncdfdi2" 2003 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2004 (fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2005 "TARGET_FP") 2006 2007 (define_expand "fixuns_truncdfdi2" 2008 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2009 (unsigned_fix:DI (match_operand:DF 1 "reg_or_0_operand")))] 2010 "TARGET_FP") 2011 2012 ;; Likewise between SFmode and SImode. 2013 2014 (define_insn_and_split "*fix_truncsfsi_ieee" 2015 [(set (match_operand:SI 0 "memory_operand" "=m") 2016 (subreg:SI 2017 (match_operator:DI 4 "fix_operator" 2018 [(float_extend:DF 2019 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2020 (clobber (match_scratch:DI 2 "=&f")) 2021 (clobber (match_scratch:SF 3 "=&f"))] 2022 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2023 "#" 2024 "&& reload_completed" 2025 [(set (match_dup 2) (match_op_dup 4 [(float_extend:DF (match_dup 1))])) 2026 (set (match_dup 3) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2027 (set (match_dup 5) (match_dup 3))] 2028 "operands[5] = adjust_address (operands[0], SFmode, 0);" 2029 [(set_attr "type" "fadd") 2030 (set_attr "trap" "yes")]) 2031 2032 (define_insn_and_split "*fix_truncsfsi_internal" 2033 [(set (match_operand:SI 0 "memory_operand" "=m") 2034 (subreg:SI 2035 (match_operator:DI 3 "fix_operator" 2036 [(float_extend:DF 2037 (match_operand:SF 1 "reg_or_0_operand" "fG"))]) 0)) 2038 (clobber (match_scratch:DI 2 "=f"))] 2039 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2040 "#" 2041 "&& reload_completed" 2042 [(set (match_dup 2) (match_op_dup 3 [(float_extend:DF (match_dup 1))])) 2043 (set (match_dup 4) (unspec:SF [(match_dup 2)] UNSPEC_CVTQL)) 2044 (set (match_dup 5) (match_dup 4))] 2045 { 2046 operands[4] = gen_rtx_REG (SFmode, REGNO (operands[2])); 2047 operands[5] = adjust_address (operands[0], SFmode, 0); 2048 } 2049 [(set_attr "type" "fadd") 2050 (set_attr "trap" "yes")]) 2051 2052 (define_insn "*fix_truncsfdi2" 2053 [(set (match_operand:DI 0 "reg_no_subreg_operand" "=f,&f") 2054 (match_operator:DI 2 "fix_operator" 2055 [(float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,fG"))]))] 2056 "TARGET_FP" 2057 "cvt%-q%/ %R1,%0" 2058 [(set_attr "type" "fadd") 2059 (set_attr "trap" "yes") 2060 (set_attr "round_suffix" "c") 2061 (set_attr "trap_suffix" "v_sv_svi") 2062 (set (attr "enabled") 2063 (cond [(eq_attr "alternative" "0") 2064 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2065 ] 2066 (symbol_ref "true")))]) 2067 2068 (define_expand "fix_truncsfdi2" 2069 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2070 (fix:DI (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2071 "TARGET_FP") 2072 2073 (define_expand "fixuns_truncsfdi2" 2074 [(set (match_operand:DI 0 "reg_no_subreg_operand") 2075 (unsigned_fix:DI 2076 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand"))))] 2077 "TARGET_FP") 2078 2079 (define_expand "fix_trunctfdi2" 2080 [(use (match_operand:DI 0 "register_operand")) 2081 (use (match_operand:TF 1 "general_operand"))] 2082 "TARGET_HAS_XFLOATING_LIBS" 2083 "alpha_emit_xfloating_cvt (FIX, operands); DONE;") 2084 2085 (define_expand "fixuns_trunctfdi2" 2086 [(use (match_operand:DI 0 "register_operand")) 2087 (use (match_operand:TF 1 "general_operand"))] 2088 "TARGET_HAS_XFLOATING_LIBS" 2089 "alpha_emit_xfloating_cvt (UNSIGNED_FIX, operands); DONE;") 2090 2091 (define_insn "floatdisf2" 2092 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2093 (float:SF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2094 "TARGET_FP" 2095 "cvtq%,%/ %1,%0" 2096 [(set_attr "type" "fadd") 2097 (set_attr "trap" "yes") 2098 (set_attr "round_suffix" "normal") 2099 (set_attr "trap_suffix" "sui") 2100 (set (attr "enabled") 2101 (cond [(eq_attr "alternative" "0") 2102 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2103 ] 2104 (symbol_ref "true")))]) 2105 2106 (define_insn_and_split "*floatsisf2_ieee" 2107 [(set (match_operand:SF 0 "register_operand" "=&f") 2108 (float:SF (match_operand:SI 1 "memory_operand" "m"))) 2109 (clobber (match_scratch:DI 2 "=&f")) 2110 (clobber (match_scratch:SF 3 "=&f"))] 2111 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2112 "#" 2113 "&& reload_completed" 2114 [(set (match_dup 3) (match_dup 1)) 2115 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2116 (set (match_dup 0) (float:SF (match_dup 2)))] 2117 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2118 2119 (define_insn_and_split "*floatsisf2" 2120 [(set (match_operand:SF 0 "register_operand" "=f") 2121 (float:SF (match_operand:SI 1 "memory_operand" "m")))] 2122 "TARGET_FP" 2123 "#" 2124 "&& reload_completed" 2125 [(set (match_dup 0) (match_dup 1)) 2126 (set (match_dup 2) (unspec:DI [(match_dup 0)] UNSPEC_CVTLQ)) 2127 (set (match_dup 0) (float:SF (match_dup 2)))] 2128 { 2129 operands[1] = adjust_address (operands[1], SFmode, 0); 2130 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2131 }) 2132 2133 (define_insn "floatdidf2" 2134 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2135 (float:DF (match_operand:DI 1 "reg_no_subreg_operand" "f,f")))] 2136 "TARGET_FP" 2137 "cvtq%-%/ %1,%0" 2138 [(set_attr "type" "fadd") 2139 (set_attr "trap" "yes") 2140 (set_attr "round_suffix" "normal") 2141 (set_attr "trap_suffix" "sui") 2142 (set (attr "enabled") 2143 (cond [(eq_attr "alternative" "0") 2144 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2145 ] 2146 (symbol_ref "true")))]) 2147 2148 (define_insn_and_split "*floatsidf2_ieee" 2149 [(set (match_operand:DF 0 "register_operand" "=&f") 2150 (float:DF (match_operand:SI 1 "memory_operand" "m"))) 2151 (clobber (match_scratch:DI 2 "=&f")) 2152 (clobber (match_scratch:SF 3 "=&f"))] 2153 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2154 "#" 2155 "&& reload_completed" 2156 [(set (match_dup 3) (match_dup 1)) 2157 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2158 (set (match_dup 0) (float:DF (match_dup 2)))] 2159 "operands[1] = adjust_address (operands[1], SFmode, 0);") 2160 2161 (define_insn_and_split "*floatsidf2" 2162 [(set (match_operand:DF 0 "register_operand" "=f") 2163 (float:DF (match_operand:SI 1 "memory_operand" "m")))] 2164 "TARGET_FP" 2165 "#" 2166 "&& reload_completed" 2167 [(set (match_dup 3) (match_dup 1)) 2168 (set (match_dup 2) (unspec:DI [(match_dup 3)] UNSPEC_CVTLQ)) 2169 (set (match_dup 0) (float:DF (match_dup 2)))] 2170 { 2171 operands[1] = adjust_address (operands[1], SFmode, 0); 2172 operands[2] = gen_rtx_REG (DImode, REGNO (operands[0])); 2173 operands[3] = gen_rtx_REG (SFmode, REGNO (operands[0])); 2174 }) 2175 2176 (define_expand "floatditf2" 2177 [(use (match_operand:TF 0 "register_operand")) 2178 (use (match_operand:DI 1 "general_operand"))] 2179 "TARGET_HAS_XFLOATING_LIBS" 2180 "alpha_emit_xfloating_cvt (FLOAT, operands); DONE;") 2181 2182 (define_expand "floatunsdisf2" 2183 [(use (match_operand:SF 0 "register_operand")) 2184 (use (match_operand:DI 1 "register_operand"))] 2185 "TARGET_FP" 2186 "alpha_emit_floatuns (operands); DONE;") 2187 2188 (define_expand "floatunsdidf2" 2189 [(use (match_operand:DF 0 "register_operand")) 2190 (use (match_operand:DI 1 "register_operand"))] 2191 "TARGET_FP" 2192 "alpha_emit_floatuns (operands); DONE;") 2193 2194 (define_expand "floatunsditf2" 2195 [(use (match_operand:TF 0 "register_operand")) 2196 (use (match_operand:DI 1 "general_operand"))] 2197 "TARGET_HAS_XFLOATING_LIBS" 2198 "alpha_emit_xfloating_cvt (UNSIGNED_FLOAT, operands); DONE;") 2199 2200 (define_expand "extendsfdf2" 2201 [(set (match_operand:DF 0 "register_operand") 2202 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand")))] 2203 "TARGET_FP" 2204 { 2205 if (alpha_fptm >= ALPHA_FPTM_SU) 2206 operands[1] = force_reg (SFmode, operands[1]); 2207 }) 2208 2209 ;; The Unicos/Mk assembler doesn't support cvtst, but we've already 2210 ;; asserted that alpha_fptm == ALPHA_FPTM_N. 2211 2212 (define_insn "*extendsfdf2_ieee" 2213 [(set (match_operand:DF 0 "register_operand" "=&f") 2214 (float_extend:DF (match_operand:SF 1 "register_operand" "f")))] 2215 "TARGET_FP && alpha_fptm >= ALPHA_FPTM_SU" 2216 "cvtsts %1,%0" 2217 [(set_attr "type" "fadd") 2218 (set_attr "trap" "yes")]) 2219 2220 (define_insn "*extendsfdf2_internal" 2221 [(set (match_operand:DF 0 "register_operand" "=f,f,m") 2222 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,m,f")))] 2223 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2224 "@ 2225 cpys %1,%1,%0 2226 ld%, %0,%1 2227 st%- %1,%0" 2228 [(set_attr "type" "fcpys,fld,fst")]) 2229 2230 ;; Use register_operand for operand 1 to prevent compress_float_constant 2231 ;; from doing something silly. When optimizing we'll put things back 2232 ;; together anyway. 2233 (define_expand "extendsftf2" 2234 [(use (match_operand:TF 0 "register_operand")) 2235 (use (match_operand:SF 1 "register_operand"))] 2236 "TARGET_HAS_XFLOATING_LIBS" 2237 { 2238 rtx tmp = gen_reg_rtx (DFmode); 2239 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 2240 emit_insn (gen_extenddftf2 (operands[0], tmp)); 2241 DONE; 2242 }) 2243 2244 (define_expand "extenddftf2" 2245 [(use (match_operand:TF 0 "register_operand")) 2246 (use (match_operand:DF 1 "register_operand"))] 2247 "TARGET_HAS_XFLOATING_LIBS" 2248 "alpha_emit_xfloating_cvt (FLOAT_EXTEND, operands); DONE;") 2249 2250 (define_insn "truncdfsf2" 2251 [(set (match_operand:SF 0 "register_operand" "=f,&f") 2252 (float_truncate:SF (match_operand:DF 1 "reg_or_0_operand" "fG,fG")))] 2253 "TARGET_FP" 2254 "cvt%-%,%/ %R1,%0" 2255 [(set_attr "type" "fadd") 2256 (set_attr "trap" "yes") 2257 (set_attr "round_suffix" "normal") 2258 (set_attr "trap_suffix" "u_su_sui") 2259 (set (attr "enabled") 2260 (cond [(eq_attr "alternative" "0") 2261 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2262 ] 2263 (symbol_ref "true")))]) 2264 2265 (define_expand "trunctfdf2" 2266 [(use (match_operand:DF 0 "register_operand")) 2267 (use (match_operand:TF 1 "general_operand"))] 2268 "TARGET_HAS_XFLOATING_LIBS" 2269 "alpha_emit_xfloating_cvt (FLOAT_TRUNCATE, operands); DONE;") 2270 2271 (define_expand "trunctfsf2" 2272 [(use (match_operand:SF 0 "register_operand")) 2273 (use (match_operand:TF 1 "general_operand"))] 2274 "TARGET_FP && TARGET_HAS_XFLOATING_LIBS" 2275 { 2276 rtx tmpf, sticky, arg, lo, hi; 2277 2278 tmpf = gen_reg_rtx (DFmode); 2279 sticky = gen_reg_rtx (DImode); 2280 arg = copy_to_mode_reg (TFmode, operands[1]); 2281 lo = gen_lowpart (DImode, arg); 2282 hi = gen_highpart (DImode, arg); 2283 2284 /* Convert the low word of the TFmode value into a sticky rounding bit, 2285 then or it into the low bit of the high word. This leaves the sticky 2286 bit at bit 48 of the fraction, which is representable in DFmode, 2287 which prevents rounding error in the final conversion to SFmode. */ 2288 2289 emit_insn (gen_rtx_SET (sticky, gen_rtx_NE (DImode, lo, const0_rtx))); 2290 emit_insn (gen_iordi3 (hi, hi, sticky)); 2291 emit_insn (gen_trunctfdf2 (tmpf, arg)); 2292 emit_insn (gen_truncdfsf2 (operands[0], tmpf)); 2293 DONE; 2294 }) 2295 2297 ;; Next are all the integer comparisons, and conditional moves and branches 2298 ;; and some of the related define_expand's and define_split's. 2299 2300 (define_insn "*setcc_internal" 2301 [(set (match_operand 0 "register_operand" "=r") 2302 (match_operator 1 "alpha_comparison_operator" 2303 [(match_operand:DI 2 "register_operand" "r") 2304 (match_operand:DI 3 "reg_or_8bit_operand" "rI")]))] 2305 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2306 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2307 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2308 "cmp%C1 %2,%3,%0" 2309 [(set_attr "type" "icmp")]) 2310 2311 ;; Yes, we can technically support reg_or_8bit_operand in operand 2, 2312 ;; but that's non-canonical rtl and allowing that causes inefficiencies 2313 ;; from cse on. 2314 (define_insn "*setcc_swapped_internal" 2315 [(set (match_operand 0 "register_operand" "=r") 2316 (match_operator 1 "alpha_swapped_comparison_operator" 2317 [(match_operand:DI 2 "register_operand" "r") 2318 (match_operand:DI 3 "reg_or_0_operand" "rJ")]))] 2319 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2320 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2321 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2322 "cmp%c1 %r3,%2,%0" 2323 [(set_attr "type" "icmp")]) 2324 2325 ;; Use match_operator rather than ne directly so that we can match 2326 ;; multiple integer modes. 2327 (define_insn "*setne_internal" 2328 [(set (match_operand 0 "register_operand" "=r") 2329 (match_operator 1 "signed_comparison_operator" 2330 [(match_operand:DI 2 "register_operand" "r") 2331 (const_int 0)]))] 2332 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT 2333 && GET_MODE_SIZE (GET_MODE (operands[0])) <= 8 2334 && GET_CODE (operands[1]) == NE 2335 && GET_MODE (operands[0]) == GET_MODE (operands[1])" 2336 "cmpult $31,%2,%0" 2337 [(set_attr "type" "icmp")]) 2338 2339 ;; The mode folding trick can't be used with const_int operands, since 2340 ;; reload needs to know the proper mode. 2341 ;; 2342 ;; Use add_operand instead of the more seemingly natural reg_or_8bit_operand 2343 ;; in order to create more pairs of constants. As long as we're allowing 2344 ;; two constants at the same time, and will have to reload one of them... 2345 2346 (define_insn "*mov<mode>cc_internal" 2347 [(set (match_operand:IMODE 0 "register_operand" "=r,r,r,r") 2348 (if_then_else:IMODE 2349 (match_operator 2 "signed_comparison_operator" 2350 [(match_operand:DI 3 "reg_or_0_operand" "rJ,rJ,J,J") 2351 (match_operand:DI 4 "reg_or_0_operand" "J,J,rJ,rJ")]) 2352 (match_operand:IMODE 1 "add_operand" "rI,0,rI,0") 2353 (match_operand:IMODE 5 "add_operand" "0,rI,0,rI")))] 2354 "(operands[3] == const0_rtx) ^ (operands[4] == const0_rtx)" 2355 "@ 2356 cmov%C2 %r3,%1,%0 2357 cmov%D2 %r3,%5,%0 2358 cmov%c2 %r4,%1,%0 2359 cmov%d2 %r4,%5,%0" 2360 [(set_attr "type" "icmov")]) 2361 2362 (define_insn "*mov<mode>cc_lbc" 2363 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2364 (if_then_else:IMODE 2365 (eq (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2366 (const_int 1) 2367 (const_int 0)) 2368 (const_int 0)) 2369 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2370 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2371 "" 2372 "@ 2373 cmovlbc %r2,%1,%0 2374 cmovlbs %r2,%3,%0" 2375 [(set_attr "type" "icmov")]) 2376 2377 (define_insn "*mov<mode>cc_lbs" 2378 [(set (match_operand:IMODE 0 "register_operand" "=r,r") 2379 (if_then_else:IMODE 2380 (ne (zero_extract:DI (match_operand:DI 2 "reg_or_0_operand" "rJ,rJ") 2381 (const_int 1) 2382 (const_int 0)) 2383 (const_int 0)) 2384 (match_operand:IMODE 1 "reg_or_8bit_operand" "rI,0") 2385 (match_operand:IMODE 3 "reg_or_8bit_operand" "0,rI")))] 2386 "" 2387 "@ 2388 cmovlbs %r2,%1,%0 2389 cmovlbc %r2,%3,%0" 2390 [(set_attr "type" "icmov")]) 2391 2392 ;; For ABS, we have two choices, depending on whether the input and output 2393 ;; registers are the same or not. 2394 (define_expand "absdi2" 2395 [(set (match_operand:DI 0 "register_operand") 2396 (abs:DI (match_operand:DI 1 "register_operand")))] 2397 "" 2398 { 2399 if (rtx_equal_p (operands[0], operands[1])) 2400 emit_insn (gen_absdi2_same (operands[0], gen_reg_rtx (DImode))); 2401 else 2402 emit_insn (gen_absdi2_diff (operands[0], operands[1])); 2403 DONE; 2404 }) 2405 2406 (define_expand "absdi2_same" 2407 [(set (match_operand:DI 1 "register_operand") 2408 (neg:DI (match_operand:DI 0 "register_operand"))) 2409 (set (match_dup 0) 2410 (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2411 (match_dup 0) 2412 (match_dup 1)))]) 2413 2414 (define_expand "absdi2_diff" 2415 [(set (match_operand:DI 0 "register_operand") 2416 (neg:DI (match_operand:DI 1 "register_operand"))) 2417 (set (match_dup 0) 2418 (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2419 (match_dup 0) 2420 (match_dup 1)))]) 2421 2422 (define_split 2423 [(set (match_operand:DI 0 "register_operand") 2424 (abs:DI (match_dup 0))) 2425 (clobber (match_operand:DI 1 "register_operand"))] 2426 "" 2427 [(set (match_dup 1) (neg:DI (match_dup 0))) 2428 (set (match_dup 0) (if_then_else:DI (ge (match_dup 0) (const_int 0)) 2429 (match_dup 0) (match_dup 1)))]) 2430 2431 (define_split 2432 [(set (match_operand:DI 0 "register_operand") 2433 (abs:DI (match_operand:DI 1 "register_operand")))] 2434 "! rtx_equal_p (operands[0], operands[1])" 2435 [(set (match_dup 0) (neg:DI (match_dup 1))) 2436 (set (match_dup 0) (if_then_else:DI (lt (match_dup 1) (const_int 0)) 2437 (match_dup 0) (match_dup 1)))]) 2438 2439 (define_split 2440 [(set (match_operand:DI 0 "register_operand") 2441 (neg:DI (abs:DI (match_dup 0)))) 2442 (clobber (match_operand:DI 1 "register_operand"))] 2443 "" 2444 [(set (match_dup 1) (neg:DI (match_dup 0))) 2445 (set (match_dup 0) (if_then_else:DI (le (match_dup 0) (const_int 0)) 2446 (match_dup 0) (match_dup 1)))]) 2447 2448 (define_split 2449 [(set (match_operand:DI 0 "register_operand") 2450 (neg:DI (abs:DI (match_operand:DI 1 "register_operand"))))] 2451 "! rtx_equal_p (operands[0], operands[1])" 2452 [(set (match_dup 0) (neg:DI (match_dup 1))) 2453 (set (match_dup 0) (if_then_else:DI (gt (match_dup 1) (const_int 0)) 2454 (match_dup 0) (match_dup 1)))]) 2455 2456 (define_insn "<code><mode>3" 2457 [(set (match_operand:I12MODE 0 "register_operand" "=r") 2458 (any_maxmin:I12MODE 2459 (match_operand:I12MODE 1 "reg_or_0_operand" "%rJ") 2460 (match_operand:I12MODE 2 "reg_or_8bit_operand" "rI")))] 2461 "TARGET_MAX" 2462 "<maxmin><vecmodesuffix> %r1,%2,%0" 2463 [(set_attr "type" "mvi")]) 2464 2465 (define_expand "smaxdi3" 2466 [(set (match_dup 3) 2467 (le:DI (match_operand:DI 1 "reg_or_0_operand") 2468 (match_operand:DI 2 "reg_or_8bit_operand"))) 2469 (set (match_operand:DI 0 "register_operand") 2470 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2471 (match_dup 1) (match_dup 2)))] 2472 "" 2473 "operands[3] = gen_reg_rtx (DImode);") 2474 2475 (define_split 2476 [(set (match_operand:DI 0 "register_operand") 2477 (smax:DI (match_operand:DI 1 "reg_or_0_operand") 2478 (match_operand:DI 2 "reg_or_8bit_operand"))) 2479 (clobber (match_operand:DI 3 "register_operand"))] 2480 "operands[2] != const0_rtx" 2481 [(set (match_dup 3) (le:DI (match_dup 1) (match_dup 2))) 2482 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2483 (match_dup 1) (match_dup 2)))]) 2484 2485 (define_insn "*smax_const0" 2486 [(set (match_operand:DI 0 "register_operand" "=r") 2487 (smax:DI (match_operand:DI 1 "register_operand" "0") 2488 (const_int 0)))] 2489 "" 2490 "cmovlt %0,0,%0" 2491 [(set_attr "type" "icmov")]) 2492 2493 (define_expand "smindi3" 2494 [(set (match_dup 3) 2495 (lt:DI (match_operand:DI 1 "reg_or_0_operand") 2496 (match_operand:DI 2 "reg_or_8bit_operand"))) 2497 (set (match_operand:DI 0 "register_operand") 2498 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2499 (match_dup 1) (match_dup 2)))] 2500 "" 2501 "operands[3] = gen_reg_rtx (DImode);") 2502 2503 (define_split 2504 [(set (match_operand:DI 0 "register_operand") 2505 (smin:DI (match_operand:DI 1 "reg_or_0_operand") 2506 (match_operand:DI 2 "reg_or_8bit_operand"))) 2507 (clobber (match_operand:DI 3 "register_operand"))] 2508 "operands[2] != const0_rtx" 2509 [(set (match_dup 3) (lt:DI (match_dup 1) (match_dup 2))) 2510 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2511 (match_dup 1) (match_dup 2)))]) 2512 2513 (define_insn "*smin_const0" 2514 [(set (match_operand:DI 0 "register_operand" "=r") 2515 (smin:DI (match_operand:DI 1 "register_operand" "0") 2516 (const_int 0)))] 2517 "" 2518 "cmovgt %0,0,%0" 2519 [(set_attr "type" "icmov")]) 2520 2521 (define_expand "umaxdi3" 2522 [(set (match_dup 3) 2523 (leu:DI (match_operand:DI 1 "reg_or_0_operand") 2524 (match_operand:DI 2 "reg_or_8bit_operand"))) 2525 (set (match_operand:DI 0 "register_operand") 2526 (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2527 (match_dup 1) (match_dup 2)))] 2528 "" 2529 "operands[3] = gen_reg_rtx (DImode);") 2530 2531 (define_split 2532 [(set (match_operand:DI 0 "register_operand") 2533 (umax:DI (match_operand:DI 1 "reg_or_0_operand") 2534 (match_operand:DI 2 "reg_or_8bit_operand"))) 2535 (clobber (match_operand:DI 3 "register_operand"))] 2536 "operands[2] != const0_rtx" 2537 [(set (match_dup 3) (leu:DI (match_dup 1) (match_dup 2))) 2538 (set (match_dup 0) (if_then_else:DI (eq (match_dup 3) (const_int 0)) 2539 (match_dup 1) (match_dup 2)))]) 2540 2541 (define_expand "umindi3" 2542 [(set (match_dup 3) 2543 (ltu:DI (match_operand:DI 1 "reg_or_0_operand") 2544 (match_operand:DI 2 "reg_or_8bit_operand"))) 2545 (set (match_operand:DI 0 "register_operand") 2546 (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2547 (match_dup 1) (match_dup 2)))] 2548 "" 2549 "operands[3] = gen_reg_rtx (DImode);") 2550 2551 (define_split 2552 [(set (match_operand:DI 0 "register_operand") 2553 (umin:DI (match_operand:DI 1 "reg_or_0_operand") 2554 (match_operand:DI 2 "reg_or_8bit_operand"))) 2555 (clobber (match_operand:DI 3 "register_operand"))] 2556 "operands[2] != const0_rtx" 2557 [(set (match_dup 3) (ltu:DI (match_dup 1) (match_dup 2))) 2558 (set (match_dup 0) (if_then_else:DI (ne (match_dup 3) (const_int 0)) 2559 (match_dup 1) (match_dup 2)))]) 2560 2561 (define_insn "*bcc_normal" 2562 [(set (pc) 2563 (if_then_else 2564 (match_operator 1 "signed_comparison_operator" 2565 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 2566 (const_int 0)]) 2567 (label_ref (match_operand 0)) 2568 (pc)))] 2569 "" 2570 "b%C1 %r2,%0" 2571 [(set_attr "type" "ibr")]) 2572 2573 (define_insn "*bcc_reverse" 2574 [(set (pc) 2575 (if_then_else 2576 (match_operator 1 "signed_comparison_operator" 2577 [(match_operand:DI 2 "register_operand" "r") 2578 (const_int 0)]) 2579 2580 (pc) 2581 (label_ref (match_operand 0))))] 2582 "" 2583 "b%c1 %2,%0" 2584 [(set_attr "type" "ibr")]) 2585 2586 (define_insn "*blbs_normal" 2587 [(set (pc) 2588 (if_then_else 2589 (ne (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2590 (const_int 1) 2591 (const_int 0)) 2592 (const_int 0)) 2593 (label_ref (match_operand 0)) 2594 (pc)))] 2595 "" 2596 "blbs %r1,%0" 2597 [(set_attr "type" "ibr")]) 2598 2599 (define_insn "*blbc_normal" 2600 [(set (pc) 2601 (if_then_else 2602 (eq (zero_extract:DI (match_operand:DI 1 "reg_or_0_operand" "rJ") 2603 (const_int 1) 2604 (const_int 0)) 2605 (const_int 0)) 2606 (label_ref (match_operand 0)) 2607 (pc)))] 2608 "" 2609 "blbc %r1,%0" 2610 [(set_attr "type" "ibr")]) 2611 2612 (define_split 2613 [(parallel 2614 [(set (pc) 2615 (if_then_else 2616 (match_operator 1 "comparison_operator" 2617 [(zero_extract:DI (match_operand:DI 2 "register_operand") 2618 (const_int 1) 2619 (match_operand:DI 3 "const_int_operand")) 2620 (const_int 0)]) 2621 (label_ref (match_operand 0)) 2622 (pc))) 2623 (clobber (match_operand:DI 4 "register_operand"))])] 2624 "INTVAL (operands[3]) != 0" 2625 [(set (match_dup 4) 2626 (lshiftrt:DI (match_dup 2) (match_dup 3))) 2627 (set (pc) 2628 (if_then_else (match_op_dup 1 2629 [(zero_extract:DI (match_dup 4) 2630 (const_int 1) 2631 (const_int 0)) 2632 (const_int 0)]) 2633 (label_ref (match_dup 0)) 2634 (pc)))] 2635 ) 2636 2638 ;; The following are the corresponding floating-point insns. Recall 2639 ;; we need to have variants that expand the arguments from SFmode 2640 ;; to DFmode. 2641 2642 (define_insn "*cmpdf_internal" 2643 [(set (match_operand:DF 0 "register_operand" "=f,&f") 2644 (match_operator:DF 1 "alpha_fp_comparison_operator" 2645 [(match_operand:DF 2 "reg_or_0_operand" "fG,fG") 2646 (match_operand:DF 3 "reg_or_0_operand" "fG,fG")]))] 2647 "TARGET_FP" 2648 "cmp%-%C1%/ %R2,%R3,%0" 2649 [(set_attr "type" "fadd") 2650 (set_attr "trap" "yes") 2651 (set_attr "trap_suffix" "su") 2652 (set (attr "enabled") 2653 (cond [(eq_attr "alternative" "0") 2654 (symbol_ref "alpha_fptm < ALPHA_FPTM_SU") 2655 ] 2656 (symbol_ref "true")))]) 2657 2658 (define_insn "*cmpdf_ext1" 2659 [(set (match_operand:DF 0 "register_operand" "=f") 2660 (match_operator:DF 1 "alpha_fp_comparison_operator" 2661 [(float_extend:DF 2662 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2663 (match_operand:DF 3 "reg_or_0_operand" "fG")]))] 2664 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2665 "cmp%-%C1%/ %R2,%R3,%0" 2666 [(set_attr "type" "fadd") 2667 (set_attr "trap" "yes") 2668 (set_attr "trap_suffix" "su")]) 2669 2670 (define_insn "*cmpdf_ext2" 2671 [(set (match_operand:DF 0 "register_operand" "=f") 2672 (match_operator:DF 1 "alpha_fp_comparison_operator" 2673 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2674 (float_extend:DF 2675 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2676 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2677 "cmp%-%C1%/ %R2,%R3,%0" 2678 [(set_attr "type" "fadd") 2679 (set_attr "trap" "yes") 2680 (set_attr "trap_suffix" "su")]) 2681 2682 (define_insn "*cmpdf_ext3" 2683 [(set (match_operand:DF 0 "register_operand" "=f") 2684 (match_operator:DF 1 "alpha_fp_comparison_operator" 2685 [(float_extend:DF 2686 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2687 (float_extend:DF 2688 (match_operand:SF 3 "reg_or_0_operand" "fG"))]))] 2689 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2690 "cmp%-%C1%/ %R2,%R3,%0" 2691 [(set_attr "type" "fadd") 2692 (set_attr "trap" "yes") 2693 (set_attr "trap_suffix" "su")]) 2694 2695 (define_insn "*mov<mode>cc_internal" 2696 [(set (match_operand:FMODE 0 "register_operand" "=f,f") 2697 (if_then_else:FMODE 2698 (match_operator 3 "signed_comparison_operator" 2699 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2700 (match_operand:DF 2 "const0_operand" "G,G")]) 2701 (match_operand:FMODE 1 "reg_or_0_operand" "fG,0") 2702 (match_operand:FMODE 5 "reg_or_0_operand" "0,fG")))] 2703 "TARGET_FP" 2704 "@ 2705 fcmov%C3 %R4,%R1,%0 2706 fcmov%D3 %R4,%R5,%0" 2707 [(set_attr "type" "fcmov")]) 2708 2709 (define_insn "*movdfcc_ext1" 2710 [(set (match_operand:DF 0 "register_operand" "=f,f") 2711 (if_then_else:DF 2712 (match_operator 3 "signed_comparison_operator" 2713 [(match_operand:DF 4 "reg_or_0_operand" "fG,fG") 2714 (match_operand:DF 2 "const0_operand" "G,G")]) 2715 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2716 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2717 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2718 "@ 2719 fcmov%C3 %R4,%R1,%0 2720 fcmov%D3 %R4,%R5,%0" 2721 [(set_attr "type" "fcmov")]) 2722 2723 (define_insn "*movdfcc_ext2" 2724 [(set (match_operand:DF 0 "register_operand" "=f,f") 2725 (if_then_else:DF 2726 (match_operator 3 "signed_comparison_operator" 2727 [(float_extend:DF 2728 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2729 (match_operand:DF 2 "const0_operand" "G,G")]) 2730 (match_operand:DF 1 "reg_or_0_operand" "fG,0") 2731 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2732 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2733 "@ 2734 fcmov%C3 %R4,%R1,%0 2735 fcmov%D3 %R4,%R5,%0" 2736 [(set_attr "type" "fcmov")]) 2737 2738 (define_insn "*movdfcc_ext3" 2739 [(set (match_operand:SF 0 "register_operand" "=f,f") 2740 (if_then_else:SF 2741 (match_operator 3 "signed_comparison_operator" 2742 [(float_extend:DF 2743 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2744 (match_operand:DF 2 "const0_operand" "G,G")]) 2745 (match_operand:SF 1 "reg_or_0_operand" "fG,0") 2746 (match_operand:SF 5 "reg_or_0_operand" "0,fG")))] 2747 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2748 "@ 2749 fcmov%C3 %R4,%R1,%0 2750 fcmov%D3 %R4,%R5,%0" 2751 [(set_attr "type" "fcmov")]) 2752 2753 (define_insn "*movdfcc_ext4" 2754 [(set (match_operand:DF 0 "register_operand" "=f,f") 2755 (if_then_else:DF 2756 (match_operator 3 "signed_comparison_operator" 2757 [(float_extend:DF 2758 (match_operand:SF 4 "reg_or_0_operand" "fG,fG")) 2759 (match_operand:DF 2 "const0_operand" "G,G")]) 2760 (float_extend:DF (match_operand:SF 1 "reg_or_0_operand" "fG,0")) 2761 (match_operand:DF 5 "reg_or_0_operand" "0,fG")))] 2762 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2763 "@ 2764 fcmov%C3 %R4,%R1,%0 2765 fcmov%D3 %R4,%R5,%0" 2766 [(set_attr "type" "fcmov")]) 2767 2768 (define_expand "smaxdf3" 2769 [(set (match_dup 3) 2770 (le:DF (match_operand:DF 1 "reg_or_0_operand") 2771 (match_operand:DF 2 "reg_or_0_operand"))) 2772 (set (match_operand:DF 0 "register_operand") 2773 (if_then_else:DF (eq (match_dup 3) (match_dup 4)) 2774 (match_dup 1) (match_dup 2)))] 2775 "TARGET_FP" 2776 { 2777 operands[3] = gen_reg_rtx (DFmode); 2778 operands[4] = CONST0_RTX (DFmode); 2779 }) 2780 2781 (define_expand "smindf3" 2782 [(set (match_dup 3) 2783 (lt:DF (match_operand:DF 1 "reg_or_0_operand") 2784 (match_operand:DF 2 "reg_or_0_operand"))) 2785 (set (match_operand:DF 0 "register_operand") 2786 (if_then_else:DF (ne (match_dup 3) (match_dup 4)) 2787 (match_dup 1) (match_dup 2)))] 2788 "TARGET_FP" 2789 { 2790 operands[3] = gen_reg_rtx (DFmode); 2791 operands[4] = CONST0_RTX (DFmode); 2792 }) 2793 2794 (define_expand "smaxsf3" 2795 [(set (match_dup 3) 2796 (le:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2797 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2798 (set (match_operand:SF 0 "register_operand") 2799 (if_then_else:SF (eq (match_dup 3) (match_dup 4)) 2800 (match_dup 1) (match_dup 2)))] 2801 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2802 { 2803 operands[3] = gen_reg_rtx (DFmode); 2804 operands[4] = CONST0_RTX (DFmode); 2805 }) 2806 2807 (define_expand "sminsf3" 2808 [(set (match_dup 3) 2809 (lt:DF (float_extend:DF (match_operand:SF 1 "reg_or_0_operand")) 2810 (float_extend:DF (match_operand:SF 2 "reg_or_0_operand")))) 2811 (set (match_operand:SF 0 "register_operand") 2812 (if_then_else:SF (ne (match_dup 3) (match_dup 4)) 2813 (match_dup 1) (match_dup 2)))] 2814 "TARGET_FP && alpha_fptm < ALPHA_FPTM_SU" 2815 { 2816 operands[3] = gen_reg_rtx (DFmode); 2817 operands[4] = CONST0_RTX (DFmode); 2818 }) 2819 2820 (define_insn "*fbcc_normal" 2821 [(set (pc) 2822 (if_then_else 2823 (match_operator 1 "signed_comparison_operator" 2824 [(match_operand:DF 2 "reg_or_0_operand" "fG") 2825 (match_operand:DF 3 "const0_operand" "G")]) 2826 (label_ref (match_operand 0)) 2827 (pc)))] 2828 "TARGET_FP" 2829 "fb%C1 %R2,%0" 2830 [(set_attr "type" "fbr")]) 2831 2832 (define_insn "*fbcc_ext_normal" 2833 [(set (pc) 2834 (if_then_else 2835 (match_operator 1 "signed_comparison_operator" 2836 [(float_extend:DF 2837 (match_operand:SF 2 "reg_or_0_operand" "fG")) 2838 (match_operand:DF 3 "const0_operand" "G")]) 2839 (label_ref (match_operand 0)) 2840 (pc)))] 2841 "TARGET_FP" 2842 "fb%C1 %R2,%0" 2843 [(set_attr "type" "fbr")]) 2844 2846 ;; These are the main define_expand's used to make conditional branches 2847 ;; and compares. 2848 2849 (define_expand "cbranchdf4" 2850 [(use (match_operator 0 "alpha_cbranch_operator" 2851 [(match_operand:DF 1 "reg_or_0_operand") 2852 (match_operand:DF 2 "reg_or_0_operand")])) 2853 (use (match_operand 3))] 2854 "TARGET_FP" 2855 "alpha_emit_conditional_branch (operands, DFmode); DONE;") 2856 2857 (define_expand "cbranchtf4" 2858 [(use (match_operator 0 "alpha_cbranch_operator" 2859 [(match_operand:TF 1 "general_operand") 2860 (match_operand:TF 2 "general_operand")])) 2861 (use (match_operand 3))] 2862 "TARGET_HAS_XFLOATING_LIBS" 2863 "alpha_emit_conditional_branch (operands, TFmode); DONE;") 2864 2865 (define_expand "cbranchdi4" 2866 [(use (match_operator 0 "alpha_cbranch_operator" 2867 [(match_operand:DI 1 "general_operand") 2868 (match_operand:DI 2 "general_operand")])) 2869 (use (match_operand 3))] 2870 "" 2871 "alpha_emit_conditional_branch (operands, DImode); DONE;") 2872 2873 (define_expand "cstoredf4" 2874 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2875 [(match_operand:DF 2 "reg_or_0_operand") 2876 (match_operand:DF 3 "reg_or_0_operand")])) 2877 (clobber (match_operand:DI 0 "register_operand"))] 2878 "TARGET_FP" 2879 { 2880 if (alpha_emit_setcc (operands, DFmode)) 2881 DONE; 2882 else 2883 FAIL; 2884 }) 2885 2886 (define_expand "cstoretf4" 2887 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2888 [(match_operand:TF 2 "general_operand") 2889 (match_operand:TF 3 "general_operand")])) 2890 (clobber (match_operand:DI 0 "register_operand"))] 2891 "TARGET_HAS_XFLOATING_LIBS" 2892 { 2893 if (alpha_emit_setcc (operands, TFmode)) 2894 DONE; 2895 else 2896 FAIL; 2897 }) 2898 2899 (define_expand "cstoredi4" 2900 [(use (match_operator:DI 1 "alpha_cbranch_operator" 2901 [(match_operand:DI 2 "general_operand") 2902 (match_operand:DI 3 "general_operand")])) 2903 (clobber (match_operand:DI 0 "register_operand"))] 2904 "" 2905 { 2906 if (alpha_emit_setcc (operands, DImode)) 2907 DONE; 2908 else 2909 FAIL; 2910 }) 2911 2913 ;; These are the main define_expand's used to make conditional moves. 2914 2915 (define_expand "mov<mode>cc" 2916 [(set (match_operand:I48MODE 0 "register_operand") 2917 (if_then_else:I48MODE 2918 (match_operand 1 "comparison_operator") 2919 (match_operand:I48MODE 2 "reg_or_8bit_operand") 2920 (match_operand:I48MODE 3 "reg_or_8bit_operand")))] 2921 "" 2922 { 2923 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2924 if (operands[1] == 0) 2925 FAIL; 2926 }) 2927 2928 (define_expand "mov<mode>cc" 2929 [(set (match_operand:FMODE 0 "register_operand") 2930 (if_then_else:FMODE 2931 (match_operand 1 "comparison_operator") 2932 (match_operand:FMODE 2 "reg_or_8bit_operand") 2933 (match_operand:FMODE 3 "reg_or_8bit_operand")))] 2934 "" 2935 { 2936 operands[1] = alpha_emit_conditional_move (operands[1], <MODE>mode); 2937 if (operands[1] == 0) 2938 FAIL; 2939 }) 2940 2942 ;; These define_split definitions are used in cases when comparisons have 2943 ;; not be stated in the correct way and we need to reverse the second 2944 ;; comparison. For example, x >= 7 has to be done as x < 6 with the 2945 ;; comparison that tests the result being reversed. We have one define_split 2946 ;; for each use of a comparison. They do not match valid insns and need 2947 ;; not generate valid insns. 2948 ;; 2949 ;; We can also handle equality comparisons (and inequality comparisons in 2950 ;; cases where the resulting add cannot overflow) by doing an add followed by 2951 ;; a comparison with zero. This is faster since the addition takes one 2952 ;; less cycle than a compare when feeding into a conditional move. 2953 ;; For this case, we also have an SImode pattern since we can merge the add 2954 ;; and sign extend and the order doesn't matter. 2955 ;; 2956 ;; We do not do this for floating-point, since it isn't clear how the "wrong" 2957 ;; operation could have been generated. 2958 2959 (define_split 2960 [(set (match_operand:DI 0 "register_operand") 2961 (if_then_else:DI 2962 (match_operator 1 "comparison_operator" 2963 [(match_operand:DI 2 "reg_or_0_operand") 2964 (match_operand:DI 3 "reg_or_cint_operand")]) 2965 (match_operand:DI 4 "reg_or_cint_operand") 2966 (match_operand:DI 5 "reg_or_cint_operand"))) 2967 (clobber (match_operand:DI 6 "register_operand"))] 2968 "operands[3] != const0_rtx" 2969 [(set (match_dup 6) (match_dup 7)) 2970 (set (match_dup 0) 2971 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 2972 { 2973 enum rtx_code code = GET_CODE (operands[1]); 2974 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 2975 2976 /* If we are comparing for equality with a constant and that constant 2977 appears in the arm when the register equals the constant, use the 2978 register since that is more likely to match (and to produce better code 2979 if both would). */ 2980 2981 if (code == EQ && CONST_INT_P (operands[3]) 2982 && rtx_equal_p (operands[4], operands[3])) 2983 operands[4] = operands[2]; 2984 2985 else if (code == NE && CONST_INT_P (operands[3]) 2986 && rtx_equal_p (operands[5], operands[3])) 2987 operands[5] = operands[2]; 2988 2989 if (code == NE || code == EQ 2990 || (extended_count (operands[2], DImode, unsignedp) >= 1 2991 && extended_count (operands[3], DImode, unsignedp) >= 1)) 2992 { 2993 if (CONST_INT_P (operands[3])) 2994 operands[7] = gen_rtx_PLUS (DImode, operands[2], 2995 GEN_INT (- INTVAL (operands[3]))); 2996 else 2997 operands[7] = gen_rtx_MINUS (DImode, operands[2], operands[3]); 2998 2999 operands[8] = gen_rtx_fmt_ee (code, VOIDmode, operands[6], const0_rtx); 3000 } 3001 3002 else if (code == EQ || code == LE || code == LT 3003 || code == LEU || code == LTU) 3004 { 3005 operands[7] = gen_rtx_fmt_ee (code, DImode, operands[2], operands[3]); 3006 operands[8] = gen_rtx_NE (VOIDmode, operands[6], const0_rtx); 3007 } 3008 else 3009 { 3010 operands[7] = gen_rtx_fmt_ee (reverse_condition (code), DImode, 3011 operands[2], operands[3]); 3012 operands[8] = gen_rtx_EQ (VOIDmode, operands[6], const0_rtx); 3013 } 3014 }) 3015 3016 (define_split 3017 [(set (match_operand:DI 0 "register_operand") 3018 (if_then_else:DI 3019 (match_operator 1 "comparison_operator" 3020 [(match_operand:SI 2 "reg_or_0_operand") 3021 (match_operand:SI 3 "reg_or_cint_operand")]) 3022 (match_operand:DI 4 "reg_or_8bit_operand") 3023 (match_operand:DI 5 "reg_or_8bit_operand"))) 3024 (clobber (match_operand:DI 6 "register_operand"))] 3025 "operands[3] != const0_rtx 3026 && (GET_CODE (operands[1]) == EQ || GET_CODE (operands[1]) == NE)" 3027 [(set (match_dup 6) (match_dup 7)) 3028 (set (match_dup 0) 3029 (if_then_else:DI (match_dup 8) (match_dup 4) (match_dup 5)))] 3030 { 3031 enum rtx_code code = GET_CODE (operands[1]); 3032 int unsignedp = (code == GEU || code == LEU || code == GTU || code == LTU); 3033 rtx tem; 3034 3035 if ((code != NE && code != EQ 3036 && ! (extended_count (operands[2], DImode, unsignedp) >= 1 3037 && extended_count (operands[3], DImode, unsignedp) >= 1))) 3038 FAIL; 3039 3040 if (CONST_INT_P (operands[3])) 3041 tem = gen_rtx_PLUS (SImode, operands[2], 3042 GEN_INT (- INTVAL (operands[3]))); 3043 else 3044 tem = gen_rtx_MINUS (SImode, operands[2], operands[3]); 3045 3046 operands[7] = gen_rtx_SIGN_EXTEND (DImode, tem); 3047 operands[8] = gen_rtx_fmt_ee (GET_CODE (operands[1]), VOIDmode, 3048 operands[6], const0_rtx); 3049 }) 3050 3051 ;; Prefer to use cmp and arithmetic when possible instead of a cmove. 3052 3053 (define_split 3054 [(set (match_operand 0 "register_operand") 3055 (if_then_else (match_operator 1 "signed_comparison_operator" 3056 [(match_operand:DI 2 "reg_or_0_operand") 3057 (const_int 0)]) 3058 (match_operand 3 "const_int_operand") 3059 (match_operand 4 "const_int_operand")))] 3060 "" 3061 [(const_int 0)] 3062 { 3063 if (alpha_split_conditional_move (GET_CODE (operands[1]), operands[0], 3064 operands[2], operands[3], operands[4])) 3065 DONE; 3066 else 3067 FAIL; 3068 }) 3069 3070 ;; ??? Why combine is allowed to create such non-canonical rtl, I don't know. 3071 ;; Oh well, we match it in movcc, so it must be partially our fault. 3072 (define_split 3073 [(set (match_operand 0 "register_operand") 3074 (if_then_else (match_operator 1 "signed_comparison_operator" 3075 [(const_int 0) 3076 (match_operand:DI 2 "reg_or_0_operand")]) 3077 (match_operand 3 "const_int_operand") 3078 (match_operand 4 "const_int_operand")))] 3079 "" 3080 [(const_int 0)] 3081 { 3082 if (alpha_split_conditional_move (swap_condition (GET_CODE (operands[1])), 3083 operands[0], operands[2], operands[3], 3084 operands[4])) 3085 DONE; 3086 else 3087 FAIL; 3088 }) 3089 3090 (define_insn_and_split "*cmp_sadd_di" 3091 [(set (match_operand:DI 0 "register_operand" "=r") 3092 (plus:DI (if_then_else:DI 3093 (match_operator 1 "alpha_zero_comparison_operator" 3094 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3095 (const_int 0)]) 3096 (match_operand:DI 3 "const48_operand" "I") 3097 (const_int 0)) 3098 (match_operand:DI 4 "sext_add_operand" "rIO"))) 3099 (clobber (match_scratch:DI 5 "=r"))] 3100 "" 3101 "#" 3102 "" 3103 [(set (match_dup 5) 3104 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3105 (set (match_dup 0) 3106 (plus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3107 (match_dup 4)))] 3108 { 3109 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3110 if (can_create_pseudo_p ()) 3111 operands[5] = gen_reg_rtx (DImode); 3112 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3113 operands[5] = operands[0]; 3114 }) 3115 3116 (define_insn_and_split "*cmp_sadd_si" 3117 [(set (match_operand:SI 0 "register_operand" "=r") 3118 (plus:SI (if_then_else:SI 3119 (match_operator 1 "alpha_zero_comparison_operator" 3120 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3121 (const_int 0)]) 3122 (match_operand:SI 3 "const48_operand" "I") 3123 (const_int 0)) 3124 (match_operand:SI 4 "sext_add_operand" "rIO"))) 3125 (clobber (match_scratch:DI 5 "=r"))] 3126 "" 3127 "#" 3128 "" 3129 [(set (match_dup 5) 3130 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3131 (set (match_dup 0) 3132 (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3133 (match_dup 4)))] 3134 { 3135 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3136 if (can_create_pseudo_p ()) 3137 operands[5] = gen_reg_rtx (DImode); 3138 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3139 operands[5] = gen_lowpart (DImode, operands[0]); 3140 3141 operands[6] = gen_lowpart (SImode, operands[5]); 3142 }) 3143 3144 (define_insn_and_split "*cmp_sadd_sidi" 3145 [(set (match_operand:DI 0 "register_operand" "=r") 3146 (sign_extend:DI 3147 (plus:SI (if_then_else:SI 3148 (match_operator 1 "alpha_zero_comparison_operator" 3149 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3150 (const_int 0)]) 3151 (match_operand:SI 3 "const48_operand" "I") 3152 (const_int 0)) 3153 (match_operand:SI 4 "sext_add_operand" "rIO")))) 3154 (clobber (match_scratch:DI 5 "=r"))] 3155 "" 3156 "#" 3157 "" 3158 [(set (match_dup 5) 3159 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3160 (set (match_dup 0) 3161 (sign_extend:DI (plus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3162 (match_dup 4))))] 3163 { 3164 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3165 if (can_create_pseudo_p ()) 3166 operands[5] = gen_reg_rtx (DImode); 3167 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3168 operands[5] = operands[0]; 3169 3170 operands[6] = gen_lowpart (SImode, operands[5]); 3171 }) 3172 3173 (define_insn_and_split "*cmp_ssub_di" 3174 [(set (match_operand:DI 0 "register_operand" "=r") 3175 (minus:DI (if_then_else:DI 3176 (match_operator 1 "alpha_zero_comparison_operator" 3177 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3178 (const_int 0)]) 3179 (match_operand:DI 3 "const48_operand" "I") 3180 (const_int 0)) 3181 (match_operand:DI 4 "reg_or_8bit_operand" "rI"))) 3182 (clobber (match_scratch:DI 5 "=r"))] 3183 "" 3184 "#" 3185 "" 3186 [(set (match_dup 5) 3187 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3188 (set (match_dup 0) 3189 (minus:DI (ashift:DI (match_dup 5) (match_dup 3)) 3190 (match_dup 4)))] 3191 { 3192 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3193 if (can_create_pseudo_p ()) 3194 operands[5] = gen_reg_rtx (DImode); 3195 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3196 operands[5] = operands[0]; 3197 }) 3198 3199 (define_insn_and_split "*cmp_ssub_si" 3200 [(set (match_operand:SI 0 "register_operand" "=r") 3201 (minus:SI (if_then_else:SI 3202 (match_operator 1 "alpha_zero_comparison_operator" 3203 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3204 (const_int 0)]) 3205 (match_operand:SI 3 "const48_operand" "I") 3206 (const_int 0)) 3207 (match_operand:SI 4 "reg_or_8bit_operand" "rI"))) 3208 (clobber (match_scratch:DI 5 "=r"))] 3209 "" 3210 "#" 3211 "" 3212 [(set (match_dup 5) 3213 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3214 (set (match_dup 0) 3215 (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3216 (match_dup 4)))] 3217 { 3218 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3219 if (can_create_pseudo_p ()) 3220 operands[5] = gen_reg_rtx (DImode); 3221 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3222 operands[5] = gen_lowpart (DImode, operands[0]); 3223 3224 operands[6] = gen_lowpart (SImode, operands[5]); 3225 }) 3226 3227 (define_insn_and_split "*cmp_ssub_sidi" 3228 [(set (match_operand:DI 0 "register_operand" "=r") 3229 (sign_extend:DI 3230 (minus:SI (if_then_else:SI 3231 (match_operator 1 "alpha_zero_comparison_operator" 3232 [(match_operand:DI 2 "reg_or_0_operand" "rJ") 3233 (const_int 0)]) 3234 (match_operand:SI 3 "const48_operand" "I") 3235 (const_int 0)) 3236 (match_operand:SI 4 "reg_or_8bit_operand" "rI")))) 3237 (clobber (match_scratch:DI 5 "=r"))] 3238 "" 3239 "#" 3240 "" 3241 [(set (match_dup 5) 3242 (match_op_dup:DI 1 [(match_dup 2) (const_int 0)])) 3243 (set (match_dup 0) 3244 (sign_extend:DI (minus:SI (ashift:SI (match_dup 6) (match_dup 3)) 3245 (match_dup 4))))] 3246 { 3247 operands[3] = GEN_INT (exact_log2 (INTVAL (operands [3]))); 3248 if (can_create_pseudo_p ()) 3249 operands[5] = gen_reg_rtx (DImode); 3250 else if (reg_overlap_mentioned_p (operands[5], operands[4])) 3251 operands[5] = operands[0]; 3252 3253 operands[6] = gen_lowpart (SImode, operands[5]); 3254 }) 3255 3257 ;; Here are the CALL and unconditional branch insns. Calls on NT and OSF 3258 ;; work differently, so we have different patterns for each. 3259 3260 (define_expand "call" 3261 [(use (match_operand:DI 0)) 3262 (use (match_operand 1)) 3263 (use (match_operand 2)) 3264 (use (match_operand 3))] 3265 "" 3266 { 3267 if (TARGET_ABI_OPEN_VMS) 3268 emit_call_insn (gen_call_vms (operands[0], operands[2])); 3269 else 3270 emit_call_insn (gen_call_osf (operands[0], operands[1])); 3271 DONE; 3272 }) 3273 3274 (define_expand "sibcall" 3275 [(parallel [(call (mem:DI (match_operand 0)) 3276 (match_operand 1)) 3277 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3278 "TARGET_ABI_OSF" 3279 { 3280 gcc_assert (MEM_P (operands[0])); 3281 operands[0] = XEXP (operands[0], 0); 3282 }) 3283 3284 (define_expand "call_osf" 3285 [(parallel [(call (mem:DI (match_operand 0)) 3286 (match_operand 1)) 3287 (use (reg:DI 29)) 3288 (clobber (reg:DI 26))])] 3289 "" 3290 { 3291 gcc_assert (MEM_P (operands[0])); 3292 3293 operands[0] = XEXP (operands[0], 0); 3294 if (! call_operand (operands[0], Pmode)) 3295 operands[0] = copy_to_mode_reg (Pmode, operands[0]); 3296 }) 3297 3298 ;; 3299 ;; call openvms/alpha 3300 ;; op 0: symbol ref for called function 3301 ;; op 1: next_arg_reg (argument information value for R25) 3302 ;; 3303 (define_expand "call_vms" 3304 [(parallel [(call (mem:DI (match_operand 0)) 3305 (match_operand 1)) 3306 (use (match_dup 2)) 3307 (use (reg:DI 25)) 3308 (use (reg:DI 26)) 3309 (clobber (reg:DI 27))])] 3310 "" 3311 { 3312 gcc_assert (MEM_P (operands[0])); 3313 3314 operands[0] = XEXP (operands[0], 0); 3315 3316 /* Always load AI with argument information, then handle symbolic and 3317 indirect call differently. Load RA and set operands[2] to PV in 3318 both cases. */ 3319 3320 emit_move_insn (gen_rtx_REG (DImode, 25), operands[1]); 3321 if (GET_CODE (operands[0]) == SYMBOL_REF) 3322 { 3323 operands[2] = const0_rtx; 3324 } 3325 else 3326 { 3327 emit_move_insn (gen_rtx_REG (Pmode, 26), 3328 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3329 operands[0], 8))); 3330 operands[2] = operands[0]; 3331 } 3332 }) 3333 3334 (define_expand "call_value" 3335 [(use (match_operand 0)) 3336 (use (match_operand:DI 1)) 3337 (use (match_operand 2)) 3338 (use (match_operand 3)) 3339 (use (match_operand 4))] 3340 "" 3341 { 3342 if (TARGET_ABI_OPEN_VMS) 3343 emit_call_insn (gen_call_value_vms (operands[0], operands[1], 3344 operands[3])); 3345 else 3346 emit_call_insn (gen_call_value_osf (operands[0], operands[1], 3347 operands[2])); 3348 DONE; 3349 }) 3350 3351 (define_expand "sibcall_value" 3352 [(parallel [(set (match_operand 0) 3353 (call (mem:DI (match_operand 1)) 3354 (match_operand 2))) 3355 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)])] 3356 "TARGET_ABI_OSF" 3357 { 3358 gcc_assert (MEM_P (operands[1])); 3359 operands[1] = XEXP (operands[1], 0); 3360 }) 3361 3362 (define_expand "call_value_osf" 3363 [(parallel [(set (match_operand 0) 3364 (call (mem:DI (match_operand 1)) 3365 (match_operand 2))) 3366 (use (reg:DI 29)) 3367 (clobber (reg:DI 26))])] 3368 "" 3369 { 3370 gcc_assert (MEM_P (operands[1])); 3371 3372 operands[1] = XEXP (operands[1], 0); 3373 if (! call_operand (operands[1], Pmode)) 3374 operands[1] = copy_to_mode_reg (Pmode, operands[1]); 3375 }) 3376 3377 (define_expand "call_value_vms" 3378 [(parallel [(set (match_operand 0) 3379 (call (mem:DI (match_operand:DI 1)) 3380 (match_operand 2))) 3381 (use (match_dup 3)) 3382 (use (reg:DI 25)) 3383 (use (reg:DI 26)) 3384 (clobber (reg:DI 27))])] 3385 "" 3386 { 3387 gcc_assert (MEM_P (operands[1])); 3388 3389 operands[1] = XEXP (operands[1], 0); 3390 3391 /* Always load AI with argument information, then handle symbolic and 3392 indirect call differently. Load RA and set operands[3] to PV in 3393 both cases. */ 3394 3395 emit_move_insn (gen_rtx_REG (DImode, 25), operands[2]); 3396 if (GET_CODE (operands[1]) == SYMBOL_REF) 3397 { 3398 operands[3] = const0_rtx; 3399 } 3400 else 3401 { 3402 emit_move_insn (gen_rtx_REG (Pmode, 26), 3403 gen_rtx_MEM (Pmode, plus_constant (Pmode, 3404 operands[1], 8))); 3405 operands[3] = operands[1]; 3406 } 3407 }) 3408 3409 (define_insn "*call_osf_1_er_noreturn" 3410 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3411 (match_operand 1)) 3412 (use (reg:DI 29)) 3413 (clobber (reg:DI 26))] 3414 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3415 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3416 "@ 3417 jsr $26,($27),0 3418 bsr $26,%0\t\t!samegp 3419 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#" 3420 [(set_attr "type" "jsr") 3421 (set_attr "length" "*,*,8")]) 3422 3423 (define_insn "*call_osf_1_er" 3424 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3425 (match_operand 1)) 3426 (use (reg:DI 29)) 3427 (clobber (reg:DI 26))] 3428 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3429 "@ 3430 jsr $26,(%0),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 3431 bsr $26,%0\t\t!samegp 3432 ldq $27,%0($29)\t\t!literal!%#\;jsr $26,($27),%0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 3433 [(set_attr "type" "jsr") 3434 (set_attr "length" "12,*,16")]) 3435 3436 ;; We must use peep2 instead of a split because we need accurate life 3437 ;; information for $gp. Consider the case of { bar(); while (1); }. 3438 (define_peephole2 3439 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3440 (match_operand 1)) 3441 (use (reg:DI 29)) 3442 (clobber (reg:DI 26))])] 3443 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3444 && ! samegp_function_operand (operands[0], Pmode) 3445 && (peep2_regno_dead_p (1, 29) 3446 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3447 [(parallel [(call (mem:DI (match_dup 2)) 3448 (match_dup 1)) 3449 (use (reg:DI 29)) 3450 (use (match_dup 0)) 3451 (use (match_dup 3)) 3452 (clobber (reg:DI 26))])] 3453 { 3454 if (CONSTANT_P (operands[0])) 3455 { 3456 operands[2] = gen_rtx_REG (Pmode, 27); 3457 operands[3] = GEN_INT (alpha_next_sequence_number++); 3458 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3459 operands[0], operands[3])); 3460 } 3461 else 3462 { 3463 operands[2] = operands[0]; 3464 operands[0] = const0_rtx; 3465 operands[3] = const0_rtx; 3466 } 3467 }) 3468 3469 (define_peephole2 3470 [(parallel [(call (mem:DI (match_operand:DI 0 "call_operand")) 3471 (match_operand 1)) 3472 (use (reg:DI 29)) 3473 (clobber (reg:DI 26))])] 3474 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 3475 && ! samegp_function_operand (operands[0], Pmode) 3476 && ! (peep2_regno_dead_p (1, 29) 3477 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 3478 [(parallel [(call (mem:DI (match_dup 2)) 3479 (match_dup 1)) 3480 (set (match_dup 5) 3481 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP1)) 3482 (use (match_dup 0)) 3483 (use (match_dup 4)) 3484 (clobber (reg:DI 26))]) 3485 (set (match_dup 5) 3486 (unspec:DI [(match_dup 5) (match_dup 3)] UNSPEC_LDGP2))] 3487 { 3488 if (CONSTANT_P (operands[0])) 3489 { 3490 operands[2] = gen_rtx_REG (Pmode, 27); 3491 operands[4] = GEN_INT (alpha_next_sequence_number++); 3492 emit_insn (gen_movdi_er_high_g (operands[2], pic_offset_table_rtx, 3493 operands[0], operands[4])); 3494 } 3495 else 3496 { 3497 operands[2] = operands[0]; 3498 operands[0] = const0_rtx; 3499 operands[4] = const0_rtx; 3500 } 3501 operands[3] = GEN_INT (alpha_next_sequence_number++); 3502 operands[5] = pic_offset_table_rtx; 3503 }) 3504 3505 (define_insn "*call_osf_2_er_nogp" 3506 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3507 (match_operand 1)) 3508 (use (reg:DI 29)) 3509 (use (match_operand 2)) 3510 (use (match_operand 3 "const_int_operand")) 3511 (clobber (reg:DI 26))] 3512 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3513 "jsr $26,(%0),%2%J3" 3514 [(set_attr "type" "jsr")]) 3515 3516 (define_insn "*call_osf_2_er" 3517 [(call (mem:DI (match_operand:DI 0 "register_operand" "c")) 3518 (match_operand 1)) 3519 (set (reg:DI 29) 3520 (unspec:DI [(reg:DI 29) (match_operand 4 "const_int_operand")] 3521 UNSPEC_LDGP1)) 3522 (use (match_operand 2)) 3523 (use (match_operand 3 "const_int_operand")) 3524 (clobber (reg:DI 26))] 3525 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3526 "jsr $26,(%0),%2%J3\;ldah $29,0($26)\t\t!gpdisp!%4" 3527 [(set_attr "type" "jsr") 3528 (set_attr "cannot_copy" "true") 3529 (set_attr "length" "8")]) 3530 3531 (define_insn "*call_osf_1_noreturn" 3532 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3533 (match_operand 1)) 3534 (use (reg:DI 29)) 3535 (clobber (reg:DI 26))] 3536 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 3537 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 3538 "@ 3539 jsr $26,($27),0 3540 bsr $26,$%0..ng 3541 jsr $26,%0" 3542 [(set_attr "type" "jsr") 3543 (set_attr "length" "*,*,8")]) 3544 3545 (define_insn "*call_osf_1" 3546 [(call (mem:DI (match_operand:DI 0 "call_operand" "c,R,s")) 3547 (match_operand 1)) 3548 (use (reg:DI 29)) 3549 (clobber (reg:DI 26))] 3550 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3551 "@ 3552 jsr $26,($27),0\;ldgp $29,0($26) 3553 bsr $26,$%0..ng 3554 jsr $26,%0\;ldgp $29,0($26)" 3555 [(set_attr "type" "jsr") 3556 (set_attr "length" "12,*,16")]) 3557 3558 (define_insn "*sibcall_osf_1_er" 3559 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3560 (match_operand 1)) 3561 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3562 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3563 "@ 3564 br $31,%0\t\t!samegp 3565 ldq $27,%0($29)\t\t!literal!%#\;jmp $31,($27),%0\t\t!lituse_jsr!%#" 3566 [(set_attr "type" "jsr") 3567 (set_attr "length" "*,8")]) 3568 3569 ;; Note that the DEC assembler expands "jmp foo" with $at, which 3570 ;; doesn't do what we want. 3571 (define_insn "*sibcall_osf_1" 3572 [(call (mem:DI (match_operand:DI 0 "symbolic_operand" "R,s")) 3573 (match_operand 1)) 3574 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 3575 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 3576 "@ 3577 br $31,$%0..ng 3578 lda $27,%0\;jmp $31,($27),%0" 3579 [(set_attr "type" "jsr") 3580 (set_attr "length" "*,8")]) 3581 3582 ; GAS relies on the order and position of instructions output below in order 3583 ; to generate relocs for VMS link to potentially optimize the call. 3584 ; Please do not molest. 3585 (define_insn "*call_vms_1" 3586 [(call (mem:DI (match_operand:DI 0 "call_operand" "r,s")) 3587 (match_operand 1)) 3588 (use (match_operand:DI 2 "nonmemory_operand" "r,n")) 3589 (use (reg:DI 25)) 3590 (use (reg:DI 26)) 3591 (clobber (reg:DI 27))] 3592 "TARGET_ABI_OPEN_VMS" 3593 { 3594 switch (which_alternative) 3595 { 3596 case 0: 3597 return "mov %2,$27\;jsr $26,0\;ldq $27,0($29)"; 3598 case 1: 3599 operands [2] = alpha_use_linkage (operands [0], true, false); 3600 operands [3] = alpha_use_linkage (operands [0], false, false); 3601 return "ldq $26,%3\;ldq $27,%2\;jsr $26,%0\;ldq $27,0($29)"; 3602 default: 3603 gcc_unreachable (); 3604 } 3605 } 3606 [(set_attr "type" "jsr") 3607 (set_attr "length" "12,16")]) 3608 3609 ;; Call subroutine returning any type. 3610 3611 (define_expand "untyped_call" 3612 [(parallel [(call (match_operand 0) 3613 (const_int 0)) 3614 (match_operand 1) 3615 (match_operand 2)])] 3616 "" 3617 { 3618 int i; 3619 3620 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 3621 3622 for (i = 0; i < XVECLEN (operands[2], 0); i++) 3623 { 3624 rtx set = XVECEXP (operands[2], 0, i); 3625 emit_move_insn (SET_DEST (set), SET_SRC (set)); 3626 } 3627 3628 /* The optimizer does not know that the call sets the function value 3629 registers we stored in the result block. We avoid problems by 3630 claiming that all hard registers are used and clobbered at this 3631 point. */ 3632 emit_insn (gen_blockage ()); 3633 3634 DONE; 3635 }) 3636 3637 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 3638 ;; all of memory. This blocks insns from being moved across this point. 3639 3640 (define_insn "blockage" 3641 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 3642 "" 3643 "" 3644 [(set_attr "length" "0") 3645 (set_attr "type" "none")]) 3646 3647 (define_insn "jump" 3648 [(set (pc) 3649 (label_ref (match_operand 0)))] 3650 "" 3651 "br $31,%l0" 3652 [(set_attr "type" "ibr")]) 3653 3654 (define_expand "return" 3655 [(return)] 3656 "direct_return ()") 3657 3658 (define_insn "*return_internal" 3659 [(return)] 3660 "reload_completed" 3661 "ret $31,($26),1" 3662 [(set_attr "type" "ibr")]) 3663 3664 (define_insn "indirect_jump" 3665 [(set (pc) (match_operand:DI 0 "register_operand" "r"))] 3666 "" 3667 "jmp $31,(%0),0" 3668 [(set_attr "type" "ibr")]) 3669 3670 (define_expand "tablejump" 3671 [(parallel [(set (pc) 3672 (match_operand 0 "register_operand")) 3673 (use (label_ref:DI (match_operand 1)))])] 3674 "" 3675 { 3676 if (TARGET_ABI_OSF) 3677 { 3678 rtx dest = gen_reg_rtx (DImode); 3679 emit_insn (gen_extendsidi2 (dest, operands[0])); 3680 emit_insn (gen_adddi3 (dest, pic_offset_table_rtx, dest)); 3681 operands[0] = dest; 3682 } 3683 }) 3684 3685 (define_insn "*tablejump_internal" 3686 [(set (pc) 3687 (match_operand:DI 0 "register_operand" "r")) 3688 (use (label_ref (match_operand 1)))] 3689 "" 3690 "jmp $31,(%0),0" 3691 [(set_attr "type" "ibr")]) 3692 3693 ;; Cache flush. Used by alpha_trampoline_init. 0x86 is PAL_imb, but we don't 3694 ;; want to have to include pal.h in our .s file. 3695 (define_insn "imb" 3696 [(unspec_volatile [(const_int 0)] UNSPECV_IMB)] 3697 "" 3698 "call_pal 0x86" 3699 [(set_attr "type" "callpal")]) 3700 3701 (define_expand "clear_cache" 3702 [(match_operand:DI 0) ; region start 3703 (match_operand:DI 1)] ; region end 3704 "" 3705 { 3706 emit_insn (gen_imb ()); 3707 DONE; 3708 }) 3709 3710 ;; BUGCHK is documented common to OSF/1 and VMS PALcode. 3711 (define_insn "trap" 3712 [(trap_if (const_int 1) (const_int 0)) 3713 (use (reg:DI 29))] 3714 "" 3715 "call_pal 0x81" 3716 [(set_attr "type" "callpal")]) 3717 3718 ;; For userland, we load the thread pointer from the TCB. 3719 ;; For the kernel, we load the per-cpu private value. 3720 3721 (define_insn "get_thread_pointerdi" 3722 [(set (match_operand:DI 0 "register_operand" "=v") 3723 (unspec:DI [(const_int 0)] UNSPEC_TP))] 3724 "TARGET_ABI_OSF" 3725 { 3726 if (TARGET_TLS_KERNEL) 3727 return "call_pal 0x32"; 3728 else 3729 return "call_pal 0x9e"; 3730 } 3731 [(set_attr "type" "callpal")]) 3732 3733 ;; For completeness, and possibly a __builtin function, here's how to 3734 ;; set the thread pointer. Since we don't describe enough of this 3735 ;; quantity for CSE, we have to use a volatile unspec, and then there's 3736 ;; not much point in creating an R16_REG register class. 3737 3738 (define_expand "set_thread_pointerdi" 3739 [(set (reg:DI 16) (match_operand:DI 0 "input_operand")) 3740 (unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3741 "TARGET_ABI_OSF") 3742 3743 (define_insn "*set_tp" 3744 [(unspec_volatile [(reg:DI 16)] UNSPECV_SET_TP)] 3745 "TARGET_ABI_OSF" 3746 { 3747 if (TARGET_TLS_KERNEL) 3748 return "call_pal 0x31"; 3749 else 3750 return "call_pal 0x9f"; 3751 } 3752 [(set_attr "type" "callpal")]) 3753 3754 ;; Special builtins for establishing and reverting VMS condition handlers. 3755 3756 (define_expand "builtin_establish_vms_condition_handler" 3757 [(set (reg:DI 0) (match_operand:DI 0 "register_operand")) 3758 (use (match_operand:DI 1 "address_operand"))] 3759 "TARGET_ABI_OPEN_VMS" 3760 { 3761 alpha_expand_builtin_establish_vms_condition_handler (operands[0], 3762 operands[1]); 3763 }) 3764 3765 (define_expand "builtin_revert_vms_condition_handler" 3766 [(set (reg:DI 0) (match_operand:DI 0 "register_operand"))] 3767 "TARGET_ABI_OPEN_VMS" 3768 "alpha_expand_builtin_revert_vms_condition_handler (operands[0]);") 3769 3771 ;; Finally, we have the basic data motion insns. The byte and word insns 3772 ;; are done via define_expand. Start with the floating-point insns, since 3773 ;; they are simpler. 3774 3775 (define_expand "movsf" 3776 [(set (match_operand:SF 0 "nonimmediate_operand") 3777 (match_operand:SF 1 "general_operand"))] 3778 "" 3779 { 3780 if (MEM_P (operands[0]) 3781 && ! reg_or_0_operand (operands[1], SFmode)) 3782 operands[1] = force_reg (SFmode, operands[1]); 3783 }) 3784 3785 (define_insn "*movsf" 3786 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3787 (match_operand:SF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3788 "register_operand (operands[0], SFmode) 3789 || reg_or_0_operand (operands[1], SFmode)" 3790 "@ 3791 cpys %R1,%R1,%0 3792 ld%, %0,%1 3793 bis $31,%r1,%0 3794 ldl %0,%1 3795 st%, %R1,%0 3796 stl %r1,%0 3797 itofs %1,%0 3798 ftois %1,%0" 3799 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3800 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3801 3802 (define_expand "movdf" 3803 [(set (match_operand:DF 0 "nonimmediate_operand") 3804 (match_operand:DF 1 "general_operand"))] 3805 "" 3806 { 3807 if (MEM_P (operands[0]) 3808 && ! reg_or_0_operand (operands[1], DFmode)) 3809 operands[1] = force_reg (DFmode, operands[1]); 3810 }) 3811 3812 (define_insn "*movdf" 3813 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,*r,*r,m,m,f,*r") 3814 (match_operand:DF 1 "input_operand" "fG,m,*rG,m,fG,*r,*r,f"))] 3815 "register_operand (operands[0], DFmode) 3816 || reg_or_0_operand (operands[1], DFmode)" 3817 "@ 3818 cpys %R1,%R1,%0 3819 ld%- %0,%1 3820 bis $31,%r1,%0 3821 ldq %0,%1 3822 st%- %R1,%0 3823 stq %r1,%0 3824 itoft %1,%0 3825 ftoit %1,%0" 3826 [(set_attr "type" "fcpys,fld,ilog,ild,fst,ist,itof,ftoi") 3827 (set_attr "isa" "*,*,*,*,*,*,fix,fix")]) 3828 3829 ;; Subregs suck for register allocation. Pretend we can move TFmode 3830 ;; data between general registers until after reload. 3831 ;; ??? Is this still true now that we have the lower-subreg pass? 3832 3833 (define_expand "movtf" 3834 [(set (match_operand:TF 0 "nonimmediate_operand") 3835 (match_operand:TF 1 "general_operand"))] 3836 "" 3837 { 3838 if (MEM_P (operands[0]) 3839 && ! reg_or_0_operand (operands[1], TFmode)) 3840 operands[1] = force_reg (TFmode, operands[1]); 3841 }) 3842 3843 (define_insn_and_split "*movtf_internal" 3844 [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o") 3845 (match_operand:TF 1 "input_operand" "roG,rG"))] 3846 "register_operand (operands[0], TFmode) 3847 || reg_or_0_operand (operands[1], TFmode)" 3848 "#" 3849 "reload_completed" 3850 [(set (match_dup 0) (match_dup 2)) 3851 (set (match_dup 1) (match_dup 3))] 3852 "alpha_split_tmode_pair (operands, TFmode, true);") 3853 3854 ;; We do two major things here: handle mem->mem and construct long 3855 ;; constants. 3856 3857 (define_expand "movsi" 3858 [(set (match_operand:SI 0 "nonimmediate_operand") 3859 (match_operand:SI 1 "general_operand"))] 3860 "" 3861 { 3862 if (alpha_expand_mov (SImode, operands)) 3863 DONE; 3864 }) 3865 3866 (define_insn "*movsi" 3867 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,r,r,m,r") 3868 (match_operand:SI 1 "input_operand" "rJ,K,L,n,m,rJ,s"))] 3869 "register_operand (operands[0], SImode) 3870 || reg_or_0_operand (operands[1], SImode)" 3871 "@ 3872 bis $31,%r1,%0 3873 lda %0,%1($31) 3874 ldah %0,%h1($31) 3875 # 3876 ldl %0,%1 3877 stl %r1,%0 3878 lda %0,%1" 3879 [(set_attr "type" "ilog,iadd,iadd,multi,ild,ist,ldsym") 3880 (set_attr "isa" "*,*,*,*,*,*,vms")]) 3881 3882 ;; Split a load of a large constant into the appropriate two-insn 3883 ;; sequence. 3884 3885 (define_split 3886 [(set (match_operand:SI 0 "register_operand") 3887 (match_operand:SI 1 "non_add_const_operand"))] 3888 "" 3889 [(const_int 0)] 3890 { 3891 if (alpha_split_const_mov (SImode, operands)) 3892 DONE; 3893 else 3894 FAIL; 3895 }) 3896 3897 (define_insn "*movdi_er_low_l" 3898 [(set (match_operand:DI 0 "register_operand" "=r") 3899 (lo_sum:DI (match_operand:DI 1 "register_operand" "r") 3900 (match_operand:DI 2 "local_symbolic_operand")))] 3901 "TARGET_EXPLICIT_RELOCS" 3902 { 3903 if (true_regnum (operands[1]) == 29) 3904 return "lda %0,%2(%1)\t\t!gprel"; 3905 else 3906 return "lda %0,%2(%1)\t\t!gprellow"; 3907 } 3908 [(set_attr "usegp" "yes")]) 3909 3910 (define_split 3911 [(set (match_operand:DI 0 "register_operand") 3912 (match_operand:DI 1 "small_symbolic_operand"))] 3913 "TARGET_EXPLICIT_RELOCS && reload_completed" 3914 [(set (match_dup 0) 3915 (lo_sum:DI (match_dup 2) (match_dup 1)))] 3916 "operands[2] = pic_offset_table_rtx;") 3917 3918 (define_split 3919 [(set (match_operand:DI 0 "register_operand") 3920 (match_operand:DI 1 "local_symbolic_operand"))] 3921 "TARGET_EXPLICIT_RELOCS && reload_completed" 3922 [(set (match_dup 0) 3923 (plus:DI (match_dup 2) (high:DI (match_dup 1)))) 3924 (set (match_dup 0) 3925 (lo_sum:DI (match_dup 0) (match_dup 1)))] 3926 "operands[2] = pic_offset_table_rtx;") 3927 3928 (define_split 3929 [(match_operand 0 "some_small_symbolic_operand")] 3930 "" 3931 [(match_dup 0)] 3932 "operands[0] = split_small_symbolic_operand (operands[0]);") 3933 3934 ;; Accepts any symbolic, not just global, since function calls that 3935 ;; don't go via bsr still use !literal in hopes of linker relaxation. 3936 (define_insn "movdi_er_high_g" 3937 [(set (match_operand:DI 0 "register_operand" "=r") 3938 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3939 (match_operand:DI 2 "symbolic_operand") 3940 (match_operand 3 "const_int_operand")] 3941 UNSPEC_LITERAL))] 3942 "TARGET_EXPLICIT_RELOCS" 3943 { 3944 if (INTVAL (operands[3]) == 0) 3945 return "ldq %0,%2(%1)\t\t!literal"; 3946 else 3947 return "ldq %0,%2(%1)\t\t!literal!%3"; 3948 } 3949 [(set_attr "type" "ldsym")]) 3950 3951 (define_split 3952 [(set (match_operand:DI 0 "register_operand") 3953 (match_operand:DI 1 "global_symbolic_operand"))] 3954 "TARGET_EXPLICIT_RELOCS && reload_completed" 3955 [(set (match_dup 0) 3956 (unspec:DI [(match_dup 2) 3957 (match_dup 1) 3958 (const_int 0)] UNSPEC_LITERAL))] 3959 "operands[2] = pic_offset_table_rtx;") 3960 3961 (define_insn "movdi_er_tlsgd" 3962 [(set (match_operand:DI 0 "register_operand" "=r") 3963 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3964 (match_operand:DI 2 "symbolic_operand") 3965 (match_operand 3 "const_int_operand")] 3966 UNSPEC_TLSGD))] 3967 "HAVE_AS_TLS" 3968 { 3969 if (INTVAL (operands[3]) == 0) 3970 return "lda %0,%2(%1)\t\t!tlsgd"; 3971 else 3972 return "lda %0,%2(%1)\t\t!tlsgd!%3"; 3973 }) 3974 3975 (define_insn "movdi_er_tlsldm" 3976 [(set (match_operand:DI 0 "register_operand" "=r") 3977 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3978 (match_operand 2 "const_int_operand")] 3979 UNSPEC_TLSLDM))] 3980 "HAVE_AS_TLS" 3981 { 3982 if (INTVAL (operands[2]) == 0) 3983 return "lda %0,%&(%1)\t\t!tlsldm"; 3984 else 3985 return "lda %0,%&(%1)\t\t!tlsldm!%2"; 3986 }) 3987 3988 (define_insn "*movdi_er_gotdtp" 3989 [(set (match_operand:DI 0 "register_operand" "=r") 3990 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 3991 (match_operand:DI 2 "symbolic_operand")] 3992 UNSPEC_DTPREL))] 3993 "HAVE_AS_TLS" 3994 "ldq %0,%2(%1)\t\t!gotdtprel" 3995 [(set_attr "type" "ild") 3996 (set_attr "usegp" "yes")]) 3997 3998 (define_split 3999 [(set (match_operand:DI 0 "register_operand") 4000 (match_operand:DI 1 "gotdtp_symbolic_operand"))] 4001 "HAVE_AS_TLS && reload_completed" 4002 [(set (match_dup 0) 4003 (unspec:DI [(match_dup 2) 4004 (match_dup 1)] UNSPEC_DTPREL))] 4005 { 4006 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4007 operands[2] = pic_offset_table_rtx; 4008 }) 4009 4010 (define_insn "*movdi_er_gottp" 4011 [(set (match_operand:DI 0 "register_operand" "=r") 4012 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4013 (match_operand:DI 2 "symbolic_operand")] 4014 UNSPEC_TPREL))] 4015 "HAVE_AS_TLS" 4016 "ldq %0,%2(%1)\t\t!gottprel" 4017 [(set_attr "type" "ild") 4018 (set_attr "usegp" "yes")]) 4019 4020 (define_split 4021 [(set (match_operand:DI 0 "register_operand") 4022 (match_operand:DI 1 "gottp_symbolic_operand"))] 4023 "HAVE_AS_TLS && reload_completed" 4024 [(set (match_dup 0) 4025 (unspec:DI [(match_dup 2) 4026 (match_dup 1)] UNSPEC_TPREL))] 4027 { 4028 operands[1] = XVECEXP (XEXP (operands[1], 0), 0, 0); 4029 operands[2] = pic_offset_table_rtx; 4030 }) 4031 4032 (define_insn "*movdi" 4033 [(set (match_operand:DI 0 "nonimmediate_operand" 4034 "=r,r,r,r,r,r,r,r, m, *f,*f, Q, r,*f") 4035 (match_operand:DI 1 "input_operand" 4036 "rJ,K,L,T,s,n,s,m,rJ,*fJ, Q,*f,*f, r"))] 4037 "register_operand (operands[0], DImode) 4038 || reg_or_0_operand (operands[1], DImode)" 4039 "@ 4040 mov %r1,%0 4041 lda %0,%1($31) 4042 ldah %0,%h1($31) 4043 # 4044 # 4045 # 4046 lda %0,%1 4047 ldq%A1 %0,%1 4048 stq%A0 %r1,%0 4049 fmov %R1,%0 4050 ldt %0,%1 4051 stt %R1,%0 4052 ftoit %1,%0 4053 itoft %1,%0" 4054 [(set_attr "type" "ilog,iadd,iadd,iadd,ldsym,multi,ldsym,ild,ist,fcpys,fld,fst,ftoi,itof") 4055 (set_attr "isa" "*,*,*,er,er,*,ner,*,*,*,*,*,fix,fix") 4056 (set_attr "usegp" "*,*,*,yes,*,*,*,*,*,*,*,*,*,*")]) 4057 4058 ;; VMS needs to set up "vms_base_regno" for unwinding. This move 4059 ;; often appears dead to the life analysis code, at which point we 4060 ;; die for emitting dead prologue instructions. Force this live. 4061 4062 (define_insn "force_movdi" 4063 [(set (match_operand:DI 0 "register_operand" "=r") 4064 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r")] 4065 UNSPECV_FORCE_MOV))] 4066 "" 4067 "mov %1,%0" 4068 [(set_attr "type" "ilog")]) 4069 4070 ;; We do three major things here: handle mem->mem, put 64-bit constants in 4071 ;; memory, and construct long 32-bit constants. 4072 4073 (define_expand "movdi" 4074 [(set (match_operand:DI 0 "nonimmediate_operand") 4075 (match_operand:DI 1 "general_operand"))] 4076 "" 4077 { 4078 if (alpha_expand_mov (DImode, operands)) 4079 DONE; 4080 }) 4081 4082 ;; Split a load of a large constant into the appropriate two-insn 4083 ;; sequence. 4084 4085 (define_split 4086 [(set (match_operand:DI 0 "register_operand") 4087 (match_operand:DI 1 "non_add_const_operand"))] 4088 "" 4089 [(const_int 0)] 4090 { 4091 if (alpha_split_const_mov (DImode, operands)) 4092 DONE; 4093 else 4094 FAIL; 4095 }) 4096 4097 ;; We need to prevent reload from splitting TImode moves, because it 4098 ;; might decide to overwrite a pointer with the value it points to. 4099 ;; In that case we have to do the loads in the appropriate order so 4100 ;; that the pointer is not destroyed too early. 4101 4102 (define_insn_and_split "*movti_internal" 4103 [(set (match_operand:TI 0 "nonimmediate_operand" "=r,o") 4104 (match_operand:TI 1 "input_operand" "roJ,rJ"))] 4105 "(register_operand (operands[0], TImode) 4106 /* Prevent rematerialization of constants. */ 4107 && ! CONSTANT_P (operands[1])) 4108 || reg_or_0_operand (operands[1], TImode)" 4109 "#" 4110 "reload_completed" 4111 [(set (match_dup 0) (match_dup 2)) 4112 (set (match_dup 1) (match_dup 3))] 4113 "alpha_split_tmode_pair (operands, TImode, true);") 4114 4115 (define_expand "movti" 4116 [(set (match_operand:TI 0 "nonimmediate_operand") 4117 (match_operand:TI 1 "general_operand"))] 4118 "" 4119 { 4120 if (MEM_P (operands[0]) 4121 && ! reg_or_0_operand (operands[1], TImode)) 4122 operands[1] = force_reg (TImode, operands[1]); 4123 4124 if (operands[1] == const0_rtx) 4125 ; 4126 /* We must put 64-bit constants in memory. We could keep the 4127 32-bit constants in TImode and rely on the splitter, but 4128 this doesn't seem to be worth the pain. */ 4129 else if (CONST_SCALAR_INT_P (operands[1])) 4130 { 4131 rtx in[2], out[2], target; 4132 4133 gcc_assert (can_create_pseudo_p ()); 4134 4135 split_double (operands[1], &in[0], &in[1]); 4136 4137 if (in[0] == const0_rtx) 4138 out[0] = const0_rtx; 4139 else 4140 { 4141 out[0] = gen_reg_rtx (DImode); 4142 emit_insn (gen_movdi (out[0], in[0])); 4143 } 4144 4145 if (in[1] == const0_rtx) 4146 out[1] = const0_rtx; 4147 else 4148 { 4149 out[1] = gen_reg_rtx (DImode); 4150 emit_insn (gen_movdi (out[1], in[1])); 4151 } 4152 4153 if (!REG_P (operands[0])) 4154 target = gen_reg_rtx (TImode); 4155 else 4156 target = operands[0]; 4157 4158 emit_insn (gen_movdi (operand_subword (target, 0, 0, TImode), out[0])); 4159 emit_insn (gen_movdi (operand_subword (target, 1, 0, TImode), out[1])); 4160 4161 if (target != operands[0]) 4162 emit_insn (gen_rtx_SET (operands[0], target)); 4163 4164 DONE; 4165 } 4166 }) 4167 4168 ;; These are the partial-word cases. 4169 ;; 4170 ;; First we have the code to load an aligned word. Operand 0 is the register 4171 ;; in which to place the result. It's mode is QImode or HImode. Operand 1 4172 ;; is an SImode MEM at the low-order byte of the proper word. Operand 2 is the 4173 ;; number of bits within the word that the value is. Operand 3 is an SImode 4174 ;; scratch register. If operand 0 is a hard register, operand 3 may be the 4175 ;; same register. It is allowed to conflict with operand 1 as well. 4176 4177 (define_expand "aligned_loadqi" 4178 [(set (match_operand:SI 3 "register_operand") 4179 (match_operand:SI 1 "memory_operand")) 4180 (set (match_operand:DI 0 "register_operand") 4181 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4182 (const_int 8) 4183 (match_operand:DI 2 "const_int_operand")))]) 4184 4185 (define_expand "aligned_loadhi" 4186 [(set (match_operand:SI 3 "register_operand") 4187 (match_operand:SI 1 "memory_operand")) 4188 (set (match_operand:DI 0 "register_operand") 4189 (zero_extract:DI (subreg:DI (match_dup 3) 0) 4190 (const_int 16) 4191 (match_operand:DI 2 "const_int_operand")))]) 4192 4193 ;; Similar for unaligned loads, where we use the sequence from the 4194 ;; Alpha Architecture manual. We have to distinguish between little-endian 4195 ;; and big-endian systems as the sequences are different. 4196 ;; 4197 ;; Operand 1 is the address. Operands 2 and 3 are temporaries, where 4198 ;; operand 3 can overlap the input and output registers. 4199 4200 (define_expand "unaligned_loadqi" 4201 [(set (match_operand:DI 2 "register_operand") 4202 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4203 (const_int -8)))) 4204 (set (match_operand:DI 3 "register_operand") 4205 (match_dup 1)) 4206 (set (match_operand:DI 0 "register_operand") 4207 (zero_extract:DI (match_dup 2) 4208 (const_int 8) 4209 (ashift:DI (match_dup 3) (const_int 3))))]) 4210 4211 (define_expand "unaligned_loadhi" 4212 [(set (match_operand:DI 2 "register_operand") 4213 (mem:DI (and:DI (match_operand:DI 1 "address_operand") 4214 (const_int -8)))) 4215 (set (match_operand:DI 3 "register_operand") 4216 (match_dup 1)) 4217 (set (match_operand:DI 0 "register_operand") 4218 (zero_extract:DI (match_dup 2) 4219 (const_int 16) 4220 (ashift:DI (match_dup 3) (const_int 3))))]) 4221 4222 ;; Storing an aligned byte or word requires two temporaries. Operand 0 is the 4223 ;; aligned SImode MEM. Operand 1 is the register containing the 4224 ;; byte or word to store. Operand 2 is the number of bits within the word that 4225 ;; the value should be placed. Operands 3 and 4 are SImode temporaries. 4226 4227 (define_expand "aligned_store" 4228 [(set (match_operand:SI 3 "register_operand") 4229 (match_operand:SI 0 "memory_operand")) 4230 (set (subreg:DI (match_dup 3) 0) 4231 (and:DI (subreg:DI (match_dup 3) 0) (match_dup 5))) 4232 (set (subreg:DI (match_operand:SI 4 "register_operand") 0) 4233 (ashift:DI (zero_extend:DI (match_operand 1 "register_operand")) 4234 (match_operand:DI 2 "const_int_operand"))) 4235 (set (subreg:DI (match_dup 4) 0) 4236 (ior:DI (subreg:DI (match_dup 4) 0) (subreg:DI (match_dup 3) 0))) 4237 (set (match_dup 0) (match_dup 4))] 4238 "" 4239 { 4240 operands[5] = GEN_INT (~ (GET_MODE_MASK (GET_MODE (operands[1])) 4241 << INTVAL (operands[2]))); 4242 }) 4243 4244 ;; For the unaligned byte and halfword cases, we use code similar to that 4245 ;; in the ;; Architecture book, but reordered to lower the number of registers 4246 ;; required. Operand 0 is the address. Operand 1 is the data to store. 4247 ;; Operands 2, 3, and 4 are DImode temporaries, where operands 2 and 4 may 4248 ;; be the same temporary, if desired. If the address is in a register, 4249 ;; operand 2 can be that register. 4250 4251 (define_expand "unaligned_store<mode>" 4252 [(set (match_operand:DI 3 "register_operand") 4253 (mem:DI (and:DI (match_operand:DI 0 "address_operand") 4254 (const_int -8)))) 4255 (set (match_operand:DI 2 "register_operand") 4256 (match_dup 0)) 4257 (set (match_dup 3) 4258 (and:DI (not:DI (ashift:DI (match_dup 5) 4259 (ashift:DI (match_dup 2) (const_int 3)))) 4260 (match_dup 3))) 4261 (set (match_operand:DI 4 "register_operand") 4262 (ashift:DI (zero_extend:DI 4263 (match_operand:I12MODE 1 "register_operand")) 4264 (ashift:DI (match_dup 2) (const_int 3)))) 4265 (set (match_dup 4) (ior:DI (match_dup 4) (match_dup 3))) 4266 (set (mem:DI (and:DI (match_dup 0) (const_int -8))) 4267 (match_dup 4))] 4268 "" 4269 "operands[5] = GEN_INT (GET_MODE_MASK (<MODE>mode));") 4270 4271 ;; Here are the define_expand's for QI and HI moves that use the above 4272 ;; patterns. We have the normal sets, plus the ones that need scratch 4273 ;; registers for reload. 4274 4275 (define_expand "mov<mode>" 4276 [(set (match_operand:I12MODE 0 "nonimmediate_operand") 4277 (match_operand:I12MODE 1 "general_operand"))] 4278 "" 4279 { 4280 if (TARGET_BWX 4281 ? alpha_expand_mov (<MODE>mode, operands) 4282 : alpha_expand_mov_nobwx (<MODE>mode, operands)) 4283 DONE; 4284 }) 4285 4286 (define_insn "*movqi" 4287 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r,m") 4288 (match_operand:QI 1 "input_operand" "rJ,n,m,rJ"))] 4289 "register_operand (operands[0], QImode) 4290 || reg_or_0_operand (operands[1], QImode)" 4291 "@ 4292 bis $31,%r1,%0 4293 lda %0,%L1($31) 4294 ldbu %0,%1 4295 stb %r1,%0" 4296 [(set_attr "type" "ilog,iadd,ild,ist") 4297 (set_attr "isa" "*,*,bwx,bwx")]) 4298 4299 (define_insn "*movhi" 4300 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m") 4301 (match_operand:HI 1 "input_operand" "rJ,n,m,rJ"))] 4302 "register_operand (operands[0], HImode) 4303 || reg_or_0_operand (operands[1], HImode)" 4304 "@ 4305 bis $31,%r1,%0 4306 lda %0,%L1($31) 4307 ldwu %0,%1 4308 stw %r1,%0" 4309 [(set_attr "type" "ilog,iadd,ild,ist") 4310 (set_attr "isa" "*,*,bwx,bwx")]) 4311 4312 ;; We need to hook into the extra support that we have for HImode 4313 ;; reloads when BWX insns are not available. 4314 (define_expand "movcqi" 4315 [(set (match_operand:CQI 0 "nonimmediate_operand") 4316 (match_operand:CQI 1 "general_operand"))] 4317 "!TARGET_BWX" 4318 { 4319 if (GET_CODE (operands[0]) == CONCAT || GET_CODE (operands[1]) == CONCAT) 4320 ; 4321 else if (!any_memory_operand (operands[0], CQImode)) 4322 { 4323 if (!any_memory_operand (operands[1], CQImode)) 4324 { 4325 emit_move_insn (gen_lowpart (HImode, operands[0]), 4326 gen_lowpart (HImode, operands[1])); 4327 DONE; 4328 } 4329 if (aligned_memory_operand (operands[1], CQImode)) 4330 { 4331 bool done; 4332 do_aligned1: 4333 operands[1] = gen_lowpart (HImode, operands[1]); 4334 do_aligned2: 4335 operands[0] = gen_lowpart (HImode, operands[0]); 4336 done = alpha_expand_mov_nobwx (HImode, operands); 4337 gcc_assert (done); 4338 DONE; 4339 } 4340 } 4341 else if (aligned_memory_operand (operands[0], CQImode)) 4342 { 4343 if (MEM_P (operands[1])) 4344 { 4345 rtx x = gen_reg_rtx (HImode); 4346 emit_move_insn (gen_lowpart (CQImode, x), operands[1]); 4347 operands[1] = x; 4348 goto do_aligned2; 4349 } 4350 goto do_aligned1; 4351 } 4352 4353 gcc_assert (!reload_in_progress); 4354 emit_move_complex_parts (operands[0], operands[1]); 4355 DONE; 4356 }) 4357 4358 ;; Here are the versions for reload. 4359 ;; 4360 ;; The aligned input case is recognized early in alpha_secondary_reload 4361 ;; in order to avoid allocating an unnecessary scratch register. 4362 ;; 4363 ;; Note that in the unaligned cases we know that the operand must not be 4364 ;; a pseudo-register because stack slots are always aligned references. 4365 4366 (define_expand "reload_in<mode>" 4367 [(parallel [(match_operand:RELOAD12 0 "register_operand" "=r") 4368 (match_operand:RELOAD12 1 "any_memory_operand" "m") 4369 (match_operand:TI 2 "register_operand" "=&r")])] 4370 "!TARGET_BWX" 4371 { 4372 rtx scratch, seq, addr; 4373 unsigned regno = REGNO (operands[2]); 4374 4375 /* It is possible that one of the registers we got for operands[2] 4376 might coincide with that of operands[0] (which is why we made 4377 it TImode). Pick the other one to use as our scratch. */ 4378 if (regno == REGNO (operands[0])) 4379 regno++; 4380 scratch = gen_rtx_REG (DImode, regno); 4381 4382 addr = get_unaligned_address (operands[1]); 4383 operands[0] = gen_rtx_REG (DImode, REGNO (operands[0])); 4384 seq = gen_unaligned_load<reloadmode> (operands[0], addr, 4385 scratch, operands[0]); 4386 alpha_set_memflags (seq, operands[1]); 4387 4388 emit_insn (seq); 4389 DONE; 4390 }) 4391 4392 (define_expand "reload_out<mode>" 4393 [(parallel [(match_operand:RELOAD12 0 "any_memory_operand" "=m") 4394 (match_operand:RELOAD12 1 "register_operand" "r") 4395 (match_operand:TI 2 "register_operand" "=&r")])] 4396 "!TARGET_BWX" 4397 { 4398 unsigned regno = REGNO (operands[2]); 4399 4400 if (<MODE>mode == CQImode) 4401 { 4402 operands[0] = gen_lowpart (HImode, operands[0]); 4403 operands[1] = gen_lowpart (HImode, operands[1]); 4404 } 4405 4406 if (aligned_memory_operand (operands[0], <MODE>mode)) 4407 { 4408 emit_insn (gen_reload_out<reloadmode>_aligned 4409 (operands[0], operands[1], 4410 gen_rtx_REG (SImode, regno), 4411 gen_rtx_REG (SImode, regno + 1))); 4412 } 4413 else 4414 { 4415 rtx addr = get_unaligned_address (operands[0]); 4416 rtx scratch1 = gen_rtx_REG (DImode, regno); 4417 rtx scratch2 = gen_rtx_REG (DImode, regno + 1); 4418 rtx scratch3 = scratch1; 4419 rtx seq; 4420 4421 if (REG_P (addr)) 4422 scratch1 = addr; 4423 4424 seq = gen_unaligned_store<reloadmode> (addr, operands[1], scratch1, 4425 scratch2, scratch3); 4426 alpha_set_memflags (seq, operands[0]); 4427 emit_insn (seq); 4428 } 4429 DONE; 4430 }) 4431 4432 ;; Helpers for the above. The way reload is structured, we can't 4433 ;; always get a proper address for a stack slot during reload_foo 4434 ;; expansion, so we must delay our address manipulations until after. 4435 4436 (define_insn_and_split "reload_in<mode>_aligned" 4437 [(set (match_operand:I12MODE 0 "register_operand" "=r") 4438 (match_operand:I12MODE 1 "memory_operand" "m"))] 4439 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4440 "#" 4441 "!TARGET_BWX && reload_completed" 4442 [(const_int 0)] 4443 { 4444 rtx aligned_mem, bitnum; 4445 get_aligned_mem (operands[1], &aligned_mem, &bitnum); 4446 emit_insn (gen_aligned_load<reloadmode> 4447 (gen_lowpart (DImode, operands[0]), aligned_mem, bitnum, 4448 gen_rtx_REG (SImode, REGNO (operands[0])))); 4449 DONE; 4450 }) 4451 4452 (define_insn_and_split "reload_out<mode>_aligned" 4453 [(set (match_operand:I12MODE 0 "memory_operand" "=m") 4454 (match_operand:I12MODE 1 "register_operand" "r")) 4455 (clobber (match_operand:SI 2 "register_operand" "=&r")) 4456 (clobber (match_operand:SI 3 "register_operand" "=&r"))] 4457 "!TARGET_BWX && (reload_in_progress || reload_completed)" 4458 "#" 4459 "!TARGET_BWX && reload_completed" 4460 [(const_int 0)] 4461 { 4462 rtx aligned_mem, bitnum; 4463 get_aligned_mem (operands[0], &aligned_mem, &bitnum); 4464 emit_insn (gen_aligned_store (aligned_mem, operands[1], bitnum, 4465 operands[2], operands[3])); 4466 DONE; 4467 }) 4468 4470 ;; Vector operations 4471 4472 (define_mode_iterator VEC [V8QI V4HI V2SI]) 4473 (define_mode_iterator VEC12 [V8QI V4HI]) 4474 4475 (define_expand "mov<mode>" 4476 [(set (match_operand:VEC 0 "nonimmediate_operand") 4477 (match_operand:VEC 1 "general_operand"))] 4478 "" 4479 { 4480 if (alpha_expand_mov (<MODE>mode, operands)) 4481 DONE; 4482 }) 4483 4484 (define_split 4485 [(set (match_operand:VEC 0 "register_operand") 4486 (match_operand:VEC 1 "non_zero_const_operand"))] 4487 "" 4488 [(const_int 0)] 4489 { 4490 if (alpha_split_const_mov (<MODE>mode, operands)) 4491 DONE; 4492 else 4493 FAIL; 4494 }) 4495 4496 4497 (define_expand "movmisalign<mode>" 4498 [(set (match_operand:VEC 0 "nonimmediate_operand") 4499 (match_operand:VEC 1 "general_operand"))] 4500 "" 4501 { 4502 alpha_expand_movmisalign (<MODE>mode, operands); 4503 DONE; 4504 }) 4505 4506 (define_insn "*mov<mode>_fix" 4507 [(set (match_operand:VEC 0 "nonimmediate_operand" "=r,r,r,m,*f,*f,m,r,*f") 4508 (match_operand:VEC 1 "input_operand" "rW,i,m,rW,*fW,m,*f,*f,r"))] 4509 "register_operand (operands[0], <MODE>mode) 4510 || reg_or_0_operand (operands[1], <MODE>mode)" 4511 "@ 4512 bis $31,%r1,%0 4513 # 4514 ldq %0,%1 4515 stq %r1,%0 4516 cpys %R1,%R1,%0 4517 ldt %0,%1 4518 stt %R1,%0 4519 ftoit %1,%0 4520 itoft %1,%0" 4521 [(set_attr "type" "ilog,multi,ild,ist,fcpys,fld,fst,ftoi,itof") 4522 (set_attr "isa" "*,*,*,*,*,*,*,fix,fix")]) 4523 4524 (define_insn "<code><mode>3" 4525 [(set (match_operand:VEC12 0 "register_operand" "=r") 4526 (any_maxmin:VEC12 4527 (match_operand:VEC12 1 "reg_or_0_operand" "rW") 4528 (match_operand:VEC12 2 "reg_or_0_operand" "rW")))] 4529 "TARGET_MAX" 4530 "<maxmin><modesuffix> %r1,%r2,%0" 4531 [(set_attr "type" "mvi")]) 4532 4533 (define_insn "one_cmpl<mode>2" 4534 [(set (match_operand:VEC 0 "register_operand" "=r") 4535 (not:VEC (match_operand:VEC 1 "register_operand" "r")))] 4536 "" 4537 "ornot $31,%1,%0" 4538 [(set_attr "type" "ilog")]) 4539 4540 (define_insn "and<mode>3" 4541 [(set (match_operand:VEC 0 "register_operand" "=r") 4542 (and:VEC (match_operand:VEC 1 "register_operand" "r") 4543 (match_operand:VEC 2 "register_operand" "r")))] 4544 "" 4545 "and %1,%2,%0" 4546 [(set_attr "type" "ilog")]) 4547 4548 (define_insn "*andnot<mode>3" 4549 [(set (match_operand:VEC 0 "register_operand" "=r") 4550 (and:VEC (not:VEC (match_operand:VEC 1 "register_operand" "r")) 4551 (match_operand:VEC 2 "register_operand" "r")))] 4552 "" 4553 "bic %2,%1,%0" 4554 [(set_attr "type" "ilog")]) 4555 4556 (define_insn "ior<mode>3" 4557 [(set (match_operand:VEC 0 "register_operand" "=r") 4558 (ior:VEC (match_operand:VEC 1 "register_operand" "r") 4559 (match_operand:VEC 2 "register_operand" "r")))] 4560 "" 4561 "bis %1,%2,%0" 4562 [(set_attr "type" "ilog")]) 4563 4564 (define_insn "*iornot<mode>3" 4565 [(set (match_operand:VEC 0 "register_operand" "=r") 4566 (ior:VEC (not:DI (match_operand:VEC 1 "register_operand" "r")) 4567 (match_operand:VEC 2 "register_operand" "r")))] 4568 "" 4569 "ornot %2,%1,%0" 4570 [(set_attr "type" "ilog")]) 4571 4572 (define_insn "xor<mode>3" 4573 [(set (match_operand:VEC 0 "register_operand" "=r") 4574 (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4575 (match_operand:VEC 2 "register_operand" "r")))] 4576 "" 4577 "xor %1,%2,%0" 4578 [(set_attr "type" "ilog")]) 4579 4580 (define_insn "*xornot<mode>3" 4581 [(set (match_operand:VEC 0 "register_operand" "=r") 4582 (not:VEC (xor:VEC (match_operand:VEC 1 "register_operand" "r") 4583 (match_operand:VEC 2 "register_operand" "r"))))] 4584 "" 4585 "eqv %1,%2,%0" 4586 [(set_attr "type" "ilog")]) 4587 4588 (define_expand "vec_shl_<mode>" 4589 [(set (match_operand:VEC 0 "register_operand") 4590 (ashift:DI (match_operand:VEC 1 "register_operand") 4591 (match_operand:DI 2 "reg_or_6bit_operand")))] 4592 "" 4593 { 4594 operands[0] = gen_lowpart (DImode, operands[0]); 4595 operands[1] = gen_lowpart (DImode, operands[1]); 4596 }) 4597 4598 (define_expand "vec_shr_<mode>" 4599 [(set (match_operand:VEC 0 "register_operand") 4600 (lshiftrt:DI (match_operand:VEC 1 "register_operand") 4601 (match_operand:DI 2 "reg_or_6bit_operand")))] 4602 "" 4603 { 4604 operands[0] = gen_lowpart (DImode, operands[0]); 4605 operands[1] = gen_lowpart (DImode, operands[1]); 4606 }) 4607 4609 ;; Bit field extract patterns which use ext[wlq][lh] 4610 4611 (define_expand "extvmisaligndi" 4612 [(set (match_operand:DI 0 "register_operand") 4613 (sign_extract:DI (match_operand:BLK 1 "memory_operand") 4614 (match_operand:DI 2 "const_int_operand") 4615 (match_operand:DI 3 "const_int_operand")))] 4616 "" 4617 { 4618 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4619 if (INTVAL (operands[3]) % 8 != 0 4620 || (INTVAL (operands[2]) != 16 4621 && INTVAL (operands[2]) != 32 4622 && INTVAL (operands[2]) != 64)) 4623 FAIL; 4624 4625 alpha_expand_unaligned_load (operands[0], operands[1], 4626 INTVAL (operands[2]) / 8, 4627 INTVAL (operands[3]) / 8, 1); 4628 DONE; 4629 }) 4630 4631 (define_expand "extzvdi" 4632 [(set (match_operand:DI 0 "register_operand") 4633 (zero_extract:DI (match_operand:DI 1 "register_operand") 4634 (match_operand:DI 2 "const_int_operand") 4635 (match_operand:DI 3 "const_int_operand")))] 4636 "" 4637 { 4638 /* We can do 8, 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4639 if (INTVAL (operands[3]) % 8 != 0 4640 || (INTVAL (operands[2]) != 8 4641 && INTVAL (operands[2]) != 16 4642 && INTVAL (operands[2]) != 32 4643 && INTVAL (operands[2]) != 64)) 4644 FAIL; 4645 }) 4646 4647 (define_expand "extzvmisaligndi" 4648 [(set (match_operand:DI 0 "register_operand") 4649 (zero_extract:DI (match_operand:BLK 1 "memory_operand") 4650 (match_operand:DI 2 "const_int_operand") 4651 (match_operand:DI 3 "const_int_operand")))] 4652 "" 4653 { 4654 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. 4655 We fail 8-bit fields, falling back on a simple byte load. */ 4656 if (INTVAL (operands[3]) % 8 != 0 4657 || (INTVAL (operands[2]) != 16 4658 && INTVAL (operands[2]) != 32 4659 && INTVAL (operands[2]) != 64)) 4660 FAIL; 4661 4662 alpha_expand_unaligned_load (operands[0], operands[1], 4663 INTVAL (operands[2]) / 8, 4664 INTVAL (operands[3]) / 8, 0); 4665 DONE; 4666 }) 4667 4668 (define_expand "insvmisaligndi" 4669 [(set (zero_extract:DI (match_operand:BLK 0 "memory_operand") 4670 (match_operand:DI 1 "const_int_operand") 4671 (match_operand:DI 2 "const_int_operand")) 4672 (match_operand:DI 3 "register_operand"))] 4673 "" 4674 { 4675 /* We can do 16, 32 and 64 bit fields, if aligned on byte boundaries. */ 4676 if (INTVAL (operands[2]) % 8 != 0 4677 || (INTVAL (operands[1]) != 16 4678 && INTVAL (operands[1]) != 32 4679 && INTVAL (operands[1]) != 64)) 4680 FAIL; 4681 4682 alpha_expand_unaligned_store (operands[0], operands[3], 4683 INTVAL (operands[1]) / 8, 4684 INTVAL (operands[2]) / 8); 4685 DONE; 4686 }) 4687 4688 ;; Block move/clear, see alpha.c for more details. 4689 ;; Argument 0 is the destination 4690 ;; Argument 1 is the source 4691 ;; Argument 2 is the length 4692 ;; Argument 3 is the alignment 4693 4694 (define_expand "movmemqi" 4695 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4696 (match_operand:BLK 1 "memory_operand")) 4697 (use (match_operand:DI 2 "immediate_operand")) 4698 (use (match_operand:DI 3 "immediate_operand"))])] 4699 "" 4700 { 4701 if (alpha_expand_block_move (operands)) 4702 DONE; 4703 else 4704 FAIL; 4705 }) 4706 4707 (define_expand "movmemdi" 4708 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4709 (match_operand:BLK 1 "memory_operand")) 4710 (use (match_operand:DI 2 "immediate_operand")) 4711 (use (match_operand:DI 3 "immediate_operand")) 4712 (use (match_dup 4)) 4713 (clobber (reg:DI 25)) 4714 (clobber (reg:DI 16)) 4715 (clobber (reg:DI 17)) 4716 (clobber (reg:DI 18)) 4717 (clobber (reg:DI 19)) 4718 (clobber (reg:DI 20)) 4719 (clobber (reg:DI 26)) 4720 (clobber (reg:DI 27))])] 4721 "TARGET_ABI_OPEN_VMS" 4722 "operands[4] = gen_rtx_SYMBOL_REF (Pmode, \"OTS$MOVE\");") 4723 4724 (define_insn "*movmemdi_1" 4725 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4726 (match_operand:BLK 1 "memory_operand" "m,m")) 4727 (use (match_operand:DI 2 "nonmemory_operand" "r,i")) 4728 (use (match_operand:DI 3 "immediate_operand")) 4729 (use (match_operand:DI 4 "call_operand" "i,i")) 4730 (clobber (reg:DI 25)) 4731 (clobber (reg:DI 16)) 4732 (clobber (reg:DI 17)) 4733 (clobber (reg:DI 18)) 4734 (clobber (reg:DI 19)) 4735 (clobber (reg:DI 20)) 4736 (clobber (reg:DI 26)) 4737 (clobber (reg:DI 27))] 4738 "TARGET_ABI_OPEN_VMS" 4739 { 4740 operands [5] = alpha_use_linkage (operands [4], false, true); 4741 switch (which_alternative) 4742 { 4743 case 0: 4744 return "lda $16,%0\;bis $31,%2,$17\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4745 case 1: 4746 return "lda $16,%0\;lda $17,%2($31)\;lda $18,%1\;ldq $26,%5\;lda $25,3($31)\;jsr $26,%4\;ldq $27,0($29)"; 4747 default: 4748 gcc_unreachable (); 4749 } 4750 } 4751 [(set_attr "type" "multi") 4752 (set_attr "length" "28")]) 4753 4754 (define_expand "setmemqi" 4755 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4756 (match_operand 2 "const_int_operand")) 4757 (use (match_operand:DI 1 "immediate_operand")) 4758 (use (match_operand:DI 3 "immediate_operand"))])] 4759 "" 4760 { 4761 /* If value to set is not zero, use the library routine. */ 4762 if (operands[2] != const0_rtx) 4763 FAIL; 4764 4765 if (alpha_expand_block_clear (operands)) 4766 DONE; 4767 else 4768 FAIL; 4769 }) 4770 4771 (define_expand "setmemdi" 4772 [(parallel [(set (match_operand:BLK 0 "memory_operand") 4773 (match_operand 2 "const_int_operand")) 4774 (use (match_operand:DI 1 "immediate_operand")) 4775 (use (match_operand:DI 3 "immediate_operand")) 4776 (use (match_dup 4)) 4777 (clobber (reg:DI 25)) 4778 (clobber (reg:DI 16)) 4779 (clobber (reg:DI 17)) 4780 (clobber (reg:DI 26)) 4781 (clobber (reg:DI 27))])] 4782 "TARGET_ABI_OPEN_VMS" 4783 { 4784 /* If value to set is not zero, use the library routine. */ 4785 if (operands[2] != const0_rtx) 4786 FAIL; 4787 4788 operands[4] = gen_rtx_SYMBOL_REF (Pmode, "OTS$ZERO"); 4789 }) 4790 4791 (define_insn "*clrmemdi_1" 4792 [(set (match_operand:BLK 0 "memory_operand" "=m,m") 4793 (const_int 0)) 4794 (use (match_operand:DI 1 "nonmemory_operand" "r,i")) 4795 (use (match_operand:DI 2 "immediate_operand")) 4796 (use (match_operand:DI 3 "call_operand" "i,i")) 4797 (clobber (reg:DI 25)) 4798 (clobber (reg:DI 16)) 4799 (clobber (reg:DI 17)) 4800 (clobber (reg:DI 26)) 4801 (clobber (reg:DI 27))] 4802 "TARGET_ABI_OPEN_VMS" 4803 { 4804 operands [4] = alpha_use_linkage (operands [3], false, true); 4805 switch (which_alternative) 4806 { 4807 case 0: 4808 return "lda $16,%0\;bis $31,%1,$17\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4809 case 1: 4810 return "lda $16,%0\;lda $17,%1($31)\;ldq $26,%4\;lda $25,2($31)\;jsr $26,%3\;ldq $27,0($29)"; 4811 default: 4812 gcc_unreachable (); 4813 } 4814 } 4815 [(set_attr "type" "multi") 4816 (set_attr "length" "24")]) 4817 4818 4820 ;; Subroutine of stack space allocation. Perform a stack probe. 4821 (define_expand "stack_probe_internal" 4822 [(set (match_dup 1) (match_operand:DI 0 "const_int_operand"))] 4823 "" 4824 { 4825 operands[1] = gen_rtx_MEM (DImode, plus_constant (Pmode, stack_pointer_rtx, 4826 INTVAL (operands[0]))); 4827 MEM_VOLATILE_P (operands[1]) = 1; 4828 4829 operands[0] = const0_rtx; 4830 }) 4831 4832 ;; This is how we allocate stack space. If we are allocating a 4833 ;; constant amount of space and we know it is less than 4096 4834 ;; bytes, we need do nothing. 4835 ;; 4836 ;; If it is more than 4096 bytes, we need to probe the stack 4837 ;; periodically. 4838 (define_expand "allocate_stack" 4839 [(set (reg:DI 30) 4840 (plus:DI (reg:DI 30) 4841 (match_operand:DI 1 "reg_or_cint_operand"))) 4842 (set (match_operand:DI 0 "register_operand" "=r") 4843 (match_dup 2))] 4844 "" 4845 { 4846 if (CONST_INT_P (operands[1]) 4847 && INTVAL (operands[1]) < 32768) 4848 { 4849 if (INTVAL (operands[1]) >= 4096) 4850 { 4851 /* We do this the same way as in the prologue and generate explicit 4852 probes. Then we update the stack by the constant. */ 4853 4854 int probed = 4096; 4855 4856 emit_insn (gen_stack_probe_internal (GEN_INT (- probed))); 4857 while (probed + 8192 < INTVAL (operands[1])) 4858 emit_insn (gen_stack_probe_internal 4859 (GEN_INT (- (probed += 8192)))); 4860 4861 if (probed + 4096 < INTVAL (operands[1])) 4862 emit_insn (gen_stack_probe_internal 4863 (GEN_INT (- INTVAL(operands[1])))); 4864 } 4865 4866 operands[1] = GEN_INT (- INTVAL (operands[1])); 4867 operands[2] = virtual_stack_dynamic_rtx; 4868 } 4869 else 4870 { 4871 rtx_code_label *out_label = 0; 4872 rtx_code_label *loop_label = gen_label_rtx (); 4873 rtx want = gen_reg_rtx (Pmode); 4874 rtx tmp = gen_reg_rtx (Pmode); 4875 rtx memref, test; 4876 4877 emit_insn (gen_subdi3 (want, stack_pointer_rtx, 4878 force_reg (Pmode, operands[1]))); 4879 4880 if (!CONST_INT_P (operands[1])) 4881 { 4882 rtx limit = GEN_INT (4096); 4883 out_label = gen_label_rtx (); 4884 test = gen_rtx_LTU (VOIDmode, operands[1], limit); 4885 emit_jump_insn 4886 (gen_cbranchdi4 (test, operands[1], limit, out_label)); 4887 } 4888 4889 emit_insn (gen_adddi3 (tmp, stack_pointer_rtx, GEN_INT (-4096))); 4890 emit_label (loop_label); 4891 memref = gen_rtx_MEM (DImode, tmp); 4892 MEM_VOLATILE_P (memref) = 1; 4893 emit_move_insn (memref, const0_rtx); 4894 emit_insn (gen_adddi3 (tmp, tmp, GEN_INT(-8192))); 4895 test = gen_rtx_GTU (VOIDmode, tmp, want); 4896 emit_jump_insn (gen_cbranchdi4 (test, tmp, want, loop_label)); 4897 4898 memref = gen_rtx_MEM (DImode, want); 4899 MEM_VOLATILE_P (memref) = 1; 4900 emit_move_insn (memref, const0_rtx); 4901 4902 if (out_label) 4903 emit_label (out_label); 4904 4905 emit_move_insn (stack_pointer_rtx, want); 4906 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 4907 DONE; 4908 } 4909 }) 4910 4911 ;; This is used by alpha_expand_prolog to do the same thing as above, 4912 ;; except we cannot at that time generate new basic blocks, so we hide 4913 ;; the loop in this one insn. 4914 4915 (define_insn "prologue_stack_probe_loop" 4916 [(unspec_volatile [(match_operand:DI 0 "register_operand" "r") 4917 (match_operand:DI 1 "register_operand" "r")] 4918 UNSPECV_PSPL)] 4919 "" 4920 { 4921 operands[2] = gen_label_rtx (); 4922 (*targetm.asm_out.internal_label) (asm_out_file, "L", 4923 CODE_LABEL_NUMBER (operands[2])); 4924 4925 return "stq $31,-8192(%1)\;subq %0,1,%0\;lda %1,-8192(%1)\;bne %0,%l2"; 4926 } 4927 [(set_attr "length" "16") 4928 (set_attr "type" "multi")]) 4929 4930 (define_expand "prologue" 4931 [(const_int 0)] 4932 "" 4933 { 4934 alpha_expand_prologue (); 4935 DONE; 4936 }) 4937 4938 ;; These take care of emitting the ldgp insn in the prologue. This will be 4939 ;; an lda/ldah pair and we want to align them properly. So we have two 4940 ;; unspec_volatile insns, the first of which emits the ldgp assembler macro 4941 ;; and the second of which emits nothing. However, both are marked as type 4942 ;; IADD (the default) so the alignment code in alpha.c does the right thing 4943 ;; with them. 4944 4945 (define_expand "prologue_ldgp" 4946 [(set (match_dup 0) 4947 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 4948 (set (match_dup 0) 4949 (unspec_volatile:DI [(match_dup 0) (match_dup 2)] UNSPECV_PLDGP2))] 4950 "" 4951 { 4952 operands[0] = pic_offset_table_rtx; 4953 operands[1] = gen_rtx_REG (Pmode, 27); 4954 operands[2] = (TARGET_EXPLICIT_RELOCS 4955 ? GEN_INT (alpha_next_sequence_number++) 4956 : const0_rtx); 4957 }) 4958 4959 (define_insn "*ldgp_er_1" 4960 [(set (match_operand:DI 0 "register_operand" "=r") 4961 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4962 (match_operand 2 "const_int_operand")] 4963 UNSPECV_LDGP1))] 4964 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4965 "ldah %0,0(%1)\t\t!gpdisp!%2" 4966 [(set_attr "cannot_copy" "true")]) 4967 4968 (define_insn "*ldgp_er_2" 4969 [(set (match_operand:DI 0 "register_operand" "=r") 4970 (unspec:DI [(match_operand:DI 1 "register_operand" "r") 4971 (match_operand 2 "const_int_operand")] 4972 UNSPEC_LDGP2))] 4973 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4974 "lda %0,0(%1)\t\t!gpdisp!%2" 4975 [(set_attr "cannot_copy" "true")]) 4976 4977 (define_insn "*prologue_ldgp_er_2" 4978 [(set (match_operand:DI 0 "register_operand" "=r") 4979 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4980 (match_operand 2 "const_int_operand")] 4981 UNSPECV_PLDGP2))] 4982 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 4983 "lda %0,0(%1)\t\t!gpdisp!%2\n$%~..ng:" 4984 [(set_attr "cannot_copy" "true")]) 4985 4986 (define_insn "*prologue_ldgp_1" 4987 [(set (match_operand:DI 0 "register_operand" "=r") 4988 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4989 (match_operand 2 "const_int_operand")] 4990 UNSPECV_LDGP1))] 4991 "" 4992 "ldgp %0,0(%1)\n$%~..ng:" 4993 [(set_attr "cannot_copy" "true")]) 4994 4995 (define_insn "*prologue_ldgp_2" 4996 [(set (match_operand:DI 0 "register_operand" "=r") 4997 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "r") 4998 (match_operand 2 "const_int_operand")] 4999 UNSPECV_PLDGP2))] 5000 "" 5001 ) 5002 5003 ;; The _mcount profiling hook has special calling conventions, and 5004 ;; does not clobber all the registers that a normal call would. So 5005 ;; hide the fact this is a call at all. 5006 5007 (define_insn "prologue_mcount" 5008 [(unspec_volatile [(const_int 0)] UNSPECV_MCOUNT)] 5009 "" 5010 { 5011 if (TARGET_EXPLICIT_RELOCS) 5012 /* Note that we cannot use a lituse_jsr reloc, since _mcount 5013 cannot be called via the PLT. */ 5014 return "ldq $28,_mcount($29)\t\t!literal\;jsr $28,($28),_mcount"; 5015 else 5016 return "lda $28,_mcount\;jsr $28,($28),_mcount"; 5017 } 5018 [(set_attr "type" "multi") 5019 (set_attr "length" "8")]) 5020 5021 (define_insn "init_fp" 5022 [(set (match_operand:DI 0 "register_operand" "=r") 5023 (match_operand:DI 1 "register_operand" "r")) 5024 (clobber (mem:BLK (match_operand:DI 2 "register_operand" "=r")))] 5025 "" 5026 "bis $31,%1,%0") 5027 5028 (define_expand "epilogue" 5029 [(return)] 5030 "" 5031 "alpha_expand_epilogue ();") 5032 5033 (define_expand "sibcall_epilogue" 5034 [(return)] 5035 "TARGET_ABI_OSF" 5036 { 5037 alpha_expand_epilogue (); 5038 DONE; 5039 }) 5040 5041 (define_expand "builtin_longjmp" 5042 [(use (match_operand:DI 0 "register_operand" "r"))] 5043 "TARGET_ABI_OSF" 5044 { 5045 /* The elements of the buffer are, in order: */ 5046 rtx fp = gen_rtx_MEM (Pmode, operands[0]); 5047 rtx lab = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 8)); 5048 rtx stack = gen_rtx_MEM (Pmode, plus_constant (Pmode, operands[0], 16)); 5049 rtx pv = gen_rtx_REG (Pmode, 27); 5050 5051 /* This bit is the same as expand_builtin_longjmp. */ 5052 emit_move_insn (hard_frame_pointer_rtx, fp); 5053 emit_move_insn (pv, lab); 5054 emit_stack_restore (SAVE_NONLOCAL, stack); 5055 emit_use (hard_frame_pointer_rtx); 5056 emit_use (stack_pointer_rtx); 5057 5058 /* Load the label we are jumping through into $27 so that we know 5059 where to look for it when we get back to setjmp's function for 5060 restoring the gp. */ 5061 emit_jump_insn (gen_builtin_longjmp_internal (pv)); 5062 emit_barrier (); 5063 DONE; 5064 }) 5065 5066 ;; This is effectively a copy of indirect_jump, but constrained such 5067 ;; that register renaming cannot foil our cunning plan with $27. 5068 (define_insn "builtin_longjmp_internal" 5069 [(set (pc) 5070 (unspec_volatile [(match_operand:DI 0 "register_operand" "c")] 5071 UNSPECV_LONGJMP))] 5072 "" 5073 "jmp $31,(%0),0" 5074 [(set_attr "type" "ibr")]) 5075 5076 (define_expand "builtin_setjmp_receiver" 5077 [(unspec_volatile [(label_ref (match_operand 0))] UNSPECV_SETJMPR)] 5078 "TARGET_ABI_OSF") 5079 5080 (define_insn_and_split "*builtin_setjmp_receiver_1" 5081 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR)] 5082 "TARGET_ABI_OSF" 5083 { 5084 if (TARGET_EXPLICIT_RELOCS) 5085 return "#"; 5086 else 5087 return "br $27,$LSJ%=\n$LSJ%=:\;ldgp $29,0($27)"; 5088 } 5089 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5090 [(set (match_dup 1) 5091 (unspec_volatile:DI [(match_dup 2) (match_dup 3)] UNSPECV_LDGP1)) 5092 (set (match_dup 1) 5093 (unspec:DI [(match_dup 1) (match_dup 3)] UNSPEC_LDGP2))] 5094 { 5095 if (prev_nonnote_insn (curr_insn) != XEXP (operands[0], 0)) 5096 emit_insn (gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, operands[0]), 5097 UNSPECV_SETJMPR_ER)); 5098 operands[1] = pic_offset_table_rtx; 5099 operands[2] = gen_rtx_REG (Pmode, 27); 5100 operands[3] = GEN_INT (alpha_next_sequence_number++); 5101 } 5102 [(set_attr "length" "12") 5103 (set_attr "type" "multi")]) 5104 5105 (define_insn "*builtin_setjmp_receiver_er_sl_1" 5106 [(unspec_volatile [(match_operand 0)] UNSPECV_SETJMPR_ER)] 5107 "TARGET_ABI_OSF && TARGET_EXPLICIT_RELOCS" 5108 "lda $27,$LSJ%=-%l0($27)\n$LSJ%=:") 5109 5110 ;; When flag_reorder_blocks_and_partition is in effect, compiler puts 5111 ;; exception landing pads in a cold section. To prevent inter-section offset 5112 ;; calculation, a jump to original landing pad is emitted in the place of the 5113 ;; original landing pad. Since landing pad is moved, RA-relative GP 5114 ;; calculation in the prologue of landing pad breaks. To solve this problem, 5115 ;; we use alternative GP load approach. 5116 5117 (define_expand "exception_receiver" 5118 [(unspec_volatile [(match_dup 0)] UNSPECV_EHR)] 5119 "TARGET_ABI_OSF" 5120 { 5121 if (flag_reorder_blocks_and_partition) 5122 operands[0] = copy_rtx (alpha_gp_save_rtx ()); 5123 else 5124 operands[0] = const0_rtx; 5125 }) 5126 5127 (define_insn "*exception_receiver_2" 5128 [(unspec_volatile [(match_operand:DI 0 "memory_operand" "m")] UNSPECV_EHR)] 5129 "TARGET_ABI_OSF && flag_reorder_blocks_and_partition" 5130 "ldq $29,%0" 5131 [(set_attr "type" "ild")]) 5132 5133 (define_insn_and_split "*exception_receiver_1" 5134 [(unspec_volatile [(const_int 0)] UNSPECV_EHR)] 5135 "TARGET_ABI_OSF" 5136 { 5137 if (TARGET_EXPLICIT_RELOCS) 5138 return "#"; 5139 else 5140 return "ldgp $29,0($26)"; 5141 } 5142 "&& TARGET_EXPLICIT_RELOCS && reload_completed" 5143 [(set (match_dup 0) 5144 (unspec_volatile:DI [(match_dup 1) (match_dup 2)] UNSPECV_LDGP1)) 5145 (set (match_dup 0) 5146 (unspec:DI [(match_dup 0) (match_dup 2)] UNSPEC_LDGP2))] 5147 { 5148 operands[0] = pic_offset_table_rtx; 5149 operands[1] = gen_rtx_REG (Pmode, 26); 5150 operands[2] = GEN_INT (alpha_next_sequence_number++); 5151 } 5152 [(set_attr "length" "8") 5153 (set_attr "type" "multi")]) 5154 5155 (define_expand "nonlocal_goto_receiver" 5156 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5157 (set (reg:DI 27) (mem:DI (reg:DI 29))) 5158 (unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE) 5159 (use (reg:DI 27))] 5160 "TARGET_ABI_OPEN_VMS") 5161 5162 (define_insn "arg_home" 5163 [(unspec [(const_int 0)] UNSPEC_ARG_HOME) 5164 (use (reg:DI 1)) 5165 (use (reg:DI 25)) 5166 (use (reg:DI 16)) 5167 (use (reg:DI 17)) 5168 (use (reg:DI 18)) 5169 (use (reg:DI 19)) 5170 (use (reg:DI 20)) 5171 (use (reg:DI 21)) 5172 (use (reg:DI 48)) 5173 (use (reg:DI 49)) 5174 (use (reg:DI 50)) 5175 (use (reg:DI 51)) 5176 (use (reg:DI 52)) 5177 (use (reg:DI 53)) 5178 (clobber (mem:BLK (const_int 0))) 5179 (clobber (reg:DI 24)) 5180 (clobber (reg:DI 25)) 5181 (clobber (reg:DI 0))] 5182 "TARGET_ABI_OPEN_VMS" 5183 "lda $0,OTS$HOME_ARGS\;ldq $0,8($0)\;jsr $0,OTS$HOME_ARGS" 5184 [(set_attr "length" "16") 5185 (set_attr "type" "multi")]) 5186 5187 ;; Prefetch data. 5188 ;; 5189 ;; On EV4, these instructions are nops -- no load occurs. 5190 ;; 5191 ;; On EV5, these instructions act as a normal load, and thus can trap 5192 ;; if the address is invalid. The OS may (or may not) handle this in 5193 ;; the entMM fault handler and suppress the fault. If so, then this 5194 ;; has the effect of a read prefetch instruction. 5195 ;; 5196 ;; On EV6, these become official prefetch instructions. 5197 5198 (define_insn "prefetch" 5199 [(prefetch (match_operand:DI 0 "address_operand" "p") 5200 (match_operand:DI 1 "const_int_operand" "n") 5201 (match_operand:DI 2 "const_int_operand" "n"))] 5202 "TARGET_FIXUP_EV5_PREFETCH || alpha_cpu == PROCESSOR_EV6" 5203 { 5204 /* Interpret "no temporal locality" as this data should be evicted once 5205 it is used. The "evict next" alternatives load the data into the cache 5206 and leave the LRU eviction counter pointing to that block. */ 5207 static const char * const alt[2][2] = { 5208 { 5209 "ldq $31,%a0", /* read, evict next */ 5210 "ldl $31,%a0", /* read, evict last */ 5211 }, 5212 { 5213 "ldt $f31,%a0", /* write, evict next */ 5214 "lds $f31,%a0", /* write, evict last */ 5215 } 5216 }; 5217 5218 bool write = INTVAL (operands[1]) != 0; 5219 bool lru = INTVAL (operands[2]) != 0; 5220 5221 return alt[write][lru]; 5222 } 5223 [(set_attr "type" "ild")]) 5224 5225 ;; Close the trap shadow of preceding instructions. This is generated 5226 ;; by alpha_reorg. 5227 5228 (define_insn "trapb" 5229 [(unspec_volatile [(const_int 0)] UNSPECV_TRAPB)] 5230 "" 5231 "trapb" 5232 [(set_attr "type" "misc")]) 5233 5234 ;; No-op instructions used by machine-dependent reorg to preserve 5235 ;; alignment for instruction issue. 5236 ;; The Unicos/Mk assembler does not support these opcodes. 5237 5238 (define_insn "nop" 5239 [(const_int 0)] 5240 "" 5241 "bis $31,$31,$31" 5242 [(set_attr "type" "ilog")]) 5243 5244 (define_insn "fnop" 5245 [(const_int 1)] 5246 "TARGET_FP" 5247 "cpys $f31,$f31,$f31" 5248 [(set_attr "type" "fcpys")]) 5249 5250 (define_insn "unop" 5251 [(const_int 2)] 5252 "" 5253 "ldq_u $31,0($30)") 5254 5255 (define_insn "realign" 5256 [(unspec_volatile [(match_operand 0 "immediate_operand" "i")] 5257 UNSPECV_REALIGN)] 5258 "" 5259 ".align %0 #realign") 5260 5262 ;; Instructions to be emitted from __builtins. 5263 5264 (define_insn "builtin_cmpbge" 5265 [(set (match_operand:DI 0 "register_operand" "=r") 5266 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "rJ") 5267 (match_operand:DI 2 "reg_or_8bit_operand" "rI")] 5268 UNSPEC_CMPBGE))] 5269 "" 5270 "cmpbge %r1,%2,%0" 5271 ;; The EV6 data sheets list this as ILOG. OTOH, EV6 doesn't 5272 ;; actually differentiate between ILOG and ICMP in the schedule. 5273 [(set_attr "type" "icmp")]) 5274 5275 (define_expand "extbl" 5276 [(match_operand:DI 0 "register_operand") 5277 (match_operand:DI 1 "reg_or_0_operand") 5278 (match_operand:DI 2 "reg_or_8bit_operand")] 5279 "" 5280 { 5281 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (8), operands[2])); 5282 DONE; 5283 }) 5284 5285 (define_expand "extwl" 5286 [(match_operand:DI 0 "register_operand") 5287 (match_operand:DI 1 "reg_or_0_operand") 5288 (match_operand:DI 2 "reg_or_8bit_operand")] 5289 "" 5290 { 5291 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (16), operands[2])); 5292 DONE; 5293 }) 5294 5295 (define_expand "extll" 5296 [(match_operand:DI 0 "register_operand") 5297 (match_operand:DI 1 "reg_or_0_operand") 5298 (match_operand:DI 2 "reg_or_8bit_operand")] 5299 "" 5300 { 5301 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (32), operands[2])); 5302 DONE; 5303 }) 5304 5305 (define_expand "extql" 5306 [(match_operand:DI 0 "register_operand") 5307 (match_operand:DI 1 "reg_or_0_operand") 5308 (match_operand:DI 2 "reg_or_8bit_operand")] 5309 "" 5310 { 5311 emit_insn (gen_extxl (operands[0], operands[1], GEN_INT (64), operands[2])); 5312 DONE; 5313 }) 5314 5315 (define_expand "builtin_insbl" 5316 [(match_operand:DI 0 "register_operand") 5317 (match_operand:DI 1 "register_operand") 5318 (match_operand:DI 2 "reg_or_8bit_operand")] 5319 "" 5320 { 5321 operands[1] = gen_lowpart (QImode, operands[1]); 5322 emit_insn (gen_insbl (operands[0], operands[1], operands[2])); 5323 DONE; 5324 }) 5325 5326 (define_expand "builtin_inswl" 5327 [(match_operand:DI 0 "register_operand") 5328 (match_operand:DI 1 "register_operand") 5329 (match_operand:DI 2 "reg_or_8bit_operand")] 5330 "" 5331 { 5332 operands[1] = gen_lowpart (HImode, operands[1]); 5333 emit_insn (gen_inswl (operands[0], operands[1], operands[2])); 5334 DONE; 5335 }) 5336 5337 (define_expand "builtin_insll" 5338 [(match_operand:DI 0 "register_operand") 5339 (match_operand:DI 1 "register_operand") 5340 (match_operand:DI 2 "reg_or_8bit_operand")] 5341 "" 5342 { 5343 operands[1] = gen_lowpart (SImode, operands[1]); 5344 emit_insn (gen_insll (operands[0], operands[1], operands[2])); 5345 DONE; 5346 }) 5347 5348 (define_expand "inswh" 5349 [(match_operand:DI 0 "register_operand") 5350 (match_operand:DI 1 "register_operand") 5351 (match_operand:DI 2 "reg_or_8bit_operand")] 5352 "" 5353 { 5354 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5355 DONE; 5356 }) 5357 5358 (define_expand "inslh" 5359 [(match_operand:DI 0 "register_operand") 5360 (match_operand:DI 1 "register_operand") 5361 (match_operand:DI 2 "reg_or_8bit_operand")] 5362 "" 5363 { 5364 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5365 DONE; 5366 }) 5367 5368 (define_expand "insqh" 5369 [(match_operand:DI 0 "register_operand") 5370 (match_operand:DI 1 "register_operand") 5371 (match_operand:DI 2 "reg_or_8bit_operand")] 5372 "" 5373 { 5374 emit_insn (gen_insxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5375 DONE; 5376 }) 5377 5378 (define_expand "mskbl" 5379 [(match_operand:DI 0 "register_operand") 5380 (match_operand:DI 1 "reg_or_0_operand") 5381 (match_operand:DI 2 "reg_or_8bit_operand")] 5382 "" 5383 { 5384 rtx mask = GEN_INT (0xff); 5385 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5386 DONE; 5387 }) 5388 5389 (define_expand "mskwl" 5390 [(match_operand:DI 0 "register_operand") 5391 (match_operand:DI 1 "reg_or_0_operand") 5392 (match_operand:DI 2 "reg_or_8bit_operand")] 5393 "" 5394 { 5395 rtx mask = GEN_INT (0xffff); 5396 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5397 DONE; 5398 }) 5399 5400 (define_expand "mskll" 5401 [(match_operand:DI 0 "register_operand") 5402 (match_operand:DI 1 "reg_or_0_operand") 5403 (match_operand:DI 2 "reg_or_8bit_operand")] 5404 "" 5405 { 5406 rtx mask = gen_int_mode (0xffffffff, DImode); 5407 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5408 DONE; 5409 }) 5410 5411 (define_expand "mskql" 5412 [(match_operand:DI 0 "register_operand") 5413 (match_operand:DI 1 "reg_or_0_operand") 5414 (match_operand:DI 2 "reg_or_8bit_operand")] 5415 "" 5416 { 5417 rtx mask = constm1_rtx; 5418 emit_insn (gen_mskxl (operands[0], operands[1], mask, operands[2])); 5419 DONE; 5420 }) 5421 5422 (define_expand "mskwh" 5423 [(match_operand:DI 0 "register_operand") 5424 (match_operand:DI 1 "register_operand") 5425 (match_operand:DI 2 "reg_or_8bit_operand")] 5426 "" 5427 { 5428 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (16), operands[2])); 5429 DONE; 5430 }) 5431 5432 (define_expand "msklh" 5433 [(match_operand:DI 0 "register_operand") 5434 (match_operand:DI 1 "register_operand") 5435 (match_operand:DI 2 "reg_or_8bit_operand")] 5436 "" 5437 { 5438 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (32), operands[2])); 5439 DONE; 5440 }) 5441 5442 (define_expand "mskqh" 5443 [(match_operand:DI 0 "register_operand") 5444 (match_operand:DI 1 "register_operand") 5445 (match_operand:DI 2 "reg_or_8bit_operand")] 5446 "" 5447 { 5448 emit_insn (gen_mskxh (operands[0], operands[1], GEN_INT (64), operands[2])); 5449 DONE; 5450 }) 5451 5452 (define_expand "builtin_zap" 5453 [(set (match_operand:DI 0 "register_operand") 5454 (and:DI (unspec:DI 5455 [(match_operand:DI 2 "reg_or_cint_operand")] 5456 UNSPEC_ZAP) 5457 (match_operand:DI 1 "reg_or_cint_operand")))] 5458 "" 5459 { 5460 if (CONST_INT_P (operands[2])) 5461 { 5462 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5463 5464 if (mask == const0_rtx) 5465 { 5466 emit_move_insn (operands[0], const0_rtx); 5467 DONE; 5468 } 5469 if (mask == constm1_rtx) 5470 { 5471 emit_move_insn (operands[0], operands[1]); 5472 DONE; 5473 } 5474 5475 operands[1] = force_reg (DImode, operands[1]); 5476 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5477 DONE; 5478 } 5479 5480 operands[1] = force_reg (DImode, operands[1]); 5481 operands[2] = gen_lowpart (QImode, operands[2]); 5482 }) 5483 5484 (define_insn "*builtin_zap_1" 5485 [(set (match_operand:DI 0 "register_operand" "=r,r,r,r") 5486 (and:DI (unspec:DI 5487 [(match_operand:QI 2 "reg_or_cint_operand" "n,n,r,r")] 5488 UNSPEC_ZAP) 5489 (match_operand:DI 1 "reg_or_cint_operand" "n,r,J,r")))] 5490 "" 5491 "@ 5492 # 5493 # 5494 bis $31,$31,%0 5495 zap %r1,%2,%0" 5496 [(set_attr "type" "shift,shift,ilog,shift")]) 5497 5498 (define_split 5499 [(set (match_operand:DI 0 "register_operand") 5500 (and:DI (unspec:DI 5501 [(match_operand:QI 2 "const_int_operand")] 5502 UNSPEC_ZAP) 5503 (match_operand:DI 1 "const_int_operand")))] 5504 "" 5505 [(const_int 0)] 5506 { 5507 rtx mask = alpha_expand_zap_mask (INTVAL (operands[2])); 5508 5509 operands[1] = gen_int_mode (INTVAL (operands[1]) & INTVAL (mask), DImode); 5510 emit_move_insn (operands[0], operands[1]); 5511 DONE; 5512 }) 5513 5514 (define_split 5515 [(set (match_operand:DI 0 "register_operand") 5516 (and:DI (unspec:DI 5517 [(match_operand:QI 2 "const_int_operand")] 5518 UNSPEC_ZAP) 5519 (match_operand:DI 1 "register_operand")))] 5520 "" 5521 [(set (match_dup 0) 5522 (and:DI (match_dup 1) (match_dup 2)))] 5523 { 5524 operands[2] = alpha_expand_zap_mask (INTVAL (operands[2])); 5525 if (operands[2] == const0_rtx) 5526 { 5527 emit_move_insn (operands[0], const0_rtx); 5528 DONE; 5529 } 5530 if (operands[2] == constm1_rtx) 5531 { 5532 emit_move_insn (operands[0], operands[1]); 5533 DONE; 5534 } 5535 }) 5536 5537 (define_expand "builtin_zapnot" 5538 [(set (match_operand:DI 0 "register_operand") 5539 (and:DI (unspec:DI 5540 [(not:QI (match_operand:DI 2 "reg_or_cint_operand"))] 5541 UNSPEC_ZAP) 5542 (match_operand:DI 1 "reg_or_cint_operand")))] 5543 "" 5544 { 5545 if (CONST_INT_P (operands[2])) 5546 { 5547 rtx mask = alpha_expand_zap_mask (~ INTVAL (operands[2])); 5548 5549 if (mask == const0_rtx) 5550 { 5551 emit_move_insn (operands[0], const0_rtx); 5552 DONE; 5553 } 5554 if (mask == constm1_rtx) 5555 { 5556 emit_move_insn (operands[0], operands[1]); 5557 DONE; 5558 } 5559 5560 operands[1] = force_reg (DImode, operands[1]); 5561 emit_insn (gen_anddi3 (operands[0], operands[1], mask)); 5562 DONE; 5563 } 5564 5565 operands[1] = force_reg (DImode, operands[1]); 5566 operands[2] = gen_lowpart (QImode, operands[2]); 5567 }) 5568 5569 (define_insn "*builtin_zapnot_1" 5570 [(set (match_operand:DI 0 "register_operand" "=r") 5571 (and:DI (unspec:DI 5572 [(not:QI (match_operand:QI 2 "register_operand" "r"))] 5573 UNSPEC_ZAP) 5574 (match_operand:DI 1 "reg_or_0_operand" "rJ")))] 5575 "" 5576 "zapnot %r1,%2,%0" 5577 [(set_attr "type" "shift")]) 5578 5579 (define_insn "builtin_amask" 5580 [(set (match_operand:DI 0 "register_operand" "=r") 5581 (unspec:DI [(match_operand:DI 1 "reg_or_8bit_operand" "rI")] 5582 UNSPEC_AMASK))] 5583 "" 5584 "amask %1,%0" 5585 [(set_attr "type" "ilog")]) 5586 5587 (define_insn "builtin_implver" 5588 [(set (match_operand:DI 0 "register_operand" "=r") 5589 (unspec:DI [(const_int 0)] UNSPEC_IMPLVER))] 5590 "" 5591 "implver %0" 5592 [(set_attr "type" "ilog")]) 5593 5594 (define_insn "builtin_rpcc" 5595 [(set (match_operand:DI 0 "register_operand" "=r") 5596 (unspec_volatile:DI [(const_int 0)] UNSPECV_RPCC))] 5597 "" 5598 "rpcc %0" 5599 [(set_attr "type" "ilog")]) 5600 5601 (define_expand "builtin_minub8" 5602 [(match_operand:DI 0 "register_operand") 5603 (match_operand:DI 1 "reg_or_0_operand") 5604 (match_operand:DI 2 "reg_or_0_operand")] 5605 "TARGET_MAX" 5606 { 5607 alpha_expand_builtin_vector_binop (gen_uminv8qi3, V8QImode, operands[0], 5608 operands[1], operands[2]); 5609 DONE; 5610 }) 5611 5612 (define_expand "builtin_minsb8" 5613 [(match_operand:DI 0 "register_operand") 5614 (match_operand:DI 1 "reg_or_0_operand") 5615 (match_operand:DI 2 "reg_or_0_operand")] 5616 "TARGET_MAX" 5617 { 5618 alpha_expand_builtin_vector_binop (gen_sminv8qi3, V8QImode, operands[0], 5619 operands[1], operands[2]); 5620 DONE; 5621 }) 5622 5623 (define_expand "builtin_minuw4" 5624 [(match_operand:DI 0 "register_operand") 5625 (match_operand:DI 1 "reg_or_0_operand") 5626 (match_operand:DI 2 "reg_or_0_operand")] 5627 "TARGET_MAX" 5628 { 5629 alpha_expand_builtin_vector_binop (gen_uminv4hi3, V4HImode, operands[0], 5630 operands[1], operands[2]); 5631 DONE; 5632 }) 5633 5634 (define_expand "builtin_minsw4" 5635 [(match_operand:DI 0 "register_operand") 5636 (match_operand:DI 1 "reg_or_0_operand") 5637 (match_operand:DI 2 "reg_or_0_operand")] 5638 "TARGET_MAX" 5639 { 5640 alpha_expand_builtin_vector_binop (gen_sminv4hi3, V4HImode, operands[0], 5641 operands[1], operands[2]); 5642 DONE; 5643 }) 5644 5645 (define_expand "builtin_maxub8" 5646 [(match_operand:DI 0 "register_operand") 5647 (match_operand:DI 1 "reg_or_0_operand") 5648 (match_operand:DI 2 "reg_or_0_operand")] 5649 "TARGET_MAX" 5650 { 5651 alpha_expand_builtin_vector_binop (gen_umaxv8qi3, V8QImode, operands[0], 5652 operands[1], operands[2]); 5653 DONE; 5654 }) 5655 5656 (define_expand "builtin_maxsb8" 5657 [(match_operand:DI 0 "register_operand") 5658 (match_operand:DI 1 "reg_or_0_operand") 5659 (match_operand:DI 2 "reg_or_0_operand")] 5660 "TARGET_MAX" 5661 { 5662 alpha_expand_builtin_vector_binop (gen_smaxv8qi3, V8QImode, operands[0], 5663 operands[1], operands[2]); 5664 DONE; 5665 }) 5666 5667 (define_expand "builtin_maxuw4" 5668 [(match_operand:DI 0 "register_operand") 5669 (match_operand:DI 1 "reg_or_0_operand") 5670 (match_operand:DI 2 "reg_or_0_operand")] 5671 "TARGET_MAX" 5672 { 5673 alpha_expand_builtin_vector_binop (gen_umaxv4hi3, V4HImode, operands[0], 5674 operands[1], operands[2]); 5675 DONE; 5676 }) 5677 5678 (define_expand "builtin_maxsw4" 5679 [(match_operand:DI 0 "register_operand") 5680 (match_operand:DI 1 "reg_or_0_operand") 5681 (match_operand:DI 2 "reg_or_0_operand")] 5682 "TARGET_MAX" 5683 { 5684 alpha_expand_builtin_vector_binop (gen_smaxv4hi3, V4HImode, operands[0], 5685 operands[1], operands[2]); 5686 DONE; 5687 }) 5688 5689 (define_insn "builtin_perr" 5690 [(set (match_operand:DI 0 "register_operand" "=r") 5691 (unspec:DI [(match_operand:DI 1 "reg_or_0_operand" "%rJ") 5692 (match_operand:DI 2 "reg_or_8bit_operand" "rJ")] 5693 UNSPEC_PERR))] 5694 "TARGET_MAX" 5695 "perr %r1,%r2,%0" 5696 [(set_attr "type" "mvi")]) 5697 5698 (define_expand "builtin_pklb" 5699 [(set (match_operand:DI 0 "register_operand") 5700 (vec_concat:V8QI 5701 (vec_concat:V4QI 5702 (truncate:V2QI (match_operand:DI 1 "register_operand")) 5703 (match_dup 2)) 5704 (match_dup 3)))] 5705 "TARGET_MAX" 5706 { 5707 operands[0] = gen_lowpart (V8QImode, operands[0]); 5708 operands[1] = gen_lowpart (V2SImode, operands[1]); 5709 operands[2] = CONST0_RTX (V2QImode); 5710 operands[3] = CONST0_RTX (V4QImode); 5711 }) 5712 5713 (define_insn "*pklb" 5714 [(set (match_operand:V8QI 0 "register_operand" "=r") 5715 (vec_concat:V8QI 5716 (vec_concat:V4QI 5717 (truncate:V2QI (match_operand:V2SI 1 "register_operand" "r")) 5718 (match_operand:V2QI 2 "const0_operand")) 5719 (match_operand:V4QI 3 "const0_operand")))] 5720 "TARGET_MAX" 5721 "pklb %r1,%0" 5722 [(set_attr "type" "mvi")]) 5723 5724 (define_expand "builtin_pkwb" 5725 [(set (match_operand:DI 0 "register_operand") 5726 (vec_concat:V8QI 5727 (truncate:V4QI (match_operand:DI 1 "register_operand")) 5728 (match_dup 2)))] 5729 "TARGET_MAX" 5730 { 5731 operands[0] = gen_lowpart (V8QImode, operands[0]); 5732 operands[1] = gen_lowpart (V4HImode, operands[1]); 5733 operands[2] = CONST0_RTX (V4QImode); 5734 }) 5735 5736 (define_insn "*pkwb" 5737 [(set (match_operand:V8QI 0 "register_operand" "=r") 5738 (vec_concat:V8QI 5739 (truncate:V4QI (match_operand:V4HI 1 "register_operand" "r")) 5740 (match_operand:V4QI 2 "const0_operand")))] 5741 "TARGET_MAX" 5742 "pkwb %r1,%0" 5743 [(set_attr "type" "mvi")]) 5744 5745 (define_expand "builtin_unpkbl" 5746 [(set (match_operand:DI 0 "register_operand") 5747 (zero_extend:V2SI 5748 (vec_select:V2QI (match_operand:DI 1 "register_operand") 5749 (parallel [(const_int 0) (const_int 1)]))))] 5750 "TARGET_MAX" 5751 { 5752 operands[0] = gen_lowpart (V2SImode, operands[0]); 5753 operands[1] = gen_lowpart (V8QImode, operands[1]); 5754 }) 5755 5756 (define_insn "*unpkbl" 5757 [(set (match_operand:V2SI 0 "register_operand" "=r") 5758 (zero_extend:V2SI 5759 (vec_select:V2QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5760 (parallel [(const_int 0) (const_int 1)]))))] 5761 "TARGET_MAX" 5762 "unpkbl %r1,%0" 5763 [(set_attr "type" "mvi")]) 5764 5765 (define_expand "builtin_unpkbw" 5766 [(set (match_operand:DI 0 "register_operand") 5767 (zero_extend:V4HI 5768 (vec_select:V4QI (match_operand:DI 1 "register_operand") 5769 (parallel [(const_int 0) 5770 (const_int 1) 5771 (const_int 2) 5772 (const_int 3)]))))] 5773 "TARGET_MAX" 5774 { 5775 operands[0] = gen_lowpart (V4HImode, operands[0]); 5776 operands[1] = gen_lowpart (V8QImode, operands[1]); 5777 }) 5778 5779 (define_insn "*unpkbw" 5780 [(set (match_operand:V4HI 0 "register_operand" "=r") 5781 (zero_extend:V4HI 5782 (vec_select:V4QI (match_operand:V8QI 1 "reg_or_0_operand" "rW") 5783 (parallel [(const_int 0) 5784 (const_int 1) 5785 (const_int 2) 5786 (const_int 3)]))))] 5787 "TARGET_MAX" 5788 "unpkbw %r1,%0" 5789 [(set_attr "type" "mvi")]) 5790 5792 (include "sync.md") 5793 5795 ;; The call patterns are at the end of the file because their 5796 ;; wildcard operand0 interferes with nice recognition. 5797 5798 (define_insn "*call_value_osf_1_er_noreturn" 5799 [(set (match_operand 0) 5800 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5801 (match_operand 2))) 5802 (use (reg:DI 29)) 5803 (clobber (reg:DI 26))] 5804 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5805 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5806 "@ 5807 jsr $26,($27),0 5808 bsr $26,%1\t\t!samegp 5809 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),%1\t\t!lituse_jsr!%#" 5810 [(set_attr "type" "jsr") 5811 (set_attr "length" "*,*,8")]) 5812 5813 (define_insn "*call_value_osf_1_er" 5814 [(set (match_operand 0) 5815 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5816 (match_operand 2))) 5817 (use (reg:DI 29)) 5818 (clobber (reg:DI 26))] 5819 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5820 "@ 5821 jsr $26,(%1),0\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%* 5822 bsr $26,%1\t\t!samegp 5823 ldq $27,%1($29)\t\t!literal!%#\;jsr $26,($27),0\t\t!lituse_jsr!%#\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5824 [(set_attr "type" "jsr") 5825 (set_attr "length" "12,*,16")]) 5826 5827 ;; We must use peep2 instead of a split because we need accurate life 5828 ;; information for $gp. Consider the case of { bar(); while (1); }. 5829 (define_peephole2 5830 [(parallel [(set (match_operand 0) 5831 (call (mem:DI (match_operand:DI 1 "call_operand")) 5832 (match_operand 2))) 5833 (use (reg:DI 29)) 5834 (clobber (reg:DI 26))])] 5835 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5836 && ! samegp_function_operand (operands[1], Pmode) 5837 && (peep2_regno_dead_p (1, 29) 5838 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5839 [(parallel [(set (match_dup 0) 5840 (call (mem:DI (match_dup 3)) 5841 (match_dup 2))) 5842 (use (reg:DI 29)) 5843 (use (match_dup 1)) 5844 (use (match_dup 4)) 5845 (clobber (reg:DI 26))])] 5846 { 5847 if (CONSTANT_P (operands[1])) 5848 { 5849 operands[3] = gen_rtx_REG (Pmode, 27); 5850 operands[4] = GEN_INT (alpha_next_sequence_number++); 5851 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5852 operands[1], operands[4])); 5853 } 5854 else 5855 { 5856 operands[3] = operands[1]; 5857 operands[1] = const0_rtx; 5858 operands[4] = const0_rtx; 5859 } 5860 }) 5861 5862 (define_peephole2 5863 [(parallel [(set (match_operand 0) 5864 (call (mem:DI (match_operand:DI 1 "call_operand")) 5865 (match_operand 2))) 5866 (use (reg:DI 29)) 5867 (clobber (reg:DI 26))])] 5868 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF && reload_completed 5869 && ! samegp_function_operand (operands[1], Pmode) 5870 && ! (peep2_regno_dead_p (1, 29) 5871 || find_reg_note (insn, REG_NORETURN, NULL_RTX))" 5872 [(parallel [(set (match_dup 0) 5873 (call (mem:DI (match_dup 3)) 5874 (match_dup 2))) 5875 (set (match_dup 6) 5876 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP1)) 5877 (use (match_dup 1)) 5878 (use (match_dup 5)) 5879 (clobber (reg:DI 26))]) 5880 (set (match_dup 6) 5881 (unspec:DI [(match_dup 6) (match_dup 4)] UNSPEC_LDGP2))] 5882 { 5883 if (CONSTANT_P (operands[1])) 5884 { 5885 operands[3] = gen_rtx_REG (Pmode, 27); 5886 operands[5] = GEN_INT (alpha_next_sequence_number++); 5887 emit_insn (gen_movdi_er_high_g (operands[3], pic_offset_table_rtx, 5888 operands[1], operands[5])); 5889 } 5890 else 5891 { 5892 operands[3] = operands[1]; 5893 operands[1] = const0_rtx; 5894 operands[5] = const0_rtx; 5895 } 5896 operands[4] = GEN_INT (alpha_next_sequence_number++); 5897 operands[6] = pic_offset_table_rtx; 5898 }) 5899 5900 (define_insn "*call_value_osf_2_er_nogp" 5901 [(set (match_operand 0) 5902 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5903 (match_operand 2))) 5904 (use (reg:DI 29)) 5905 (use (match_operand 3)) 5906 (use (match_operand 4)) 5907 (clobber (reg:DI 26))] 5908 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5909 "jsr $26,(%1),%3%J4" 5910 [(set_attr "type" "jsr")]) 5911 5912 (define_insn "*call_value_osf_2_er" 5913 [(set (match_operand 0) 5914 (call (mem:DI (match_operand:DI 1 "register_operand" "c")) 5915 (match_operand 2))) 5916 (set (reg:DI 29) 5917 (unspec:DI [(reg:DI 29) (match_operand 5 "const_int_operand")] 5918 UNSPEC_LDGP1)) 5919 (use (match_operand 3)) 5920 (use (match_operand 4)) 5921 (clobber (reg:DI 26))] 5922 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 5923 "jsr $26,(%1),%3%J4\;ldah $29,0($26)\t\t!gpdisp!%5" 5924 [(set_attr "type" "jsr") 5925 (set_attr "cannot_copy" "true") 5926 (set_attr "length" "8")]) 5927 5928 (define_insn "*call_value_osf_1_noreturn" 5929 [(set (match_operand 0) 5930 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 5931 (match_operand 2))) 5932 (use (reg:DI 29)) 5933 (clobber (reg:DI 26))] 5934 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF 5935 && find_reg_note (insn, REG_NORETURN, NULL_RTX)" 5936 "@ 5937 jsr $26,($27),0 5938 bsr $26,$%1..ng 5939 jsr $26,%1" 5940 [(set_attr "type" "jsr") 5941 (set_attr "length" "*,*,8")]) 5942 5943 (define_int_iterator TLS_CALL 5944 [UNSPEC_TLSGD_CALL 5945 UNSPEC_TLSLDM_CALL]) 5946 5947 (define_int_attr tls 5948 [(UNSPEC_TLSGD_CALL "tlsgd") 5949 (UNSPEC_TLSLDM_CALL "tlsldm")]) 5950 5951 (define_insn "call_value_osf_<tls>" 5952 [(set (match_operand 0) 5953 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5954 (const_int 0))) 5955 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5956 (use (reg:DI 29)) 5957 (clobber (reg:DI 26))] 5958 "HAVE_AS_TLS" 5959 "ldq $27,%1($29)\t\t!literal!%2\;jsr $26,($27),%1\t\t!lituse_<tls>!%2\;ldah $29,0($26)\t\t!gpdisp!%*\;lda $29,0($29)\t\t!gpdisp!%*" 5960 [(set_attr "type" "jsr") 5961 (set_attr "length" "16")]) 5962 5963 ;; We must use peep2 instead of a split because we need accurate life 5964 ;; information for $gp. 5965 (define_peephole2 5966 [(parallel 5967 [(set (match_operand 0) 5968 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5969 (const_int 0))) 5970 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 5971 (use (reg:DI 29)) 5972 (clobber (reg:DI 26))])] 5973 "HAVE_AS_TLS && reload_completed 5974 && peep2_regno_dead_p (1, 29)" 5975 [(set (match_dup 3) 5976 (unspec:DI [(match_dup 5) 5977 (match_dup 1) 5978 (match_dup 2)] UNSPEC_LITERAL)) 5979 (parallel [(set (match_dup 0) 5980 (call (mem:DI (match_dup 3)) 5981 (const_int 0))) 5982 (use (match_dup 5)) 5983 (use (match_dup 1)) 5984 (use (unspec [(match_dup 2)] TLS_CALL)) 5985 (clobber (reg:DI 26))]) 5986 (set (match_dup 5) 5987 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 5988 { 5989 operands[3] = gen_rtx_REG (Pmode, 27); 5990 operands[4] = GEN_INT (alpha_next_sequence_number++); 5991 operands[5] = pic_offset_table_rtx; 5992 }) 5993 5994 (define_peephole2 5995 [(parallel 5996 [(set (match_operand 0) 5997 (call (mem:DI (match_operand:DI 1 "symbolic_operand")) 5998 (const_int 0))) 5999 (unspec [(match_operand:DI 2 "const_int_operand")] TLS_CALL) 6000 (use (reg:DI 29)) 6001 (clobber (reg:DI 26))])] 6002 "HAVE_AS_TLS && reload_completed 6003 && !peep2_regno_dead_p (1, 29)" 6004 [(set (match_dup 3) 6005 (unspec:DI [(match_dup 5) 6006 (match_dup 1) 6007 (match_dup 2)] UNSPEC_LITERAL)) 6008 (parallel [(set (match_dup 0) 6009 (call (mem:DI (match_dup 3)) 6010 (const_int 0))) 6011 (set (match_dup 5) 6012 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP1)) 6013 (use (match_dup 1)) 6014 (use (unspec [(match_dup 2)] TLS_CALL)) 6015 (clobber (reg:DI 26))]) 6016 (set (match_dup 5) 6017 (unspec:DI [(match_dup 5) (match_dup 4)] UNSPEC_LDGP2))] 6018 { 6019 operands[3] = gen_rtx_REG (Pmode, 27); 6020 operands[4] = GEN_INT (alpha_next_sequence_number++); 6021 operands[5] = pic_offset_table_rtx; 6022 }) 6023 6024 (define_insn "*call_value_osf_1" 6025 [(set (match_operand 0) 6026 (call (mem:DI (match_operand:DI 1 "call_operand" "c,R,s")) 6027 (match_operand 2))) 6028 (use (reg:DI 29)) 6029 (clobber (reg:DI 26))] 6030 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6031 "@ 6032 jsr $26,($27),0\;ldgp $29,0($26) 6033 bsr $26,$%1..ng 6034 jsr $26,%1\;ldgp $29,0($26)" 6035 [(set_attr "type" "jsr") 6036 (set_attr "length" "12,*,16")]) 6037 6038 (define_insn "*sibcall_value_osf_1_er" 6039 [(set (match_operand 0) 6040 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6041 (match_operand 2))) 6042 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6043 "TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6044 "@ 6045 br $31,%1\t\t!samegp 6046 ldq $27,%1($29)\t\t!literal!%#\;jmp $31,($27),%1\t\t!lituse_jsr!%#" 6047 [(set_attr "type" "jsr") 6048 (set_attr "length" "*,8")]) 6049 6050 (define_insn "*sibcall_value_osf_1" 6051 [(set (match_operand 0) 6052 (call (mem:DI (match_operand:DI 1 "symbolic_operand" "R,s")) 6053 (match_operand 2))) 6054 (unspec [(reg:DI 29)] UNSPEC_SIBCALL)] 6055 "! TARGET_EXPLICIT_RELOCS && TARGET_ABI_OSF" 6056 "@ 6057 br $31,$%1..ng 6058 lda $27,%1\;jmp $31,($27),%1" 6059 [(set_attr "type" "jsr") 6060 (set_attr "length" "*,8")]) 6061 6062 ; GAS relies on the order and position of instructions output below in order 6063 ; to generate relocs for VMS link to potentially optimize the call. 6064 ; Please do not molest. 6065 (define_insn "*call_value_vms_1" 6066 [(set (match_operand 0) 6067 (call (mem:DI (match_operand:DI 1 "call_operand" "r,s")) 6068 (match_operand 2))) 6069 (use (match_operand:DI 3 "nonmemory_operand" "r,n")) 6070 (use (reg:DI 25)) 6071 (use (reg:DI 26)) 6072 (clobber (reg:DI 27))] 6073 "TARGET_ABI_OPEN_VMS" 6074 { 6075 switch (which_alternative) 6076 { 6077 case 0: 6078 return "mov %3,$27\;jsr $26,0\;ldq $27,0($29)"; 6079 case 1: 6080 operands [3] = alpha_use_linkage (operands [1], true, false); 6081 operands [4] = alpha_use_linkage (operands [1], false, false); 6082 return "ldq $26,%4\;ldq $27,%3\;jsr $26,%1\;ldq $27,0($29)"; 6083 default: 6084 gcc_unreachable (); 6085 } 6086 } 6087 [(set_attr "type" "jsr") 6088 (set_attr "length" "12,16")]) 6089
Indexes created Thu Sep 10 00:26:39 UTC 2026