arm-cpus.in revision 1.1.1.3
1 1.1 mrg # CPU, FPU and architecture specifications for ARM. 2 1.1 mrg # 3 1.1.1.3 mrg # Copyright (C) 2011-2019 Free Software Foundation, Inc. 4 1.1 mrg # 5 1.1 mrg # This file is part of GCC. 6 1.1 mrg # 7 1.1 mrg # GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg # the terms of the GNU General Public License as published by the Free 9 1.1 mrg # Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg # version. 11 1.1 mrg # 12 1.1 mrg # GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg # WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg # FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg # for more details. 16 1.1 mrg # 17 1.1 mrg # You should have received a copy of the GNU General Public License 18 1.1 mrg # along with GCC; see the file COPYING3. If not see 19 1.1 mrg # <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg # This file describes all the various CPUs, FPUs and architectures supported 22 1.1 mrg # by the compiler. It is pre-processed by parsecpu.awk for a number of 23 1.1 mrg # purposes. 24 1.1 mrg # 25 1.1 mrg # The general form is a sequence of begin..end blocks with the following 26 1.1 mrg # syntax: 27 1.1 mrg # begin <object-type> <name> 28 1.1 mrg # attribute-statement* 29 1.1 mrg # end <object-type> <name> 30 1.1 mrg # 31 1.1 mrg # where object type is one of "cpu" "arch" "fpu". Each object type has 32 1.1 mrg # a specific set of permitted attributes, some of which are optional; further 33 1.1 mrg # details can be found below. 34 1.1 mrg # 35 1.1 mrg # Some objects cross-reference other objects by name. Objects are permitted 36 1.1 mrg # in any order and it is not necessary to place a cross-referenced object 37 1.1 mrg # earlier in the file. 38 1.1 mrg # 39 1.1 mrg # The object names for cpu, arch and fpu objects are used for the public option 40 1.1 mrg # names in the final compiler. The order within each group is preserved and 41 1.1 mrg # forms the order for the list within the compiler. 42 1.1 mrg 43 1.1.1.2 mrg # Most objects in this file support forward references. The major 44 1.1.1.2 mrg # exception is feature groups, which may only refer to previously 45 1.1.1.2 mrg # defined features or feature groups. This is done to avoid the risk 46 1.1.1.2 mrg # of feature groups recursively referencing each other and causing 47 1.1.1.2 mrg # the parser to hang. 48 1.1.1.2 mrg 49 1.1.1.2 mrg # Features - general convention: all lower case. 50 1.1.1.2 mrg 51 1.1.1.2 mrg # Architecture rel 4 52 1.1.1.2 mrg define feature armv4 53 1.1.1.2 mrg 54 1.1.1.2 mrg # Thumb aware. 55 1.1.1.2 mrg define feature thumb 56 1.1.1.2 mrg 57 1.1.1.3 mrg # Architecture rel 5t. 58 1.1.1.3 mrg define feature armv5t 59 1.1.1.3 mrg 60 1.1.1.3 mrg # Architecture rel 5te. 61 1.1.1.3 mrg define feature armv5te 62 1.1.1.2 mrg 63 1.1.1.2 mrg # XScale. 64 1.1.1.2 mrg define feature xscale 65 1.1.1.2 mrg 66 1.1.1.2 mrg # Architecture rel 6. 67 1.1.1.2 mrg define feature armv6 68 1.1.1.2 mrg 69 1.1.1.2 mrg # Architecture rel 6k. 70 1.1.1.2 mrg define feature armv6k 71 1.1.1.2 mrg 72 1.1.1.2 mrg # Thumb-2. 73 1.1.1.2 mrg define feature thumb2 74 1.1.1.2 mrg 75 1.1.1.2 mrg # Instructions not present in 'M' profile. 76 1.1.1.2 mrg define feature notm 77 1.1.1.2 mrg 78 1.1.1.2 mrg # Architecture uses be8 mode in big-endian. 79 1.1.1.2 mrg define feature be8 80 1.1.1.2 mrg 81 1.1.1.2 mrg # Thumb division instructions. 82 1.1.1.2 mrg define feature tdiv 83 1.1.1.2 mrg 84 1.1.1.2 mrg # Architecture rel 7e-m. 85 1.1.1.2 mrg define feature armv7em 86 1.1.1.2 mrg 87 1.1.1.2 mrg # Architecture rel 7. 88 1.1.1.2 mrg define feature armv7 89 1.1.1.2 mrg 90 1.1.1.2 mrg # MP extension to ArmV7-A 91 1.1.1.2 mrg define feature mp 92 1.1.1.2 mrg 93 1.1.1.2 mrg # SEC extension to ArmV7-A 94 1.1.1.2 mrg define feature sec 95 1.1.1.2 mrg 96 1.1.1.2 mrg # ARM division instructions. 97 1.1.1.2 mrg define feature adiv 98 1.1.1.2 mrg 99 1.1.1.2 mrg # Architecture rel 8. 100 1.1.1.2 mrg define feature armv8 101 1.1.1.2 mrg 102 1.1.1.2 mrg # ARMv8 CRC32 instructions. 103 1.1.1.2 mrg define feature crc32 104 1.1.1.2 mrg 105 1.1.1.2 mrg # XScale v2 (Wireless MMX). 106 1.1.1.2 mrg define feature iwmmxt 107 1.1.1.2 mrg 108 1.1.1.2 mrg # XScale Wireless MMX2. 109 1.1.1.2 mrg define feature iwmmxt2 110 1.1.1.2 mrg 111 1.1.1.2 mrg # Architecture rel 8.1. 112 1.1.1.2 mrg define feature armv8_1 113 1.1.1.2 mrg 114 1.1.1.2 mrg # Architecture rel 8.2. 115 1.1.1.2 mrg define feature armv8_2 116 1.1.1.2 mrg 117 1.1.1.2 mrg # Architecture rel 8.3. 118 1.1.1.2 mrg define feature armv8_3 119 1.1.1.2 mrg 120 1.1.1.2 mrg # Architecture rel 8.4. 121 1.1.1.2 mrg define feature armv8_4 122 1.1.1.2 mrg 123 1.1.1.3 mrg # Architecture rel 8.5. 124 1.1.1.3 mrg define feature armv8_5 125 1.1.1.3 mrg 126 1.1.1.2 mrg # M-Profile security extensions. 127 1.1.1.2 mrg define feature cmse 128 1.1.1.2 mrg 129 1.1.1.2 mrg # Floating point and Neon extensions. 130 1.1.1.2 mrg # VFPv1 is not supported in GCC. 131 1.1.1.2 mrg 132 1.1.1.2 mrg # Vector floating point v2. 133 1.1.1.2 mrg define feature vfpv2 134 1.1.1.2 mrg 135 1.1.1.2 mrg # Vector floating point v3. 136 1.1.1.2 mrg define feature vfpv3 137 1.1.1.2 mrg 138 1.1.1.2 mrg # Vector floating point v4. 139 1.1.1.2 mrg define feature vfpv4 140 1.1.1.2 mrg 141 1.1.1.2 mrg # Floating point v5. 142 1.1.1.2 mrg define feature fpv5 143 1.1.1.2 mrg 144 1.1.1.2 mrg # ARMv7-A LPAE. 145 1.1.1.2 mrg define feature lpae 146 1.1.1.2 mrg 147 1.1.1.2 mrg # Advanced SIMD instructions. 148 1.1.1.2 mrg define feature neon 149 1.1.1.2 mrg 150 1.1.1.2 mrg # Conversions to/from fp16 (VFPv3 extension). 151 1.1.1.2 mrg define feature fp16conv 152 1.1.1.2 mrg 153 1.1.1.2 mrg # Double precision operations supported. 154 1.1.1.2 mrg define feature fp_dbl 155 1.1.1.2 mrg 156 1.1.1.2 mrg # 32 Double precision registers. 157 1.1.1.2 mrg define feature fp_d32 158 1.1.1.2 mrg 159 1.1.1.2 mrg # Crypto extension to ARMv8. 160 1.1.1.2 mrg define feature crypto 161 1.1.1.2 mrg 162 1.1.1.2 mrg # FP16 data processing (half-precision float). 163 1.1.1.2 mrg define feature fp16 164 1.1.1.2 mrg 165 1.1.1.2 mrg # Dot Product instructions extension to ARMv8.2-a. 166 1.1.1.2 mrg define feature dotprod 167 1.1.1.2 mrg 168 1.1.1.2 mrg # Half-precision floating-point instructions in ARMv8.4-A. 169 1.1.1.2 mrg define feature fp16fml 170 1.1.1.2 mrg 171 1.1.1.2 mrg # ISA Quirks (errata?). Don't forget to add this to the fgroup 172 1.1.1.2 mrg # ALL_QUIRKS below. 173 1.1.1.2 mrg 174 1.1.1.2 mrg # No volatile memory in IT blocks. 175 1.1.1.2 mrg define feature quirk_no_volatile_ce 176 1.1.1.2 mrg 177 1.1.1.2 mrg # Previously mis-identified by GCC. 178 1.1.1.2 mrg define feature quirk_armv6kz 179 1.1.1.2 mrg 180 1.1.1.2 mrg # Cortex-M3 LDRD quirk. 181 1.1.1.2 mrg define feature quirk_cm3_ldrd 182 1.1.1.2 mrg 183 1.1.1.2 mrg # (Very) slow multiply operations. Should probably be a tuning bit. 184 1.1.1.2 mrg define feature smallmul 185 1.1.1.2 mrg 186 1.1.1.3 mrg # Speculation Barrier Instruction for v8-A architectures, added by 187 1.1.1.3 mrg # default to v8.5-A 188 1.1.1.3 mrg define feature sb 189 1.1.1.3 mrg 190 1.1.1.3 mrg # Execution and Data Prediction Restriction Instruction for 191 1.1.1.3 mrg # v8-A architectures, added by default from v8.5-A 192 1.1.1.3 mrg define feature predres 193 1.1.1.3 mrg 194 1.1.1.2 mrg # Feature groups. Conventionally all (or mostly) upper case. 195 1.1.1.2 mrg # ALL_FPU lists all the feature bits associated with the floating-point 196 1.1.1.2 mrg # unit; these will all be removed if the floating-point unit is disabled 197 1.1.1.2 mrg # (eg -mfloat-abi=soft). ALL_FPU_INTERNAL must ONLY contain features that 198 1.1.1.2 mrg # form part of a named -mfpu option; it is used to map the capabilities 199 1.1.1.2 mrg # back to a named FPU for the benefit of the assembler. 200 1.1.1.2 mrg # 201 1.1.1.2 mrg # ALL_SIMD_INTERNAL and ALL_SIMD are similarly defined to help with the 202 1.1.1.2 mrg # construction of ALL_FPU and ALL_FPU_INTERNAL; they describe the SIMD 203 1.1.1.2 mrg # extensions that are either part of a named FPU or optional extensions 204 1.1.1.2 mrg # respectively. 205 1.1.1.2 mrg 206 1.1.1.2 mrg 207 1.1.1.2 mrg # List of all cryptographic extensions to stripout if crypto is 208 1.1.1.2 mrg # disabled. Currently, that's trivial, but we define it anyway for 209 1.1.1.2 mrg # consistency with the SIMD and FP disable lists. 210 1.1.1.2 mrg define fgroup ALL_CRYPTO crypto 211 1.1.1.2 mrg 212 1.1.1.2 mrg # List of all SIMD bits to strip out if SIMD is disabled. This does 213 1.1.1.2 mrg # strip off 32 D-registers, but does not remove support for 214 1.1.1.2 mrg # double-precision FP. 215 1.1.1.2 mrg define fgroup ALL_SIMD_INTERNAL fp_d32 neon ALL_CRYPTO 216 1.1.1.2 mrg define fgroup ALL_SIMD ALL_SIMD_INTERNAL dotprod fp16fml 217 1.1.1.2 mrg 218 1.1.1.2 mrg # List of all FPU bits to strip out if -mfpu is used to override the 219 1.1.1.2 mrg # default. fp16 is deliberately missing from this list. 220 1.1.1.2 mrg define fgroup ALL_FPU_INTERNAL vfpv2 vfpv3 vfpv4 fpv5 fp16conv fp_dbl ALL_SIMD_INTERNAL 221 1.1.1.2 mrg 222 1.1.1.2 mrg # Similarly, but including fp16 and other extensions that aren't part of 223 1.1.1.2 mrg # -mfpu support. 224 1.1.1.2 mrg define fgroup ALL_FP fp16 ALL_FPU_INTERNAL 225 1.1.1.2 mrg 226 1.1.1.3 mrg define fgroup ARMv4 armv4 notm 227 1.1.1.2 mrg define fgroup ARMv4t ARMv4 thumb 228 1.1.1.3 mrg define fgroup ARMv5t ARMv4t armv5t 229 1.1.1.3 mrg define fgroup ARMv5te ARMv5t armv5te 230 1.1.1.2 mrg define fgroup ARMv5tej ARMv5te 231 1.1.1.2 mrg define fgroup ARMv6 ARMv5te armv6 be8 232 1.1.1.2 mrg define fgroup ARMv6j ARMv6 233 1.1.1.2 mrg define fgroup ARMv6k ARMv6 armv6k 234 1.1.1.2 mrg define fgroup ARMv6z ARMv6 235 1.1.1.2 mrg define fgroup ARMv6kz ARMv6k quirk_armv6kz 236 1.1.1.2 mrg define fgroup ARMv6zk ARMv6k 237 1.1.1.2 mrg define fgroup ARMv6t2 ARMv6 thumb2 238 1.1.1.2 mrg # This is suspect. ARMv6-m doesn't really pull in any useful features 239 1.1.1.2 mrg # from ARMv5* or ARMv6. 240 1.1.1.3 mrg define fgroup ARMv6m armv4 thumb armv5t armv5te armv6 be8 241 1.1.1.2 mrg # This is suspect, the 'common' ARMv7 subset excludes the thumb2 'DSP' and 242 1.1.1.2 mrg # integer SIMD instructions that are in ARMv6T2. */ 243 1.1.1.2 mrg define fgroup ARMv7 ARMv6m thumb2 armv7 244 1.1.1.2 mrg 245 1.1.1.2 mrg define fgroup ARMv7a ARMv7 notm armv6k 246 1.1.1.2 mrg define fgroup ARMv7ve ARMv7a adiv tdiv lpae mp sec 247 1.1.1.2 mrg define fgroup ARMv7r ARMv7a tdiv 248 1.1.1.2 mrg define fgroup ARMv7m ARMv7 tdiv 249 1.1.1.2 mrg define fgroup ARMv7em ARMv7m armv7em 250 1.1.1.2 mrg define fgroup ARMv8a ARMv7ve armv8 251 1.1.1.2 mrg define fgroup ARMv8_1a ARMv8a crc32 armv8_1 252 1.1.1.2 mrg define fgroup ARMv8_2a ARMv8_1a armv8_2 253 1.1.1.2 mrg define fgroup ARMv8_3a ARMv8_2a armv8_3 254 1.1.1.2 mrg define fgroup ARMv8_4a ARMv8_3a armv8_4 255 1.1.1.3 mrg define fgroup ARMv8_5a ARMv8_4a armv8_5 sb predres 256 1.1.1.2 mrg define fgroup ARMv8m_base ARMv6m armv8 cmse tdiv 257 1.1.1.2 mrg define fgroup ARMv8m_main ARMv7m armv8 cmse 258 1.1.1.2 mrg define fgroup ARMv8r ARMv8a 259 1.1.1.2 mrg 260 1.1.1.2 mrg # Useful combinations. 261 1.1.1.2 mrg define fgroup VFPv2 vfpv2 262 1.1.1.2 mrg define fgroup VFPv3 VFPv2 vfpv3 263 1.1.1.2 mrg define fgroup VFPv4 VFPv3 vfpv4 fp16conv 264 1.1.1.2 mrg define fgroup FPv5 VFPv4 fpv5 265 1.1.1.2 mrg 266 1.1.1.2 mrg define fgroup FP_DBL fp_dbl 267 1.1.1.2 mrg define fgroup FP_D32 FP_DBL fp_d32 268 1.1.1.2 mrg define fgroup FP_ARMv8 FPv5 FP_D32 269 1.1.1.2 mrg define fgroup NEON FP_D32 neon 270 1.1.1.2 mrg define fgroup CRYPTO NEON crypto 271 1.1.1.2 mrg define fgroup DOTPROD NEON dotprod 272 1.1.1.2 mrg 273 1.1.1.2 mrg # List of all quirk bits to strip out when comparing CPU features with 274 1.1.1.2 mrg # architectures. 275 1.1.1.2 mrg # xscale isn't really a 'quirk', but it isn't an architecture either and we 276 1.1.1.2 mrg # need to ignore it for matching purposes. 277 1.1.1.2 mrg define fgroup ALL_QUIRKS quirk_no_volatile_ce quirk_armv6kz quirk_cm3_ldrd xscale 278 1.1.1.2 mrg 279 1.1 mrg # Architecture entries 280 1.1 mrg # format: 281 1.1 mrg # begin arch <name> 282 1.1 mrg # tune for <cpu> 283 1.1 mrg # [tune flags <list>] 284 1.1 mrg # base <name> 285 1.1.1.2 mrg # [profile <A|R|M>] 286 1.1 mrg # isa <isa-flags-list> 287 1.1 mrg # end arch <name> 288 1.1 mrg # 289 1.1 mrg 290 1.1 mrg begin arch armv4 291 1.1 mrg tune for arm7tdmi 292 1.1 mrg tune flags CO_PROC 293 1.1 mrg base 4 294 1.1.1.3 mrg isa ARMv4 295 1.1 mrg end arch armv4 296 1.1 mrg 297 1.1 mrg begin arch armv4t 298 1.1 mrg tune for arm7tdmi 299 1.1 mrg tune flags CO_PROC 300 1.1 mrg base 4T 301 1.1 mrg isa ARMv4t 302 1.1 mrg end arch armv4t 303 1.1 mrg 304 1.1 mrg begin arch armv5t 305 1.1 mrg tune for arm10tdmi 306 1.1 mrg tune flags CO_PROC 307 1.1 mrg base 5T 308 1.1 mrg isa ARMv5t 309 1.1 mrg end arch armv5t 310 1.1 mrg 311 1.1 mrg begin arch armv5te 312 1.1 mrg tune for arm1026ej-s 313 1.1 mrg tune flags CO_PROC 314 1.1 mrg base 5TE 315 1.1 mrg isa ARMv5te 316 1.1.1.2 mrg option fp add VFPv2 FP_DBL 317 1.1.1.2 mrg optalias vfpv2 fp 318 1.1.1.2 mrg option nofp remove ALL_FP 319 1.1 mrg end arch armv5te 320 1.1 mrg 321 1.1 mrg begin arch armv5tej 322 1.1 mrg tune for arm1026ej-s 323 1.1 mrg tune flags CO_PROC 324 1.1 mrg base 5TEJ 325 1.1 mrg isa ARMv5tej 326 1.1.1.2 mrg option fp add VFPv2 FP_DBL 327 1.1.1.2 mrg optalias vfpv2 fp 328 1.1.1.2 mrg option nofp remove ALL_FP 329 1.1 mrg end arch armv5tej 330 1.1 mrg 331 1.1 mrg begin arch armv6 332 1.1 mrg tune for arm1136j-s 333 1.1 mrg tune flags CO_PROC 334 1.1 mrg base 6 335 1.1 mrg isa ARMv6 336 1.1.1.2 mrg option fp add VFPv2 FP_DBL 337 1.1.1.2 mrg optalias vfpv2 fp 338 1.1.1.2 mrg option nofp remove ALL_FP 339 1.1 mrg end arch armv6 340 1.1 mrg 341 1.1 mrg begin arch armv6j 342 1.1 mrg tune for arm1136j-s 343 1.1 mrg tune flags CO_PROC 344 1.1 mrg base 6J 345 1.1 mrg isa ARMv6j 346 1.1.1.2 mrg option fp add VFPv2 FP_DBL 347 1.1.1.2 mrg optalias vfpv2 fp 348 1.1.1.2 mrg option nofp remove ALL_FP 349 1.1 mrg end arch armv6j 350 1.1 mrg 351 1.1 mrg begin arch armv6k 352 1.1 mrg tune for mpcore 353 1.1 mrg tune flags CO_PROC 354 1.1 mrg base 6K 355 1.1 mrg isa ARMv6k 356 1.1.1.2 mrg option fp add VFPv2 FP_DBL 357 1.1.1.2 mrg optalias vfpv2 fp 358 1.1.1.2 mrg option nofp remove ALL_FP 359 1.1 mrg end arch armv6k 360 1.1 mrg 361 1.1 mrg begin arch armv6z 362 1.1 mrg tune for arm1176jz-s 363 1.1 mrg tune flags CO_PROC 364 1.1 mrg base 6Z 365 1.1 mrg isa ARMv6z 366 1.1.1.2 mrg option fp add VFPv2 FP_DBL 367 1.1.1.2 mrg optalias vfpv2 fp 368 1.1.1.2 mrg option nofp remove ALL_FP 369 1.1 mrg end arch armv6z 370 1.1 mrg 371 1.1 mrg begin arch armv6kz 372 1.1 mrg tune for arm1176jz-s 373 1.1 mrg tune flags CO_PROC 374 1.1 mrg base 6KZ 375 1.1 mrg isa ARMv6kz 376 1.1.1.2 mrg option fp add VFPv2 FP_DBL 377 1.1.1.2 mrg optalias vfpv2 fp 378 1.1.1.2 mrg option nofp remove ALL_FP 379 1.1 mrg end arch armv6kz 380 1.1 mrg 381 1.1 mrg begin arch armv6zk 382 1.1 mrg tune for arm1176jz-s 383 1.1 mrg tune flags CO_PROC 384 1.1 mrg base 6KZ 385 1.1 mrg isa ARMv6kz 386 1.1.1.2 mrg option fp add VFPv2 FP_DBL 387 1.1.1.2 mrg optalias vfpv2 fp 388 1.1.1.2 mrg option nofp remove ALL_FP 389 1.1 mrg end arch armv6zk 390 1.1 mrg 391 1.1 mrg begin arch armv6t2 392 1.1 mrg tune for arm1156t2-s 393 1.1 mrg tune flags CO_PROC 394 1.1 mrg base 6T2 395 1.1 mrg isa ARMv6t2 396 1.1.1.2 mrg option fp add VFPv2 FP_DBL 397 1.1.1.2 mrg optalias vfpv2 fp 398 1.1.1.2 mrg option nofp remove ALL_FP 399 1.1 mrg end arch armv6t2 400 1.1 mrg 401 1.1 mrg begin arch armv6-m 402 1.1 mrg tune for cortex-m1 403 1.1 mrg base 6M 404 1.1.1.2 mrg profile M 405 1.1 mrg isa ARMv6m 406 1.1 mrg end arch armv6-m 407 1.1 mrg 408 1.1.1.2 mrg # This is now equivalent to armv6-m, but we keep it because some 409 1.1.1.2 mrg # versions of GAS still distinguish between the two. 410 1.1 mrg begin arch armv6s-m 411 1.1 mrg tune for cortex-m1 412 1.1 mrg base 6M 413 1.1.1.2 mrg profile M 414 1.1 mrg isa ARMv6m 415 1.1 mrg end arch armv6s-m 416 1.1 mrg 417 1.1 mrg begin arch armv7 418 1.1 mrg tune for cortex-a8 419 1.1 mrg tune flags CO_PROC 420 1.1 mrg base 7 421 1.1 mrg isa ARMv7 422 1.1.1.2 mrg # fp => VFPv3-d16 (only useful for the A+R profile subset). 423 1.1.1.2 mrg option fp add VFPv3 FP_DBL 424 1.1.1.2 mrg optalias vfpv3-d16 fp 425 1.1.1.2 mrg option nofp remove ALL_FP 426 1.1 mrg end arch armv7 427 1.1 mrg 428 1.1 mrg begin arch armv7-a 429 1.1 mrg tune for cortex-a8 430 1.1 mrg tune flags CO_PROC 431 1.1 mrg base 7A 432 1.1.1.2 mrg profile A 433 1.1 mrg isa ARMv7a 434 1.1.1.2 mrg option mp add mp 435 1.1.1.2 mrg option sec add sec 436 1.1.1.2 mrg # fp => VFPv3-d16, simd => neon-vfpv3 437 1.1.1.2 mrg option fp add VFPv3 FP_DBL 438 1.1.1.2 mrg optalias vfpv3-d16 fp 439 1.1.1.2 mrg option vfpv3 add VFPv3 FP_D32 440 1.1.1.2 mrg option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 441 1.1.1.2 mrg option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 fp16conv 442 1.1.1.2 mrg option vfpv4-d16 add VFPv4 FP_DBL 443 1.1.1.2 mrg option vfpv4 add VFPv4 FP_D32 444 1.1.1.2 mrg option simd add VFPv3 NEON 445 1.1.1.2 mrg optalias neon simd 446 1.1.1.2 mrg optalias neon-vfpv3 simd 447 1.1.1.2 mrg option neon-fp16 add VFPv3 NEON fp16conv 448 1.1.1.2 mrg option neon-vfpv4 add VFPv4 NEON 449 1.1.1.2 mrg option nosimd remove ALL_SIMD 450 1.1.1.2 mrg option nofp remove ALL_FP 451 1.1 mrg end arch armv7-a 452 1.1 mrg 453 1.1 mrg begin arch armv7ve 454 1.1 mrg tune for cortex-a8 455 1.1 mrg tune flags CO_PROC 456 1.1 mrg base 7A 457 1.1.1.2 mrg profile A 458 1.1 mrg isa ARMv7ve 459 1.1.1.2 mrg # fp => VFPv4-d16, simd => neon-vfpv4 460 1.1.1.2 mrg option vfpv3-d16 add VFPv3 FP_DBL 461 1.1.1.2 mrg option vfpv3 add VFPv3 FP_D32 462 1.1.1.2 mrg option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 463 1.1.1.2 mrg option vfpv3-fp16 add VFPv3 FP_DBL FP_D32 fp16conv 464 1.1.1.2 mrg option fp add VFPv4 FP_DBL 465 1.1.1.2 mrg optalias vfpv4-d16 fp 466 1.1.1.2 mrg option vfpv4 add VFPv4 FP_D32 467 1.1.1.2 mrg option neon add VFPv3 NEON 468 1.1.1.2 mrg optalias neon-vfpv3 neon 469 1.1.1.2 mrg option neon-fp16 add VFPv3 NEON fp16conv 470 1.1.1.2 mrg option simd add VFPv4 NEON 471 1.1.1.2 mrg optalias neon-vfpv4 simd 472 1.1.1.2 mrg option nosimd remove ALL_SIMD 473 1.1.1.2 mrg option nofp remove ALL_FP 474 1.1 mrg end arch armv7ve 475 1.1 mrg 476 1.1 mrg begin arch armv7-r 477 1.1 mrg tune for cortex-r4 478 1.1 mrg tune flags CO_PROC 479 1.1 mrg base 7R 480 1.1.1.2 mrg profile R 481 1.1 mrg isa ARMv7r 482 1.1.1.2 mrg # ARMv7-r uses VFPv3-d16 483 1.1.1.2 mrg option fp.sp add VFPv3 484 1.1.1.2 mrg optalias vfpv3xd fp.sp 485 1.1.1.2 mrg option fp add VFPv3 FP_DBL 486 1.1.1.2 mrg optalias vfpv3-d16 fp 487 1.1.1.2 mrg option vfpv3xd-fp16 add VFPv3 fp16conv 488 1.1.1.2 mrg option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 489 1.1.1.2 mrg option idiv add adiv 490 1.1.1.2 mrg option nofp remove ALL_FP 491 1.1.1.2 mrg option noidiv remove adiv 492 1.1 mrg end arch armv7-r 493 1.1 mrg 494 1.1 mrg begin arch armv7-m 495 1.1 mrg tune for cortex-m3 496 1.1 mrg tune flags CO_PROC 497 1.1 mrg base 7M 498 1.1.1.2 mrg profile M 499 1.1 mrg isa ARMv7m 500 1.1.1.2 mrg # In theory FP is permitted in v7-m, but in practice no implementations exist. 501 1.1.1.2 mrg # leave it out for now. 502 1.1 mrg end arch armv7-m 503 1.1 mrg 504 1.1 mrg begin arch armv7e-m 505 1.1 mrg tune for cortex-m4 506 1.1 mrg tune flags CO_PROC 507 1.1 mrg base 7EM 508 1.1.1.2 mrg profile M 509 1.1 mrg isa ARMv7em 510 1.1.1.2 mrg # fp => VFPv4-sp-d16; fpv5 => FPv5-sp-d16; fp.dp => FPv5-d16 511 1.1.1.2 mrg option fp add VFPv4 512 1.1.1.2 mrg optalias vfpv4-sp-d16 fp 513 1.1.1.2 mrg option fpv5 add FPv5 514 1.1.1.2 mrg option fp.dp add FPv5 FP_DBL 515 1.1.1.2 mrg optalias fpv5-d16 fp.dp 516 1.1.1.2 mrg option nofp remove ALL_FP 517 1.1 mrg end arch armv7e-m 518 1.1 mrg 519 1.1 mrg begin arch armv8-a 520 1.1 mrg tune for cortex-a53 521 1.1 mrg tune flags CO_PROC 522 1.1 mrg base 8A 523 1.1.1.2 mrg profile A 524 1.1 mrg isa ARMv8a 525 1.1.1.2 mrg option crc add crc32 526 1.1.1.2 mrg option simd add FP_ARMv8 NEON 527 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 528 1.1.1.2 mrg option nocrypto remove ALL_CRYPTO 529 1.1.1.2 mrg option nofp remove ALL_FP 530 1.1.1.3 mrg option sb add sb 531 1.1.1.3 mrg option predres add predres 532 1.1 mrg end arch armv8-a 533 1.1 mrg 534 1.1 mrg begin arch armv8.1-a 535 1.1 mrg tune for cortex-a53 536 1.1 mrg tune flags CO_PROC 537 1.1 mrg base 8A 538 1.1.1.2 mrg profile A 539 1.1 mrg isa ARMv8_1a 540 1.1.1.2 mrg option simd add FP_ARMv8 NEON 541 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 542 1.1.1.2 mrg option nocrypto remove ALL_CRYPTO 543 1.1.1.2 mrg option nofp remove ALL_FP 544 1.1.1.3 mrg option sb add sb 545 1.1.1.3 mrg option predres add predres 546 1.1 mrg end arch armv8.1-a 547 1.1 mrg 548 1.1 mrg begin arch armv8.2-a 549 1.1 mrg tune for cortex-a53 550 1.1 mrg tune flags CO_PROC 551 1.1 mrg base 8A 552 1.1.1.2 mrg profile A 553 1.1 mrg isa ARMv8_2a 554 1.1.1.2 mrg option simd add FP_ARMv8 NEON 555 1.1.1.2 mrg option fp16 add fp16 FP_ARMv8 NEON 556 1.1.1.2 mrg option fp16fml add fp16fml fp16 FP_ARMv8 NEON 557 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 558 1.1.1.2 mrg option nocrypto remove ALL_CRYPTO 559 1.1.1.2 mrg option nofp remove ALL_FP 560 1.1.1.2 mrg option dotprod add FP_ARMv8 DOTPROD 561 1.1.1.3 mrg option sb add sb 562 1.1.1.3 mrg option predres add predres 563 1.1 mrg end arch armv8.2-a 564 1.1 mrg 565 1.1.1.2 mrg begin arch armv8.3-a 566 1.1.1.2 mrg tune for cortex-a53 567 1.1.1.2 mrg tune flags CO_PROC 568 1.1.1.2 mrg base 8A 569 1.1.1.2 mrg profile A 570 1.1.1.2 mrg isa ARMv8_3a 571 1.1.1.2 mrg option simd add FP_ARMv8 NEON 572 1.1.1.2 mrg option fp16 add fp16 FP_ARMv8 NEON 573 1.1.1.2 mrg option fp16fml add fp16fml fp16 FP_ARMv8 NEON 574 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 575 1.1.1.2 mrg option nocrypto remove ALL_CRYPTO 576 1.1.1.2 mrg option nofp remove ALL_FP 577 1.1.1.2 mrg option dotprod add FP_ARMv8 DOTPROD 578 1.1.1.3 mrg option sb add sb 579 1.1.1.3 mrg option predres add predres 580 1.1.1.2 mrg end arch armv8.3-a 581 1.1.1.2 mrg 582 1.1.1.2 mrg begin arch armv8.4-a 583 1.1 mrg tune for cortex-a53 584 1.1 mrg tune flags CO_PROC 585 1.1 mrg base 8A 586 1.1.1.2 mrg profile A 587 1.1.1.2 mrg isa ARMv8_4a 588 1.1.1.2 mrg option simd add FP_ARMv8 DOTPROD 589 1.1.1.2 mrg option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 590 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO DOTPROD 591 1.1.1.2 mrg option nocrypto remove ALL_CRYPTO 592 1.1.1.2 mrg option nofp remove ALL_FP 593 1.1.1.3 mrg option sb add sb 594 1.1.1.3 mrg option predres add predres 595 1.1.1.2 mrg end arch armv8.4-a 596 1.1 mrg 597 1.1.1.3 mrg begin arch armv8.5-a 598 1.1.1.3 mrg tune for cortex-a53 599 1.1.1.3 mrg tune flags CO_PROC 600 1.1.1.3 mrg base 8A 601 1.1.1.3 mrg profile A 602 1.1.1.3 mrg isa ARMv8_5a 603 1.1.1.3 mrg option simd add FP_ARMv8 DOTPROD 604 1.1.1.3 mrg option fp16 add fp16 fp16fml FP_ARMv8 DOTPROD 605 1.1.1.3 mrg option crypto add FP_ARMv8 CRYPTO DOTPROD 606 1.1.1.3 mrg option nocrypto remove ALL_CRYPTO 607 1.1.1.3 mrg option nofp remove ALL_FP 608 1.1.1.3 mrg end arch armv8.5-a 609 1.1.1.3 mrg 610 1.1 mrg begin arch armv8-m.base 611 1.1 mrg tune for cortex-m23 612 1.1 mrg base 8M_BASE 613 1.1.1.2 mrg profile M 614 1.1 mrg isa ARMv8m_base 615 1.1 mrg end arch armv8-m.base 616 1.1 mrg 617 1.1 mrg begin arch armv8-m.main 618 1.1 mrg tune for cortex-m7 619 1.1 mrg tune flags CO_PROC 620 1.1 mrg base 8M_MAIN 621 1.1.1.2 mrg profile M 622 1.1 mrg isa ARMv8m_main 623 1.1.1.2 mrg option dsp add armv7em 624 1.1.1.2 mrg # fp => FPv5-sp-d16; fp.dp => FPv5-d16 625 1.1.1.2 mrg option fp add FPv5 626 1.1.1.2 mrg option fp.dp add FPv5 FP_DBL 627 1.1.1.2 mrg option nofp remove ALL_FP 628 1.1.1.2 mrg option nodsp remove armv7em 629 1.1 mrg end arch armv8-m.main 630 1.1 mrg 631 1.1.1.2 mrg begin arch armv8-r 632 1.1.1.2 mrg tune for cortex-r52 633 1.1 mrg tune flags CO_PROC 634 1.1.1.2 mrg base 8R 635 1.1.1.2 mrg profile R 636 1.1.1.2 mrg isa ARMv8r 637 1.1.1.2 mrg option crc add crc32 638 1.1.1.2 mrg # fp.sp => fp-armv8 (d16); simd => simd + fp-armv8 + d32 + double precision 639 1.1.1.2 mrg # note: no fp option for fp-armv8 (d16) + double precision at the moment 640 1.1.1.2 mrg option fp.sp add FPv5 641 1.1.1.2 mrg option simd add FP_ARMv8 NEON 642 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 643 1.1.1.2 mrg option nocrypto remove ALL_CRYPTO 644 1.1.1.2 mrg option nofp remove ALL_FP 645 1.1.1.2 mrg end arch armv8-r 646 1.1 mrg 647 1.1 mrg begin arch iwmmxt 648 1.1 mrg tune for iwmmxt 649 1.1 mrg tune flags LDSCHED STRONG XSCALE 650 1.1 mrg base 5TE 651 1.1.1.2 mrg isa ARMv5te xscale iwmmxt 652 1.1 mrg end arch iwmmxt 653 1.1 mrg 654 1.1 mrg begin arch iwmmxt2 655 1.1 mrg tune for iwmmxt2 656 1.1 mrg tune flags LDSCHED STRONG XSCALE 657 1.1 mrg base 5TE 658 1.1.1.2 mrg isa ARMv5te xscale iwmmxt iwmmxt2 659 1.1 mrg end arch iwmmxt2 660 1.1 mrg 661 1.1 mrg # CPU entries 662 1.1 mrg # format: 663 1.1 mrg # begin cpu <name> 664 1.1 mrg # [cname <c-compatible-name>] 665 1.1.1.3 mrg # [alias <name>+] 666 1.1 mrg # [tune for <cpu-name>] 667 1.1 mrg # [tune flags <list>] 668 1.1 mrg # architecture <name> 669 1.1 mrg # [isa <additional-isa-flags-list>] 670 1.1.1.2 mrg # [option <name> add|remove <isa-list>]* 671 1.1.1.2 mrg # [optalias <name> <optname>]* 672 1.1 mrg # [costs <name>] 673 1.1.1.3 mrg # [vendor <vendor-id> 674 1.1.1.3 mrg # [part <part-id> [minrev [maxrev]]] 675 1.1 mrg # end cpu <name> 676 1.1 mrg # 677 1.1 mrg # If omitted, cname is formed from transforming the cpuname to convert 678 1.1 mrg # non-valid punctuation characters to '_'. 679 1.1.1.3 mrg # Any number of alias names may be specified for a CPU. If the name starts 680 1.1.1.3 mrg # with a '!' then it will be recognized as a valid name, but will not 681 1.1.1.3 mrg # be printed in any help text listing permitted CPUs. 682 1.1 mrg # If specified, tune for specifies a CPU target to use for tuning this core. 683 1.1 mrg # isa flags are appended to those defined by the architecture. 684 1.1.1.2 mrg # Each add option must have a distinct feature set and each remove 685 1.1.1.2 mrg # option must similarly have a distinct feature set. Option aliases can be 686 1.1.1.3 mrg # added with the optalias statement. 687 1.1.1.3 mrg # Vendor, part and revision information is used for native CPU and architecture 688 1.1.1.3 mrg # detection. All values must be in hex (lower case) with the leading '0x' 689 1.1.1.3 mrg # omitted. For example the cortex-a9 will have vendor 41 and part c09. 690 1.1.1.3 mrg # Revision information is used to match a subrange of part 691 1.1.1.3 mrg # revisions: minrev <= detected <= maxrev. 692 1.1.1.3 mrg # If a minrev or maxrev are omitted then minrev defaults to zero and maxrev 693 1.1.1.3 mrg # to infinity. 694 1.1.1.3 mrg # Revision information is not implemented yet; no part uses it. 695 1.1 mrg 696 1.1 mrg # V4 Architecture Processors 697 1.1 mrg begin cpu arm8 698 1.1 mrg tune flags LDSCHED 699 1.1 mrg architecture armv4 700 1.1 mrg costs fastmul 701 1.1 mrg end cpu arm8 702 1.1 mrg 703 1.1 mrg begin cpu arm810 704 1.1 mrg tune flags LDSCHED 705 1.1 mrg architecture armv4 706 1.1 mrg costs fastmul 707 1.1 mrg end cpu arm810 708 1.1 mrg 709 1.1 mrg begin cpu strongarm 710 1.1.1.3 mrg alias strongarm110 !strongarm1100 !strongarm1110 711 1.1 mrg tune flags LDSCHED STRONG 712 1.1 mrg architecture armv4 713 1.1 mrg costs strongarm 714 1.1 mrg end cpu strongarm 715 1.1 mrg 716 1.1 mrg begin cpu fa526 717 1.1 mrg tune flags LDSCHED 718 1.1 mrg architecture armv4 719 1.1 mrg costs fastmul 720 1.1 mrg end cpu fa526 721 1.1 mrg 722 1.1 mrg begin cpu fa626 723 1.1 mrg tune flags LDSCHED 724 1.1 mrg architecture armv4 725 1.1 mrg costs fastmul 726 1.1 mrg end cpu fa626 727 1.1 mrg 728 1.1 mrg 729 1.1 mrg # V4T Architecture Processors 730 1.1 mrg begin cpu arm7tdmi 731 1.1.1.3 mrg alias arm7tdmi-s 732 1.1 mrg tune flags CO_PROC 733 1.1 mrg architecture armv4t 734 1.1 mrg costs fastmul 735 1.1 mrg end cpu arm7tdmi 736 1.1 mrg 737 1.1 mrg begin cpu arm710t 738 1.1.1.3 mrg alias arm720t arm740t 739 1.1 mrg tune flags WBUF 740 1.1 mrg architecture armv4t 741 1.1 mrg costs fastmul 742 1.1 mrg end cpu arm710t 743 1.1 mrg 744 1.1 mrg begin cpu arm9 745 1.1 mrg tune flags LDSCHED 746 1.1 mrg architecture armv4t 747 1.1 mrg costs fastmul 748 1.1 mrg end cpu arm9 749 1.1 mrg 750 1.1 mrg begin cpu arm9tdmi 751 1.1 mrg tune flags LDSCHED 752 1.1 mrg architecture armv4t 753 1.1 mrg costs fastmul 754 1.1 mrg end cpu arm9tdmi 755 1.1 mrg 756 1.1 mrg begin cpu arm920t 757 1.1.1.3 mrg alias arm920 arm922t arm940t ep9312 758 1.1 mrg tune flags LDSCHED 759 1.1 mrg architecture armv4t 760 1.1 mrg costs fastmul 761 1.1 mrg end cpu arm920t 762 1.1 mrg 763 1.1 mrg 764 1.1 mrg # V5T Architecture Processors 765 1.1.1.2 mrg # These used VFPv1 which isn't supported by GCC 766 1.1 mrg begin cpu arm10tdmi 767 1.1.1.3 mrg alias arm1020t 768 1.1 mrg tune flags LDSCHED 769 1.1 mrg architecture armv5t 770 1.1 mrg costs fastmul 771 1.1 mrg end cpu arm10tdmi 772 1.1 mrg 773 1.1 mrg 774 1.1 mrg # V5TE Architecture Processors 775 1.1 mrg begin cpu arm9e 776 1.1.1.3 mrg alias arm946e-s arm966e-s arm968e-s 777 1.1 mrg tune flags LDSCHED 778 1.1.1.3 mrg architecture armv5te+fp 779 1.1.1.2 mrg option nofp remove ALL_FP 780 1.1 mrg costs 9e 781 1.1 mrg end cpu arm9e 782 1.1 mrg 783 1.1 mrg begin cpu arm10e 784 1.1.1.3 mrg alias arm1020e arm1022e 785 1.1 mrg tune flags LDSCHED 786 1.1.1.3 mrg architecture armv5te+fp 787 1.1.1.2 mrg option nofp remove ALL_FP 788 1.1 mrg costs fastmul 789 1.1 mrg end cpu arm10e 790 1.1 mrg 791 1.1 mrg begin cpu xscale 792 1.1 mrg tune flags LDSCHED XSCALE 793 1.1 mrg architecture armv5te 794 1.1.1.2 mrg isa xscale 795 1.1 mrg costs xscale 796 1.1 mrg end cpu xscale 797 1.1 mrg 798 1.1 mrg begin cpu iwmmxt 799 1.1 mrg tune flags LDSCHED XSCALE 800 1.1 mrg architecture iwmmxt 801 1.1 mrg costs xscale 802 1.1 mrg end cpu iwmmxt 803 1.1 mrg 804 1.1 mrg begin cpu iwmmxt2 805 1.1 mrg tune flags LDSCHED XSCALE 806 1.1 mrg architecture iwmmxt2 807 1.1 mrg costs xscale 808 1.1 mrg end cpu iwmmxt2 809 1.1 mrg 810 1.1 mrg begin cpu fa606te 811 1.1 mrg tune flags LDSCHED 812 1.1 mrg architecture armv5te 813 1.1 mrg costs 9e 814 1.1 mrg end cpu fa606te 815 1.1 mrg 816 1.1 mrg begin cpu fa626te 817 1.1 mrg tune flags LDSCHED 818 1.1 mrg architecture armv5te 819 1.1 mrg costs 9e 820 1.1 mrg end cpu fa626te 821 1.1 mrg 822 1.1 mrg begin cpu fmp626 823 1.1 mrg tune flags LDSCHED 824 1.1 mrg architecture armv5te 825 1.1 mrg costs 9e 826 1.1 mrg end cpu fmp626 827 1.1 mrg 828 1.1 mrg begin cpu fa726te 829 1.1 mrg tune flags LDSCHED 830 1.1 mrg architecture armv5te 831 1.1 mrg costs fa726te 832 1.1 mrg end cpu fa726te 833 1.1 mrg 834 1.1 mrg 835 1.1 mrg # V5TEJ Architecture Processors 836 1.1 mrg begin cpu arm926ej-s 837 1.1 mrg cname arm926ejs 838 1.1 mrg tune flags LDSCHED 839 1.1.1.3 mrg architecture armv5tej+fp 840 1.1.1.2 mrg option nofp remove ALL_FP 841 1.1 mrg costs 9e 842 1.1.1.3 mrg vendor 41 843 1.1.1.3 mrg part 926 844 1.1 mrg end cpu arm926ej-s 845 1.1 mrg 846 1.1 mrg begin cpu arm1026ej-s 847 1.1 mrg cname arm1026ejs 848 1.1 mrg tune flags LDSCHED 849 1.1.1.3 mrg architecture armv5tej+fp 850 1.1.1.2 mrg option nofp remove ALL_FP 851 1.1 mrg costs 9e 852 1.1.1.3 mrg vendor 41 853 1.1.1.3 mrg part a26 854 1.1 mrg end cpu arm1026ej-s 855 1.1 mrg 856 1.1 mrg 857 1.1 mrg # V6 Architecture Processors 858 1.1 mrg begin cpu arm1136j-s 859 1.1 mrg cname arm1136js 860 1.1 mrg tune flags LDSCHED 861 1.1 mrg architecture armv6j 862 1.1 mrg costs 9e 863 1.1 mrg end cpu arm1136j-s 864 1.1 mrg 865 1.1 mrg begin cpu arm1136jf-s 866 1.1 mrg cname arm1136jfs 867 1.1 mrg tune flags LDSCHED 868 1.1.1.3 mrg architecture armv6j+fp 869 1.1 mrg costs 9e 870 1.1.1.3 mrg vendor 41 871 1.1.1.3 mrg part b36 872 1.1 mrg end cpu arm1136jf-s 873 1.1 mrg 874 1.1 mrg begin cpu arm1176jz-s 875 1.1 mrg cname arm1176jzs 876 1.1 mrg tune flags LDSCHED 877 1.1 mrg architecture armv6kz 878 1.1 mrg costs 9e 879 1.1 mrg end cpu arm1176jz-s 880 1.1 mrg 881 1.1 mrg begin cpu arm1176jzf-s 882 1.1 mrg cname arm1176jzfs 883 1.1 mrg tune flags LDSCHED 884 1.1.1.3 mrg architecture armv6kz+fp 885 1.1 mrg costs 9e 886 1.1.1.3 mrg vendor 41 887 1.1.1.3 mrg part b76 888 1.1 mrg end cpu arm1176jzf-s 889 1.1 mrg 890 1.1 mrg begin cpu mpcorenovfp 891 1.1 mrg tune flags LDSCHED 892 1.1 mrg architecture armv6k 893 1.1 mrg costs 9e 894 1.1 mrg end cpu mpcorenovfp 895 1.1 mrg 896 1.1 mrg begin cpu mpcore 897 1.1 mrg tune flags LDSCHED 898 1.1.1.3 mrg architecture armv6k+fp 899 1.1 mrg costs 9e 900 1.1.1.3 mrg vendor 41 901 1.1.1.3 mrg part b02 902 1.1 mrg end cpu mpcore 903 1.1 mrg 904 1.1 mrg begin cpu arm1156t2-s 905 1.1 mrg cname arm1156t2s 906 1.1 mrg tune flags LDSCHED 907 1.1 mrg architecture armv6t2 908 1.1 mrg costs v6t2 909 1.1 mrg end cpu arm1156t2-s 910 1.1 mrg 911 1.1 mrg begin cpu arm1156t2f-s 912 1.1 mrg cname arm1156t2fs 913 1.1 mrg tune flags LDSCHED 914 1.1.1.3 mrg architecture armv6t2+fp 915 1.1 mrg costs v6t2 916 1.1.1.3 mrg vendor 41 917 1.1.1.3 mrg part b56 918 1.1 mrg end cpu arm1156t2f-s 919 1.1 mrg 920 1.1 mrg 921 1.1 mrg # V6M Architecture Processors 922 1.1 mrg begin cpu cortex-m1 923 1.1 mrg cname cortexm1 924 1.1 mrg tune flags LDSCHED 925 1.1.1.2 mrg architecture armv6s-m 926 1.1 mrg costs v6m 927 1.1.1.3 mrg vendor 41 928 1.1.1.3 mrg part c21 929 1.1 mrg end cpu cortex-m1 930 1.1 mrg 931 1.1 mrg begin cpu cortex-m0 932 1.1 mrg cname cortexm0 933 1.1 mrg tune flags LDSCHED 934 1.1.1.2 mrg architecture armv6s-m 935 1.1 mrg costs v6m 936 1.1.1.3 mrg vendor 41 937 1.1.1.3 mrg part c20 938 1.1 mrg end cpu cortex-m0 939 1.1 mrg 940 1.1 mrg begin cpu cortex-m0plus 941 1.1 mrg cname cortexm0plus 942 1.1 mrg tune flags LDSCHED 943 1.1.1.2 mrg architecture armv6s-m 944 1.1 mrg costs v6m 945 1.1 mrg end cpu cortex-m0plus 946 1.1 mrg 947 1.1 mrg 948 1.1 mrg # V6M Architecture Processors for small-multiply implementations. 949 1.1 mrg begin cpu cortex-m1.small-multiply 950 1.1 mrg cname cortexm1smallmultiply 951 1.1 mrg tune for cortex-m1 952 1.1 mrg tune flags LDSCHED SMALLMUL 953 1.1.1.2 mrg architecture armv6s-m 954 1.1 mrg costs v6m 955 1.1 mrg end cpu cortex-m1.small-multiply 956 1.1 mrg 957 1.1 mrg begin cpu cortex-m0.small-multiply 958 1.1 mrg cname cortexm0smallmultiply 959 1.1 mrg tune for cortex-m0 960 1.1 mrg tune flags LDSCHED SMALLMUL 961 1.1.1.2 mrg architecture armv6s-m 962 1.1 mrg costs v6m 963 1.1 mrg end cpu cortex-m0.small-multiply 964 1.1 mrg 965 1.1 mrg begin cpu cortex-m0plus.small-multiply 966 1.1 mrg cname cortexm0plussmallmultiply 967 1.1 mrg tune for cortex-m0plus 968 1.1 mrg tune flags LDSCHED SMALLMUL 969 1.1.1.2 mrg architecture armv6s-m 970 1.1 mrg costs v6m 971 1.1 mrg end cpu cortex-m0plus.small-multiply 972 1.1 mrg 973 1.1 mrg 974 1.1 mrg # V7 Architecture Processors 975 1.1 mrg begin cpu generic-armv7-a 976 1.1 mrg cname genericv7a 977 1.1 mrg tune flags LDSCHED 978 1.1.1.3 mrg architecture armv7-a+fp 979 1.1.1.2 mrg option mp add mp 980 1.1.1.2 mrg option sec add sec 981 1.1.1.2 mrg option vfpv3-d16 add VFPv3 FP_DBL 982 1.1.1.2 mrg option vfpv3 add VFPv3 FP_D32 983 1.1.1.2 mrg option vfpv3-d16-fp16 add VFPv3 FP_DBL fp16conv 984 1.1.1.2 mrg option vfpv3-fp16 add VFPv3 FP_D32 fp16conv 985 1.1.1.2 mrg option vfpv4-d16 add VFPv4 FP_DBL 986 1.1.1.2 mrg option vfpv4 add VFPv4 FP_D32 987 1.1.1.2 mrg option simd add VFPv3 NEON 988 1.1.1.2 mrg optalias neon simd 989 1.1.1.2 mrg optalias neon-vfpv3 simd 990 1.1.1.2 mrg option neon-fp16 add VFPv3 NEON fp16conv 991 1.1.1.2 mrg option neon-vfpv4 add VFPv4 NEON 992 1.1.1.2 mrg option nosimd remove ALL_SIMD 993 1.1.1.2 mrg option nofp remove ALL_FP 994 1.1 mrg costs cortex 995 1.1 mrg end cpu generic-armv7-a 996 1.1 mrg 997 1.1 mrg begin cpu cortex-a5 998 1.1 mrg cname cortexa5 999 1.1 mrg tune flags LDSCHED 1000 1.1.1.3 mrg architecture armv7-a+mp+sec+neon-fp16 1001 1.1.1.2 mrg option nosimd remove ALL_SIMD 1002 1.1.1.2 mrg option nofp remove ALL_FP 1003 1.1 mrg costs cortex_a5 1004 1.1.1.3 mrg vendor 41 1005 1.1.1.3 mrg part c05 1006 1.1 mrg end cpu cortex-a5 1007 1.1 mrg 1008 1.1 mrg begin cpu cortex-a7 1009 1.1 mrg cname cortexa7 1010 1.1 mrg tune flags LDSCHED 1011 1.1.1.3 mrg architecture armv7ve+simd 1012 1.1.1.2 mrg option nosimd remove ALL_SIMD 1013 1.1.1.2 mrg option nofp remove ALL_FP 1014 1.1 mrg costs cortex_a7 1015 1.1.1.3 mrg vendor 41 1016 1.1.1.3 mrg part c07 1017 1.1 mrg end cpu cortex-a7 1018 1.1 mrg 1019 1.1 mrg begin cpu cortex-a8 1020 1.1 mrg cname cortexa8 1021 1.1 mrg tune flags LDSCHED 1022 1.1.1.3 mrg architecture armv7-a+sec+simd 1023 1.1.1.2 mrg option nofp remove ALL_FP 1024 1.1 mrg costs cortex_a8 1025 1.1.1.3 mrg vendor 41 1026 1.1.1.3 mrg part c08 1027 1.1 mrg end cpu cortex-a8 1028 1.1 mrg 1029 1.1 mrg begin cpu cortex-a9 1030 1.1 mrg cname cortexa9 1031 1.1 mrg tune flags LDSCHED 1032 1.1.1.3 mrg architecture armv7-a+mp+sec+neon-fp16 1033 1.1.1.2 mrg option nosimd remove ALL_SIMD 1034 1.1.1.2 mrg option nofp remove ALL_FP 1035 1.1 mrg costs cortex_a9 1036 1.1.1.3 mrg vendor 41 1037 1.1.1.3 mrg part c09 1038 1.1 mrg end cpu cortex-a9 1039 1.1 mrg 1040 1.1 mrg begin cpu cortex-a12 1041 1.1 mrg cname cortexa12 1042 1.1 mrg tune for cortex-a17 1043 1.1 mrg tune flags LDSCHED 1044 1.1.1.3 mrg architecture armv7ve+simd 1045 1.1.1.2 mrg option nofp remove ALL_FP 1046 1.1 mrg costs cortex_a12 1047 1.1.1.3 mrg vendor 41 1048 1.1.1.3 mrg part c0d 1049 1.1 mrg end cpu cortex-a12 1050 1.1 mrg 1051 1.1 mrg begin cpu cortex-a15 1052 1.1 mrg cname cortexa15 1053 1.1 mrg tune flags LDSCHED 1054 1.1.1.3 mrg architecture armv7ve+simd 1055 1.1.1.2 mrg option nofp remove ALL_FP 1056 1.1 mrg costs cortex_a15 1057 1.1.1.3 mrg vendor 41 1058 1.1.1.3 mrg part c0f 1059 1.1 mrg end cpu cortex-a15 1060 1.1 mrg 1061 1.1 mrg begin cpu cortex-a17 1062 1.1 mrg cname cortexa17 1063 1.1 mrg tune flags LDSCHED 1064 1.1.1.3 mrg architecture armv7ve+simd 1065 1.1.1.2 mrg option nofp remove ALL_FP 1066 1.1 mrg costs cortex_a12 1067 1.1.1.3 mrg vendor 41 1068 1.1.1.3 mrg part c0e 1069 1.1 mrg end cpu cortex-a17 1070 1.1 mrg 1071 1.1 mrg begin cpu cortex-r4 1072 1.1 mrg cname cortexr4 1073 1.1 mrg tune flags LDSCHED 1074 1.1 mrg architecture armv7-r 1075 1.1 mrg costs cortex 1076 1.1 mrg end cpu cortex-r4 1077 1.1 mrg 1078 1.1 mrg begin cpu cortex-r4f 1079 1.1 mrg cname cortexr4f 1080 1.1 mrg tune flags LDSCHED 1081 1.1.1.3 mrg architecture armv7-r+fp 1082 1.1 mrg costs cortex 1083 1.1.1.3 mrg vendor 41 1084 1.1.1.3 mrg part c14 1085 1.1 mrg end cpu cortex-r4f 1086 1.1 mrg 1087 1.1 mrg begin cpu cortex-r5 1088 1.1 mrg cname cortexr5 1089 1.1 mrg tune flags LDSCHED 1090 1.1.1.3 mrg architecture armv7-r+idiv+fp 1091 1.1.1.2 mrg option nofp.dp remove FP_DBL 1092 1.1.1.2 mrg option nofp remove ALL_FP 1093 1.1 mrg costs cortex 1094 1.1.1.3 mrg vendor 41 1095 1.1.1.3 mrg part c15 1096 1.1 mrg end cpu cortex-r5 1097 1.1 mrg 1098 1.1 mrg begin cpu cortex-r7 1099 1.1 mrg cname cortexr7 1100 1.1 mrg tune flags LDSCHED 1101 1.1.1.3 mrg architecture armv7-r+idiv+vfpv3-d16-fp16 1102 1.1.1.2 mrg option nofp.dp remove FP_DBL 1103 1.1.1.2 mrg option nofp remove ALL_FP 1104 1.1 mrg costs cortex 1105 1.1.1.3 mrg vendor 41 1106 1.1.1.3 mrg part c17 1107 1.1 mrg end cpu cortex-r7 1108 1.1 mrg 1109 1.1 mrg begin cpu cortex-r8 1110 1.1 mrg cname cortexr8 1111 1.1 mrg tune for cortex-r7 1112 1.1 mrg tune flags LDSCHED 1113 1.1.1.3 mrg architecture armv7-r+idiv+vfpv3-d16-fp16 1114 1.1.1.2 mrg option nofp.dp remove FP_DBL 1115 1.1.1.2 mrg option nofp remove ALL_FP 1116 1.1 mrg costs cortex 1117 1.1.1.3 mrg vendor 41 1118 1.1.1.3 mrg part c18 1119 1.1 mrg end cpu cortex-r8 1120 1.1 mrg 1121 1.1 mrg begin cpu cortex-m7 1122 1.1 mrg cname cortexm7 1123 1.1 mrg tune flags LDSCHED 1124 1.1.1.3 mrg architecture armv7e-m+fp.dp 1125 1.1 mrg isa quirk_no_volatile_ce 1126 1.1.1.2 mrg option nofp.dp remove FP_DBL 1127 1.1.1.2 mrg option nofp remove ALL_FP 1128 1.1 mrg costs cortex_m7 1129 1.1 mrg end cpu cortex-m7 1130 1.1 mrg 1131 1.1 mrg begin cpu cortex-m4 1132 1.1 mrg cname cortexm4 1133 1.1 mrg tune flags LDSCHED 1134 1.1.1.3 mrg architecture armv7e-m+fp 1135 1.1.1.2 mrg option nofp remove ALL_FP 1136 1.1 mrg costs v7m 1137 1.1.1.3 mrg vendor 41 1138 1.1.1.3 mrg part c24 1139 1.1 mrg end cpu cortex-m4 1140 1.1 mrg 1141 1.1 mrg begin cpu cortex-m3 1142 1.1 mrg cname cortexm3 1143 1.1 mrg tune flags LDSCHED 1144 1.1 mrg architecture armv7-m 1145 1.1 mrg isa quirk_cm3_ldrd 1146 1.1 mrg costs v7m 1147 1.1.1.3 mrg vendor 41 1148 1.1.1.3 mrg part c23 1149 1.1 mrg end cpu cortex-m3 1150 1.1 mrg 1151 1.1 mrg begin cpu marvell-pj4 1152 1.1 mrg tune flags LDSCHED 1153 1.1.1.2 mrg architecture armv7-a+mp+sec 1154 1.1 mrg costs marvell_pj4 1155 1.1 mrg end cpu marvell-pj4 1156 1.1 mrg 1157 1.1 mrg 1158 1.1 mrg # V7 big.LITTLE implementations 1159 1.1 mrg begin cpu cortex-a15.cortex-a7 1160 1.1 mrg cname cortexa15cortexa7 1161 1.1 mrg tune for cortex-a7 1162 1.1 mrg tune flags LDSCHED 1163 1.1.1.3 mrg architecture armv7ve+simd 1164 1.1.1.2 mrg option nofp remove ALL_FP 1165 1.1 mrg costs cortex_a15 1166 1.1 mrg end cpu cortex-a15.cortex-a7 1167 1.1 mrg 1168 1.1 mrg begin cpu cortex-a17.cortex-a7 1169 1.1 mrg cname cortexa17cortexa7 1170 1.1 mrg tune for cortex-a7 1171 1.1 mrg tune flags LDSCHED 1172 1.1.1.3 mrg architecture armv7ve+simd 1173 1.1.1.2 mrg option nofp remove ALL_FP 1174 1.1 mrg costs cortex_a12 1175 1.1 mrg end cpu cortex-a17.cortex-a7 1176 1.1 mrg 1177 1.1 mrg 1178 1.1 mrg # V8 A-profile Architecture Processors 1179 1.1 mrg begin cpu cortex-a32 1180 1.1 mrg cname cortexa32 1181 1.1 mrg tune for cortex-a53 1182 1.1 mrg tune flags LDSCHED 1183 1.1.1.3 mrg architecture armv8-a+crc+simd 1184 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1185 1.1.1.2 mrg option nofp remove ALL_FP 1186 1.1 mrg costs cortex_a35 1187 1.1.1.3 mrg vendor 41 1188 1.1.1.3 mrg part d01 1189 1.1 mrg end cpu cortex-a32 1190 1.1 mrg 1191 1.1 mrg begin cpu cortex-a35 1192 1.1 mrg cname cortexa35 1193 1.1 mrg tune for cortex-a53 1194 1.1 mrg tune flags LDSCHED 1195 1.1.1.3 mrg architecture armv8-a+crc+simd 1196 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1197 1.1.1.2 mrg option nofp remove ALL_FP 1198 1.1 mrg costs cortex_a35 1199 1.1.1.3 mrg vendor 41 1200 1.1.1.3 mrg part d04 1201 1.1 mrg end cpu cortex-a35 1202 1.1 mrg 1203 1.1 mrg begin cpu cortex-a53 1204 1.1 mrg cname cortexa53 1205 1.1 mrg tune flags LDSCHED 1206 1.1.1.3 mrg architecture armv8-a+crc+simd 1207 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1208 1.1.1.2 mrg option nofp remove ALL_FP 1209 1.1 mrg costs cortex_a53 1210 1.1.1.3 mrg vendor 41 1211 1.1.1.3 mrg part d03 1212 1.1 mrg end cpu cortex-a53 1213 1.1 mrg 1214 1.1 mrg begin cpu cortex-a57 1215 1.1 mrg cname cortexa57 1216 1.1 mrg tune flags LDSCHED 1217 1.1.1.3 mrg architecture armv8-a+crc+simd 1218 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1219 1.1 mrg costs cortex_a57 1220 1.1.1.3 mrg vendor 41 1221 1.1.1.3 mrg part d07 1222 1.1 mrg end cpu cortex-a57 1223 1.1 mrg 1224 1.1 mrg begin cpu cortex-a72 1225 1.1 mrg cname cortexa72 1226 1.1 mrg tune for cortex-a57 1227 1.1 mrg tune flags LDSCHED 1228 1.1.1.3 mrg architecture armv8-a+crc+simd 1229 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1230 1.1 mrg costs cortex_a57 1231 1.1.1.3 mrg vendor 41 1232 1.1.1.3 mrg part d08 1233 1.1 mrg end cpu cortex-a72 1234 1.1 mrg 1235 1.1 mrg begin cpu cortex-a73 1236 1.1 mrg cname cortexa73 1237 1.1 mrg tune for cortex-a57 1238 1.1 mrg tune flags LDSCHED 1239 1.1.1.3 mrg architecture armv8-a+crc+simd 1240 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1241 1.1 mrg costs cortex_a73 1242 1.1.1.3 mrg vendor 41 1243 1.1.1.3 mrg part d09 1244 1.1 mrg end cpu cortex-a73 1245 1.1 mrg 1246 1.1 mrg begin cpu exynos-m1 1247 1.1 mrg cname exynosm1 1248 1.1 mrg tune flags LDSCHED 1249 1.1.1.3 mrg architecture armv8-a+crc+simd 1250 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1251 1.1 mrg costs exynosm1 1252 1.1 mrg end cpu exynos-m1 1253 1.1 mrg 1254 1.1 mrg begin cpu xgene1 1255 1.1 mrg tune flags LDSCHED 1256 1.1.1.3 mrg architecture armv8-a+simd 1257 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1258 1.1 mrg costs xgene1 1259 1.1 mrg end cpu xgene1 1260 1.1 mrg 1261 1.1 mrg # V8 A-profile big.LITTLE implementations 1262 1.1 mrg begin cpu cortex-a57.cortex-a53 1263 1.1 mrg cname cortexa57cortexa53 1264 1.1 mrg tune for cortex-a53 1265 1.1 mrg tune flags LDSCHED 1266 1.1.1.3 mrg architecture armv8-a+crc+simd 1267 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1268 1.1 mrg costs cortex_a57 1269 1.1 mrg end cpu cortex-a57.cortex-a53 1270 1.1 mrg 1271 1.1 mrg begin cpu cortex-a72.cortex-a53 1272 1.1 mrg cname cortexa72cortexa53 1273 1.1 mrg tune for cortex-a53 1274 1.1 mrg tune flags LDSCHED 1275 1.1.1.3 mrg architecture armv8-a+crc+simd 1276 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1277 1.1 mrg costs cortex_a57 1278 1.1 mrg end cpu cortex-a72.cortex-a53 1279 1.1 mrg 1280 1.1 mrg begin cpu cortex-a73.cortex-a35 1281 1.1 mrg cname cortexa73cortexa35 1282 1.1 mrg tune for cortex-a53 1283 1.1 mrg tune flags LDSCHED 1284 1.1.1.3 mrg architecture armv8-a+crc+simd 1285 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1286 1.1 mrg costs cortex_a73 1287 1.1 mrg end cpu cortex-a73.cortex-a35 1288 1.1 mrg 1289 1.1 mrg begin cpu cortex-a73.cortex-a53 1290 1.1 mrg cname cortexa73cortexa53 1291 1.1 mrg tune for cortex-a53 1292 1.1 mrg tune flags LDSCHED 1293 1.1.1.3 mrg architecture armv8-a+crc+simd 1294 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1295 1.1 mrg costs cortex_a73 1296 1.1 mrg end cpu cortex-a73.cortex-a53 1297 1.1 mrg 1298 1.1 mrg 1299 1.1.1.2 mrg # ARMv8.2 A-profile Architecture Processors 1300 1.1.1.2 mrg begin cpu cortex-a55 1301 1.1.1.2 mrg cname cortexa55 1302 1.1.1.2 mrg tune for cortex-a53 1303 1.1.1.2 mrg tune flags LDSCHED 1304 1.1.1.3 mrg architecture armv8.2-a+fp16+dotprod+simd 1305 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1306 1.1.1.2 mrg option nofp remove ALL_FP 1307 1.1.1.2 mrg costs cortex_a53 1308 1.1.1.3 mrg vendor 41 1309 1.1.1.3 mrg part d05 1310 1.1.1.2 mrg end cpu cortex-a55 1311 1.1.1.2 mrg 1312 1.1.1.2 mrg begin cpu cortex-a75 1313 1.1.1.2 mrg cname cortexa75 1314 1.1.1.2 mrg tune for cortex-a57 1315 1.1.1.2 mrg tune flags LDSCHED 1316 1.1.1.3 mrg architecture armv8.2-a+fp16+dotprod+simd 1317 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1318 1.1.1.2 mrg costs cortex_a73 1319 1.1.1.3 mrg vendor 41 1320 1.1.1.3 mrg part d0a 1321 1.1.1.2 mrg end cpu cortex-a75 1322 1.1.1.2 mrg 1323 1.1.1.3 mrg begin cpu cortex-a76 1324 1.1.1.3 mrg cname cortexa76 1325 1.1.1.3 mrg tune for cortex-a57 1326 1.1.1.3 mrg tune flags LDSCHED 1327 1.1.1.3 mrg architecture armv8.2-a+fp16+dotprod+simd 1328 1.1.1.3 mrg option crypto add FP_ARMv8 CRYPTO 1329 1.1.1.3 mrg costs cortex_a57 1330 1.1.1.3 mrg vendor 41 1331 1.1.1.3 mrg part d0b 1332 1.1.1.3 mrg end cpu cortex-a76 1333 1.1.1.3 mrg 1334 1.1.1.3 mrg begin cpu neoverse-n1 1335 1.1.1.3 mrg cname neoversen1 1336 1.1.1.3 mrg alias !ares 1337 1.1.1.3 mrg tune for cortex-a57 1338 1.1.1.3 mrg tune flags LDSCHED 1339 1.1.1.3 mrg architecture armv8.2-a+fp16+dotprod+simd 1340 1.1.1.3 mrg option crypto add FP_ARMv8 CRYPTO 1341 1.1.1.3 mrg costs cortex_a57 1342 1.1.1.3 mrg vendor 41 1343 1.1.1.3 mrg part d0c 1344 1.1.1.3 mrg end cpu neoverse-n1 1345 1.1.1.2 mrg 1346 1.1.1.2 mrg # ARMv8.2 A-profile ARM DynamIQ big.LITTLE implementations 1347 1.1.1.2 mrg begin cpu cortex-a75.cortex-a55 1348 1.1.1.2 mrg cname cortexa75cortexa55 1349 1.1.1.2 mrg tune for cortex-a53 1350 1.1.1.2 mrg tune flags LDSCHED 1351 1.1.1.3 mrg architecture armv8.2-a+fp16+dotprod+simd 1352 1.1.1.2 mrg option crypto add FP_ARMv8 CRYPTO 1353 1.1.1.2 mrg costs cortex_a73 1354 1.1.1.2 mrg end cpu cortex-a75.cortex-a55 1355 1.1.1.2 mrg 1356 1.1.1.3 mrg begin cpu cortex-a76.cortex-a55 1357 1.1.1.3 mrg cname cortexa76cortexa55 1358 1.1.1.3 mrg tune for cortex-a53 1359 1.1.1.3 mrg tune flags LDSCHED 1360 1.1.1.3 mrg architecture armv8.2-a+fp16+dotprod+simd 1361 1.1.1.3 mrg option crypto add FP_ARMv8 CRYPTO 1362 1.1.1.3 mrg costs cortex_a57 1363 1.1.1.3 mrg end cpu cortex-a76.cortex-a55 1364 1.1.1.3 mrg 1365 1.1 mrg # V8 M-profile implementations. 1366 1.1 mrg begin cpu cortex-m23 1367 1.1 mrg cname cortexm23 1368 1.1 mrg tune flags LDSCHED 1369 1.1 mrg architecture armv8-m.base 1370 1.1 mrg costs v6m 1371 1.1 mrg end cpu cortex-m23 1372 1.1 mrg 1373 1.1 mrg begin cpu cortex-m33 1374 1.1 mrg cname cortexm33 1375 1.1 mrg tune flags LDSCHED 1376 1.1.1.3 mrg architecture armv8-m.main+dsp+fp 1377 1.1.1.2 mrg option nofp remove ALL_FP 1378 1.1.1.2 mrg option nodsp remove armv7em 1379 1.1 mrg costs v7m 1380 1.1 mrg end cpu cortex-m33 1381 1.1 mrg 1382 1.1.1.2 mrg # V8 R-profile implementations. 1383 1.1.1.2 mrg begin cpu cortex-r52 1384 1.1.1.2 mrg cname cortexr52 1385 1.1.1.2 mrg tune flags LDSCHED 1386 1.1.1.2 mrg architecture armv8-r+crc+simd 1387 1.1.1.2 mrg option nofp.dp remove FP_DBL ALL_SIMD 1388 1.1.1.2 mrg costs cortex 1389 1.1.1.3 mrg vendor 41 1390 1.1.1.3 mrg part d13 1391 1.1.1.2 mrg end cpu cortex-r52 1392 1.1.1.2 mrg 1393 1.1 mrg # FPU entries 1394 1.1 mrg # format: 1395 1.1 mrg # begin fpu <name> 1396 1.1 mrg # isa <isa-flags-list> 1397 1.1 mrg # end fpu <name> 1398 1.1 mrg 1399 1.1 mrg begin fpu vfp 1400 1.1 mrg isa VFPv2 FP_DBL 1401 1.1 mrg end fpu vfp 1402 1.1 mrg 1403 1.1 mrg begin fpu vfpv2 1404 1.1 mrg isa VFPv2 FP_DBL 1405 1.1 mrg end fpu vfpv2 1406 1.1 mrg 1407 1.1 mrg begin fpu vfpv3 1408 1.1 mrg isa VFPv3 FP_D32 1409 1.1 mrg end fpu vfpv3 1410 1.1 mrg 1411 1.1 mrg begin fpu vfpv3-fp16 1412 1.1.1.2 mrg isa VFPv3 FP_D32 fp16conv 1413 1.1 mrg end fpu vfpv3-fp16 1414 1.1 mrg 1415 1.1 mrg begin fpu vfpv3-d16 1416 1.1 mrg isa VFPv3 FP_DBL 1417 1.1 mrg end fpu vfpv3-d16 1418 1.1 mrg 1419 1.1 mrg begin fpu vfpv3-d16-fp16 1420 1.1.1.2 mrg isa VFPv3 FP_DBL fp16conv 1421 1.1 mrg end fpu vfpv3-d16-fp16 1422 1.1 mrg 1423 1.1 mrg begin fpu vfpv3xd 1424 1.1 mrg isa VFPv3 1425 1.1 mrg end fpu vfpv3xd 1426 1.1 mrg 1427 1.1 mrg begin fpu vfpv3xd-fp16 1428 1.1.1.2 mrg isa VFPv3 fp16conv 1429 1.1 mrg end fpu vfpv3xd-fp16 1430 1.1 mrg 1431 1.1 mrg begin fpu neon 1432 1.1 mrg isa VFPv3 NEON 1433 1.1 mrg end fpu neon 1434 1.1 mrg 1435 1.1 mrg begin fpu neon-vfpv3 1436 1.1 mrg isa VFPv3 NEON 1437 1.1 mrg end fpu neon-vfpv3 1438 1.1 mrg 1439 1.1 mrg begin fpu neon-fp16 1440 1.1.1.2 mrg isa VFPv3 NEON fp16conv 1441 1.1 mrg end fpu neon-fp16 1442 1.1 mrg 1443 1.1 mrg begin fpu vfpv4 1444 1.1 mrg isa VFPv4 FP_D32 1445 1.1 mrg end fpu vfpv4 1446 1.1 mrg 1447 1.1 mrg begin fpu neon-vfpv4 1448 1.1 mrg isa VFPv4 NEON 1449 1.1 mrg end fpu neon-vfpv4 1450 1.1 mrg 1451 1.1 mrg begin fpu vfpv4-d16 1452 1.1 mrg isa VFPv4 FP_DBL 1453 1.1 mrg end fpu vfpv4-d16 1454 1.1 mrg 1455 1.1 mrg begin fpu fpv4-sp-d16 1456 1.1 mrg isa VFPv4 1457 1.1 mrg end fpu fpv4-sp-d16 1458 1.1 mrg 1459 1.1 mrg begin fpu fpv5-sp-d16 1460 1.1 mrg isa FPv5 1461 1.1 mrg end fpu fpv5-sp-d16 1462 1.1 mrg 1463 1.1 mrg begin fpu fpv5-d16 1464 1.1 mrg isa FPv5 FP_DBL 1465 1.1 mrg end fpu fpv5-d16 1466 1.1 mrg 1467 1.1 mrg begin fpu fp-armv8 1468 1.1.1.2 mrg isa FP_ARMv8 1469 1.1 mrg end fpu fp-armv8 1470 1.1 mrg 1471 1.1 mrg begin fpu neon-fp-armv8 1472 1.1 mrg isa FP_ARMv8 NEON 1473 1.1 mrg end fpu neon-fp-armv8 1474 1.1 mrg 1475 1.1 mrg begin fpu crypto-neon-fp-armv8 1476 1.1 mrg isa FP_ARMv8 CRYPTO 1477 1.1 mrg end fpu crypto-neon-fp-armv8 1478 1.1 mrg 1479 1.1 mrg # Compatibility aliases. 1480 1.1 mrg begin fpu vfp3 1481 1.1 mrg isa VFPv3 FP_D32 1482 1.1 mrg end fpu vfp3 1483
Indexes created Sun May 03 00:22:47 UTC 2026