arm.h revision 1.1.1.1
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 6 and Martin Simmons (@harleqn.co.uk). 7 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 8 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 9 10 This file is part of GCC. 11 12 GCC is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published 14 by the Free Software Foundation; either version 3, or (at your 15 option) any later version. 16 17 GCC is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with GCC; see the file COPYING3. If not see 24 <http://www.gnu.org/licenses/>. */ 25 26 #ifndef GCC_ARM_H 27 #define GCC_ARM_H 28 29 /* We can't use enum machine_mode inside a generator file because it 30 hasn't been created yet; we shouldn't be using any code that 31 needs the real definition though, so this ought to be safe. */ 32 #ifdef GENERATOR_FILE 33 #define MACHMODE int 34 #else 35 #include "insn-modes.h" 36 #define MACHMODE enum machine_mode 37 #endif 38 39 #include "config/vxworks-dummy.h" 40 41 /* The architecture define. */ 42 extern char arm_arch_name[]; 43 44 /* Target CPU builtins. */ 45 #define TARGET_CPU_CPP_BUILTINS() \ 46 do \ 47 { \ 48 /* Define __arm__ even when in thumb mode, for \ 49 consistency with armcc. */ \ 50 builtin_define ("__arm__"); \ 51 builtin_define ("__APCS_32__"); \ 52 if (TARGET_THUMB) \ 53 builtin_define ("__thumb__"); \ 54 if (TARGET_THUMB2) \ 55 builtin_define ("__thumb2__"); \ 56 \ 57 if (TARGET_BIG_END) \ 58 { \ 59 builtin_define ("__ARMEB__"); \ 60 if (TARGET_THUMB) \ 61 builtin_define ("__THUMBEB__"); \ 62 if (TARGET_LITTLE_WORDS) \ 63 builtin_define ("__ARMWEL__"); \ 64 } \ 65 else \ 66 { \ 67 builtin_define ("__ARMEL__"); \ 68 if (TARGET_THUMB) \ 69 builtin_define ("__THUMBEL__"); \ 70 } \ 71 \ 72 if (TARGET_SOFT_FLOAT) \ 73 builtin_define ("__SOFTFP__"); \ 74 \ 75 if (TARGET_VFP) \ 76 builtin_define ("__VFP_FP__"); \ 77 \ 78 if (TARGET_NEON) \ 79 builtin_define ("__ARM_NEON__"); \ 80 \ 81 /* Add a define for interworking. \ 82 Needed when building libgcc.a. */ \ 83 if (arm_cpp_interwork) \ 84 builtin_define ("__THUMB_INTERWORK__"); \ 85 \ 86 builtin_assert ("cpu=arm"); \ 87 builtin_assert ("machine=arm"); \ 88 \ 89 builtin_define (arm_arch_name); \ 90 if (arm_arch_cirrus) \ 91 builtin_define ("__MAVERICK__"); \ 92 if (arm_arch_xscale) \ 93 builtin_define ("__XSCALE__"); \ 94 if (arm_arch_iwmmxt) \ 95 builtin_define ("__IWMMXT__"); \ 96 if (TARGET_AAPCS_BASED) \ 97 { \ 98 builtin_define ("__ARM_EABI__"); \ 99 builtin_define ("__ARM_PCS"); \ 100 if (TARGET_HARD_FLOAT && TARGET_VFP) \ 101 builtin_define ("__ARM_PCS_VFP"); \ 102 } \ 103 if (TARGET_IDIV) \ 104 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 105 } while (0) 106 107 /* The various ARM cores. */ 108 enum processor_type 109 { 110 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 111 IDENT, 112 #include "arm-cores.def" 113 #undef ARM_CORE 114 /* Used to indicate that no processor has been specified. */ 115 arm_none 116 }; 117 118 enum target_cpus 119 { 120 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 121 TARGET_CPU_##IDENT, 122 #include "arm-cores.def" 123 #undef ARM_CORE 124 TARGET_CPU_generic 125 }; 126 127 /* The processor for which instructions should be scheduled. */ 128 extern enum processor_type arm_tune; 129 130 typedef enum arm_cond_code 131 { 132 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 133 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 134 } 135 arm_cc; 136 137 extern arm_cc arm_current_cc; 138 139 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 140 141 extern int arm_target_label; 142 extern int arm_ccfsm_state; 143 extern GTY(()) rtx arm_target_insn; 144 /* The label of the current constant pool. */ 145 extern rtx pool_vector_label; 146 /* Set to 1 when a return insn is output, this means that the epilogue 147 is not needed. */ 148 extern int return_used_this_function; 149 /* Callback to output language specific object attributes. */ 150 extern void (*arm_lang_output_object_attributes_hook)(void); 151 152 /* Just in case configure has failed to define anything. */ 154 #ifndef TARGET_CPU_DEFAULT 155 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 156 #endif 157 158 159 #undef CPP_SPEC 160 #define CPP_SPEC "%(subtarget_cpp_spec) \ 161 %{msoft-float:%{mhard-float: \ 162 %e-msoft-float and -mhard_float may not be used together}} \ 163 %{mbig-endian:%{mlittle-endian: \ 164 %e-mbig-endian and -mlittle-endian may not be used together}}" 165 166 #ifndef CC1_SPEC 167 #define CC1_SPEC "" 168 #endif 169 170 /* This macro defines names of additional specifications to put in the specs 171 that can be used in various specifications like CC1_SPEC. Its definition 172 is an initializer with a subgrouping for each command option. 173 174 Each subgrouping contains a string constant, that defines the 175 specification name, and a string constant that used by the GCC driver 176 program. 177 178 Do not define this macro if it does not need to do anything. */ 179 #define EXTRA_SPECS \ 180 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 181 SUBTARGET_EXTRA_SPECS 182 183 #ifndef SUBTARGET_EXTRA_SPECS 184 #define SUBTARGET_EXTRA_SPECS 185 #endif 186 187 #ifndef SUBTARGET_CPP_SPEC 188 #define SUBTARGET_CPP_SPEC "" 189 #endif 190 191 /* Run-time Target Specification. */ 193 #ifndef TARGET_VERSION 194 #define TARGET_VERSION fputs (" (ARM/generic)", stderr); 195 #endif 196 197 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 198 /* Use hardware floating point instructions. */ 199 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 200 /* Use hardware floating point calling convention. */ 201 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 202 #define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA) 203 #define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) 204 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 205 #define TARGET_IWMMXT (arm_arch_iwmmxt) 206 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 207 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 208 #define TARGET_ARM (! TARGET_THUMB) 209 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 210 #define TARGET_BACKTRACE (leaf_function_p () \ 211 ? TARGET_TPCS_LEAF_FRAME \ 212 : TARGET_TPCS_FRAME) 213 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) 214 #define TARGET_AAPCS_BASED \ 215 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 216 217 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 218 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 219 220 /* Only 16-bit thumb code. */ 221 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 222 /* Arm or Thumb-2 32-bit code. */ 223 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 224 /* 32-bit Thumb-2 code. */ 225 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 226 /* Thumb-1 only. */ 227 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 228 /* FPA emulator without LFM. */ 229 #define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2) 230 231 /* The following two macros concern the ability to execute coprocessor 232 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 233 only ever tested when we know we are generating for VFP hardware; we need 234 to be more careful with TARGET_NEON as noted below. */ 235 236 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 237 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 238 239 /* FPU supports VFPv3 instructions. */ 240 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 241 242 /* FPU only supports VFP single-precision instructions. */ 243 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 244 245 /* FPU supports VFP double-precision instructions. */ 246 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 247 248 /* FPU supports half-precision floating-point with NEON element load/store. */ 249 #define TARGET_NEON_FP16 \ 250 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 251 252 /* FPU supports VFP half-precision floating-point. */ 253 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 254 255 /* FPU supports Neon instructions. The setting of this macro gets 256 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 257 and TARGET_HARD_FLOAT to ensure that NEON instructions are 258 available. */ 259 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 260 && TARGET_VFP && arm_fpu_desc->neon) 261 262 /* "DSP" multiply instructions, eg. SMULxy. */ 263 #define TARGET_DSP_MULTIPLY \ 264 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 265 /* Integer SIMD instructions, and extend-accumulate instructions. */ 266 #define TARGET_INT_SIMD \ 267 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 268 269 /* Should MOVW/MOVT be used in preference to a constant pool. */ 270 #define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) 271 272 /* We could use unified syntax for arm mode, but for now we just use it 273 for Thumb-2. */ 274 #define TARGET_UNIFIED_ASM TARGET_THUMB2 275 276 /* Nonzero if integer division instructions supported. */ 277 #define TARGET_IDIV (arm_arch_hwdiv) 278 279 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 280 then TARGET_AAPCS_BASED must be true -- but the converse does not 281 hold. TARGET_BPABI implies the use of the BPABI runtime library, 282 etc., in addition to just the AAPCS calling conventions. */ 283 #ifndef TARGET_BPABI 284 #define TARGET_BPABI false 285 #endif 286 287 /* Support for a compile-time default CPU, et cetera. The rules are: 288 --with-arch is ignored if -march or -mcpu are specified. 289 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 290 by --with-arch. 291 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 292 by -march). 293 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are 294 specified. 295 --with-fpu is ignored if -mfpu is specified. 296 --with-abi is ignored is -mabi is specified. */ 297 #define OPTION_DEFAULT_SPECS \ 298 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 299 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 300 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 301 {"float", \ 302 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ 303 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 304 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 305 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, 306 307 /* Which floating point model to use. */ 308 enum arm_fp_model 309 { 310 ARM_FP_MODEL_UNKNOWN, 311 /* FPA model (Hardware or software). */ 312 ARM_FP_MODEL_FPA, 313 /* Cirrus Maverick floating point model. */ 314 ARM_FP_MODEL_MAVERICK, 315 /* VFP floating point model. */ 316 ARM_FP_MODEL_VFP 317 }; 318 319 enum vfp_reg_type 320 { 321 VFP_NONE = 0, 322 VFP_REG_D16, 323 VFP_REG_D32, 324 VFP_REG_SINGLE 325 }; 326 327 extern const struct arm_fpu_desc 328 { 329 const char *name; 330 enum arm_fp_model model; 331 int rev; 332 enum vfp_reg_type regs; 333 int neon; 334 int fp16; 335 } *arm_fpu_desc; 336 337 /* Which floating point hardware to schedule for. */ 338 extern int arm_fpu_attr; 339 340 enum float_abi_type 341 { 342 ARM_FLOAT_ABI_SOFT, 343 ARM_FLOAT_ABI_SOFTFP, 344 ARM_FLOAT_ABI_HARD 345 }; 346 347 extern enum float_abi_type arm_float_abi; 348 349 #ifndef TARGET_DEFAULT_FLOAT_ABI 350 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 351 #endif 352 353 /* Which __fp16 format to use. 354 The enumeration values correspond to the numbering for the 355 Tag_ABI_FP_16bit_format attribute. 356 */ 357 enum arm_fp16_format_type 358 { 359 ARM_FP16_FORMAT_NONE = 0, 360 ARM_FP16_FORMAT_IEEE = 1, 361 ARM_FP16_FORMAT_ALTERNATIVE = 2 362 }; 363 364 extern enum arm_fp16_format_type arm_fp16_format; 365 #define LARGEST_EXPONENT_IS_NORMAL(bits) \ 366 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) 367 368 /* Which ABI to use. */ 369 enum arm_abi_type 370 { 371 ARM_ABI_APCS, 372 ARM_ABI_ATPCS, 373 ARM_ABI_AAPCS, 374 ARM_ABI_IWMMXT, 375 ARM_ABI_AAPCS_LINUX 376 }; 377 378 extern enum arm_abi_type arm_abi; 379 380 #ifndef ARM_DEFAULT_ABI 381 #define ARM_DEFAULT_ABI ARM_ABI_APCS 382 #endif 383 384 /* Which thread pointer access sequence to use. */ 385 enum arm_tp_type { 386 TP_AUTO, 387 TP_SOFT, 388 TP_CP15 389 }; 390 391 extern enum arm_tp_type target_thread_pointer; 392 393 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 394 extern int arm_arch3m; 395 396 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 397 extern int arm_arch4; 398 399 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 400 extern int arm_arch4t; 401 402 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 403 extern int arm_arch5; 404 405 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 406 extern int arm_arch5e; 407 408 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 409 extern int arm_arch6; 410 411 /* Nonzero if instructions not present in the 'M' profile can be used. */ 412 extern int arm_arch_notm; 413 414 /* Nonzero if instructions present in ARMv7E-M can be used. */ 415 extern int arm_arch7em; 416 417 /* Nonzero if this chip can benefit from load scheduling. */ 418 extern int arm_ld_sched; 419 420 /* Nonzero if generating thumb code. */ 421 extern int thumb_code; 422 423 /* Nonzero if this chip is a StrongARM. */ 424 extern int arm_tune_strongarm; 425 426 /* Nonzero if this chip is a Cirrus variant. */ 427 extern int arm_arch_cirrus; 428 429 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 430 extern int arm_arch_iwmmxt; 431 432 /* Nonzero if this chip is an XScale. */ 433 extern int arm_arch_xscale; 434 435 /* Nonzero if tuning for XScale. */ 436 extern int arm_tune_xscale; 437 438 /* Nonzero if tuning for stores via the write buffer. */ 439 extern int arm_tune_wbuf; 440 441 /* Nonzero if tuning for Cortex-A9. */ 442 extern int arm_tune_cortex_a9; 443 444 /* Nonzero if we should define __THUMB_INTERWORK__ in the 445 preprocessor. 446 XXX This is a bit of a hack, it's intended to help work around 447 problems in GLD which doesn't understand that armv5t code is 448 interworking clean. */ 449 extern int arm_cpp_interwork; 450 451 /* Nonzero if chip supports Thumb 2. */ 452 extern int arm_arch_thumb2; 453 454 /* Nonzero if chip supports integer division instruction. */ 455 extern int arm_arch_hwdiv; 456 457 #ifndef TARGET_DEFAULT 458 #define TARGET_DEFAULT (MASK_APCS_FRAME) 459 #endif 460 461 /* The frame pointer register used in gcc has nothing to do with debugging; 462 that is controlled by the APCS-FRAME option. */ 463 #define CAN_DEBUG_WITHOUT_FP 464 465 #define OVERRIDE_OPTIONS arm_override_options () 466 467 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 468 arm_optimization_options ((LEVEL), (SIZE)) 469 470 /* Nonzero if PIC code requires explicit qualifiers to generate 471 PLT and GOT relocs rather than the assembler doing so implicitly. 472 Subtargets can override these if required. */ 473 #ifndef NEED_GOT_RELOC 474 #define NEED_GOT_RELOC 0 475 #endif 476 #ifndef NEED_PLT_RELOC 477 #define NEED_PLT_RELOC 0 478 #endif 479 480 /* Nonzero if we need to refer to the GOT with a PC-relative 481 offset. In other words, generate 482 483 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 484 485 rather than 486 487 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 488 489 The default is true, which matches NetBSD. Subtargets can 490 override this if required. */ 491 #ifndef GOT_PCREL 492 #define GOT_PCREL 1 493 #endif 494 495 /* Target machine storage Layout. */ 497 498 499 /* Define this macro if it is advisable to hold scalars in registers 500 in a wider mode than that declared by the program. In such cases, 501 the value is constrained to be within the bounds of the declared 502 type, but kept valid in the wider mode. The signedness of the 503 extension may differ from that of the type. */ 504 505 /* It is far faster to zero extend chars than to sign extend them */ 506 507 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 508 if (GET_MODE_CLASS (MODE) == MODE_INT \ 509 && GET_MODE_SIZE (MODE) < 4) \ 510 { \ 511 if (MODE == QImode) \ 512 UNSIGNEDP = 1; \ 513 else if (MODE == HImode) \ 514 UNSIGNEDP = 1; \ 515 (MODE) = SImode; \ 516 } 517 518 /* Define this if most significant bit is lowest numbered 519 in instructions that operate on numbered bit-fields. */ 520 #define BITS_BIG_ENDIAN 0 521 522 /* Define this if most significant byte of a word is the lowest numbered. 523 Most ARM processors are run in little endian mode, so that is the default. 524 If you want to have it run-time selectable, change the definition in a 525 cover file to be TARGET_BIG_ENDIAN. */ 526 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 527 528 /* Define this if most significant word of a multiword number is the lowest 529 numbered. 530 This is always false, even when in big-endian mode. */ 531 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 532 533 /* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 534 on processor pre-defineds when compiling libgcc2.c. */ 535 #if defined(__ARMEB__) && !defined(__ARMWEL__) 536 #define LIBGCC2_WORDS_BIG_ENDIAN 1 537 #else 538 #define LIBGCC2_WORDS_BIG_ENDIAN 0 539 #endif 540 541 /* Define this if most significant word of doubles is the lowest numbered. 542 The rules are different based on whether or not we use FPA-format, 543 VFP-format or some other floating point co-processor's format doubles. */ 544 #define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 545 546 #define UNITS_PER_WORD 4 547 548 /* Use the option -mvectorize-with-neon-quad to override the use of doubleword 549 registers when autovectorizing for Neon, at least until multiple vector 550 widths are supported properly by the middle-end. */ 551 #define UNITS_PER_SIMD_WORD(MODE) \ 552 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD) 553 554 /* True if natural alignment is used for doubleword types. */ 555 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 556 557 #define DOUBLEWORD_ALIGNMENT 64 558 559 #define PARM_BOUNDARY 32 560 561 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 562 563 #define PREFERRED_STACK_BOUNDARY \ 564 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 565 566 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 567 568 /* The lowest bit is used to indicate Thumb-mode functions, so the 569 vbit must go into the delta field of pointers to member 570 functions. */ 571 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 572 573 #define EMPTY_FIELD_BOUNDARY 32 574 575 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 576 577 /* XXX Blah -- this macro is used directly by libobjc. Since it 578 supports no vector modes, cut out the complexity and fall back 579 on BIGGEST_FIELD_ALIGNMENT. */ 580 #ifdef IN_TARGET_LIBS 581 #define BIGGEST_FIELD_ALIGNMENT 64 582 #endif 583 584 /* Make strings word-aligned so strcpy from constants will be faster. */ 585 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 586 587 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 588 ((TREE_CODE (EXP) == STRING_CST \ 589 && !optimize_size \ 590 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 591 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 592 593 /* Align definitions of arrays, unions and structures so that 594 initializations and copies can be made more efficient. This is not 595 ABI-changing, so it only affects places where we can see the 596 definition. */ 597 #define DATA_ALIGNMENT(EXP, ALIGN) \ 598 ((((ALIGN) < BITS_PER_WORD) \ 599 && (TREE_CODE (EXP) == ARRAY_TYPE \ 600 || TREE_CODE (EXP) == UNION_TYPE \ 601 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 602 603 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 604 #define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 605 606 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 607 value set in previous versions of this toolchain was 8, which produces more 608 compact structures. The command line option -mstructure_size_boundary=<n> 609 can be used to change this value. For compatibility with the ARM SDK 610 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 611 0020D) page 2-20 says "Structures are aligned on word boundaries". 612 The AAPCS specifies a value of 8. */ 613 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 614 extern int arm_structure_size_boundary; 615 616 /* This is the value used to initialize arm_structure_size_boundary. If a 617 particular arm target wants to change the default value it should change 618 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 619 for an example of this. */ 620 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 621 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 622 #endif 623 624 /* Nonzero if move instructions will actually fail to work 625 when given unaligned data. */ 626 #define STRICT_ALIGNMENT 1 627 628 /* wchar_t is unsigned under the AAPCS. */ 629 #ifndef WCHAR_TYPE 630 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 631 632 #define WCHAR_TYPE_SIZE BITS_PER_WORD 633 #endif 634 635 #ifndef SIZE_TYPE 636 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 637 #endif 638 639 #ifndef PTRDIFF_TYPE 640 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 641 #endif 642 643 /* AAPCS requires that structure alignment is affected by bitfields. */ 644 #ifndef PCC_BITFIELD_TYPE_MATTERS 645 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 646 #endif 647 648 649 /* Standard register usage. */ 651 652 /* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 653 (S - saved over call). 654 655 r0 * argument word/integer result 656 r1-r3 argument word 657 658 r4-r8 S register variable 659 r9 S (rfp) register variable (real frame pointer) 660 661 r10 F S (sl) stack limit (used by -mapcs-stack-check) 662 r11 F S (fp) argument pointer 663 r12 (ip) temp workspace 664 r13 F S (sp) lower end of current stack frame 665 r14 (lr) link address/workspace 666 r15 F (pc) program counter 667 668 f0 floating point result 669 f1-f3 floating point scratch 670 671 f4-f7 S floating point variable 672 673 cc This is NOT a real register, but is used internally 674 to represent things that use or set the condition 675 codes. 676 sfp This isn't either. It is used during rtl generation 677 since the offset between the frame pointer and the 678 auto's isn't known until after register allocation. 679 afp Nor this, we only need this because of non-local 680 goto. Without it fp appears to be used and the 681 elimination code won't get rid of sfp. It tracks 682 fp exactly at all times. 683 684 *: See CONDITIONAL_REGISTER_USAGE */ 685 686 /* 687 mvf0 Cirrus floating point result 688 mvf1-mvf3 Cirrus floating point scratch 689 mvf4-mvf15 S Cirrus floating point variable. */ 690 691 /* s0-s15 VFP scratch (aka d0-d7). 692 s16-s31 S VFP variable (aka d8-d15). 693 vfpcc Not a real register. Represents the VFP condition 694 code flags. */ 695 696 /* The stack backtrace structure is as follows: 697 fp points to here: | save code pointer | [fp] 698 | return link value | [fp, #-4] 699 | return sp value | [fp, #-8] 700 | return fp value | [fp, #-12] 701 [| saved r10 value |] 702 [| saved r9 value |] 703 [| saved r8 value |] 704 [| saved r7 value |] 705 [| saved r6 value |] 706 [| saved r5 value |] 707 [| saved r4 value |] 708 [| saved r3 value |] 709 [| saved r2 value |] 710 [| saved r1 value |] 711 [| saved r0 value |] 712 [| saved f7 value |] three words 713 [| saved f6 value |] three words 714 [| saved f5 value |] three words 715 [| saved f4 value |] three words 716 r0-r3 are not normally saved in a C function. */ 717 718 /* 1 for registers that have pervasive standard uses 719 and are not available for the register allocator. */ 720 #define FIXED_REGISTERS \ 721 { \ 722 0,0,0,0,0,0,0,0, \ 723 0,0,0,0,0,1,0,1, \ 724 0,0,0,0,0,0,0,0, \ 725 1,1,1, \ 726 1,1,1,1,1,1,1,1, \ 727 1,1,1,1,1,1,1,1, \ 728 1,1,1,1,1,1,1,1, \ 729 1,1,1,1,1,1,1,1, \ 730 1,1,1,1, \ 731 1,1,1,1,1,1,1,1, \ 732 1,1,1,1,1,1,1,1, \ 733 1,1,1,1,1,1,1,1, \ 734 1,1,1,1,1,1,1,1, \ 735 1,1,1,1,1,1,1,1, \ 736 1,1,1,1,1,1,1,1, \ 737 1,1,1,1,1,1,1,1, \ 738 1,1,1,1,1,1,1,1, \ 739 1 \ 740 } 741 742 /* 1 for registers not available across function calls. 743 These must include the FIXED_REGISTERS and also any 744 registers that can be used without being saved. 745 The latter must include the registers where values are returned 746 and the register where structure-value addresses are passed. 747 Aside from that, you can include as many other registers as you like. 748 The CC is not preserved over function calls on the ARM 6, so it is 749 easier to assume this for all. SFP is preserved, since FP is. */ 750 #define CALL_USED_REGISTERS \ 751 { \ 752 1,1,1,1,0,0,0,0, \ 753 0,0,0,0,1,1,1,1, \ 754 1,1,1,1,0,0,0,0, \ 755 1,1,1, \ 756 1,1,1,1,1,1,1,1, \ 757 1,1,1,1,1,1,1,1, \ 758 1,1,1,1,1,1,1,1, \ 759 1,1,1,1,1,1,1,1, \ 760 1,1,1,1, \ 761 1,1,1,1,1,1,1,1, \ 762 1,1,1,1,1,1,1,1, \ 763 1,1,1,1,1,1,1,1, \ 764 1,1,1,1,1,1,1,1, \ 765 1,1,1,1,1,1,1,1, \ 766 1,1,1,1,1,1,1,1, \ 767 1,1,1,1,1,1,1,1, \ 768 1,1,1,1,1,1,1,1, \ 769 1 \ 770 } 771 772 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 773 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 774 #endif 775 776 #define CONDITIONAL_REGISTER_USAGE \ 777 { \ 778 int regno; \ 779 \ 780 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \ 781 { \ 782 for (regno = FIRST_FPA_REGNUM; \ 783 regno <= LAST_FPA_REGNUM; ++regno) \ 784 fixed_regs[regno] = call_used_regs[regno] = 1; \ 785 } \ 786 \ 787 if (TARGET_THUMB && optimize_size) \ 788 { \ 789 /* When optimizing for size, it's better not to use \ 790 the HI regs, because of the overhead of stacking \ 791 them. */ \ 792 /* ??? Is this still true for thumb2? */ \ 793 for (regno = FIRST_HI_REGNUM; \ 794 regno <= LAST_HI_REGNUM; ++regno) \ 795 fixed_regs[regno] = call_used_regs[regno] = 1; \ 796 } \ 797 \ 798 /* The link register can be clobbered by any branch insn, \ 799 but we have no way to track that at present, so mark \ 800 it as unavailable. */ \ 801 if (TARGET_THUMB1) \ 802 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ 803 \ 804 if (TARGET_32BIT && TARGET_HARD_FLOAT) \ 805 { \ 806 if (TARGET_MAVERICK) \ 807 { \ 808 for (regno = FIRST_FPA_REGNUM; \ 809 regno <= LAST_FPA_REGNUM; ++ regno) \ 810 fixed_regs[regno] = call_used_regs[regno] = 1; \ 811 for (regno = FIRST_CIRRUS_FP_REGNUM; \ 812 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ 813 { \ 814 fixed_regs[regno] = 0; \ 815 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ 816 } \ 817 } \ 818 if (TARGET_VFP) \ 819 { \ 820 /* VFPv3 registers are disabled when earlier VFP \ 821 versions are selected due to the definition of \ 822 LAST_VFP_REGNUM. */ \ 823 for (regno = FIRST_VFP_REGNUM; \ 824 regno <= LAST_VFP_REGNUM; ++ regno) \ 825 { \ 826 fixed_regs[regno] = 0; \ 827 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \ 828 || regno >= FIRST_VFP_REGNUM + 32; \ 829 } \ 830 } \ 831 } \ 832 \ 833 if (TARGET_REALLY_IWMMXT) \ 834 { \ 835 regno = FIRST_IWMMXT_GR_REGNUM; \ 836 /* The 2002/10/09 revision of the XScale ABI has wCG0 \ 837 and wCG1 as call-preserved registers. The 2002/11/21 \ 838 revision changed this so that all wCG registers are \ 839 scratch registers. */ \ 840 for (regno = FIRST_IWMMXT_GR_REGNUM; \ 841 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ 842 fixed_regs[regno] = 0; \ 843 /* The XScale ABI has wR0 - wR9 as scratch registers, \ 844 the rest as call-preserved registers. */ \ 845 for (regno = FIRST_IWMMXT_REGNUM; \ 846 regno <= LAST_IWMMXT_REGNUM; ++ regno) \ 847 { \ 848 fixed_regs[regno] = 0; \ 849 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ 850 } \ 851 } \ 852 \ 853 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 854 { \ 855 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 856 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 857 } \ 858 else if (TARGET_APCS_STACK) \ 859 { \ 860 fixed_regs[10] = 1; \ 861 call_used_regs[10] = 1; \ 862 } \ 863 /* -mcaller-super-interworking reserves r11 for calls to \ 864 _interwork_r11_call_via_rN(). Making the register global \ 865 is an easy way of ensuring that it remains valid for all \ 866 calls. */ \ 867 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \ 868 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \ 869 { \ 870 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 871 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 872 if (TARGET_CALLER_INTERWORKING) \ 873 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 874 } \ 875 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 876 } 877 878 /* These are a couple of extensions to the formats accepted 879 by asm_fprintf: 880 %@ prints out ASM_COMMENT_START 881 %r prints out REGISTER_PREFIX reg_names[arg] */ 882 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 883 case '@': \ 884 fputs (ASM_COMMENT_START, FILE); \ 885 break; \ 886 \ 887 case 'r': \ 888 fputs (REGISTER_PREFIX, FILE); \ 889 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 890 break; 891 892 /* Round X up to the nearest word. */ 893 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 894 895 /* Convert fron bytes to ints. */ 896 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 897 898 /* The number of (integer) registers required to hold a quantity of type MODE. 899 Also used for VFP registers. */ 900 #define ARM_NUM_REGS(MODE) \ 901 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 902 903 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 904 #define ARM_NUM_REGS2(MODE, TYPE) \ 905 ARM_NUM_INTS ((MODE) == BLKmode ? \ 906 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 907 908 /* The number of (integer) argument register available. */ 909 #define NUM_ARG_REGS 4 910 911 /* And similarly for the VFP. */ 912 #define NUM_VFP_ARG_REGS 16 913 914 /* Return the register number of the N'th (integer) argument. */ 915 #define ARG_REGISTER(N) (N - 1) 916 917 /* Specify the registers used for certain standard purposes. 918 The values of these macros are register numbers. */ 919 920 /* The number of the last argument register. */ 921 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 922 923 /* The numbers of the Thumb register ranges. */ 924 #define FIRST_LO_REGNUM 0 925 #define LAST_LO_REGNUM 7 926 #define FIRST_HI_REGNUM 8 927 #define LAST_HI_REGNUM 11 928 929 #ifndef TARGET_UNWIND_INFO 930 /* We use sjlj exceptions for backwards compatibility. */ 931 #define MUST_USE_SJLJ_EXCEPTIONS 1 932 #endif 933 934 /* We can generate DWARF2 Unwind info, even though we don't use it. */ 935 #define DWARF2_UNWIND_INFO 1 936 937 /* Use r0 and r1 to pass exception handling information. */ 938 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 939 940 /* The register that holds the return address in exception handlers. */ 941 #define ARM_EH_STACKADJ_REGNUM 2 942 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 943 944 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 945 as an invisible last argument (possible since varargs don't exist in 946 Pascal), so the following is not true. */ 947 #define STATIC_CHAIN_REGNUM 12 948 949 /* Define this to be where the real frame pointer is if it is not possible to 950 work out the offset between the frame pointer and the automatic variables 951 until after register allocation has taken place. FRAME_POINTER_REGNUM 952 should point to a special register that we will make sure is eliminated. 953 954 For the Thumb we have another problem. The TPCS defines the frame pointer 955 as r11, and GCC believes that it is always possible to use the frame pointer 956 as base register for addressing purposes. (See comments in 957 find_reloads_address()). But - the Thumb does not allow high registers, 958 including r11, to be used as base address registers. Hence our problem. 959 960 The solution used here, and in the old thumb port is to use r7 instead of 961 r11 as the hard frame pointer and to have special code to generate 962 backtrace structures on the stack (if required to do so via a command line 963 option) using r11. This is the only 'user visible' use of r11 as a frame 964 pointer. */ 965 #define ARM_HARD_FRAME_POINTER_REGNUM 11 966 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 967 968 #define HARD_FRAME_POINTER_REGNUM \ 969 (TARGET_ARM \ 970 ? ARM_HARD_FRAME_POINTER_REGNUM \ 971 : THUMB_HARD_FRAME_POINTER_REGNUM) 972 973 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 974 975 /* Register to use for pushing function arguments. */ 976 #define STACK_POINTER_REGNUM SP_REGNUM 977 978 /* ARM floating pointer registers. */ 979 #define FIRST_FPA_REGNUM 16 980 #define LAST_FPA_REGNUM 23 981 #define IS_FPA_REGNUM(REGNUM) \ 982 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) 983 984 #define FIRST_IWMMXT_GR_REGNUM 43 985 #define LAST_IWMMXT_GR_REGNUM 46 986 #define FIRST_IWMMXT_REGNUM 47 987 #define LAST_IWMMXT_REGNUM 62 988 #define IS_IWMMXT_REGNUM(REGNUM) \ 989 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 990 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 991 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 992 993 /* Base register for access to local variables of the function. */ 994 #define FRAME_POINTER_REGNUM 25 995 996 /* Base register for access to arguments of the function. */ 997 #define ARG_POINTER_REGNUM 26 998 999 #define FIRST_CIRRUS_FP_REGNUM 27 1000 #define LAST_CIRRUS_FP_REGNUM 42 1001 #define IS_CIRRUS_REGNUM(REGNUM) \ 1002 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 1003 1004 #define FIRST_VFP_REGNUM 63 1005 #define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ 1006 #define LAST_VFP_REGNUM \ 1007 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1008 1009 #define IS_VFP_REGNUM(REGNUM) \ 1010 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1011 1012 /* VFP registers are split into two types: those defined by VFP versions < 3 1013 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1014 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1015 in various parts of the backend, we implement as "fake" single-precision 1016 registers (which would be S32-S63, but cannot be used in that way). The 1017 following macros define these ranges of registers. */ 1018 #define LAST_LO_VFP_REGNUM 94 1019 #define FIRST_HI_VFP_REGNUM 95 1020 #define LAST_HI_VFP_REGNUM 126 1021 1022 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1023 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1024 1025 /* DFmode values are only valid in even register pairs. */ 1026 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1027 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1028 1029 /* Neon Quad values must start at a multiple of four registers. */ 1030 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1031 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1032 1033 /* Neon structures of vectors must be in even register pairs and there 1034 must be enough registers available. Because of various patterns 1035 requiring quad registers, we require them to start at a multiple of 1036 four. */ 1037 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1038 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1039 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1040 1041 /* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 1042 /* + 16 Cirrus registers take us up to 43. */ 1043 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1044 /* VFP (VFP3) adds 32 (64) + 1 more. */ 1045 #define FIRST_PSEUDO_REGISTER 128 1046 1047 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1048 1049 /* Value should be nonzero if functions must have frame pointers. 1050 Zero means the frame pointer need not be set up (and parms may be accessed 1051 via the stack pointer) in functions that seem suitable. 1052 If we have to have a frame pointer we might as well make use of it. 1053 APCS says that the frame pointer does not need to be pushed in leaf 1054 functions, or simple tail call functions. */ 1055 1056 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1057 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1058 #endif 1059 1060 /* Return number of consecutive hard regs needed starting at reg REGNO 1061 to hold something of mode MODE. 1062 This is ordinarily the length in words of a value of mode MODE 1063 but can be less for certain modes in special long registers. 1064 1065 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 1066 mode. */ 1067 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1068 ((TARGET_32BIT \ 1069 && REGNO >= FIRST_FPA_REGNUM \ 1070 && REGNO != FRAME_POINTER_REGNUM \ 1071 && REGNO != ARG_POINTER_REGNUM) \ 1072 && !IS_VFP_REGNUM (REGNO) \ 1073 ? 1 : ARM_NUM_REGS (MODE)) 1074 1075 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1076 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1077 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1078 1079 /* Value is 1 if it is a good idea to tie two pseudo registers 1080 when one has mode MODE1 and one has mode MODE2. 1081 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1082 for any hard reg, then this must be 0 for correct output. */ 1083 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1084 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1085 1086 #define VALID_IWMMXT_REG_MODE(MODE) \ 1087 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1088 1089 /* Modes valid for Neon D registers. */ 1090 #define VALID_NEON_DREG_MODE(MODE) \ 1091 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1092 || (MODE) == V2SFmode || (MODE) == DImode) 1093 1094 /* Modes valid for Neon Q registers. */ 1095 #define VALID_NEON_QREG_MODE(MODE) \ 1096 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1097 || (MODE) == V4SFmode || (MODE) == V2DImode) 1098 1099 /* Structure modes valid for Neon registers. */ 1100 #define VALID_NEON_STRUCT_MODE(MODE) \ 1101 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1102 || (MODE) == CImode || (MODE) == XImode) 1103 1104 /* The order in which register should be allocated. It is good to use ip 1105 since no saving is required (though calls clobber it) and it never contains 1106 function parameters. It is quite good to use lr since other calls may 1107 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1108 least likely to contain a function parameter; in addition results are 1109 returned in r0. 1110 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1111 then D8-D15. The reason for doing this is to attempt to reduce register 1112 pressure when both single- and double-precision registers are used in a 1113 function. */ 1114 1115 #define REG_ALLOC_ORDER \ 1116 { \ 1117 3, 2, 1, 0, 12, 14, 4, 5, \ 1118 6, 7, 8, 10, 9, 11, 13, 15, \ 1119 16, 17, 18, 19, 20, 21, 22, 23, \ 1120 27, 28, 29, 30, 31, 32, 33, 34, \ 1121 35, 36, 37, 38, 39, 40, 41, 42, \ 1122 43, 44, 45, 46, 47, 48, 49, 50, \ 1123 51, 52, 53, 54, 55, 56, 57, 58, \ 1124 59, 60, 61, 62, \ 1125 24, 25, 26, \ 1126 95, 96, 97, 98, 99, 100, 101, 102, \ 1127 103, 104, 105, 106, 107, 108, 109, 110, \ 1128 111, 112, 113, 114, 115, 116, 117, 118, \ 1129 119, 120, 121, 122, 123, 124, 125, 126, \ 1130 78, 77, 76, 75, 74, 73, 72, 71, \ 1131 70, 69, 68, 67, 66, 65, 64, 63, \ 1132 79, 80, 81, 82, 83, 84, 85, 86, \ 1133 87, 88, 89, 90, 91, 92, 93, 94, \ 1134 127 \ 1135 } 1136 1137 /* Use different register alloc ordering for Thumb. */ 1138 #define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () 1139 1140 /* Interrupt functions can only use registers that have already been 1141 saved by the prologue, even if they would normally be 1142 call-clobbered. */ 1143 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1144 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1145 df_regs_ever_live_p (DST)) 1146 1147 /* Register and constant classes. */ 1149 1150 /* Register classes: used to be simple, just all ARM regs or all FPA regs 1151 Now that the Thumb is involved it has become more complicated. */ 1152 enum reg_class 1153 { 1154 NO_REGS, 1155 FPA_REGS, 1156 CIRRUS_REGS, 1157 VFP_D0_D7_REGS, 1158 VFP_LO_REGS, 1159 VFP_HI_REGS, 1160 VFP_REGS, 1161 IWMMXT_GR_REGS, 1162 IWMMXT_REGS, 1163 LO_REGS, 1164 STACK_REG, 1165 BASE_REGS, 1166 HI_REGS, 1167 CC_REG, 1168 VFPCC_REG, 1169 GENERAL_REGS, 1170 CORE_REGS, 1171 ALL_REGS, 1172 LIM_REG_CLASSES 1173 }; 1174 1175 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1176 1177 /* Give names of register classes as strings for dump file. */ 1178 #define REG_CLASS_NAMES \ 1179 { \ 1180 "NO_REGS", \ 1181 "FPA_REGS", \ 1182 "CIRRUS_REGS", \ 1183 "VFP_D0_D7_REGS", \ 1184 "VFP_LO_REGS", \ 1185 "VFP_HI_REGS", \ 1186 "VFP_REGS", \ 1187 "IWMMXT_GR_REGS", \ 1188 "IWMMXT_REGS", \ 1189 "LO_REGS", \ 1190 "STACK_REG", \ 1191 "BASE_REGS", \ 1192 "HI_REGS", \ 1193 "CC_REG", \ 1194 "VFPCC_REG", \ 1195 "GENERAL_REGS", \ 1196 "CORE_REGS", \ 1197 "ALL_REGS", \ 1198 } 1199 1200 /* Define which registers fit in which classes. 1201 This is an initializer for a vector of HARD_REG_SET 1202 of length N_REG_CLASSES. */ 1203 #define REG_CLASS_CONTENTS \ 1204 { \ 1205 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1206 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ 1207 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ 1208 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1209 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ 1210 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ 1211 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ 1212 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ 1213 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ 1214 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1215 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1216 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1217 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1218 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ 1219 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ 1220 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1221 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1222 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 1223 } 1224 1225 /* Any of the VFP register classes. */ 1226 #define IS_VFP_CLASS(X) \ 1227 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1228 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1229 1230 /* The same information, inverted: 1231 Return the class number of the smallest class containing 1232 reg number REGNO. This could be a conditional expression 1233 or could index an array. */ 1234 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1235 1236 /* The following macro defines cover classes for Integrated Register 1237 Allocator. Cover classes is a set of non-intersected register 1238 classes covering all hard registers used for register allocation 1239 purpose. Any move between two registers of a cover class should be 1240 cheaper than load or store of the registers. The macro value is 1241 array of register classes with LIM_REG_CLASSES used as the end 1242 marker. */ 1243 1244 #define IRA_COVER_CLASSES \ 1245 { \ 1246 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ 1247 LIM_REG_CLASSES \ 1248 } 1249 1250 /* FPA registers can't do subreg as all values are reformatted to internal 1251 precision. VFP registers may only be accessed in the mode they 1252 were set. */ 1253 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1254 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1255 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ 1256 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ 1257 : 0) 1258 1259 /* We need to define this for LO_REGS on thumb. Otherwise we can end up 1260 using r0-r4 for function arguments, r7 for the stack frame and don't 1261 have enough left over to do doubleword arithmetic. */ 1262 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 1263 ((TARGET_THUMB && (CLASS) == LO_REGS) \ 1264 || (CLASS) == CC_REG) 1265 1266 /* The class value for index registers, and the one for base regs. */ 1267 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1268 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1269 1270 /* For the Thumb the high registers cannot be used as base registers 1271 when addressing quantities in QI or HI mode; if we don't know the 1272 mode, then we must be conservative. */ 1273 #define MODE_BASE_REG_CLASS(MODE) \ 1274 (TARGET_32BIT ? CORE_REGS : \ 1275 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) 1276 1277 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1278 instead of BASE_REGS. */ 1279 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1280 1281 /* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1282 registers explicitly used in the rtl to be used as spill registers 1283 but prevents the compiler from extending the lifetime of these 1284 registers. */ 1285 #define SMALL_REGISTER_CLASSES TARGET_THUMB1 1286 1287 /* Given an rtx X being reloaded into a reg required to be 1288 in class CLASS, return the class of reg to actually use. 1289 In general this is just CLASS, but for the Thumb core registers and 1290 immediate constants we prefer a LO_REGS class or a subset. */ 1291 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1292 (TARGET_32BIT ? (CLASS) : \ 1293 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ 1294 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ 1295 ? LO_REGS : (CLASS))) 1296 1297 /* Must leave BASE_REGS reloads alone */ 1298 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1299 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1300 ? ((true_regnum (X) == -1 ? LO_REGS \ 1301 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1302 : NO_REGS)) \ 1303 : NO_REGS) 1304 1305 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1306 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1307 ? ((true_regnum (X) == -1 ? LO_REGS \ 1308 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1309 : NO_REGS)) \ 1310 : NO_REGS) 1311 1312 /* Return the register class of a scratch register needed to copy IN into 1313 or out of a register in CLASS in MODE. If it can be done directly, 1314 NO_REGS is returned. */ 1315 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1316 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1317 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1318 && IS_VFP_CLASS (CLASS)) \ 1319 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1320 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1321 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1322 : TARGET_32BIT \ 1323 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1324 ? GENERAL_REGS : NO_REGS) \ 1325 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1326 1327 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1328 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1329 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1330 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1331 && IS_VFP_CLASS (CLASS)) \ 1332 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1333 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1334 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1335 /* Cannot load constants into Cirrus registers. */ \ 1336 (TARGET_MAVERICK && TARGET_HARD_FLOAT \ 1337 && (CLASS) == CIRRUS_REGS \ 1338 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1339 ? GENERAL_REGS : \ 1340 (TARGET_32BIT ? \ 1341 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1342 && CONSTANT_P (X)) \ 1343 ? GENERAL_REGS : \ 1344 (((MODE) == HImode && ! arm_arch4 \ 1345 && (GET_CODE (X) == MEM \ 1346 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1347 && true_regnum (X) == -1))) \ 1348 ? GENERAL_REGS : NO_REGS) \ 1349 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1350 1351 /* Try a machine-dependent way of reloading an illegitimate address 1352 operand. If we find one, push the reload and jump to WIN. This 1353 macro is used in only one place: `find_reloads_address' in reload.c. 1354 1355 For the ARM, we wish to handle large displacements off a base 1356 register by splitting the addend across a MOV and the mem insn. 1357 This can cut the number of reloads needed. */ 1358 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1359 do \ 1360 { \ 1361 if (GET_CODE (X) == PLUS \ 1362 && GET_CODE (XEXP (X, 0)) == REG \ 1363 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 1364 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 1365 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1366 { \ 1367 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1368 HOST_WIDE_INT low, high; \ 1369 \ 1370 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \ 1371 low = ((val & 0xf) ^ 0x8) - 0x8; \ 1372 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ 1373 /* Need to be careful, -256 is not a valid offset. */ \ 1374 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1375 else if (MODE == SImode \ 1376 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 1377 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 1378 /* Need to be careful, -4096 is not a valid offset. */ \ 1379 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 1380 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 1381 /* Need to be careful, -256 is not a valid offset. */ \ 1382 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1383 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1384 && TARGET_HARD_FLOAT && TARGET_FPA) \ 1385 /* Need to be careful, -1024 is not a valid offset. */ \ 1386 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 1387 else \ 1388 break; \ 1389 \ 1390 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 1391 ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 1392 - (unsigned HOST_WIDE_INT) 0x80000000); \ 1393 /* Check for overflow or zero */ \ 1394 if (low == 0 || high == 0 || (high + low != val)) \ 1395 break; \ 1396 \ 1397 /* Reload the high part into a base reg; leave the low part \ 1398 in the mem. */ \ 1399 X = gen_rtx_PLUS (GET_MODE (X), \ 1400 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 1401 GEN_INT (high)), \ 1402 GEN_INT (low)); \ 1403 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1404 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 1405 VOIDmode, 0, 0, OPNUM, TYPE); \ 1406 goto WIN; \ 1407 } \ 1408 } \ 1409 while (0) 1410 1411 /* XXX If an HImode FP+large_offset address is converted to an HImode 1412 SP+large_offset address, then reload won't know how to fix it. It sees 1413 only that SP isn't valid for HImode, and so reloads the SP into an index 1414 register, but the resulting address is still invalid because the offset 1415 is too big. We fix it here instead by reloading the entire address. */ 1416 /* We could probably achieve better results by defining PROMOTE_MODE to help 1417 cope with the variances between the Thumb's signed and unsigned byte and 1418 halfword load instructions. */ 1419 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1420 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1421 do { \ 1422 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1423 if (new_x) \ 1424 { \ 1425 X = new_x; \ 1426 goto WIN; \ 1427 } \ 1428 } while (0) 1429 1430 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1431 if (TARGET_ARM) \ 1432 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1433 else \ 1434 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1435 1436 /* Return the maximum number of consecutive registers 1437 needed to represent mode MODE in a register of class CLASS. 1438 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 1439 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1440 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 1441 1442 /* If defined, gives a class of registers that cannot be used as the 1443 operand of a SUBREG that changes the mode of the object illegally. */ 1444 1445 /* Moves between FPA_REGS and GENERAL_REGS are two memory insns. 1446 Moves between VFP_REGS and GENERAL_REGS are a single insn, but 1447 it is typically more expensive than a single memory access. We set 1448 the cost to less than two memory accesses so that floating 1449 point to integer conversion does not go through memory. */ 1450 #define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1451 (TARGET_32BIT ? \ 1452 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1453 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1454 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ 1455 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ 1456 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1457 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1458 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1459 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1460 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1461 2) \ 1462 : \ 1463 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1464 1465 /* Stack layout; function entry, exit and calling. */ 1467 1468 /* Define this if pushing a word on the stack 1469 makes the stack pointer a smaller address. */ 1470 #define STACK_GROWS_DOWNWARD 1 1471 1472 /* Define this to nonzero if the nominal address of the stack frame 1473 is at the high-address end of the local variables; 1474 that is, each additional local variable allocated 1475 goes at a more negative offset in the frame. */ 1476 #define FRAME_GROWS_DOWNWARD 1 1477 1478 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1479 When present, it is one word in size, and sits at the top of the frame, 1480 between the soft frame pointer and either r7 or r11. 1481 1482 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1483 and only then if some outgoing arguments are passed on the stack. It would 1484 be tempting to also check whether the stack arguments are passed by indirect 1485 calls, but there seems to be no reason in principle why a post-reload pass 1486 couldn't convert a direct call into an indirect one. */ 1487 #define CALLER_INTERWORKING_SLOT_SIZE \ 1488 (TARGET_CALLER_INTERWORKING \ 1489 && crtl->outgoing_args_size != 0 \ 1490 ? UNITS_PER_WORD : 0) 1491 1492 /* Offset within stack frame to start allocating local variables at. 1493 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1494 first local allocated. Otherwise, it is the offset to the BEGINNING 1495 of the first local allocated. */ 1496 #define STARTING_FRAME_OFFSET 0 1497 1498 /* If we generate an insn to push BYTES bytes, 1499 this says how many the stack pointer really advances by. */ 1500 /* The push insns do not do this rounding implicitly. 1501 So don't define this. */ 1502 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1503 1504 /* Define this if the maximum size of all the outgoing args is to be 1505 accumulated and pushed during the prologue. The amount can be 1506 found in the variable crtl->outgoing_args_size. */ 1507 #define ACCUMULATE_OUTGOING_ARGS 1 1508 1509 /* Offset of first parameter from the argument pointer register value. */ 1510 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1511 1512 /* Value is the number of byte of arguments automatically 1513 popped when returning from a subroutine call. 1514 FUNDECL is the declaration node of the function (as a tree), 1515 FUNTYPE is the data type of the function (as a tree), 1516 or for a library call it is an identifier node for the subroutine name. 1517 SIZE is the number of bytes of arguments passed on the stack. 1518 1519 On the ARM, the caller does not pop any of its arguments that were passed 1520 on the stack. */ 1521 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 1522 1523 /* Define how to find the value returned by a library function 1524 assuming the value has mode MODE. */ 1525 #define LIBCALL_VALUE(MODE) \ 1526 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \ 1527 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ 1528 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1529 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ 1530 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ 1531 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1532 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1533 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ 1534 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 1535 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1536 1537 /* 1 if REGNO is a possible register number for a function value. */ 1538 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1539 ((REGNO) == ARG_REGISTER (1) \ 1540 || (TARGET_AAPCS_BASED && TARGET_32BIT \ 1541 && TARGET_VFP && TARGET_HARD_FLOAT \ 1542 && (REGNO) == FIRST_VFP_REGNUM) \ 1543 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ 1544 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ 1545 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ 1546 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ 1547 && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) 1548 1549 /* Amount of memory needed for an untyped call to save all possible return 1550 registers. */ 1551 #define APPLY_RESULT_SIZE arm_apply_result_size() 1552 1553 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1554 values must be in memory. On the ARM, they need only do so if larger 1555 than a word, or if they contain elements offset from zero in the struct. */ 1556 #define DEFAULT_PCC_STRUCT_RETURN 0 1557 1558 /* These bits describe the different types of function supported 1559 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1560 normal function and an interworked function, for example. Knowing the 1561 type of a function is important for determining its prologue and 1562 epilogue sequences. 1563 Note value 7 is currently unassigned. Also note that the interrupt 1564 function types all have bit 2 set, so that they can be tested for easily. 1565 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1566 machine_function structure is initialized (to zero) func_type will 1567 default to unknown. This will force the first use of arm_current_func_type 1568 to call arm_compute_func_type. */ 1569 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1570 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1571 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1572 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1573 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1574 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1575 1576 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1577 1578 /* In addition functions can have several type modifiers, 1579 outlined by these bit masks: */ 1580 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1581 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1582 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1583 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1584 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1585 1586 /* Some macros to test these flags. */ 1587 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1588 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1589 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1590 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1591 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1592 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1593 1594 1595 /* Structure used to hold the function stack frame layout. Offsets are 1596 relative to the stack pointer on function entry. Positive offsets are 1597 in the direction of stack growth. 1598 Only soft_frame is used in thumb mode. */ 1599 1600 typedef struct GTY(()) arm_stack_offsets 1601 { 1602 int saved_args; /* ARG_POINTER_REGNUM. */ 1603 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1604 int saved_regs; 1605 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1606 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1607 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1608 unsigned int saved_regs_mask; 1609 } 1610 arm_stack_offsets; 1611 1612 /* A C structure for machine-specific, per-function data. 1613 This is added to the cfun structure. */ 1614 typedef struct GTY(()) machine_function 1615 { 1616 /* Additional stack adjustment in __builtin_eh_throw. */ 1617 rtx eh_epilogue_sp_ofs; 1618 /* Records if LR has to be saved for far jumps. */ 1619 int far_jump_used; 1620 /* Records if ARG_POINTER was ever live. */ 1621 int arg_pointer_live; 1622 /* Records if the save of LR has been eliminated. */ 1623 int lr_save_eliminated; 1624 /* The size of the stack frame. Only valid after reload. */ 1625 arm_stack_offsets stack_offsets; 1626 /* Records the type of the current function. */ 1627 unsigned long func_type; 1628 /* Record if the function has a variable argument list. */ 1629 int uses_anonymous_args; 1630 /* Records if sibcalls are blocked because an argument 1631 register is needed to preserve stack alignment. */ 1632 int sibcall_blocked; 1633 /* The PIC register for this function. This might be a pseudo. */ 1634 rtx pic_reg; 1635 /* Labels for per-function Thumb call-via stubs. One per potential calling 1636 register. We can never call via LR or PC. We can call via SP if a 1637 trampoline happens to be on the top of the stack. */ 1638 rtx call_via[14]; 1639 /* Set to 1 when a return insn is output, this means that the epilogue 1640 is not needed. */ 1641 int return_used_this_function; 1642 } 1643 machine_function; 1644 1645 /* As in the machine_function, a global set of call-via labels, for code 1646 that is in text_section. */ 1647 extern GTY(()) rtx thumb_call_via_label[14]; 1648 1649 /* The number of potential ways of assigning to a co-processor. */ 1650 #define ARM_NUM_COPROC_SLOTS 1 1651 1652 /* Enumeration of procedure calling standard variants. We don't really 1653 support all of these yet. */ 1654 enum arm_pcs 1655 { 1656 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1657 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1658 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1659 /* This must be the last AAPCS variant. */ 1660 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1661 ARM_PCS_ATPCS, /* ATPCS. */ 1662 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1663 ARM_PCS_UNKNOWN 1664 }; 1665 1666 /* A C type for declaring a variable that is used as the first argument of 1667 `FUNCTION_ARG' and other related values. */ 1668 typedef struct 1669 { 1670 /* This is the number of registers of arguments scanned so far. */ 1671 int nregs; 1672 /* This is the number of iWMMXt register arguments scanned so far. */ 1673 int iwmmxt_nregs; 1674 int named_count; 1675 int nargs; 1676 /* Which procedure call variant to use for this call. */ 1677 enum arm_pcs pcs_variant; 1678 1679 /* AAPCS related state tracking. */ 1680 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1681 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1682 this argument, or -1 if using core 1683 registers. */ 1684 int aapcs_ncrn; 1685 int aapcs_next_ncrn; 1686 rtx aapcs_reg; /* Register assigned to this argument. */ 1687 int aapcs_partial; /* How many bytes are passed in regs (if 1688 split between core regs and stack. 1689 Zero otherwise. */ 1690 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1691 int can_split; /* Argument can be split between core regs 1692 and the stack. */ 1693 /* Private data for tracking VFP register allocation */ 1694 unsigned aapcs_vfp_regs_free; 1695 unsigned aapcs_vfp_reg_alloc; 1696 int aapcs_vfp_rcount; 1697 MACHMODE aapcs_vfp_rmode; 1698 } CUMULATIVE_ARGS; 1699 1700 /* Define where to put the arguments to a function. 1701 Value is zero to push the argument on the stack, 1702 or a hard register in which to store the argument. 1703 1704 MODE is the argument's machine mode. 1705 TYPE is the data type of the argument (as a tree). 1706 This is null for libcalls where that information may 1707 not be available. 1708 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1709 the preceding args and about the function being called. 1710 NAMED is nonzero if this argument is a named parameter 1711 (otherwise it is an extra parameter matching an ellipsis). 1712 1713 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1714 other arguments are passed on the stack. If (NAMED == 0) (which happens 1715 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is 1716 defined), say it is passed in the stack (function_prologue will 1717 indeed make it pass in the stack if necessary). */ 1718 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1719 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1720 1721 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1722 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1723 1724 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1725 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1726 1727 /* For AAPCS, padding should never be below the argument. For other ABIs, 1728 * mimic the default. */ 1729 #define PAD_VARARGS_DOWN \ 1730 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1731 1732 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1733 for a call to a function whose data type is FNTYPE. 1734 For a library call, FNTYPE is 0. 1735 On the ARM, the offset starts at 0. */ 1736 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1737 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1738 1739 /* Update the data in CUM to advance over an argument 1740 of mode MODE and data type TYPE. 1741 (TYPE is null for libcalls where that information may not be available.) */ 1742 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1743 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1744 1745 /* If defined, a C expression that gives the alignment boundary, in bits, of an 1746 argument with the specified mode and type. If it is not defined, 1747 `PARM_BOUNDARY' is used for all arguments. */ 1748 #define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ 1749 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \ 1750 ? DOUBLEWORD_ALIGNMENT \ 1751 : PARM_BOUNDARY ) 1752 1753 /* 1 if N is a possible register number for function argument passing. 1754 On the ARM, r0-r3 are used to pass args. */ 1755 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1756 (IN_RANGE ((REGNO), 0, 3) \ 1757 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1758 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1759 || (TARGET_IWMMXT_ABI \ 1760 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1761 1762 1763 /* If your target environment doesn't prefix user functions with an 1765 underscore, you may wish to re-define this to prevent any conflicts. */ 1766 #ifndef ARM_MCOUNT_NAME 1767 #define ARM_MCOUNT_NAME "*mcount" 1768 #endif 1769 1770 /* Call the function profiler with a given profile label. The Acorn 1771 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1772 On the ARM the full profile code will look like: 1773 .data 1774 LP1 1775 .word 0 1776 .text 1777 mov ip, lr 1778 bl mcount 1779 .word LP1 1780 1781 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1782 will output the .text section. 1783 1784 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1785 ``prof'' doesn't seem to mind about this! 1786 1787 Note - this version of the code is designed to work in both ARM and 1788 Thumb modes. */ 1789 #ifndef ARM_FUNCTION_PROFILER 1790 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1791 { \ 1792 char temp[20]; \ 1793 rtx sym; \ 1794 \ 1795 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1796 IP_REGNUM, LR_REGNUM); \ 1797 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1798 fputc ('\n', STREAM); \ 1799 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1800 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1801 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1802 } 1803 #endif 1804 1805 #ifdef THUMB_FUNCTION_PROFILER 1806 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1807 if (TARGET_ARM) \ 1808 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1809 else \ 1810 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1811 #else 1812 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1813 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1814 #endif 1815 1816 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1817 the stack pointer does not matter. The value is tested only in 1818 functions that have frame pointers. 1819 No definition is equivalent to always zero. 1820 1821 On the ARM, the function epilogue recovers the stack pointer from the 1822 frame. */ 1823 #define EXIT_IGNORE_STACK 1 1824 1825 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) 1826 1827 /* Determine if the epilogue should be output as RTL. 1828 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1829 /* This is disabled for Thumb-2 because it will confuse the 1830 conditional insn counter. */ 1831 #define USE_RETURN_INSN(ISCOND) \ 1832 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) 1833 1834 /* Definitions for register eliminations. 1835 1836 This is an array of structures. Each structure initializes one pair 1837 of eliminable registers. The "from" register number is given first, 1838 followed by "to". Eliminations of the same "from" register are listed 1839 in order of preference. 1840 1841 We have two registers that can be eliminated on the ARM. First, the 1842 arg pointer register can often be eliminated in favor of the stack 1843 pointer register. Secondly, the pseudo frame pointer register can always 1844 be eliminated; it is replaced with either the stack or the real frame 1845 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1846 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1847 1848 #define ELIMINABLE_REGS \ 1849 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1850 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1851 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1852 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1853 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1854 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1855 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1856 1857 /* Define the offset between two registers, one to be eliminated, and the 1858 other its replacement, at the start of a routine. */ 1859 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1860 if (TARGET_ARM) \ 1861 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1862 else \ 1863 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1864 1865 /* Special case handling of the location of arguments passed on the stack. */ 1866 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1867 1868 /* Initialize data used by insn expanders. This is called from insn_emit, 1869 once for every function before code is generated. */ 1870 #define INIT_EXPANDERS arm_init_expanders () 1871 1872 /* Length in units of the trampoline for entering a nested function. */ 1873 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1874 1875 /* Alignment required for a trampoline in bits. */ 1876 #define TRAMPOLINE_ALIGNMENT 32 1877 1878 /* Addressing modes, and classification of registers for them. */ 1880 #define HAVE_POST_INCREMENT 1 1881 #define HAVE_PRE_INCREMENT TARGET_32BIT 1882 #define HAVE_POST_DECREMENT TARGET_32BIT 1883 #define HAVE_PRE_DECREMENT TARGET_32BIT 1884 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1885 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1886 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1887 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1888 1889 /* Macros to check register numbers against specific register classes. */ 1890 1891 /* These assume that REGNO is a hard or pseudo reg number. 1892 They give nonzero only if REGNO is a hard reg of the suitable class 1893 or a pseudo reg currently allocated to a suitable hard reg. 1894 Since they use reg_renumber, they are safe only once reg_renumber 1895 has been allocated, which happens in local-alloc.c. */ 1896 #define TEST_REGNO(R, TEST, VALUE) \ 1897 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1898 1899 /* Don't allow the pc to be used. */ 1900 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1901 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1902 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1903 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1904 1905 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1906 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1907 || (GET_MODE_SIZE (MODE) >= 4 \ 1908 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1909 1910 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1911 (TARGET_THUMB1 \ 1912 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1913 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1914 1915 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1916 For Thumb, we can not use SP + reg, so reject SP. */ 1917 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1918 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1919 1920 /* For ARM code, we don't care about the mode, but for Thumb, the index 1921 must be suitable for use in a QImode load. */ 1922 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1923 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1924 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1925 1926 /* Maximum number of registers that can appear in a valid memory address. 1927 Shifts in addresses can't be by a register. */ 1928 #define MAX_REGS_PER_ADDRESS 2 1929 1930 /* Recognize any constant value that is a valid address. */ 1931 /* XXX We can address any constant, eventually... */ 1932 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1933 #define CONSTANT_ADDRESS_P(X) \ 1934 (GET_CODE (X) == SYMBOL_REF \ 1935 && (CONSTANT_POOL_ADDRESS_P (X) \ 1936 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1937 1938 /* True if SYMBOL + OFFSET constants must refer to something within 1939 SYMBOL's section. */ 1940 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1941 1942 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1943 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1944 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1945 #endif 1946 1947 /* Nonzero if the constant value X is a legitimate general operand. 1948 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1949 1950 On the ARM, allow any integer (invalid ones are removed later by insn 1951 patterns), nice doubles and symbol_refs which refer to the function's 1952 constant pool XXX. 1953 1954 When generating pic allow anything. */ 1955 #define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 1956 1957 #define THUMB_LEGITIMATE_CONSTANT_P(X) \ 1958 ( GET_CODE (X) == CONST_INT \ 1959 || GET_CODE (X) == CONST_DOUBLE \ 1960 || CONSTANT_ADDRESS_P (X) \ 1961 || flag_pic) 1962 1963 #define LEGITIMATE_CONSTANT_P(X) \ 1964 (!arm_cannot_force_const_mem (X) \ 1965 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ 1966 : THUMB_LEGITIMATE_CONSTANT_P (X))) 1967 1968 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1969 #define SUBTARGET_NAME_ENCODING_LENGTHS 1970 #endif 1971 1972 /* This is a C fragment for the inside of a switch statement. 1973 Each case label should return the number of characters to 1974 be stripped from the start of a function's name, if that 1975 name starts with the indicated character. */ 1976 #define ARM_NAME_ENCODING_LENGTHS \ 1977 case '*': return 1; \ 1978 SUBTARGET_NAME_ENCODING_LENGTHS 1979 1980 /* This is how to output a reference to a user-level label named NAME. 1981 `assemble_name' uses this. */ 1982 #undef ASM_OUTPUT_LABELREF 1983 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1984 arm_asm_output_labelref (FILE, NAME) 1985 1986 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1987 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1988 if (TARGET_THUMB2) \ 1989 thumb2_asm_output_opcode (STREAM); 1990 1991 /* The EABI specifies that constructors should go in .init_array. 1992 Other targets use .ctors for compatibility. */ 1993 #ifndef ARM_EABI_CTORS_SECTION_OP 1994 #define ARM_EABI_CTORS_SECTION_OP \ 1995 "\t.section\t.init_array,\"aw\",%init_array" 1996 #endif 1997 #ifndef ARM_EABI_DTORS_SECTION_OP 1998 #define ARM_EABI_DTORS_SECTION_OP \ 1999 "\t.section\t.fini_array,\"aw\",%fini_array" 2000 #endif 2001 #define ARM_CTORS_SECTION_OP \ 2002 "\t.section\t.ctors,\"aw\",%progbits" 2003 #define ARM_DTORS_SECTION_OP \ 2004 "\t.section\t.dtors,\"aw\",%progbits" 2005 2006 /* Define CTORS_SECTION_ASM_OP. */ 2007 #undef CTORS_SECTION_ASM_OP 2008 #undef DTORS_SECTION_ASM_OP 2009 #ifndef IN_LIBGCC2 2010 # define CTORS_SECTION_ASM_OP \ 2011 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 2012 # define DTORS_SECTION_ASM_OP \ 2013 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 2014 #else /* !defined (IN_LIBGCC2) */ 2015 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 2016 so we cannot use the definition above. */ 2017 # ifdef __ARM_EABI__ 2018 /* The .ctors section is not part of the EABI, so we do not define 2019 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 2020 from trying to use it. We do define it when doing normal 2021 compilation, as .init_array can be used instead of .ctors. */ 2022 /* There is no need to emit begin or end markers when using 2023 init_array; the dynamic linker will compute the size of the 2024 array itself based on special symbols created by the static 2025 linker. However, we do need to arrange to set up 2026 exception-handling here. */ 2027 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 2028 # define CTOR_LIST_END /* empty */ 2029 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 2030 # define DTOR_LIST_END /* empty */ 2031 # else /* !defined (__ARM_EABI__) */ 2032 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 2033 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 2034 # endif /* !defined (__ARM_EABI__) */ 2035 #endif /* !defined (IN_LIBCC2) */ 2036 2037 /* True if the operating system can merge entities with vague linkage 2038 (e.g., symbols in COMDAT group) during dynamic linking. */ 2039 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 2040 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 2041 #endif 2042 2043 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 2044 2045 #ifdef TARGET_UNWIND_INFO 2046 #define ARM_EABI_UNWIND_TABLES \ 2047 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables) 2048 #else 2049 #define ARM_EABI_UNWIND_TABLES 0 2050 #endif 2051 2052 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2053 and check its validity for a certain class. 2054 We have two alternate definitions for each of them. 2055 The usual definition accepts all pseudo regs; the other rejects 2056 them unless they have been allocated suitable hard regs. 2057 The symbol REG_OK_STRICT causes the latter definition to be used. 2058 Thumb-2 has the same restrictions as arm. */ 2059 #ifndef REG_OK_STRICT 2060 2061 #define ARM_REG_OK_FOR_BASE_P(X) \ 2062 (REGNO (X) <= LAST_ARM_REGNUM \ 2063 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2064 || REGNO (X) == FRAME_POINTER_REGNUM \ 2065 || REGNO (X) == ARG_POINTER_REGNUM) 2066 2067 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2068 ((REGNO (X) <= LAST_ARM_REGNUM \ 2069 && REGNO (X) != STACK_POINTER_REGNUM) \ 2070 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2071 || REGNO (X) == FRAME_POINTER_REGNUM \ 2072 || REGNO (X) == ARG_POINTER_REGNUM) 2073 2074 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2075 (REGNO (X) <= LAST_LO_REGNUM \ 2076 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2077 || (GET_MODE_SIZE (MODE) >= 4 \ 2078 && (REGNO (X) == STACK_POINTER_REGNUM \ 2079 || (X) == hard_frame_pointer_rtx \ 2080 || (X) == arg_pointer_rtx))) 2081 2082 #define REG_STRICT_P 0 2083 2084 #else /* REG_OK_STRICT */ 2085 2086 #define ARM_REG_OK_FOR_BASE_P(X) \ 2087 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2088 2089 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2090 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2091 2092 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2093 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2094 2095 #define REG_STRICT_P 1 2096 2097 #endif /* REG_OK_STRICT */ 2098 2099 /* Now define some helpers in terms of the above. */ 2100 2101 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2102 (TARGET_THUMB1 \ 2103 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2104 : ARM_REG_OK_FOR_BASE_P (X)) 2105 2106 /* For 16-bit Thumb, a valid index register is anything that can be used in 2107 a byte load instruction. */ 2108 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2109 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2110 2111 /* Nonzero if X is a hard reg that can be used as an index 2112 or if it is a pseudo reg. On the Thumb, the stack pointer 2113 is not suitable. */ 2114 #define REG_OK_FOR_INDEX_P(X) \ 2115 (TARGET_THUMB1 \ 2116 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2117 : ARM_REG_OK_FOR_INDEX_P (X)) 2118 2119 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2120 For Thumb, we can not use SP + reg, so reject SP. */ 2121 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2122 REG_OK_FOR_INDEX_P (X) 2123 2124 #define ARM_BASE_REGISTER_RTX_P(X) \ 2126 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 2127 2128 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2129 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 2130 2131 /* Define this for compatibility reasons. */ 2133 #define HANDLE_PRAGMA_PACK_PUSH_POP 1 2134 2135 /* Specify the machine mode that this machine uses 2136 for the index in the tablejump instruction. */ 2137 #define CASE_VECTOR_MODE Pmode 2138 2139 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2140 || (TARGET_THUMB1 \ 2141 && (optimize_size || flag_pic))) 2142 2143 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2144 (TARGET_THUMB1 \ 2145 ? (min >= 0 && max < 512 \ 2146 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2147 : min >= -256 && max < 256 \ 2148 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2149 : min >= 0 && max < 8192 \ 2150 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2151 : min >= -4096 && max < 4096 \ 2152 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2153 : SImode) \ 2154 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ 2155 : (max >= 0x200) ? HImode \ 2156 : QImode)) 2157 2158 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2159 unsigned is probably best, but may break some code. */ 2160 #ifndef DEFAULT_SIGNED_CHAR 2161 #define DEFAULT_SIGNED_CHAR 0 2162 #endif 2163 2164 /* Max number of bytes we can move from memory to memory 2165 in one reasonably fast instruction. */ 2166 #define MOVE_MAX 4 2167 2168 #undef MOVE_RATIO 2169 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2170 2171 /* Define if operations between registers always perform the operation 2172 on the full register even if a narrower mode is specified. */ 2173 #define WORD_REGISTER_OPERATIONS 2174 2175 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2176 will either zero-extend or sign-extend. The value of this macro should 2177 be the code that says which one of the two operations is implicitly 2178 done, UNKNOWN if none. */ 2179 #define LOAD_EXTEND_OP(MODE) \ 2180 (TARGET_THUMB ? ZERO_EXTEND : \ 2181 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2182 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2183 2184 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2185 #define SLOW_BYTE_ACCESS 0 2186 2187 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2188 2189 /* Immediate shift counts are truncated by the output routines (or was it 2190 the assembler?). Shift counts in a register are truncated by ARM. Note 2191 that the native compiler puts too large (> 32) immediate shift counts 2192 into a register and shifts by the register, letting the ARM decide what 2193 to do instead of doing that itself. */ 2194 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2195 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2196 On the arm, Y in a register is used modulo 256 for the shift. Only for 2197 rotates is modulo 32 used. */ 2198 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2199 2200 /* All integers have the same format so truncation is easy. */ 2201 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2202 2203 /* Calling from registers is a massive pain. */ 2204 #define NO_FUNCTION_CSE 1 2205 2206 /* The machine modes of pointers and functions */ 2207 #define Pmode SImode 2208 #define FUNCTION_MODE Pmode 2209 2210 #define ARM_FRAME_RTX(X) \ 2211 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2212 || (X) == arg_pointer_rtx) 2213 2214 /* Moves to and from memory are quite expensive */ 2215 #define MEMORY_MOVE_COST(M, CLASS, IN) \ 2216 (TARGET_32BIT ? 10 : \ 2217 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2218 * (CLASS == LO_REGS ? 1 : 2))) 2219 2220 /* Try to generate sequences that don't involve branches, we can then use 2221 conditional instructions */ 2222 #define BRANCH_COST(speed_p, predictable_p) \ 2223 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) 2224 2225 /* Position Independent Code. */ 2227 /* We decide which register to use based on the compilation options and 2228 the assembler in use; this is more general than the APCS restriction of 2229 using sb (r9) all the time. */ 2230 extern unsigned arm_pic_register; 2231 2232 /* The register number of the register used to address a table of static 2233 data addresses in memory. */ 2234 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2235 2236 /* We can't directly access anything that contains a symbol, 2237 nor can we indirect via the constant pool. One exception is 2238 UNSPEC_TLS, which is always PIC. */ 2239 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2240 (!(symbol_mentioned_p (X) \ 2241 || label_mentioned_p (X) \ 2242 || (GET_CODE (X) == SYMBOL_REF \ 2243 && CONSTANT_POOL_ADDRESS_P (X) \ 2244 && (symbol_mentioned_p (get_pool_constant (X)) \ 2245 || label_mentioned_p (get_pool_constant (X))))) \ 2246 || tls_mentioned_p (X)) 2247 2248 /* We need to know when we are making a constant pool; this determines 2249 whether data needs to be in the GOT or can be referenced via a GOT 2250 offset. */ 2251 extern int making_const_table; 2252 2253 /* Handle pragmas for compatibility with Intel's compilers. */ 2255 /* Also abuse this to register additional C specific EABI attributes. */ 2256 #define REGISTER_TARGET_PRAGMAS() do { \ 2257 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2258 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2259 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2260 arm_lang_object_attributes_init(); \ 2261 } while (0) 2262 2263 /* Condition code information. */ 2264 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2265 return the mode to be used for the comparison. */ 2266 2267 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2268 2269 #define REVERSIBLE_CC_MODE(MODE) 1 2270 2271 #define REVERSE_CONDITION(CODE,MODE) \ 2272 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2273 ? reverse_condition_maybe_unordered (code) \ 2274 : reverse_condition (code)) 2275 2276 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2277 do \ 2278 { \ 2279 if (GET_CODE (OP1) == CONST_INT \ 2280 && ! (const_ok_for_arm (INTVAL (OP1)) \ 2281 || (const_ok_for_arm (- INTVAL (OP1))))) \ 2282 { \ 2283 rtx const_op = OP1; \ 2284 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ 2285 &const_op); \ 2286 OP1 = const_op; \ 2287 } \ 2288 } \ 2289 while (0) 2290 2291 /* The arm5 clz instruction returns 32. */ 2292 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2293 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2294 2295 #undef ASM_APP_OFF 2297 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2298 TARGET_THUMB2 ? "\t.thumb\n" : "") 2299 2300 /* Output a push or a pop instruction (only used when profiling). 2301 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2302 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2303 that r7 isn't used by the function profiler, so we can use it as a 2304 scratch reg. WARNING: This isn't safe in the general case! It may be 2305 sensitive to future changes in final.c:profile_function. */ 2306 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2307 do \ 2308 { \ 2309 if (TARGET_ARM) \ 2310 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2311 STACK_POINTER_REGNUM, REGNO); \ 2312 else if (TARGET_THUMB1 \ 2313 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2314 { \ 2315 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2316 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2317 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2318 } \ 2319 else \ 2320 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2321 } while (0) 2322 2323 2324 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2325 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2326 do \ 2327 { \ 2328 if (TARGET_ARM) \ 2329 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2330 STACK_POINTER_REGNUM, REGNO); \ 2331 else if (TARGET_THUMB1 \ 2332 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2333 { \ 2334 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2335 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2336 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2337 } \ 2338 else \ 2339 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2340 } while (0) 2341 2342 /* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 2343 #define ADDR_VEC_ALIGN(JUMPTABLE) 0 2344 2345 /* This is how to output a label which precedes a jumptable. Since 2346 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2347 #undef ASM_OUTPUT_CASE_LABEL 2348 #define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2349 do \ 2350 { \ 2351 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ 2352 ASM_OUTPUT_ALIGN (FILE, 2); \ 2353 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 2354 } \ 2355 while (0) 2356 2357 /* Make sure subsequent insns are aligned after a TBB. */ 2358 #define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 2359 do \ 2360 { \ 2361 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ 2362 ASM_OUTPUT_ALIGN (FILE, 1); \ 2363 } \ 2364 while (0) 2365 2366 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2367 do \ 2368 { \ 2369 if (TARGET_THUMB) \ 2370 { \ 2371 if (is_called_in_ARM_mode (DECL) \ 2372 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2373 && cfun->is_thunk)) \ 2374 fprintf (STREAM, "\t.code 32\n") ; \ 2375 else if (TARGET_THUMB1) \ 2376 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2377 else \ 2378 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2379 } \ 2380 if (TARGET_POKE_FUNCTION_NAME) \ 2381 arm_poke_function_name (STREAM, (const char *) NAME); \ 2382 } \ 2383 while (0) 2384 2385 /* For aliases of functions we use .thumb_set instead. */ 2386 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2387 do \ 2388 { \ 2389 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2390 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2391 \ 2392 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2393 { \ 2394 fprintf (FILE, "\t.thumb_set "); \ 2395 assemble_name (FILE, LABEL1); \ 2396 fprintf (FILE, ","); \ 2397 assemble_name (FILE, LABEL2); \ 2398 fprintf (FILE, "\n"); \ 2399 } \ 2400 else \ 2401 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2402 } \ 2403 while (0) 2404 2405 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2406 /* To support -falign-* switches we need to use .p2align so 2407 that alignment directives in code sections will be padded 2408 with no-op instructions, rather than zeroes. */ 2409 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2410 if ((LOG) != 0) \ 2411 { \ 2412 if ((MAX_SKIP) == 0) \ 2413 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2414 else \ 2415 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2416 (int) (LOG), (int) (MAX_SKIP)); \ 2417 } 2418 #endif 2419 2420 /* Add two bytes to the length of conditionally executed Thumb-2 2422 instructions for the IT instruction. */ 2423 #define ADJUST_INSN_LENGTH(insn, length) \ 2424 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2425 length += 2; 2426 2427 /* Only perform branch elimination (by making instructions conditional) if 2428 we're optimizing. For Thumb-2 check if any IT instructions need 2429 outputting. */ 2430 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2431 if (TARGET_ARM && optimize) \ 2432 arm_final_prescan_insn (INSN); \ 2433 else if (TARGET_THUMB2) \ 2434 thumb2_final_prescan_insn (INSN); \ 2435 else if (TARGET_THUMB1) \ 2436 thumb1_final_prescan_insn (INSN) 2437 2438 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2439 (CODE == '@' || CODE == '|' || CODE == '.' \ 2440 || CODE == '(' || CODE == ')' || CODE == '#' \ 2441 || (TARGET_32BIT && (CODE == '?')) \ 2442 || (TARGET_THUMB2 && (CODE == '!')) \ 2443 || (TARGET_THUMB && (CODE == '_'))) 2444 2445 /* Output an operand of an instruction. */ 2446 #define PRINT_OPERAND(STREAM, X, CODE) \ 2447 arm_print_operand (STREAM, X, CODE) 2448 2449 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2450 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2451 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2452 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2453 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2454 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2455 : 0)))) 2456 2457 /* Output the address of an operand. */ 2458 #define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2459 { \ 2460 int is_minus = GET_CODE (X) == MINUS; \ 2461 \ 2462 if (GET_CODE (X) == REG) \ 2463 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2464 else if (GET_CODE (X) == PLUS || is_minus) \ 2465 { \ 2466 rtx base = XEXP (X, 0); \ 2467 rtx index = XEXP (X, 1); \ 2468 HOST_WIDE_INT offset = 0; \ 2469 if (GET_CODE (base) != REG \ 2470 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \ 2471 { \ 2472 /* Ensure that BASE is a register. */ \ 2473 /* (one of them must be). */ \ 2474 /* Also ensure the SP is not used as in index register. */ \ 2475 rtx temp = base; \ 2476 base = index; \ 2477 index = temp; \ 2478 } \ 2479 switch (GET_CODE (index)) \ 2480 { \ 2481 case CONST_INT: \ 2482 offset = INTVAL (index); \ 2483 if (is_minus) \ 2484 offset = -offset; \ 2485 asm_fprintf (STREAM, "[%r, #%wd]", \ 2486 REGNO (base), offset); \ 2487 break; \ 2488 \ 2489 case REG: \ 2490 asm_fprintf (STREAM, "[%r, %s%r]", \ 2491 REGNO (base), is_minus ? "-" : "", \ 2492 REGNO (index)); \ 2493 break; \ 2494 \ 2495 case MULT: \ 2496 case ASHIFTRT: \ 2497 case LSHIFTRT: \ 2498 case ASHIFT: \ 2499 case ROTATERT: \ 2500 { \ 2501 asm_fprintf (STREAM, "[%r, %s%r", \ 2502 REGNO (base), is_minus ? "-" : "", \ 2503 REGNO (XEXP (index, 0))); \ 2504 arm_print_operand (STREAM, index, 'S'); \ 2505 fputs ("]", STREAM); \ 2506 break; \ 2507 } \ 2508 \ 2509 default: \ 2510 gcc_unreachable (); \ 2511 } \ 2512 } \ 2513 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2514 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2515 { \ 2516 extern enum machine_mode output_memory_reference_mode; \ 2517 \ 2518 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2519 \ 2520 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2521 asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2522 REGNO (XEXP (X, 0)), \ 2523 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2524 GET_MODE_SIZE (output_memory_reference_mode)); \ 2525 else \ 2526 asm_fprintf (STREAM, "[%r], #%s%d", \ 2527 REGNO (XEXP (X, 0)), \ 2528 GET_CODE (X) == POST_DEC ? "-" : "", \ 2529 GET_MODE_SIZE (output_memory_reference_mode)); \ 2530 } \ 2531 else if (GET_CODE (X) == PRE_MODIFY) \ 2532 { \ 2533 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ 2534 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2535 asm_fprintf (STREAM, "#%wd]!", \ 2536 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2537 else \ 2538 asm_fprintf (STREAM, "%r]!", \ 2539 REGNO (XEXP (XEXP (X, 1), 1))); \ 2540 } \ 2541 else if (GET_CODE (X) == POST_MODIFY) \ 2542 { \ 2543 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ 2544 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2545 asm_fprintf (STREAM, "#%wd", \ 2546 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2547 else \ 2548 asm_fprintf (STREAM, "%r", \ 2549 REGNO (XEXP (XEXP (X, 1), 1))); \ 2550 } \ 2551 else output_addr_const (STREAM, X); \ 2552 } 2553 2554 #define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2555 { \ 2556 if (GET_CODE (X) == REG) \ 2557 asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 2558 else if (GET_CODE (X) == POST_INC) \ 2559 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 2560 else if (GET_CODE (X) == PLUS) \ 2561 { \ 2562 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2563 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2564 asm_fprintf (STREAM, "[%r, #%wd]", \ 2565 REGNO (XEXP (X, 0)), \ 2566 INTVAL (XEXP (X, 1))); \ 2567 else \ 2568 asm_fprintf (STREAM, "[%r, %r]", \ 2569 REGNO (XEXP (X, 0)), \ 2570 REGNO (XEXP (X, 1))); \ 2571 } \ 2572 else \ 2573 output_addr_const (STREAM, X); \ 2574 } 2575 2576 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2577 if (TARGET_32BIT) \ 2578 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 2579 else \ 2580 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2581 2582 #define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \ 2583 if (arm_output_addr_const_extra (file, x) == FALSE) \ 2584 goto fail 2585 2586 /* A C expression whose value is RTL representing the value of the return 2587 address for the frame COUNT steps up from the current frame. */ 2588 2589 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2590 arm_return_addr (COUNT, FRAME) 2591 2592 /* Mask of the bits in the PC that contain the real return address 2593 when running in 26-bit mode. */ 2594 #define RETURN_ADDR_MASK26 (0x03fffffc) 2595 2596 /* Pick up the return address upon entry to a procedure. Used for 2597 dwarf2 unwind information. This also enables the table driven 2598 mechanism. */ 2599 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2600 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2601 2602 /* Used to mask out junk bits from the return address, such as 2603 processor state, interrupt status, condition codes and the like. */ 2604 #define MASK_RETURN_ADDR \ 2605 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2606 in 26 bit mode, the condition codes must be masked out of the \ 2607 return address. This does not apply to ARM6 and later processors \ 2608 when running in 32 bit mode. */ \ 2609 ((arm_arch4 || TARGET_THUMB) \ 2610 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2611 : arm_gen_return_addr_mask ()) 2612 2613 2614 /* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have 2616 symbolic names defined here (which would require too much duplication). 2617 FIXME? */ 2618 enum arm_builtins 2619 { 2620 ARM_BUILTIN_GETWCX, 2621 ARM_BUILTIN_SETWCX, 2622 2623 ARM_BUILTIN_WZERO, 2624 2625 ARM_BUILTIN_WAVG2BR, 2626 ARM_BUILTIN_WAVG2HR, 2627 ARM_BUILTIN_WAVG2B, 2628 ARM_BUILTIN_WAVG2H, 2629 2630 ARM_BUILTIN_WACCB, 2631 ARM_BUILTIN_WACCH, 2632 ARM_BUILTIN_WACCW, 2633 2634 ARM_BUILTIN_WMACS, 2635 ARM_BUILTIN_WMACSZ, 2636 ARM_BUILTIN_WMACU, 2637 ARM_BUILTIN_WMACUZ, 2638 2639 ARM_BUILTIN_WSADB, 2640 ARM_BUILTIN_WSADBZ, 2641 ARM_BUILTIN_WSADH, 2642 ARM_BUILTIN_WSADHZ, 2643 2644 ARM_BUILTIN_WALIGN, 2645 2646 ARM_BUILTIN_TMIA, 2647 ARM_BUILTIN_TMIAPH, 2648 ARM_BUILTIN_TMIABB, 2649 ARM_BUILTIN_TMIABT, 2650 ARM_BUILTIN_TMIATB, 2651 ARM_BUILTIN_TMIATT, 2652 2653 ARM_BUILTIN_TMOVMSKB, 2654 ARM_BUILTIN_TMOVMSKH, 2655 ARM_BUILTIN_TMOVMSKW, 2656 2657 ARM_BUILTIN_TBCSTB, 2658 ARM_BUILTIN_TBCSTH, 2659 ARM_BUILTIN_TBCSTW, 2660 2661 ARM_BUILTIN_WMADDS, 2662 ARM_BUILTIN_WMADDU, 2663 2664 ARM_BUILTIN_WPACKHSS, 2665 ARM_BUILTIN_WPACKWSS, 2666 ARM_BUILTIN_WPACKDSS, 2667 ARM_BUILTIN_WPACKHUS, 2668 ARM_BUILTIN_WPACKWUS, 2669 ARM_BUILTIN_WPACKDUS, 2670 2671 ARM_BUILTIN_WADDB, 2672 ARM_BUILTIN_WADDH, 2673 ARM_BUILTIN_WADDW, 2674 ARM_BUILTIN_WADDSSB, 2675 ARM_BUILTIN_WADDSSH, 2676 ARM_BUILTIN_WADDSSW, 2677 ARM_BUILTIN_WADDUSB, 2678 ARM_BUILTIN_WADDUSH, 2679 ARM_BUILTIN_WADDUSW, 2680 ARM_BUILTIN_WSUBB, 2681 ARM_BUILTIN_WSUBH, 2682 ARM_BUILTIN_WSUBW, 2683 ARM_BUILTIN_WSUBSSB, 2684 ARM_BUILTIN_WSUBSSH, 2685 ARM_BUILTIN_WSUBSSW, 2686 ARM_BUILTIN_WSUBUSB, 2687 ARM_BUILTIN_WSUBUSH, 2688 ARM_BUILTIN_WSUBUSW, 2689 2690 ARM_BUILTIN_WAND, 2691 ARM_BUILTIN_WANDN, 2692 ARM_BUILTIN_WOR, 2693 ARM_BUILTIN_WXOR, 2694 2695 ARM_BUILTIN_WCMPEQB, 2696 ARM_BUILTIN_WCMPEQH, 2697 ARM_BUILTIN_WCMPEQW, 2698 ARM_BUILTIN_WCMPGTUB, 2699 ARM_BUILTIN_WCMPGTUH, 2700 ARM_BUILTIN_WCMPGTUW, 2701 ARM_BUILTIN_WCMPGTSB, 2702 ARM_BUILTIN_WCMPGTSH, 2703 ARM_BUILTIN_WCMPGTSW, 2704 2705 ARM_BUILTIN_TEXTRMSB, 2706 ARM_BUILTIN_TEXTRMSH, 2707 ARM_BUILTIN_TEXTRMSW, 2708 ARM_BUILTIN_TEXTRMUB, 2709 ARM_BUILTIN_TEXTRMUH, 2710 ARM_BUILTIN_TEXTRMUW, 2711 ARM_BUILTIN_TINSRB, 2712 ARM_BUILTIN_TINSRH, 2713 ARM_BUILTIN_TINSRW, 2714 2715 ARM_BUILTIN_WMAXSW, 2716 ARM_BUILTIN_WMAXSH, 2717 ARM_BUILTIN_WMAXSB, 2718 ARM_BUILTIN_WMAXUW, 2719 ARM_BUILTIN_WMAXUH, 2720 ARM_BUILTIN_WMAXUB, 2721 ARM_BUILTIN_WMINSW, 2722 ARM_BUILTIN_WMINSH, 2723 ARM_BUILTIN_WMINSB, 2724 ARM_BUILTIN_WMINUW, 2725 ARM_BUILTIN_WMINUH, 2726 ARM_BUILTIN_WMINUB, 2727 2728 ARM_BUILTIN_WMULUM, 2729 ARM_BUILTIN_WMULSM, 2730 ARM_BUILTIN_WMULUL, 2731 2732 ARM_BUILTIN_PSADBH, 2733 ARM_BUILTIN_WSHUFH, 2734 2735 ARM_BUILTIN_WSLLH, 2736 ARM_BUILTIN_WSLLW, 2737 ARM_BUILTIN_WSLLD, 2738 ARM_BUILTIN_WSRAH, 2739 ARM_BUILTIN_WSRAW, 2740 ARM_BUILTIN_WSRAD, 2741 ARM_BUILTIN_WSRLH, 2742 ARM_BUILTIN_WSRLW, 2743 ARM_BUILTIN_WSRLD, 2744 ARM_BUILTIN_WRORH, 2745 ARM_BUILTIN_WRORW, 2746 ARM_BUILTIN_WRORD, 2747 ARM_BUILTIN_WSLLHI, 2748 ARM_BUILTIN_WSLLWI, 2749 ARM_BUILTIN_WSLLDI, 2750 ARM_BUILTIN_WSRAHI, 2751 ARM_BUILTIN_WSRAWI, 2752 ARM_BUILTIN_WSRADI, 2753 ARM_BUILTIN_WSRLHI, 2754 ARM_BUILTIN_WSRLWI, 2755 ARM_BUILTIN_WSRLDI, 2756 ARM_BUILTIN_WRORHI, 2757 ARM_BUILTIN_WRORWI, 2758 ARM_BUILTIN_WRORDI, 2759 2760 ARM_BUILTIN_WUNPCKIHB, 2761 ARM_BUILTIN_WUNPCKIHH, 2762 ARM_BUILTIN_WUNPCKIHW, 2763 ARM_BUILTIN_WUNPCKILB, 2764 ARM_BUILTIN_WUNPCKILH, 2765 ARM_BUILTIN_WUNPCKILW, 2766 2767 ARM_BUILTIN_WUNPCKEHSB, 2768 ARM_BUILTIN_WUNPCKEHSH, 2769 ARM_BUILTIN_WUNPCKEHSW, 2770 ARM_BUILTIN_WUNPCKEHUB, 2771 ARM_BUILTIN_WUNPCKEHUH, 2772 ARM_BUILTIN_WUNPCKEHUW, 2773 ARM_BUILTIN_WUNPCKELSB, 2774 ARM_BUILTIN_WUNPCKELSH, 2775 ARM_BUILTIN_WUNPCKELSW, 2776 ARM_BUILTIN_WUNPCKELUB, 2777 ARM_BUILTIN_WUNPCKELUH, 2778 ARM_BUILTIN_WUNPCKELUW, 2779 2780 ARM_BUILTIN_THREAD_POINTER, 2781 2782 ARM_BUILTIN_NEON_BASE, 2783 2784 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ 2785 }; 2786 2787 /* Do not emit .note.GNU-stack by default. */ 2788 #ifndef NEED_INDICATE_EXEC_STACK 2789 #define NEED_INDICATE_EXEC_STACK 0 2790 #endif 2791 2792 #endif /* ! GCC_ARM_H */ 2793
Indexes created Wed Apr 15 00:22:22 UTC 2026