arm.h revision 1.1.1.10
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2020 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 /* Target CPU versions for D. */ 51 #define TARGET_D_CPU_VERSIONS arm_d_target_versions 52 53 #include "config/arm/arm-opts.h" 54 55 /* The processor for which instructions should be scheduled. */ 56 extern enum processor_type arm_tune; 57 58 typedef enum arm_cond_code 59 { 60 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 61 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 62 } 63 arm_cc; 64 65 extern arm_cc arm_current_cc; 66 67 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 68 69 /* The maximum number of instructions that is beneficial to 70 conditionally execute. */ 71 #undef MAX_CONDITIONAL_EXECUTE 72 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 73 74 extern int arm_target_label; 75 extern int arm_ccfsm_state; 76 extern GTY(()) rtx arm_target_insn; 77 /* Callback to output language specific object attributes. */ 78 extern void (*arm_lang_output_object_attributes_hook)(void); 79 80 /* This type is the user-visible __fp16. We need it in a few places in 81 the backend. Defined in arm-builtins.c. */ 82 extern tree arm_fp16_type_node; 83 84 /* This type is the user-visible __bf16. We need it in a few places in 85 the backend. Defined in arm-builtins.c. */ 86 extern tree arm_bf16_type_node; 87 extern tree arm_bf16_ptr_type_node; 88 89 90 #undef CPP_SPEC 92 #define CPP_SPEC "%(subtarget_cpp_spec) \ 93 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 94 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 95 %{mbig-endian:%{mlittle-endian: \ 96 %e-mbig-endian and -mlittle-endian may not be used together}}" 97 98 #ifndef CC1_SPEC 99 #define CC1_SPEC "" 100 #endif 101 102 /* This macro defines names of additional specifications to put in the specs 103 that can be used in various specifications like CC1_SPEC. Its definition 104 is an initializer with a subgrouping for each command option. 105 106 Each subgrouping contains a string constant, that defines the 107 specification name, and a string constant that used by the GCC driver 108 program. 109 110 Do not define this macro if it does not need to do anything. */ 111 #define EXTRA_SPECS \ 112 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 113 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 114 SUBTARGET_EXTRA_SPECS 115 116 #ifndef SUBTARGET_EXTRA_SPECS 117 #define SUBTARGET_EXTRA_SPECS 118 #endif 119 120 #ifndef SUBTARGET_CPP_SPEC 121 #define SUBTARGET_CPP_SPEC "" 122 #endif 123 124 /* Tree Target Specification. */ 126 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 127 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 128 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 129 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 130 131 /* Run-time Target Specification. */ 132 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 133 the use of floating point instructions and registers but does not prevent 134 emission of floating point pcs attributes. */ 135 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 136 && bitmap_bit_p (arm_active_target.isa, \ 137 isa_bit_vfpv2) \ 138 && TARGET_32BIT) 139 140 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 141 && !TARGET_GENERAL_REGS_ONLY) 142 143 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 144 /* User has permitted use of FP instructions, if they exist for this 145 target. */ 146 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 147 /* Use hardware floating point calling convention. */ 148 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 149 #define TARGET_IWMMXT (arm_arch_iwmmxt) 150 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 151 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 152 && !TARGET_GENERAL_REGS_ONLY) 153 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 154 && !TARGET_GENERAL_REGS_ONLY) 155 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 156 #define TARGET_ARM (! TARGET_THUMB) 157 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 158 #define TARGET_BACKTRACE (crtl->is_leaf \ 159 ? TARGET_TPCS_LEAF_FRAME \ 160 : TARGET_TPCS_FRAME) 161 #define TARGET_AAPCS_BASED \ 162 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 163 164 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 165 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 166 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 167 168 /* Only 16-bit thumb code. */ 169 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 170 /* Arm or Thumb-2 32-bit code. */ 171 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 172 /* 32-bit Thumb-2 code. */ 173 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 174 /* Thumb-1 only. */ 175 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 176 177 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 178 && !TARGET_THUMB1) 179 180 #define TARGET_CRC32 (arm_arch_crc) 181 182 /* The following two macros concern the ability to execute coprocessor 183 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 184 only ever tested when we know we are generating for VFP hardware; we need 185 to be more careful with TARGET_NEON as noted below. */ 186 187 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 188 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 189 190 /* FPU supports VFPv3 instructions. */ 191 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 192 193 /* FPU supports FPv5 instructions. */ 194 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 195 196 /* FPU only supports VFP single-precision instructions. */ 197 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 198 199 /* FPU supports VFP double-precision instructions. */ 200 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 201 202 /* FPU supports half-precision floating-point with NEON element load/store. */ 203 #define TARGET_NEON_FP16 \ 204 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 205 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 206 207 /* FPU supports VFP half-precision floating-point conversions. */ 208 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 209 210 /* FPU supports converting between HFmode and DFmode in a single hardware 211 step. */ 212 #define TARGET_FP16_TO_DOUBLE \ 213 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 214 215 /* FPU supports fused-multiply-add operations. */ 216 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 217 218 /* FPU supports Crypto extensions. */ 219 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 220 221 /* FPU supports Neon instructions. The setting of this macro gets 222 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 223 and TARGET_HARD_FLOAT to ensure that NEON instructions are 224 available. */ 225 #define TARGET_NEON \ 226 (TARGET_32BIT && TARGET_HARD_FLOAT \ 227 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 228 229 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 230 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 231 232 /* Supports the Dot Product AdvSIMD extensions. */ 233 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 234 && bitmap_bit_p (arm_active_target.isa, \ 235 isa_bit_dotprod) \ 236 && arm_arch8_2) 237 238 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 239 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 240 241 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 242 and later. */ 243 #define TARGET_VFP_FP16INST \ 244 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 245 246 /* Target supports the floating point FP16 instructions from ARMv8.2-A 247 and later. */ 248 #define TARGET_FP16FML (TARGET_NEON \ 249 && bitmap_bit_p (arm_active_target.isa, \ 250 isa_bit_fp16fml) \ 251 && arm_arch8_2) 252 253 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 254 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 255 256 /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ 257 #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) 258 259 /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ 260 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ 261 && arm_arch8_2 && arm_arch_bf16) 262 #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ 263 && arm_arch8_2 && arm_arch_bf16) 264 265 /* Q-bit is present. */ 266 #define TARGET_ARM_QBIT \ 267 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 268 /* Saturation operation, e.g. SSAT. */ 269 #define TARGET_ARM_SAT \ 270 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 271 /* "DSP" multiply instructions, eg. SMULxy. */ 272 #define TARGET_DSP_MULTIPLY \ 273 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 274 /* Integer SIMD instructions, and extend-accumulate instructions. */ 275 #define TARGET_INT_SIMD \ 276 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 277 278 /* Should MOVW/MOVT be used in preference to a constant pool. */ 279 #define TARGET_USE_MOVT \ 280 (TARGET_HAVE_MOVT \ 281 && (arm_disable_literal_pool \ 282 || (!optimize_size && !current_tune->prefer_constant_pool))) 283 284 /* Nonzero if this chip provides the DMB instruction. */ 285 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 286 287 /* Nonzero if this chip implements a memory barrier via CP15. */ 288 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 289 && ! TARGET_THUMB1) 290 291 /* Nonzero if this chip implements a memory barrier instruction. */ 292 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 293 294 /* Nonzero if this chip supports ldrex and strex */ 295 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 296 || arm_arch7 \ 297 || (arm_arch8 && !arm_arch_notm)) 298 299 /* Nonzero if this chip supports LPAE. */ 300 #define TARGET_HAVE_LPAE (arm_arch_lpae) 301 302 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 303 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 304 || arm_arch7 \ 305 || (arm_arch8 && !arm_arch_notm)) 306 307 /* Nonzero if this chip supports ldrexd and strexd. */ 308 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 309 || arm_arch7) && arm_arch_notm) 310 311 /* Nonzero if this chip supports load-acquire and store-release. */ 312 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 313 314 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 315 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 316 && TARGET_32BIT \ 317 && arm_arch_notm) 318 319 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 320 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 321 322 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 323 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 324 325 /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions 326 instructions (most are floating-point related). */ 327 #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) 328 329 #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 330 && bitmap_bit_p (arm_active_target.isa, \ 331 isa_bit_mve) \ 332 && !TARGET_GENERAL_REGS_ONLY) 333 334 #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 335 && bitmap_bit_p (arm_active_target.isa, \ 336 isa_bit_mve_float) \ 337 && !TARGET_GENERAL_REGS_ONLY) 338 339 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM 340 alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few 341 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All 342 the VFP instructions, RTL patterns and register are guarded by 343 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers 344 between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE 345 hereafter. */ 346 347 #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 348 && bitmap_bit_p (arm_active_target.isa, \ 349 isa_bit_vfp_base) \ 350 && !TARGET_GENERAL_REGS_ONLY) 351 352 /* Nonzero if integer division instructions supported. */ 353 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 354 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 355 356 /* Nonzero if disallow volatile memory access in IT block. */ 357 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 358 359 /* Nonzero if chip supports the Custom Datapath Extension. */ 360 #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm) 361 362 /* Should constant I be slplit for OP. */ 363 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 364 ((optimize >= 2) \ 365 && can_create_pseudo_p () \ 366 && !const_ok_for_op (i, op)) 367 368 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 369 then TARGET_AAPCS_BASED must be true -- but the converse does not 370 hold. TARGET_BPABI implies the use of the BPABI runtime library, 371 etc., in addition to just the AAPCS calling conventions. */ 372 #ifndef TARGET_BPABI 373 #define TARGET_BPABI false 374 #endif 375 376 /* Transform lane numbers on big endian targets. This is used to allow for the 377 endianness difference between NEON architectural lane numbers and those 378 used in RTL */ 379 #define NEON_ENDIAN_LANE_N(mode, n) \ 380 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 381 382 /* Support for a compile-time default CPU, et cetera. The rules are: 383 --with-arch is ignored if -march or -mcpu are specified. 384 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 385 by --with-arch. 386 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 387 by -march). 388 --with-float is ignored if -mfloat-abi is specified. 389 --with-fpu is ignored if -mfpu is specified. 390 --with-abi is ignored if -mabi is specified. 391 --with-tls is ignored if -mtls-dialect is specified. */ 392 #define OPTION_DEFAULT_SPECS \ 393 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 394 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 395 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 396 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 397 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 398 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 399 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 400 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 401 402 extern const struct arm_fpu_desc 403 { 404 const char *name; 405 enum isa_feature isa_bits[isa_num_bits]; 406 } all_fpus[]; 407 408 /* Which floating point hardware to schedule for. */ 409 extern int arm_fpu_attr; 410 411 #ifndef TARGET_DEFAULT_FLOAT_ABI 412 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 413 #endif 414 415 #ifndef ARM_DEFAULT_ABI 416 #define ARM_DEFAULT_ABI ARM_ABI_APCS 417 #endif 418 419 /* AAPCS based ABIs use short enums by default. */ 420 #ifndef ARM_DEFAULT_SHORT_ENUMS 421 #define ARM_DEFAULT_SHORT_ENUMS \ 422 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 423 #endif 424 425 /* Map each of the micro-architecture variants to their corresponding 426 major architecture revision. */ 427 428 enum base_architecture 429 { 430 BASE_ARCH_0 = 0, 431 BASE_ARCH_2 = 2, 432 BASE_ARCH_3 = 3, 433 BASE_ARCH_3M = 3, 434 BASE_ARCH_4 = 4, 435 BASE_ARCH_4T = 4, 436 BASE_ARCH_5T = 5, 437 BASE_ARCH_5TE = 5, 438 BASE_ARCH_5TEJ = 5, 439 BASE_ARCH_6 = 6, 440 BASE_ARCH_6J = 6, 441 BASE_ARCH_6KZ = 6, 442 BASE_ARCH_6K = 6, 443 BASE_ARCH_6T2 = 6, 444 BASE_ARCH_6M = 6, 445 BASE_ARCH_6Z = 6, 446 BASE_ARCH_7 = 7, 447 BASE_ARCH_7A = 7, 448 BASE_ARCH_7R = 7, 449 BASE_ARCH_7M = 7, 450 BASE_ARCH_7EM = 7, 451 BASE_ARCH_8A = 8, 452 BASE_ARCH_8M_BASE = 8, 453 BASE_ARCH_8M_MAIN = 8, 454 BASE_ARCH_8R = 8 455 }; 456 457 /* The major revision number of the ARM Architecture implemented by the target. */ 458 extern enum base_architecture arm_base_arch; 459 460 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 461 extern int arm_arch4; 462 463 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 464 extern int arm_arch4t; 465 466 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 467 extern int arm_arch5t; 468 469 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 470 extern int arm_arch5te; 471 472 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 473 extern int arm_arch6; 474 475 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 476 extern int arm_arch6k; 477 478 /* Nonzero if instructions present in ARMv6-M can be used. */ 479 extern int arm_arch6m; 480 481 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 482 extern int arm_arch7; 483 484 /* Nonzero if instructions not present in the 'M' profile can be used. */ 485 extern int arm_arch_notm; 486 487 /* Nonzero if instructions present in ARMv7E-M can be used. */ 488 extern int arm_arch7em; 489 490 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 491 extern int arm_arch8; 492 493 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 494 extern int arm_arch8_1; 495 496 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 497 extern int arm_arch8_2; 498 499 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 500 extern int arm_arch8_3; 501 502 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 503 extern int arm_arch8_4; 504 505 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline 506 extensions. */ 507 extern int arm_arch8_1m_main; 508 509 /* Nonzero if this chip supports the FP16 instructions extension of ARM 510 Architecture 8.2. */ 511 extern int arm_fp16_inst; 512 513 /* Nonzero if this chip can benefit from load scheduling. */ 514 extern int arm_ld_sched; 515 516 /* Nonzero if this chip is a StrongARM. */ 517 extern int arm_tune_strongarm; 518 519 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 520 extern int arm_arch_iwmmxt; 521 522 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 523 extern int arm_arch_iwmmxt2; 524 525 /* Nonzero if this chip is an XScale. */ 526 extern int arm_arch_xscale; 527 528 /* Nonzero if tuning for XScale. */ 529 extern int arm_tune_xscale; 530 531 /* Nonzero if tuning for stores via the write buffer. */ 532 extern int arm_tune_wbuf; 533 534 /* Nonzero if tuning for Cortex-A9. */ 535 extern int arm_tune_cortex_a9; 536 537 /* Nonzero if we should define __THUMB_INTERWORK__ in the 538 preprocessor. 539 XXX This is a bit of a hack, it's intended to help work around 540 problems in GLD which doesn't understand that armv5t code is 541 interworking clean. */ 542 extern int arm_cpp_interwork; 543 544 /* Nonzero if chip supports Thumb 1. */ 545 extern int arm_arch_thumb1; 546 547 /* Nonzero if chip supports Thumb 2. */ 548 extern int arm_arch_thumb2; 549 550 /* Nonzero if chip supports integer division instruction in ARM mode. */ 551 extern int arm_arch_arm_hwdiv; 552 553 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 554 extern int arm_arch_thumb_hwdiv; 555 556 /* Nonzero if chip disallows volatile memory access in IT block. */ 557 extern int arm_arch_no_volatile_ce; 558 559 /* Nonzero if we shouldn't use literal pools. */ 560 #ifndef USED_FOR_TARGET 561 extern bool arm_disable_literal_pool; 562 #endif 563 564 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 565 extern int arm_arch_crc; 566 567 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 568 extern int arm_arch_cmse; 569 570 /* Nonzero if chip supports the I8MM instructions. */ 571 extern int arm_arch_i8mm; 572 573 /* Nonzero if chip supports the BFloat16 instructions. */ 574 extern int arm_arch_bf16; 575 576 /* Nonzero if chip supports the Custom Datapath Extension. */ 577 extern int arm_arch_cde; 578 extern int arm_arch_cde_coproc; 579 extern const int arm_arch_cde_coproc_bits[]; 580 #define ARM_CDE_CONST_COPROC 7 581 #define ARM_CCDE_CONST_1 ((1 << 13) - 1) 582 #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1) 583 #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1) 584 #define ARM_VCDE_CONST_1 ((1 << 11) - 1) 585 #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1) 586 #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1) 587 #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1) 588 #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1) 589 #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1) 590 591 #ifndef TARGET_DEFAULT 592 #define TARGET_DEFAULT (MASK_APCS_FRAME) 593 #endif 594 595 /* Nonzero if PIC code requires explicit qualifiers to generate 596 PLT and GOT relocs rather than the assembler doing so implicitly. 597 Subtargets can override these if required. */ 598 #ifndef NEED_GOT_RELOC 599 #define NEED_GOT_RELOC 0 600 #endif 601 #ifndef NEED_PLT_RELOC 602 #define NEED_PLT_RELOC 0 603 #endif 604 605 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 606 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 607 #endif 608 609 /* Nonzero if we need to refer to the GOT with a PC-relative 610 offset. In other words, generate 611 612 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 613 614 rather than 615 616 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 617 618 The default is true, which matches NetBSD. Subtargets can 619 override this if required. */ 620 #ifndef GOT_PCREL 621 #define GOT_PCREL 1 622 #endif 623 624 /* Target machine storage Layout. */ 626 627 628 /* Define this macro if it is advisable to hold scalars in registers 629 in a wider mode than that declared by the program. In such cases, 630 the value is constrained to be within the bounds of the declared 631 type, but kept valid in the wider mode. The signedness of the 632 extension may differ from that of the type. */ 633 634 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 635 if (GET_MODE_CLASS (MODE) == MODE_INT \ 636 && GET_MODE_SIZE (MODE) < 4) \ 637 { \ 638 (MODE) = SImode; \ 639 } 640 641 /* Define this if most significant bit is lowest numbered 642 in instructions that operate on numbered bit-fields. */ 643 #define BITS_BIG_ENDIAN 0 644 645 /* Define this if most significant byte of a word is the lowest numbered. 646 Most ARM processors are run in little endian mode, so that is the default. 647 If you want to have it run-time selectable, change the definition in a 648 cover file to be TARGET_BIG_ENDIAN. */ 649 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 650 651 /* Define this if most significant word of a multiword number is the lowest 652 numbered. */ 653 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 654 655 #define UNITS_PER_WORD 4 656 657 /* True if natural alignment is used for doubleword types. */ 658 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 659 660 #define DOUBLEWORD_ALIGNMENT 64 661 662 #define PARM_BOUNDARY 32 663 664 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 665 666 #define PREFERRED_STACK_BOUNDARY \ 667 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 668 669 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 670 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 671 672 /* The lowest bit is used to indicate Thumb-mode functions, so the 673 vbit must go into the delta field of pointers to member 674 functions. */ 675 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 676 677 #define EMPTY_FIELD_BOUNDARY 32 678 679 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 680 681 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 682 683 /* XXX Blah -- this macro is used directly by libobjc. Since it 684 supports no vector modes, cut out the complexity and fall back 685 on BIGGEST_FIELD_ALIGNMENT. */ 686 #ifdef IN_TARGET_LIBS 687 #define BIGGEST_FIELD_ALIGNMENT 64 688 #endif 689 690 /* Align definitions of arrays, unions and structures so that 691 initializations and copies can be made more efficient. This is not 692 ABI-changing, so it only affects places where we can see the 693 definition. Increasing the alignment tends to introduce padding, 694 so don't do this when optimizing for size/conserving stack space. */ 695 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 696 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 697 && (TREE_CODE (EXP) == ARRAY_TYPE \ 698 || TREE_CODE (EXP) == UNION_TYPE \ 699 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 700 701 /* Align global data. */ 702 #define DATA_ALIGNMENT(EXP, ALIGN) \ 703 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 704 705 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 706 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 707 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 708 709 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 710 value set in previous versions of this toolchain was 8, which produces more 711 compact structures. The command line option -mstructure_size_boundary=<n> 712 can be used to change this value. For compatibility with the ARM SDK 713 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 714 0020D) page 2-20 says "Structures are aligned on word boundaries". 715 The AAPCS specifies a value of 8. */ 716 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 717 718 /* This is the value used to initialize arm_structure_size_boundary. If a 719 particular arm target wants to change the default value it should change 720 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 721 for an example of this. */ 722 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 723 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 724 #endif 725 726 /* Nonzero if move instructions will actually fail to work 727 when given unaligned data. */ 728 #define STRICT_ALIGNMENT 1 729 730 /* wchar_t is unsigned under the AAPCS. */ 731 #ifndef WCHAR_TYPE 732 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 733 734 #define WCHAR_TYPE_SIZE BITS_PER_WORD 735 #endif 736 737 /* Sized for fixed-point types. */ 738 739 #define SHORT_FRACT_TYPE_SIZE 8 740 #define FRACT_TYPE_SIZE 16 741 #define LONG_FRACT_TYPE_SIZE 32 742 #define LONG_LONG_FRACT_TYPE_SIZE 64 743 744 #define SHORT_ACCUM_TYPE_SIZE 16 745 #define ACCUM_TYPE_SIZE 32 746 #define LONG_ACCUM_TYPE_SIZE 64 747 #define LONG_LONG_ACCUM_TYPE_SIZE 64 748 749 #define MAX_FIXED_MODE_SIZE 64 750 751 #ifndef SIZE_TYPE 752 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 753 #endif 754 755 #ifndef PTRDIFF_TYPE 756 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 757 #endif 758 759 /* AAPCS requires that structure alignment is affected by bitfields. */ 760 #ifndef PCC_BITFIELD_TYPE_MATTERS 761 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 762 #endif 763 764 /* The maximum size of the sync library functions supported. */ 765 #ifndef MAX_SYNC_LIBFUNC_SIZE 766 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 767 #endif 768 769 770 /* Standard register usage. */ 772 773 /* Register allocation in ARM Procedure Call Standard 774 (S - saved over call, F - Frame-related). 775 776 r0 * argument word/integer result 777 r1-r3 argument word 778 779 r4-r8 S register variable 780 r9 S (rfp) register variable (real frame pointer) 781 782 r10 F S (sl) stack limit (used by -mapcs-stack-check) 783 r11 F S (fp) argument pointer 784 r12 (ip) temp workspace 785 r13 F S (sp) lower end of current stack frame 786 r14 (lr) link address/workspace 787 r15 F (pc) program counter 788 789 cc This is NOT a real register, but is used internally 790 to represent things that use or set the condition 791 codes. 792 sfp This isn't either. It is used during rtl generation 793 since the offset between the frame pointer and the 794 auto's isn't known until after register allocation. 795 afp Nor this, we only need this because of non-local 796 goto. Without it fp appears to be used and the 797 elimination code won't get rid of sfp. It tracks 798 fp exactly at all times. 799 apsrq Nor this, it is used to track operations on the Q bit 800 of APSR by ACLE saturating intrinsics. 801 apsrge Nor this, it is used to track operations on the GE bits 802 of APSR by ACLE SIMD32 intrinsics 803 804 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 805 806 /* s0-s15 VFP scratch (aka d0-d7). 807 s16-s31 S VFP variable (aka d8-d15). 808 vfpcc Not a real register. Represents the VFP condition 809 code flags. 810 vpr Used to represent MVE VPR predication. */ 811 812 /* The stack backtrace structure is as follows: 813 fp points to here: | save code pointer | [fp] 814 | return link value | [fp, #-4] 815 | return sp value | [fp, #-8] 816 | return fp value | [fp, #-12] 817 [| saved r10 value |] 818 [| saved r9 value |] 819 [| saved r8 value |] 820 [| saved r7 value |] 821 [| saved r6 value |] 822 [| saved r5 value |] 823 [| saved r4 value |] 824 [| saved r3 value |] 825 [| saved r2 value |] 826 [| saved r1 value |] 827 [| saved r0 value |] 828 r0-r3 are not normally saved in a C function. */ 829 830 /* 1 for registers that have pervasive standard uses 831 and are not available for the register allocator. */ 832 #define FIXED_REGISTERS \ 833 { \ 834 /* Core regs. */ \ 835 0,0,0,0,0,0,0,0, \ 836 0,0,0,0,0,1,0,1, \ 837 /* VFP regs. */ \ 838 1,1,1,1,1,1,1,1, \ 839 1,1,1,1,1,1,1,1, \ 840 1,1,1,1,1,1,1,1, \ 841 1,1,1,1,1,1,1,1, \ 842 1,1,1,1,1,1,1,1, \ 843 1,1,1,1,1,1,1,1, \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1,1,1,1,1, \ 846 /* IWMMXT regs. */ \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1,1,1,1,1, \ 849 1,1,1,1, \ 850 /* Specials. */ \ 851 1,1,1,1,1,1,1 \ 852 } 853 854 /* 1 for registers not available across function calls. 855 These must include the FIXED_REGISTERS and also any 856 registers that can be used without being saved. 857 The latter must include the registers where values are returned 858 and the register where structure-value addresses are passed. 859 Aside from that, you can include as many other registers as you like. 860 The CC is not preserved over function calls on the ARM 6, so it is 861 easier to assume this for all. SFP is preserved, since FP is. */ 862 #define CALL_USED_REGISTERS \ 863 { \ 864 /* Core regs. */ \ 865 1,1,1,1,0,0,0,0, \ 866 0,0,0,0,1,1,1,1, \ 867 /* VFP Regs. */ \ 868 1,1,1,1,1,1,1,1, \ 869 1,1,1,1,1,1,1,1, \ 870 1,1,1,1,1,1,1,1, \ 871 1,1,1,1,1,1,1,1, \ 872 1,1,1,1,1,1,1,1, \ 873 1,1,1,1,1,1,1,1, \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1,1,1,1,1, \ 876 /* IWMMXT regs. */ \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1,1,1,1,1, \ 879 1,1,1,1, \ 880 /* Specials. */ \ 881 1,1,1,1,1,1,1 \ 882 } 883 884 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 885 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 886 #endif 887 888 /* These are a couple of extensions to the formats accepted 889 by asm_fprintf: 890 %@ prints out ASM_COMMENT_START 891 %r prints out REGISTER_PREFIX reg_names[arg] */ 892 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 893 case '@': \ 894 fputs (ASM_COMMENT_START, FILE); \ 895 break; \ 896 \ 897 case 'r': \ 898 fputs (REGISTER_PREFIX, FILE); \ 899 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 900 break; 901 902 /* Round X up to the nearest word. */ 903 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 904 905 /* Convert fron bytes to ints. */ 906 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 907 908 /* The number of (integer) registers required to hold a quantity of type MODE. 909 Also used for VFP registers. */ 910 #define ARM_NUM_REGS(MODE) \ 911 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 912 913 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 914 #define ARM_NUM_REGS2(MODE, TYPE) \ 915 ARM_NUM_INTS ((MODE) == BLKmode ? \ 916 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 917 918 /* The number of (integer) argument register available. */ 919 #define NUM_ARG_REGS 4 920 921 /* And similarly for the VFP. */ 922 #define NUM_VFP_ARG_REGS 16 923 924 /* Return the register number of the N'th (integer) argument. */ 925 #define ARG_REGISTER(N) (N - 1) 926 927 /* Specify the registers used for certain standard purposes. 928 The values of these macros are register numbers. */ 929 930 /* The number of the last argument register. */ 931 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 932 933 /* The numbers of the Thumb register ranges. */ 934 #define FIRST_LO_REGNUM 0 935 #define LAST_LO_REGNUM 7 936 #define FIRST_HI_REGNUM 8 937 #define LAST_HI_REGNUM 11 938 939 /* Overridden by config/arm/bpabi.h. */ 940 #ifndef ARM_UNWIND_INFO 941 #define ARM_UNWIND_INFO 0 942 #endif 943 944 /* Overriden by config/arm/netbsd-eabi.h. */ 945 #ifndef ARM_DWARF_UNWIND_TABLES 946 #define ARM_DWARF_UNWIND_TABLES 0 947 #endif 948 949 /* Use r0 and r1 to pass exception handling information. */ 950 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 951 952 /* The register that holds the return address in exception handlers. */ 953 #define ARM_EH_STACKADJ_REGNUM 2 954 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 955 956 #ifndef ARM_TARGET2_DWARF_FORMAT 957 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 958 #endif 959 960 #if ARM_DWARF_UNWIND_TABLES 961 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 962 for 32bit platforms. */ 963 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 964 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 965 : DW_EH_PE_absptr) 966 #else 967 /* ttype entries (the only interesting data references used) 968 use TARGET2 relocations. */ 969 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 970 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 971 : DW_EH_PE_absptr) 972 #endif 973 974 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 975 as an invisible last argument (possible since varargs don't exist in 976 Pascal), so the following is not true. */ 977 #define STATIC_CHAIN_REGNUM 12 978 979 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ 980 #define FDPIC_REGNUM 9 981 982 /* Define this to be where the real frame pointer is if it is not possible to 983 work out the offset between the frame pointer and the automatic variables 984 until after register allocation has taken place. FRAME_POINTER_REGNUM 985 should point to a special register that we will make sure is eliminated. 986 987 For the Thumb we have another problem. The TPCS defines the frame pointer 988 as r11, and GCC believes that it is always possible to use the frame pointer 989 as base register for addressing purposes. (See comments in 990 find_reloads_address()). But - the Thumb does not allow high registers, 991 including r11, to be used as base address registers. Hence our problem. 992 993 The solution used here, and in the old thumb port is to use r7 instead of 994 r11 as the hard frame pointer and to have special code to generate 995 backtrace structures on the stack (if required to do so via a command line 996 option) using r11. This is the only 'user visible' use of r11 as a frame 997 pointer. */ 998 #define ARM_HARD_FRAME_POINTER_REGNUM 11 999 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 1000 1001 #define HARD_FRAME_POINTER_REGNUM \ 1002 (TARGET_ARM \ 1003 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1004 : THUMB_HARD_FRAME_POINTER_REGNUM) 1005 1006 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1007 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1008 1009 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1010 1011 /* Register to use for pushing function arguments. */ 1012 #define STACK_POINTER_REGNUM SP_REGNUM 1013 1014 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1015 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1016 1017 /* Need to sync with WCGR in iwmmxt.md. */ 1018 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1019 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1020 1021 #define IS_IWMMXT_REGNUM(REGNUM) \ 1022 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1023 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1024 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1025 1026 /* Base register for access to local variables of the function. */ 1027 #define FRAME_POINTER_REGNUM 102 1028 1029 /* Base register for access to arguments of the function. */ 1030 #define ARG_POINTER_REGNUM 103 1031 1032 #define FIRST_VFP_REGNUM 16 1033 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1034 #define LAST_VFP_REGNUM \ 1035 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1036 1037 #define IS_VFP_REGNUM(REGNUM) \ 1038 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1039 1040 /* VFP registers are split into two types: those defined by VFP versions < 3 1041 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1042 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1043 in various parts of the backend, we implement as "fake" single-precision 1044 registers (which would be S32-S63, but cannot be used in that way). The 1045 following macros define these ranges of registers. */ 1046 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1047 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1048 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1049 1050 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1051 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1052 1053 /* DFmode values are only valid in even register pairs. */ 1054 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1055 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1056 1057 /* Neon Quad values must start at a multiple of four registers. */ 1058 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1059 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1060 1061 /* Neon structures of vectors must be in even register pairs and there 1062 must be enough registers available. Because of various patterns 1063 requiring quad registers, we require them to start at a multiple of 1064 four. */ 1065 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1066 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1067 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1068 1069 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP 1070 + 1 APSRQ + 1 APSRGE + 1 VPR. */ 1071 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1072 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1073 #define FIRST_PSEUDO_REGISTER 107 1074 1075 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1076 1077 /* Value should be nonzero if functions must have frame pointers. 1078 Zero means the frame pointer need not be set up (and parms may be accessed 1079 via the stack pointer) in functions that seem suitable. 1080 If we have to have a frame pointer we might as well make use of it. 1081 APCS says that the frame pointer does not need to be pushed in leaf 1082 functions, or simple tail call functions. */ 1083 1084 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1085 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1086 #endif 1087 1088 #define VALID_IWMMXT_REG_MODE(MODE) \ 1089 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1090 1091 /* Modes valid for Neon D registers. */ 1092 #define VALID_NEON_DREG_MODE(MODE) \ 1093 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1094 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ 1095 || (MODE) == V4BFmode) 1096 1097 /* Modes valid for Neon Q registers. */ 1098 #define VALID_NEON_QREG_MODE(MODE) \ 1099 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1100 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ 1101 || (MODE) == V8BFmode) 1102 1103 #define VALID_MVE_MODE(MODE) \ 1104 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1105 || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ 1106 || (MODE) == V2DFmode) 1107 1108 #define VALID_MVE_SI_MODE(MODE) \ 1109 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1110 || (MODE) == V16QImode) 1111 1112 #define VALID_MVE_SF_MODE(MODE) \ 1113 ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) 1114 1115 /* Structure modes valid for Neon registers. */ 1116 #define VALID_NEON_STRUCT_MODE(MODE) \ 1117 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1118 || (MODE) == CImode || (MODE) == XImode) 1119 1120 #define VALID_MVE_STRUCT_MODE(MODE) \ 1121 ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) 1122 1123 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1124 extern int arm_regs_in_sequence[]; 1125 1126 /* The order in which register should be allocated. It is good to use ip 1127 since no saving is required (though calls clobber it) and it never contains 1128 function parameters. It is quite good to use lr since other calls may 1129 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1130 least likely to contain a function parameter; in addition results are 1131 returned in r0. 1132 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1133 then D8-D15. The reason for doing this is to attempt to reduce register 1134 pressure when both single- and double-precision registers are used in a 1135 function. */ 1136 1137 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1138 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1139 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1140 1141 #define REG_ALLOC_ORDER \ 1142 { \ 1143 /* General registers. */ \ 1144 3, 2, 1, 0, 12, 14, 4, 5, \ 1145 6, 7, 8, 9, 10, 11, \ 1146 /* High VFP registers. */ \ 1147 VREG(32), VREG(33), VREG(34), VREG(35), \ 1148 VREG(36), VREG(37), VREG(38), VREG(39), \ 1149 VREG(40), VREG(41), VREG(42), VREG(43), \ 1150 VREG(44), VREG(45), VREG(46), VREG(47), \ 1151 VREG(48), VREG(49), VREG(50), VREG(51), \ 1152 VREG(52), VREG(53), VREG(54), VREG(55), \ 1153 VREG(56), VREG(57), VREG(58), VREG(59), \ 1154 VREG(60), VREG(61), VREG(62), VREG(63), \ 1155 /* VFP argument registers. */ \ 1156 VREG(15), VREG(14), VREG(13), VREG(12), \ 1157 VREG(11), VREG(10), VREG(9), VREG(8), \ 1158 VREG(7), VREG(6), VREG(5), VREG(4), \ 1159 VREG(3), VREG(2), VREG(1), VREG(0), \ 1160 /* VFP call-saved registers. */ \ 1161 VREG(16), VREG(17), VREG(18), VREG(19), \ 1162 VREG(20), VREG(21), VREG(22), VREG(23), \ 1163 VREG(24), VREG(25), VREG(26), VREG(27), \ 1164 VREG(28), VREG(29), VREG(30), VREG(31), \ 1165 /* IWMMX registers. */ \ 1166 WREG(0), WREG(1), WREG(2), WREG(3), \ 1167 WREG(4), WREG(5), WREG(6), WREG(7), \ 1168 WREG(8), WREG(9), WREG(10), WREG(11), \ 1169 WREG(12), WREG(13), WREG(14), WREG(15), \ 1170 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1171 /* Registers not for general use. */ \ 1172 CC_REGNUM, VFPCC_REGNUM, \ 1173 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1174 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ 1175 APSRGE_REGNUM, VPR_REGNUM \ 1176 } 1177 1178 #define IS_VPR_REGNUM(REGNUM) \ 1179 ((REGNUM) == VPR_REGNUM) 1180 1181 /* Use different register alloc ordering for Thumb. */ 1182 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1183 1184 /* Tell IRA to use the order we define when optimizing for size. */ 1185 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) 1186 1187 /* Interrupt functions can only use registers that have already been 1188 saved by the prologue, even if they would normally be 1189 call-clobbered. */ 1190 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1191 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1192 df_regs_ever_live_p (DST)) 1193 1194 /* Register and constant classes. */ 1196 1197 /* Register classes. */ 1198 enum reg_class 1199 { 1200 NO_REGS, 1201 LO_REGS, 1202 STACK_REG, 1203 BASE_REGS, 1204 HI_REGS, 1205 CALLER_SAVE_REGS, 1206 EVEN_REG, 1207 GENERAL_REGS, 1208 CORE_REGS, 1209 VFP_D0_D7_REGS, 1210 VFP_LO_REGS, 1211 VFP_HI_REGS, 1212 VFP_REGS, 1213 IWMMXT_REGS, 1214 IWMMXT_GR_REGS, 1215 CC_REG, 1216 VFPCC_REG, 1217 SFP_REG, 1218 AFP_REG, 1219 VPR_REG, 1220 ALL_REGS, 1221 LIM_REG_CLASSES 1222 }; 1223 1224 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1225 1226 /* Give names of register classes as strings for dump file. */ 1227 #define REG_CLASS_NAMES \ 1228 { \ 1229 "NO_REGS", \ 1230 "LO_REGS", \ 1231 "STACK_REG", \ 1232 "BASE_REGS", \ 1233 "HI_REGS", \ 1234 "CALLER_SAVE_REGS", \ 1235 "EVEN_REG", \ 1236 "GENERAL_REGS", \ 1237 "CORE_REGS", \ 1238 "VFP_D0_D7_REGS", \ 1239 "VFP_LO_REGS", \ 1240 "VFP_HI_REGS", \ 1241 "VFP_REGS", \ 1242 "IWMMXT_REGS", \ 1243 "IWMMXT_GR_REGS", \ 1244 "CC_REG", \ 1245 "VFPCC_REG", \ 1246 "SFP_REG", \ 1247 "AFP_REG", \ 1248 "VPR_REG", \ 1249 "ALL_REGS" \ 1250 } 1251 1252 /* Define which registers fit in which classes. 1253 This is an initializer for a vector of HARD_REG_SET 1254 of length N_REG_CLASSES. */ 1255 #define REG_CLASS_CONTENTS \ 1256 { \ 1257 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1258 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1259 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1260 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1261 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1262 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1263 { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ 1264 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1265 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1266 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1267 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1268 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1269 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1270 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1271 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1272 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1273 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1274 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1275 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1276 { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ 1277 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS. */ \ 1278 } 1279 1280 #define FP_SYSREGS \ 1281 DEF_FP_SYSREG (FPSCR) \ 1282 DEF_FP_SYSREG (FPSCR_nzcvqc) \ 1283 DEF_FP_SYSREG (VPR) \ 1284 DEF_FP_SYSREG (P0) \ 1285 DEF_FP_SYSREG (FPCXTNS) \ 1286 DEF_FP_SYSREG (FPCXTS) 1287 1288 #define DEF_FP_SYSREG(reg) reg ## _ENUM, 1289 enum vfp_sysregs_encoding { 1290 FP_SYSREGS 1291 NB_FP_SYSREGS 1292 }; 1293 #undef DEF_FP_SYSREG 1294 extern const char *fp_sysreg_names[NB_FP_SYSREGS]; 1295 1296 /* Any of the VFP register classes. */ 1297 #define IS_VFP_CLASS(X) \ 1298 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1299 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1300 1301 /* The same information, inverted: 1302 Return the class number of the smallest class containing 1303 reg number REGNO. This could be a conditional expression 1304 or could index an array. */ 1305 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1306 1307 /* The class value for index registers, and the one for base regs. */ 1308 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1309 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1310 1311 /* For the Thumb the high registers cannot be used as base registers 1312 when addressing quantities in QI or HI mode; if we don't know the 1313 mode, then we must be conservative. For MVE we need to load from 1314 memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */ 1315 #define MODE_BASE_REG_CLASS(MODE) \ 1316 (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \ 1317 :(TARGET_32BIT ? CORE_REGS \ 1318 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1319 : LO_REGS)) 1320 1321 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1322 instead of BASE_REGS. */ 1323 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1324 1325 /* When this hook returns true for MODE, the compiler allows 1326 registers explicitly used in the rtl to be used as spill registers 1327 but prevents the compiler from extending the lifetime of these 1328 registers. */ 1329 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1330 arm_small_register_classes_for_mode_p 1331 1332 /* Must leave BASE_REGS reloads alone */ 1333 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1334 (lra_in_progress ? NO_REGS \ 1335 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1336 ? ((true_regnum (X) == -1 ? LO_REGS \ 1337 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1338 : NO_REGS)) \ 1339 : NO_REGS)) 1340 1341 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1342 (lra_in_progress ? NO_REGS \ 1343 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1344 ? ((true_regnum (X) == -1 ? LO_REGS \ 1345 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1346 : NO_REGS)) \ 1347 : NO_REGS) 1348 1349 /* Return the register class of a scratch register needed to copy IN into 1350 or out of a register in CLASS in MODE. If it can be done directly, 1351 NO_REGS is returned. */ 1352 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1353 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1354 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1355 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1356 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1357 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1358 : TARGET_32BIT \ 1359 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1360 ? GENERAL_REGS : NO_REGS) \ 1361 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1362 1363 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1364 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1365 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1366 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1367 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1368 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1369 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1370 (TARGET_32BIT ? \ 1371 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1372 && CONSTANT_P (X)) \ 1373 ? GENERAL_REGS : \ 1374 (((MODE) == HImode && ! arm_arch4 \ 1375 && (MEM_P (X) \ 1376 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1377 && true_regnum (X) == -1))) \ 1378 ? GENERAL_REGS : NO_REGS) \ 1379 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1380 1381 /* Return the maximum number of consecutive registers 1382 needed to represent mode MODE in a register of class CLASS. 1383 ARM regs are UNITS_PER_WORD bits. 1384 FIXME: Is this true for iWMMX? */ 1385 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1386 (ARM_NUM_REGS (MODE)) 1387 1388 /* If defined, gives a class of registers that cannot be used as the 1389 operand of a SUBREG that changes the mode of the object illegally. */ 1390 1391 /* Stack layout; function entry, exit and calling. */ 1393 1394 /* Define this if pushing a word on the stack 1395 makes the stack pointer a smaller address. */ 1396 #define STACK_GROWS_DOWNWARD 1 1397 1398 /* Define this to nonzero if the nominal address of the stack frame 1399 is at the high-address end of the local variables; 1400 that is, each additional local variable allocated 1401 goes at a more negative offset in the frame. */ 1402 #define FRAME_GROWS_DOWNWARD 1 1403 1404 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1405 When present, it is one word in size, and sits at the top of the frame, 1406 between the soft frame pointer and either r7 or r11. 1407 1408 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1409 and only then if some outgoing arguments are passed on the stack. It would 1410 be tempting to also check whether the stack arguments are passed by indirect 1411 calls, but there seems to be no reason in principle why a post-reload pass 1412 couldn't convert a direct call into an indirect one. */ 1413 #define CALLER_INTERWORKING_SLOT_SIZE \ 1414 (TARGET_CALLER_INTERWORKING \ 1415 && maybe_ne (crtl->outgoing_args_size, 0) \ 1416 ? UNITS_PER_WORD : 0) 1417 1418 /* If we generate an insn to push BYTES bytes, 1419 this says how many the stack pointer really advances by. */ 1420 /* The push insns do not do this rounding implicitly. 1421 So don't define this. */ 1422 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1423 1424 /* Define this if the maximum size of all the outgoing args is to be 1425 accumulated and pushed during the prologue. The amount can be 1426 found in the variable crtl->outgoing_args_size. */ 1427 #define ACCUMULATE_OUTGOING_ARGS 1 1428 1429 /* Offset of first parameter from the argument pointer register value. */ 1430 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1431 1432 /* Amount of memory needed for an untyped call to save all possible return 1433 registers. */ 1434 #define APPLY_RESULT_SIZE arm_apply_result_size() 1435 1436 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1437 values must be in memory. On the ARM, they need only do so if larger 1438 than a word, or if they contain elements offset from zero in the struct. */ 1439 #define DEFAULT_PCC_STRUCT_RETURN 0 1440 1441 /* These bits describe the different types of function supported 1442 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1443 normal function and an interworked function, for example. Knowing the 1444 type of a function is important for determining its prologue and 1445 epilogue sequences. 1446 Note value 7 is currently unassigned. Also note that the interrupt 1447 function types all have bit 2 set, so that they can be tested for easily. 1448 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1449 machine_function structure is initialized (to zero) func_type will 1450 default to unknown. This will force the first use of arm_current_func_type 1451 to call arm_compute_func_type. */ 1452 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1453 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1454 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1455 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1456 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1457 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1458 1459 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1460 1461 /* In addition functions can have several type modifiers, 1462 outlined by these bit masks: */ 1463 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1464 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1465 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1466 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1467 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1468 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1469 1470 /* Some macros to test these flags. */ 1471 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1472 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1473 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1474 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1475 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1476 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1477 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1478 1479 1480 /* Structure used to hold the function stack frame layout. Offsets are 1481 relative to the stack pointer on function entry. Positive offsets are 1482 in the direction of stack growth. 1483 Only soft_frame is used in thumb mode. */ 1484 1485 typedef struct GTY(()) arm_stack_offsets 1486 { 1487 int saved_args; /* ARG_POINTER_REGNUM. */ 1488 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1489 int saved_regs; 1490 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1491 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1492 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1493 unsigned int saved_regs_mask; 1494 } 1495 arm_stack_offsets; 1496 1497 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1498 /* A C structure for machine-specific, per-function data. 1499 This is added to the cfun structure. */ 1500 typedef struct GTY(()) machine_function 1501 { 1502 /* Additional stack adjustment in __builtin_eh_throw. */ 1503 rtx eh_epilogue_sp_ofs; 1504 /* Records if LR has to be saved for far jumps. */ 1505 int far_jump_used; 1506 /* Records if ARG_POINTER was ever live. */ 1507 int arg_pointer_live; 1508 /* Records if the save of LR has been eliminated. */ 1509 int lr_save_eliminated; 1510 /* The size of the stack frame. Only valid after reload. */ 1511 arm_stack_offsets stack_offsets; 1512 /* Records the type of the current function. */ 1513 unsigned long func_type; 1514 /* Record if the function has a variable argument list. */ 1515 int uses_anonymous_args; 1516 /* Records if sibcalls are blocked because an argument 1517 register is needed to preserve stack alignment. */ 1518 int sibcall_blocked; 1519 /* The PIC register for this function. This might be a pseudo. */ 1520 rtx pic_reg; 1521 /* Labels for per-function Thumb call-via stubs. One per potential calling 1522 register. We can never call via LR or PC. We can call via SP if a 1523 trampoline happens to be on the top of the stack. */ 1524 rtx call_via[14]; 1525 /* Set to 1 when a return insn is output, this means that the epilogue 1526 is not needed. */ 1527 int return_used_this_function; 1528 /* When outputting Thumb-1 code, record the last insn that provides 1529 information about condition codes, and the comparison operands. */ 1530 rtx thumb1_cc_insn; 1531 rtx thumb1_cc_op0; 1532 rtx thumb1_cc_op1; 1533 /* Also record the CC mode that is supported. */ 1534 machine_mode thumb1_cc_mode; 1535 /* Set to 1 after arm_reorg has started. */ 1536 int after_arm_reorg; 1537 /* The number of bytes used to store the static chain register on the 1538 stack, above the stack frame. */ 1539 int static_chain_stack_bytes; 1540 } 1541 machine_function; 1542 #endif 1543 1544 #define ARM_Q_BIT_READ (arm_q_bit_access ()) 1545 #define ARM_GE_BITS_READ (arm_ge_bits_access ()) 1546 1547 /* As in the machine_function, a global set of call-via labels, for code 1548 that is in text_section. */ 1549 extern GTY(()) rtx thumb_call_via_label[14]; 1550 1551 /* The number of potential ways of assigning to a co-processor. */ 1552 #define ARM_NUM_COPROC_SLOTS 1 1553 1554 /* Enumeration of procedure calling standard variants. We don't really 1555 support all of these yet. */ 1556 enum arm_pcs 1557 { 1558 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1559 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1560 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1561 /* This must be the last AAPCS variant. */ 1562 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1563 ARM_PCS_ATPCS, /* ATPCS. */ 1564 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1565 ARM_PCS_UNKNOWN 1566 }; 1567 1568 /* Default procedure calling standard of current compilation unit. */ 1569 extern enum arm_pcs arm_pcs_default; 1570 1571 #if !defined (USED_FOR_TARGET) 1572 /* A C type for declaring a variable that is used as the first argument of 1573 `FUNCTION_ARG' and other related values. */ 1574 typedef struct 1575 { 1576 /* This is the number of registers of arguments scanned so far. */ 1577 int nregs; 1578 /* This is the number of iWMMXt register arguments scanned so far. */ 1579 int iwmmxt_nregs; 1580 int named_count; 1581 int nargs; 1582 /* Which procedure call variant to use for this call. */ 1583 enum arm_pcs pcs_variant; 1584 1585 /* AAPCS related state tracking. */ 1586 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1587 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1588 this argument, or -1 if using core 1589 registers. */ 1590 int aapcs_ncrn; 1591 int aapcs_next_ncrn; 1592 rtx aapcs_reg; /* Register assigned to this argument. */ 1593 int aapcs_partial; /* How many bytes are passed in regs (if 1594 split between core regs and stack. 1595 Zero otherwise. */ 1596 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1597 int can_split; /* Argument can be split between core regs 1598 and the stack. */ 1599 /* Private data for tracking VFP register allocation */ 1600 unsigned aapcs_vfp_regs_free; 1601 unsigned aapcs_vfp_reg_alloc; 1602 int aapcs_vfp_rcount; 1603 MACHMODE aapcs_vfp_rmode; 1604 } CUMULATIVE_ARGS; 1605 #endif 1606 1607 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1608 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1609 1610 /* For AAPCS, padding should never be below the argument. For other ABIs, 1611 * mimic the default. */ 1612 #define PAD_VARARGS_DOWN \ 1613 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1614 1615 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1616 for a call to a function whose data type is FNTYPE. 1617 For a library call, FNTYPE is 0. 1618 On the ARM, the offset starts at 0. */ 1619 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1620 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1621 1622 /* 1 if N is a possible register number for function argument passing. 1623 On the ARM, r0-r3 are used to pass args. */ 1624 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1625 (IN_RANGE ((REGNO), 0, 3) \ 1626 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1627 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1628 || (TARGET_IWMMXT_ABI \ 1629 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1630 1631 1632 /* If your target environment doesn't prefix user functions with an 1634 underscore, you may wish to re-define this to prevent any conflicts. */ 1635 #ifndef ARM_MCOUNT_NAME 1636 #define ARM_MCOUNT_NAME "*mcount" 1637 #endif 1638 1639 /* Call the function profiler with a given profile label. The Acorn 1640 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1641 On the ARM the full profile code will look like: 1642 .data 1643 LP1 1644 .word 0 1645 .text 1646 mov ip, lr 1647 bl mcount 1648 .word LP1 1649 1650 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1651 will output the .text section. 1652 1653 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1654 ``prof'' doesn't seem to mind about this! 1655 1656 Note - this version of the code is designed to work in both ARM and 1657 Thumb modes. */ 1658 #ifndef ARM_FUNCTION_PROFILER 1659 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1660 { \ 1661 char temp[20]; \ 1662 rtx sym; \ 1663 \ 1664 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1665 IP_REGNUM, LR_REGNUM); \ 1666 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1667 fputc ('\n', STREAM); \ 1668 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1669 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1670 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1671 } 1672 #endif 1673 1674 #ifdef THUMB_FUNCTION_PROFILER 1675 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1676 if (TARGET_ARM) \ 1677 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1678 else \ 1679 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1680 #else 1681 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1682 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1683 #endif 1684 1685 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1686 the stack pointer does not matter. The value is tested only in 1687 functions that have frame pointers. 1688 No definition is equivalent to always zero. 1689 1690 On the ARM, the function epilogue recovers the stack pointer from the 1691 frame. */ 1692 #define EXIT_IGNORE_STACK 1 1693 1694 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1695 1696 /* Determine if the epilogue should be output as RTL. 1697 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1698 #define USE_RETURN_INSN(ISCOND) \ 1699 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1700 1701 /* Definitions for register eliminations. 1702 1703 This is an array of structures. Each structure initializes one pair 1704 of eliminable registers. The "from" register number is given first, 1705 followed by "to". Eliminations of the same "from" register are listed 1706 in order of preference. 1707 1708 We have two registers that can be eliminated on the ARM. First, the 1709 arg pointer register can often be eliminated in favor of the stack 1710 pointer register. Secondly, the pseudo frame pointer register can always 1711 be eliminated; it is replaced with either the stack or the real frame 1712 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1713 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1714 1715 #define ELIMINABLE_REGS \ 1716 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1717 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1718 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1719 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1720 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1721 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1722 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1723 1724 /* Define the offset between two registers, one to be eliminated, and the 1725 other its replacement, at the start of a routine. */ 1726 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1727 if (TARGET_ARM) \ 1728 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1729 else \ 1730 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1731 1732 /* Special case handling of the location of arguments passed on the stack. */ 1733 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1734 1735 /* Initialize data used by insn expanders. This is called from insn_emit, 1736 once for every function before code is generated. */ 1737 #define INIT_EXPANDERS arm_init_expanders () 1738 1739 /* Length in units of the trampoline for entering a nested function. */ 1740 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) 1741 1742 /* Alignment required for a trampoline in bits. */ 1743 #define TRAMPOLINE_ALIGNMENT 32 1744 1745 /* Addressing modes, and classification of registers for them. */ 1747 #define HAVE_POST_INCREMENT 1 1748 #define HAVE_PRE_INCREMENT TARGET_32BIT 1749 #define HAVE_POST_DECREMENT TARGET_32BIT 1750 #define HAVE_PRE_DECREMENT TARGET_32BIT 1751 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1752 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1753 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1754 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1755 1756 enum arm_auto_incmodes 1757 { 1758 ARM_POST_INC, 1759 ARM_PRE_INC, 1760 ARM_POST_DEC, 1761 ARM_PRE_DEC 1762 }; 1763 1764 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1765 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1766 #define USE_LOAD_POST_INCREMENT(mode) \ 1767 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1768 #define USE_LOAD_PRE_INCREMENT(mode) \ 1769 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1770 #define USE_LOAD_POST_DECREMENT(mode) \ 1771 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1772 #define USE_LOAD_PRE_DECREMENT(mode) \ 1773 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1774 1775 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1776 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1777 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1778 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1779 1780 /* Macros to check register numbers against specific register classes. */ 1781 1782 /* These assume that REGNO is a hard or pseudo reg number. 1783 They give nonzero only if REGNO is a hard reg of the suitable class 1784 or a pseudo reg currently allocated to a suitable hard reg. */ 1785 #define TEST_REGNO(R, TEST, VALUE) \ 1786 ((R TEST VALUE) \ 1787 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1788 1789 /* Don't allow the pc to be used. */ 1790 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1791 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1792 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1793 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1794 1795 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1796 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1797 || (GET_MODE_SIZE (MODE) >= 4 \ 1798 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1799 1800 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1801 (TARGET_THUMB1 \ 1802 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1803 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1804 1805 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1806 For Thumb, we cannot use SP + reg, so reject SP. */ 1807 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1808 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1809 1810 /* For ARM code, we don't care about the mode, but for Thumb, the index 1811 must be suitable for use in a QImode load. */ 1812 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1813 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1814 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1815 1816 /* Maximum number of registers that can appear in a valid memory address. 1817 Shifts in addresses can't be by a register. */ 1818 #define MAX_REGS_PER_ADDRESS 2 1819 1820 /* Recognize any constant value that is a valid address. */ 1821 /* XXX We can address any constant, eventually... */ 1822 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1823 #define CONSTANT_ADDRESS_P(X) \ 1824 (GET_CODE (X) == SYMBOL_REF \ 1825 && (CONSTANT_POOL_ADDRESS_P (X) \ 1826 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1827 1828 /* True if SYMBOL + OFFSET constants must refer to something within 1829 SYMBOL's section. */ 1830 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1831 1832 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1833 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1834 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1835 #endif 1836 1837 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1838 #define SUBTARGET_NAME_ENCODING_LENGTHS 1839 #endif 1840 1841 /* This is a C fragment for the inside of a switch statement. 1842 Each case label should return the number of characters to 1843 be stripped from the start of a function's name, if that 1844 name starts with the indicated character. */ 1845 #define ARM_NAME_ENCODING_LENGTHS \ 1846 case '*': return 1; \ 1847 SUBTARGET_NAME_ENCODING_LENGTHS 1848 1849 /* This is how to output a reference to a user-level label named NAME. 1850 `assemble_name' uses this. */ 1851 #undef ASM_OUTPUT_LABELREF 1852 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1853 arm_asm_output_labelref (FILE, NAME) 1854 1855 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1856 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1857 if (TARGET_THUMB2) \ 1858 thumb2_asm_output_opcode (STREAM); 1859 1860 /* The EABI specifies that constructors should go in .init_array. 1861 Other targets use .ctors for compatibility. */ 1862 #ifndef ARM_EABI_CTORS_SECTION_OP 1863 #define ARM_EABI_CTORS_SECTION_OP \ 1864 "\t.section\t.init_array,\"aw\",%init_array" 1865 #endif 1866 #ifndef ARM_EABI_DTORS_SECTION_OP 1867 #define ARM_EABI_DTORS_SECTION_OP \ 1868 "\t.section\t.fini_array,\"aw\",%fini_array" 1869 #endif 1870 #define ARM_CTORS_SECTION_OP \ 1871 "\t.section\t.ctors,\"aw\",%progbits" 1872 #define ARM_DTORS_SECTION_OP \ 1873 "\t.section\t.dtors,\"aw\",%progbits" 1874 1875 /* Define CTORS_SECTION_ASM_OP. */ 1876 #undef CTORS_SECTION_ASM_OP 1877 #undef DTORS_SECTION_ASM_OP 1878 #ifndef IN_LIBGCC2 1879 # define CTORS_SECTION_ASM_OP \ 1880 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1881 # define DTORS_SECTION_ASM_OP \ 1882 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1883 #else /* !defined (IN_LIBGCC2) */ 1884 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1885 so we cannot use the definition above. */ 1886 # ifdef __ARM_EABI__ 1887 /* The .ctors section is not part of the EABI, so we do not define 1888 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1889 from trying to use it. We do define it when doing normal 1890 compilation, as .init_array can be used instead of .ctors. */ 1891 /* There is no need to emit begin or end markers when using 1892 init_array; the dynamic linker will compute the size of the 1893 array itself based on special symbols created by the static 1894 linker. However, we do need to arrange to set up 1895 exception-handling here. */ 1896 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1897 # define CTOR_LIST_END /* empty */ 1898 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1899 # define DTOR_LIST_END /* empty */ 1900 # else /* !defined (__ARM_EABI__) */ 1901 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1902 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1903 # endif /* !defined (__ARM_EABI__) */ 1904 #endif /* !defined (IN_LIBCC2) */ 1905 1906 /* True if the operating system can merge entities with vague linkage 1907 (e.g., symbols in COMDAT group) during dynamic linking. */ 1908 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1909 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1910 #endif 1911 1912 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1913 1914 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1915 and check its validity for a certain class. 1916 We have two alternate definitions for each of them. 1917 The usual definition accepts all pseudo regs; the other rejects 1918 them unless they have been allocated suitable hard regs. 1919 The symbol REG_OK_STRICT causes the latter definition to be used. 1920 Thumb-2 has the same restrictions as arm. */ 1921 #ifndef REG_OK_STRICT 1922 1923 #define ARM_REG_OK_FOR_BASE_P(X) \ 1924 (REGNO (X) <= LAST_ARM_REGNUM \ 1925 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1926 || REGNO (X) == FRAME_POINTER_REGNUM \ 1927 || REGNO (X) == ARG_POINTER_REGNUM) 1928 1929 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1930 ((REGNO (X) <= LAST_ARM_REGNUM \ 1931 && REGNO (X) != STACK_POINTER_REGNUM) \ 1932 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1933 || REGNO (X) == FRAME_POINTER_REGNUM \ 1934 || REGNO (X) == ARG_POINTER_REGNUM) 1935 1936 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1937 (REGNO (X) <= LAST_LO_REGNUM \ 1938 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1939 || (GET_MODE_SIZE (MODE) >= 4 \ 1940 && (REGNO (X) == STACK_POINTER_REGNUM \ 1941 || (X) == hard_frame_pointer_rtx \ 1942 || (X) == arg_pointer_rtx))) 1943 1944 #define REG_STRICT_P 0 1945 1946 #else /* REG_OK_STRICT */ 1947 1948 #define ARM_REG_OK_FOR_BASE_P(X) \ 1949 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1950 1951 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1952 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1953 1954 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1955 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1956 1957 #define REG_STRICT_P 1 1958 1959 #endif /* REG_OK_STRICT */ 1960 1961 /* Now define some helpers in terms of the above. */ 1962 1963 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1964 (TARGET_THUMB1 \ 1965 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1966 : ARM_REG_OK_FOR_BASE_P (X)) 1967 1968 /* For 16-bit Thumb, a valid index register is anything that can be used in 1969 a byte load instruction. */ 1970 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1971 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1972 1973 /* Nonzero if X is a hard reg that can be used as an index 1974 or if it is a pseudo reg. On the Thumb, the stack pointer 1975 is not suitable. */ 1976 #define REG_OK_FOR_INDEX_P(X) \ 1977 (TARGET_THUMB1 \ 1978 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1979 : ARM_REG_OK_FOR_INDEX_P (X)) 1980 1981 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1982 For Thumb, we cannot use SP + reg, so reject SP. */ 1983 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1984 REG_OK_FOR_INDEX_P (X) 1985 1986 #define ARM_BASE_REGISTER_RTX_P(X) \ 1988 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1989 1990 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1991 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1992 1993 /* Specify the machine mode that this machine uses 1995 for the index in the tablejump instruction. */ 1996 #define CASE_VECTOR_MODE Pmode 1997 1998 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 1999 || (TARGET_THUMB1 \ 2000 && (optimize_size || flag_pic))) \ 2001 && (!target_pure_code)) 2002 2003 2004 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2005 (TARGET_THUMB1 \ 2006 ? (min >= 0 && max < 512 \ 2007 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2008 : min >= -256 && max < 256 \ 2009 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2010 : min >= 0 && max < 8192 \ 2011 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2012 : min >= -4096 && max < 4096 \ 2013 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2014 : SImode) \ 2015 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2016 : (max >= 0x200) ? HImode \ 2017 : QImode)) 2018 2019 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2020 unsigned is probably best, but may break some code. */ 2021 #ifndef DEFAULT_SIGNED_CHAR 2022 #define DEFAULT_SIGNED_CHAR 0 2023 #endif 2024 2025 /* Max number of bytes we can move from memory to memory 2026 in one reasonably fast instruction. */ 2027 #define MOVE_MAX 4 2028 2029 #undef MOVE_RATIO 2030 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2031 2032 /* Define if operations between registers always perform the operation 2033 on the full register even if a narrower mode is specified. */ 2034 #define WORD_REGISTER_OPERATIONS 1 2035 2036 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2037 will either zero-extend or sign-extend. The value of this macro should 2038 be the code that says which one of the two operations is implicitly 2039 done, UNKNOWN if none. */ 2040 #define LOAD_EXTEND_OP(MODE) \ 2041 (TARGET_THUMB ? ZERO_EXTEND : \ 2042 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2043 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2044 2045 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2046 #define SLOW_BYTE_ACCESS 0 2047 2048 /* Immediate shift counts are truncated by the output routines (or was it 2049 the assembler?). Shift counts in a register are truncated by ARM. Note 2050 that the native compiler puts too large (> 32) immediate shift counts 2051 into a register and shifts by the register, letting the ARM decide what 2052 to do instead of doing that itself. */ 2053 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2054 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2055 On the arm, Y in a register is used modulo 256 for the shift. Only for 2056 rotates is modulo 32 used. */ 2057 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2058 2059 /* Calling from registers is a massive pain. */ 2060 #define NO_FUNCTION_CSE 1 2061 2062 /* The machine modes of pointers and functions */ 2063 #define Pmode SImode 2064 #define FUNCTION_MODE Pmode 2065 2066 #define ARM_FRAME_RTX(X) \ 2067 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2068 || (X) == arg_pointer_rtx) 2069 2070 /* Try to generate sequences that don't involve branches, we can then use 2071 conditional instructions. */ 2072 #define BRANCH_COST(speed_p, predictable_p) \ 2073 ((arm_branch_cost != -1) ? arm_branch_cost : \ 2074 (current_tune->branch_cost (speed_p, predictable_p))) 2075 2076 /* False if short circuit operation is preferred. */ 2077 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2078 ((optimize_size) \ 2079 ? (TARGET_THUMB ? false : true) \ 2080 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 2081 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 2082 2083 2084 /* Position Independent Code. */ 2086 /* We decide which register to use based on the compilation options and 2087 the assembler in use; this is more general than the APCS restriction of 2088 using sb (r9) all the time. */ 2089 extern unsigned arm_pic_register; 2090 2091 /* The register number of the register used to address a table of static 2092 data addresses in memory. */ 2093 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2094 2095 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 2096 entries would need to handle saving and restoring it). */ 2097 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 2098 2099 /* We can't directly access anything that contains a symbol, 2100 nor can we indirect via the constant pool. One exception is 2101 UNSPEC_TLS, which is always PIC. */ 2102 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2103 (!(symbol_mentioned_p (X) \ 2104 || label_mentioned_p (X) \ 2105 || (GET_CODE (X) == SYMBOL_REF \ 2106 && CONSTANT_POOL_ADDRESS_P (X) \ 2107 && (symbol_mentioned_p (get_pool_constant (X)) \ 2108 || label_mentioned_p (get_pool_constant (X))))) \ 2109 || tls_mentioned_p (X)) 2110 2111 /* We may want to save the PIC register if it is a dedicated one. */ 2112 #define PIC_REGISTER_MAY_NEED_SAVING \ 2113 (flag_pic \ 2114 && !TARGET_SINGLE_PIC_BASE \ 2115 && !TARGET_FDPIC \ 2116 && arm_pic_register != INVALID_REGNUM) 2117 2118 /* We need to know when we are making a constant pool; this determines 2119 whether data needs to be in the GOT or can be referenced via a GOT 2120 offset. */ 2121 extern int making_const_table; 2122 2123 /* Handle pragmas for compatibility with Intel's compilers. */ 2125 /* Also abuse this to register additional C specific EABI attributes. */ 2126 #define REGISTER_TARGET_PRAGMAS() do { \ 2127 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2128 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2129 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2130 arm_lang_object_attributes_init(); \ 2131 arm_register_target_pragmas(); \ 2132 } while (0) 2133 2134 /* Condition code information. */ 2135 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2136 return the mode to be used for the comparison. */ 2137 2138 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2139 2140 #define REVERSIBLE_CC_MODE(MODE) 1 2141 2142 #define REVERSE_CONDITION(CODE,MODE) \ 2143 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2144 ? reverse_condition_maybe_unordered (code) \ 2145 : reverse_condition (code)) 2146 2147 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2148 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2149 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2150 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2151 2152 #define CC_STATUS_INIT \ 2154 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2155 2156 #undef ASM_APP_ON 2157 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2158 "\t.syntax divided\n") 2159 2160 #undef ASM_APP_OFF 2161 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2162 "\t.thumb\n\t.syntax unified\n") 2163 2164 /* Output a push or a pop instruction (only used when profiling). 2165 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2166 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2167 that r7 isn't used by the function profiler, so we can use it as a 2168 scratch reg. WARNING: This isn't safe in the general case! It may be 2169 sensitive to future changes in final.c:profile_function. */ 2170 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2171 do \ 2172 { \ 2173 if (TARGET_THUMB1 \ 2174 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2175 { \ 2176 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2177 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2178 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2179 } \ 2180 else \ 2181 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2182 } while (0) 2183 2184 2185 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2186 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2187 do \ 2188 { \ 2189 if (TARGET_THUMB1 \ 2190 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2191 { \ 2192 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2193 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2194 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2195 } \ 2196 else \ 2197 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2198 } while (0) 2199 2200 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2201 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2202 2203 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2204 default alignment from elfos.h. */ 2205 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2206 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2207 2208 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2209 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2210 ? 1 : 0) 2211 2212 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2213 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2214 2215 /* For aliases of functions we use .thumb_set instead. */ 2216 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2217 do \ 2218 { \ 2219 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2220 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2221 \ 2222 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2223 { \ 2224 fprintf (FILE, "\t.thumb_set "); \ 2225 assemble_name (FILE, LABEL1); \ 2226 fprintf (FILE, ","); \ 2227 assemble_name (FILE, LABEL2); \ 2228 fprintf (FILE, "\n"); \ 2229 } \ 2230 else \ 2231 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2232 } \ 2233 while (0) 2234 2235 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2236 /* To support -falign-* switches we need to use .p2align so 2237 that alignment directives in code sections will be padded 2238 with no-op instructions, rather than zeroes. */ 2239 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2240 if ((LOG) != 0) \ 2241 { \ 2242 if ((MAX_SKIP) == 0) \ 2243 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2244 else \ 2245 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2246 (int) (LOG), (int) (MAX_SKIP)); \ 2247 } 2248 #endif 2249 2250 /* Add two bytes to the length of conditionally executed Thumb-2 2252 instructions for the IT instruction. */ 2253 #define ADJUST_INSN_LENGTH(insn, length) \ 2254 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2255 length += 2; 2256 2257 /* Only perform branch elimination (by making instructions conditional) if 2258 we're optimizing. For Thumb-2 check if any IT instructions need 2259 outputting. */ 2260 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2261 if (TARGET_ARM && optimize) \ 2262 arm_final_prescan_insn (INSN); \ 2263 else if (TARGET_THUMB2) \ 2264 thumb2_final_prescan_insn (INSN); \ 2265 else if (TARGET_THUMB1) \ 2266 thumb1_final_prescan_insn (INSN) 2267 2268 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2269 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2270 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2271 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2272 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2273 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2274 : 0)))) 2275 2276 /* A C expression whose value is RTL representing the value of the return 2277 address for the frame COUNT steps up from the current frame. */ 2278 2279 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2280 arm_return_addr (COUNT, FRAME) 2281 2282 /* Mask of the bits in the PC that contain the real return address 2283 when running in 26-bit mode. */ 2284 #define RETURN_ADDR_MASK26 (0x03fffffc) 2285 2286 /* Pick up the return address upon entry to a procedure. Used for 2287 dwarf2 unwind information. This also enables the table driven 2288 mechanism. */ 2289 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2290 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2291 2292 /* Used to mask out junk bits from the return address, such as 2293 processor state, interrupt status, condition codes and the like. */ 2294 #define MASK_RETURN_ADDR \ 2295 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2296 in 26 bit mode, the condition codes must be masked out of the \ 2297 return address. This does not apply to ARM6 and later processors \ 2298 when running in 32 bit mode. */ \ 2299 ((arm_arch4 || TARGET_THUMB) \ 2300 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2301 : arm_gen_return_addr_mask ()) 2302 2303 2304 /* Do not emit .note.GNU-stack by default. */ 2306 #ifndef NEED_INDICATE_EXEC_STACK 2307 #define NEED_INDICATE_EXEC_STACK 0 2308 #endif 2309 2310 #define TARGET_ARM_ARCH \ 2311 (arm_base_arch) \ 2312 2313 /* The highest Thumb instruction set version supported by the chip. */ 2314 #define TARGET_ARM_ARCH_ISA_THUMB \ 2315 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2316 2317 /* Expands to an upper-case char of the target's architectural 2318 profile. */ 2319 #define TARGET_ARM_ARCH_PROFILE \ 2320 (arm_active_target.profile) 2321 2322 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2323 Bit 0 for bytes, up to bit 3 for double-words. */ 2324 #define TARGET_ARM_FEATURE_LDREX \ 2325 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2326 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2327 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2328 2329 /* Set as a bit mask indicating the available widths of hardware floating 2330 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2331 32-bit support, bit 3 indicates 64-bit support. */ 2332 #define TARGET_ARM_FP \ 2333 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2334 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2335 : 0) 2336 2337 2338 /* Set as a bit mask indicating the available widths of floating point 2339 types for hardware NEON floating point. This is the same as 2340 TARGET_ARM_FP without the 64-bit bit set. */ 2341 #define TARGET_NEON_FP \ 2342 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2343 : 0) 2344 2345 /* Name of the automatic fpu-selection option. */ 2346 #define FPUTYPE_AUTO "auto" 2347 2348 /* The maximum number of parallel loads or stores we support in an ldm/stm 2349 instruction. */ 2350 #define MAX_LDM_STM_OPS 4 2351 2352 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2353 extern const char *arm_rewrite_march (int argc, const char **argv); 2354 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2355 #define ASM_CPU_SPEC_FUNCTIONS \ 2356 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2357 { "rewrite_march", arm_rewrite_march }, \ 2358 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2359 2360 #define ASM_CPU_SPEC \ 2361 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2362 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2363 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2364 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2365 " }" 2366 2367 extern const char *arm_target_thumb_only (int argc, const char **argv); 2368 #define TARGET_MODE_SPEC_FUNCTIONS \ 2369 { "target_mode_check", arm_target_thumb_only }, 2370 2371 /* -mcpu=native handling only makes sense with compiler running on 2372 an ARM chip. */ 2373 #if defined(__arm__) && defined(__linux__) 2374 extern const char *host_detect_local_cpu (int argc, const char **argv); 2375 #define HAVE_LOCAL_CPU_DETECT 2376 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2377 { "local_cpu_detect", host_detect_local_cpu }, 2378 # define MCPU_MTUNE_NATIVE_SPECS \ 2379 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2380 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2381 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2382 #else 2383 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2384 # define MCPU_MTUNE_NATIVE_SPECS "" 2385 #endif 2386 2387 const char *arm_canon_arch_option (int argc, const char **argv); 2388 const char *arm_canon_arch_multilib_option (int argc, const char **argv); 2389 2390 #define CANON_ARCH_SPEC_FUNCTION \ 2391 { "canon_arch", arm_canon_arch_option }, 2392 2393 #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2394 { "canon_arch_multilib", arm_canon_arch_multilib_option }, 2395 2396 const char *arm_be8_option (int argc, const char **argv); 2397 #define BE8_SPEC_FUNCTION \ 2398 { "be8_linkopt", arm_be8_option }, 2399 2400 # define EXTRA_SPEC_FUNCTIONS \ 2401 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2402 ASM_CPU_SPEC_FUNCTIONS \ 2403 CANON_ARCH_SPEC_FUNCTION \ 2404 CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2405 TARGET_MODE_SPEC_FUNCTIONS \ 2406 BE8_SPEC_FUNCTION 2407 2408 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2409 via the configuration option --with-mode or via the command line. The 2410 function target_mode_check is called to do the check with either: 2411 - an array of -march values if any is given; 2412 - an array of -mcpu values if any is given; 2413 - an empty array. */ 2414 #define TARGET_MODE_SPECS \ 2415 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2416 2417 /* Generate a canonical string to represent the architecture selected. */ 2418 #define ARCH_CANONICAL_SPECS \ 2419 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2420 " %{march=*: arch %*} " \ 2421 " %{mfpu=*: fpu %*} " \ 2422 " %{mfloat-abi=*: abi %*}" \ 2423 " %<march=*) " 2424 2425 /* Generate a canonical string to represent the architecture selected ignoring 2426 the options not required for multilib linking. */ 2427 #define MULTILIB_ARCH_CANONICAL_SPECS \ 2428 "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \ 2429 " %{march=*: arch %*} " \ 2430 " %{mfpu=*: fpu %*} " \ 2431 " %{mfloat-abi=*: abi %*}" \ 2432 " %<mlibarch=*) " 2433 2434 /* Complete set of specs for the driver. Commas separate the 2435 individual rules so that any option suppression (%<opt...)is 2436 completed before starting subsequent rules. */ 2437 #define DRIVER_SELF_SPECS \ 2438 MCPU_MTUNE_NATIVE_SPECS, \ 2439 TARGET_MODE_SPECS, \ 2440 MULTILIB_ARCH_CANONICAL_SPECS, \ 2441 ARCH_CANONICAL_SPECS 2442 2443 #define TARGET_SUPPORTS_WIDE_INT 1 2444 2445 /* For switching between functions with different target attributes. */ 2446 #define SWITCHABLE_TARGET 1 2447 2448 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2449 representation for SHF_ARM_PURECODE in GCC. */ 2450 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2451 2452 #endif /* ! GCC_ARM_H */ 2453
Indexes created Wed Apr 15 00:22:22 UTC 2026