arm.h revision 1.1.1.11
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2022 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 #include "config/arm/arm-opts.h" 51 52 /* The processor for which instructions should be scheduled. */ 53 extern enum processor_type arm_tune; 54 55 typedef enum arm_cond_code 56 { 57 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 58 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 59 } 60 arm_cc; 61 62 extern arm_cc arm_current_cc; 63 64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 65 66 /* The maximum number of instructions that is beneficial to 67 conditionally execute. */ 68 #undef MAX_CONDITIONAL_EXECUTE 69 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 70 71 extern int arm_target_label; 72 extern int arm_ccfsm_state; 73 extern GTY(()) rtx arm_target_insn; 74 /* Callback to output language specific object attributes. */ 75 extern void (*arm_lang_output_object_attributes_hook)(void); 76 77 /* This type is the user-visible __fp16. We need it in a few places in 78 the backend. Defined in arm-builtins.cc. */ 79 extern tree arm_fp16_type_node; 80 81 /* This type is the user-visible __bf16. We need it in a few places in 82 the backend. Defined in arm-builtins.cc. */ 83 extern tree arm_bf16_type_node; 84 extern tree arm_bf16_ptr_type_node; 85 86 87 #undef CPP_SPEC 89 #define CPP_SPEC "%(subtarget_cpp_spec)" 90 91 #ifndef CC1_SPEC 92 #define CC1_SPEC "" 93 #endif 94 95 /* This macro defines names of additional specifications to put in the specs 96 that can be used in various specifications like CC1_SPEC. Its definition 97 is an initializer with a subgrouping for each command option. 98 99 Each subgrouping contains a string constant, that defines the 100 specification name, and a string constant that used by the GCC driver 101 program. 102 103 Do not define this macro if it does not need to do anything. */ 104 #define EXTRA_SPECS \ 105 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 106 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 107 SUBTARGET_EXTRA_SPECS 108 109 #ifndef SUBTARGET_EXTRA_SPECS 110 #define SUBTARGET_EXTRA_SPECS 111 #endif 112 113 #ifndef SUBTARGET_CPP_SPEC 114 #define SUBTARGET_CPP_SPEC "" 115 #endif 116 117 /* Tree Target Specification. */ 119 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 120 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 121 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 122 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 123 124 /* Run-time Target Specification. */ 125 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 126 the use of floating point instructions and registers but does not prevent 127 emission of floating point pcs attributes. */ 128 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 129 && bitmap_bit_p (arm_active_target.isa, \ 130 isa_bit_vfpv2) \ 131 && TARGET_32BIT) 132 133 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 134 && !TARGET_GENERAL_REGS_ONLY) 135 136 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 137 /* User has permitted use of FP instructions, if they exist for this 138 target. */ 139 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 140 /* Use hardware floating point calling convention. */ 141 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 142 #define TARGET_IWMMXT (arm_arch_iwmmxt) 143 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 144 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 145 && !TARGET_GENERAL_REGS_ONLY) 146 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 147 && !TARGET_GENERAL_REGS_ONLY) 148 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 149 #define TARGET_ARM (! TARGET_THUMB) 150 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 151 #define TARGET_BACKTRACE (crtl->is_leaf \ 152 ? TARGET_TPCS_LEAF_FRAME \ 153 : TARGET_TPCS_FRAME) 154 #define TARGET_AAPCS_BASED \ 155 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 156 157 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 158 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 159 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 160 161 /* Only 16-bit thumb code. */ 162 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 163 /* Arm or Thumb-2 32-bit code. */ 164 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 165 /* 32-bit Thumb-2 code. */ 166 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 167 /* Thumb-1 only. */ 168 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 169 170 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 171 && !TARGET_THUMB1) 172 173 #define TARGET_CRC32 (arm_arch_crc) 174 175 /* Thumb-2 but also has some conditional arithmetic instructions like csinc, 176 csinv, etc. */ 177 #define TARGET_COND_ARITH (arm_arch8_1m_main) 178 179 /* The following two macros concern the ability to execute coprocessor 180 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 181 only ever tested when we know we are generating for VFP hardware; we need 182 to be more careful with TARGET_NEON as noted below. */ 183 184 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 185 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 186 187 /* FPU supports VFPv3 instructions. */ 188 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 189 190 /* FPU supports FPv5 instructions. */ 191 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 192 193 /* FPU only supports VFP single-precision instructions. */ 194 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 195 196 /* FPU supports VFP double-precision instructions. */ 197 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 198 199 /* FPU supports half-precision floating-point with NEON element load/store. */ 200 #define TARGET_NEON_FP16 \ 201 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 202 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 203 204 /* FPU supports VFP half-precision floating-point conversions. */ 205 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 206 207 /* FPU supports converting between HFmode and DFmode in a single hardware 208 step. */ 209 #define TARGET_FP16_TO_DOUBLE \ 210 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 211 212 /* FPU supports fused-multiply-add operations. */ 213 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 214 215 /* FPU supports Crypto extensions. */ 216 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 217 218 /* FPU supports Neon instructions. The setting of this macro gets 219 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 220 and TARGET_HARD_FLOAT to ensure that NEON instructions are 221 available. */ 222 #define TARGET_NEON \ 223 (TARGET_32BIT && TARGET_HARD_FLOAT \ 224 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 225 226 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 227 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 228 229 /* Supports the Dot Product AdvSIMD extensions. */ 230 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 231 && bitmap_bit_p (arm_active_target.isa, \ 232 isa_bit_dotprod) \ 233 && arm_arch8_2) 234 235 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 236 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 237 238 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 239 and later. */ 240 #define TARGET_VFP_FP16INST \ 241 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 242 243 /* Target supports the floating point FP16 instructions from ARMv8.2-A 244 and later. */ 245 #define TARGET_FP16FML (TARGET_NEON \ 246 && bitmap_bit_p (arm_active_target.isa, \ 247 isa_bit_fp16fml) \ 248 && arm_arch8_2) 249 250 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 251 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 252 253 /* FPU supports 8-bit Integer Matrix Multiply (I8MM) AdvSIMD extensions. */ 254 #define TARGET_I8MM (TARGET_NEON && arm_arch8_2 && arm_arch_i8mm) 255 256 /* FPU supports Brain half-precision floating-point (BFloat16) extension. */ 257 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \ 258 && arm_arch8_2 && arm_arch_bf16) 259 #define TARGET_BF16_SIMD (TARGET_NEON && TARGET_VFP5 \ 260 && arm_arch8_2 && arm_arch_bf16) 261 262 /* Q-bit is present. */ 263 #define TARGET_ARM_QBIT \ 264 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 265 /* Saturation operation, e.g. SSAT. */ 266 #define TARGET_ARM_SAT \ 267 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 268 /* "DSP" multiply instructions, eg. SMULxy. */ 269 #define TARGET_DSP_MULTIPLY \ 270 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 271 /* Integer SIMD instructions, and extend-accumulate instructions. */ 272 #define TARGET_INT_SIMD \ 273 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 274 275 /* Should MOVW/MOVT be used in preference to a constant pool. */ 276 #define TARGET_USE_MOVT \ 277 (TARGET_HAVE_MOVT \ 278 && (arm_disable_literal_pool \ 279 || (!optimize_size && !current_tune->prefer_constant_pool))) 280 281 /* Nonzero if this chip provides the DMB instruction. */ 282 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 283 284 /* Nonzero if this chip implements a memory barrier via CP15. */ 285 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 286 && ! TARGET_THUMB1) 287 288 /* Nonzero if this chip implements a memory barrier instruction. */ 289 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 290 291 /* Nonzero if this chip supports ldrex and strex */ 292 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 293 || arm_arch7 \ 294 || (arm_arch8 && !arm_arch_notm)) 295 296 /* Nonzero if this chip supports LPAE. */ 297 #define TARGET_HAVE_LPAE (arm_arch_lpae) 298 299 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 300 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 301 || arm_arch7 \ 302 || (arm_arch8 && !arm_arch_notm)) 303 304 /* Nonzero if this chip supports ldrexd and strexd. */ 305 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 306 || arm_arch7) && arm_arch_notm) 307 308 /* Nonzero if this chip supports load-acquire and store-release. */ 309 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 310 311 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 312 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 313 && TARGET_32BIT \ 314 && arm_arch_notm) 315 316 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 317 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 318 319 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 320 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 321 322 /* Nonzero if this chip provides Armv8.1-M Mainline Security extensions 323 instructions (most are floating-point related). */ 324 #define TARGET_HAVE_FPCXT_CMSE (arm_arch8_1m_main) 325 326 #define TARGET_HAVE_MVE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 327 && bitmap_bit_p (arm_active_target.isa, \ 328 isa_bit_mve) \ 329 && !TARGET_GENERAL_REGS_ONLY) 330 331 #define TARGET_HAVE_MVE_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 332 && bitmap_bit_p (arm_active_target.isa, \ 333 isa_bit_mve_float) \ 334 && !TARGET_GENERAL_REGS_ONLY) 335 336 /* MVE have few common instructions as VFP, like VLDM alias VPOP, VLDR, VSTM 337 alia VPUSH, VSTR and VMOV, VMSR and VMRS. In the same manner it updates few 338 registers such as FPCAR, FPCCR, FPDSCR, FPSCR, MVFR0, MVFR1 and MVFR2. All 339 the VFP instructions, RTL patterns and register are guarded by 340 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers 341 between MVE and VFP will be guarded by the following macro TARGET_VFP_BASE 342 hereafter. */ 343 344 #define TARGET_VFP_BASE (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 345 && bitmap_bit_p (arm_active_target.isa, \ 346 isa_bit_vfp_base) \ 347 && !TARGET_GENERAL_REGS_ONLY) 348 349 /* Nonzero if integer division instructions supported. */ 350 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 351 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 352 353 /* Nonzero if disallow volatile memory access in IT block. */ 354 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 355 356 /* Nonzero if chip supports the Custom Datapath Extension. */ 357 #define TARGET_CDE (arm_arch_cde && arm_arch8 && !arm_arch_notm) 358 359 /* Should constant I be slplit for OP. */ 360 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 361 ((optimize >= 2) \ 362 && can_create_pseudo_p () \ 363 && !const_ok_for_op (i, op)) 364 365 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 366 then TARGET_AAPCS_BASED must be true -- but the converse does not 367 hold. TARGET_BPABI implies the use of the BPABI runtime library, 368 etc., in addition to just the AAPCS calling conventions. */ 369 #ifndef TARGET_BPABI 370 #define TARGET_BPABI false 371 #endif 372 373 /* Transform lane numbers on big endian targets. This is used to allow for the 374 endianness difference between NEON architectural lane numbers and those 375 used in RTL */ 376 #define NEON_ENDIAN_LANE_N(mode, n) \ 377 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 378 379 /* Support for a compile-time default CPU, et cetera. The rules are: 380 --with-arch is ignored if -march or -mcpu are specified. 381 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 382 by --with-arch. 383 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 384 by -march). 385 --with-float is ignored if -mfloat-abi is specified. 386 --with-fpu is ignored if -mfpu is specified. 387 --with-abi is ignored if -mabi is specified. 388 --with-tls is ignored if -mtls-dialect is specified. 389 Note: --with-mode is not handled here, that has a special rule 390 TARGET_MODE_CHECK that also takes into account the selected CPU and 391 architecture. */ 392 #define OPTION_DEFAULT_SPECS \ 393 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 394 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 395 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 396 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 397 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 398 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 399 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 400 401 extern const struct arm_fpu_desc 402 { 403 const char *name; 404 enum isa_feature isa_bits[isa_num_bits]; 405 } all_fpus[]; 406 407 /* Which floating point hardware to schedule for. */ 408 extern int arm_fpu_attr; 409 410 #ifndef TARGET_DEFAULT_FLOAT_ABI 411 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 412 #endif 413 414 #ifndef ARM_DEFAULT_ABI 415 #define ARM_DEFAULT_ABI ARM_ABI_APCS 416 #endif 417 418 /* AAPCS based ABIs use short enums by default. */ 419 #ifndef ARM_DEFAULT_SHORT_ENUMS 420 #define ARM_DEFAULT_SHORT_ENUMS \ 421 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 422 #endif 423 424 /* Map each of the micro-architecture variants to their corresponding 425 major architecture revision. */ 426 427 enum base_architecture 428 { 429 BASE_ARCH_0 = 0, 430 BASE_ARCH_2 = 2, 431 BASE_ARCH_3 = 3, 432 BASE_ARCH_3M = 3, 433 BASE_ARCH_4 = 4, 434 BASE_ARCH_4T = 4, 435 BASE_ARCH_5T = 5, 436 BASE_ARCH_5TE = 5, 437 BASE_ARCH_5TEJ = 5, 438 BASE_ARCH_6 = 6, 439 BASE_ARCH_6J = 6, 440 BASE_ARCH_6KZ = 6, 441 BASE_ARCH_6K = 6, 442 BASE_ARCH_6T2 = 6, 443 BASE_ARCH_6M = 6, 444 BASE_ARCH_6Z = 6, 445 BASE_ARCH_7 = 7, 446 BASE_ARCH_7A = 7, 447 BASE_ARCH_7R = 7, 448 BASE_ARCH_7M = 7, 449 BASE_ARCH_7EM = 7, 450 BASE_ARCH_8A = 8, 451 BASE_ARCH_8M_BASE = 8, 452 BASE_ARCH_8M_MAIN = 8, 453 BASE_ARCH_8R = 8, 454 BASE_ARCH_9A = 9 455 }; 456 457 /* The major revision number of the ARM Architecture implemented by the target. */ 458 extern enum base_architecture arm_base_arch; 459 460 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 461 extern int arm_arch4; 462 463 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 464 extern int arm_arch4t; 465 466 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 467 extern int arm_arch5t; 468 469 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 470 extern int arm_arch5te; 471 472 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 473 extern int arm_arch6; 474 475 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 476 extern int arm_arch6k; 477 478 /* Nonzero if instructions present in ARMv6-M can be used. */ 479 extern int arm_arch6m; 480 481 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 482 extern int arm_arch7; 483 484 /* Nonzero if instructions not present in the 'M' profile can be used. */ 485 extern int arm_arch_notm; 486 487 /* Nonzero if instructions present in ARMv7E-M can be used. */ 488 extern int arm_arch7em; 489 490 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 491 extern int arm_arch8; 492 493 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 494 extern int arm_arch8_1; 495 496 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 497 extern int arm_arch8_2; 498 499 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 500 extern int arm_arch8_3; 501 502 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 503 extern int arm_arch8_4; 504 505 /* Nonzero if this chip supports the ARM Architecture 8.1-M Mainline 506 extensions. */ 507 extern int arm_arch8_1m_main; 508 509 /* Nonzero if this chip supports the FP16 instructions extension of ARM 510 Architecture 8.2. */ 511 extern int arm_fp16_inst; 512 513 /* Nonzero if this chip can benefit from load scheduling. */ 514 extern int arm_ld_sched; 515 516 /* Nonzero if this chip is a StrongARM. */ 517 extern int arm_tune_strongarm; 518 519 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 520 extern int arm_arch_iwmmxt; 521 522 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 523 extern int arm_arch_iwmmxt2; 524 525 /* Nonzero if this chip is an XScale. */ 526 extern int arm_arch_xscale; 527 528 /* Nonzero if tuning for XScale. */ 529 extern int arm_tune_xscale; 530 531 /* Nonzero if tuning for stores via the write buffer. */ 532 extern int arm_tune_wbuf; 533 534 /* Nonzero if tuning for Cortex-A9. */ 535 extern int arm_tune_cortex_a9; 536 537 /* Nonzero if we should define __THUMB_INTERWORK__ in the 538 preprocessor. 539 XXX This is a bit of a hack, it's intended to help work around 540 problems in GLD which doesn't understand that armv5t code is 541 interworking clean. */ 542 extern int arm_cpp_interwork; 543 544 /* Nonzero if chip supports Thumb 1. */ 545 extern int arm_arch_thumb1; 546 547 /* Nonzero if chip supports Thumb 2. */ 548 extern int arm_arch_thumb2; 549 550 /* Nonzero if chip supports integer division instruction in ARM mode. */ 551 extern int arm_arch_arm_hwdiv; 552 553 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 554 extern int arm_arch_thumb_hwdiv; 555 556 /* Nonzero if chip disallows volatile memory access in IT block. */ 557 extern int arm_arch_no_volatile_ce; 558 559 /* Nonzero if we shouldn't use literal pools. */ 560 #ifndef USED_FOR_TARGET 561 extern bool arm_disable_literal_pool; 562 #endif 563 564 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 565 extern int arm_arch_crc; 566 567 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 568 extern int arm_arch_cmse; 569 570 /* Nonzero if chip supports the I8MM instructions. */ 571 extern int arm_arch_i8mm; 572 573 /* Nonzero if chip supports the BFloat16 instructions. */ 574 extern int arm_arch_bf16; 575 576 /* Nonzero if chip supports the Custom Datapath Extension. */ 577 extern int arm_arch_cde; 578 extern int arm_arch_cde_coproc; 579 extern const int arm_arch_cde_coproc_bits[]; 580 #define ARM_CDE_CONST_COPROC 7 581 #define ARM_CCDE_CONST_1 ((1 << 13) - 1) 582 #define ARM_CCDE_CONST_2 ((1 << 9 ) - 1) 583 #define ARM_CCDE_CONST_3 ((1 << 6 ) - 1) 584 #define ARM_VCDE_CONST_1 ((1 << 11) - 1) 585 #define ARM_VCDE_CONST_2 ((1 << 6 ) - 1) 586 #define ARM_VCDE_CONST_3 ((1 << 3 ) - 1) 587 #define ARM_MVE_CDE_CONST_1 ((1 << 12) - 1) 588 #define ARM_MVE_CDE_CONST_2 ((1 << 7 ) - 1) 589 #define ARM_MVE_CDE_CONST_3 ((1 << 4 ) - 1) 590 591 #ifndef TARGET_DEFAULT 592 #define TARGET_DEFAULT (MASK_APCS_FRAME) 593 #endif 594 595 /* Nonzero if PIC code requires explicit qualifiers to generate 596 PLT and GOT relocs rather than the assembler doing so implicitly. 597 Subtargets can override these if required. */ 598 #ifndef NEED_GOT_RELOC 599 #define NEED_GOT_RELOC 0 600 #endif 601 #ifndef NEED_PLT_RELOC 602 #define NEED_PLT_RELOC 0 603 #endif 604 605 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 606 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 607 #endif 608 609 /* Nonzero if we need to refer to the GOT with a PC-relative 610 offset. In other words, generate 611 612 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 613 614 rather than 615 616 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 617 618 The default is true, which matches NetBSD. Subtargets can 619 override this if required. */ 620 #ifndef GOT_PCREL 621 #define GOT_PCREL 1 622 #endif 623 624 /* Target machine storage Layout. */ 626 627 /* Nonzero if this chip provides Armv8.1-M Mainline 628 LOB (low overhead branch features) extension instructions. */ 629 #define TARGET_HAVE_LOB (arm_arch8_1m_main) 630 631 /* Define this macro if it is advisable to hold scalars in registers 632 in a wider mode than that declared by the program. In such cases, 633 the value is constrained to be within the bounds of the declared 634 type, but kept valid in the wider mode. The signedness of the 635 extension may differ from that of the type. */ 636 637 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 638 if (GET_MODE_CLASS (MODE) == MODE_INT \ 639 && GET_MODE_SIZE (MODE) < 4) \ 640 { \ 641 (MODE) = SImode; \ 642 } 643 644 /* Define this if most significant bit is lowest numbered 645 in instructions that operate on numbered bit-fields. */ 646 #define BITS_BIG_ENDIAN 0 647 648 /* Define this if most significant byte of a word is the lowest numbered. 649 Most ARM processors are run in little endian mode, so that is the default. 650 If you want to have it run-time selectable, change the definition in a 651 cover file to be TARGET_BIG_ENDIAN. */ 652 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 653 654 /* Define this if most significant word of a multiword number is the lowest 655 numbered. */ 656 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 657 658 #define UNITS_PER_WORD 4 659 660 /* True if natural alignment is used for doubleword types. */ 661 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 662 663 #define DOUBLEWORD_ALIGNMENT 64 664 665 #define PARM_BOUNDARY 32 666 667 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 668 669 #define PREFERRED_STACK_BOUNDARY \ 670 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 671 672 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 673 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 674 675 /* The lowest bit is used to indicate Thumb-mode functions, so the 676 vbit must go into the delta field of pointers to member 677 functions. */ 678 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 679 680 #define EMPTY_FIELD_BOUNDARY 32 681 682 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 683 684 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 685 686 /* XXX Blah -- this macro is used directly by libobjc. Since it 687 supports no vector modes, cut out the complexity and fall back 688 on BIGGEST_FIELD_ALIGNMENT. */ 689 #ifdef IN_TARGET_LIBS 690 #define BIGGEST_FIELD_ALIGNMENT 64 691 #endif 692 693 /* Align definitions of arrays, unions and structures so that 694 initializations and copies can be made more efficient. This is not 695 ABI-changing, so it only affects places where we can see the 696 definition. Increasing the alignment tends to introduce padding, 697 so don't do this when optimizing for size/conserving stack space. */ 698 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 699 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 700 && (TREE_CODE (EXP) == ARRAY_TYPE \ 701 || TREE_CODE (EXP) == UNION_TYPE \ 702 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 703 704 /* Align global data. */ 705 #define DATA_ALIGNMENT(EXP, ALIGN) \ 706 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 707 708 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 709 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 710 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 711 712 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 713 value set in previous versions of this toolchain was 8, which produces more 714 compact structures. The command line option -mstructure_size_boundary=<n> 715 can be used to change this value. For compatibility with the ARM SDK 716 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 717 0020D) page 2-20 says "Structures are aligned on word boundaries". 718 The AAPCS specifies a value of 8. */ 719 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 720 721 /* This is the value used to initialize arm_structure_size_boundary. If a 722 particular arm target wants to change the default value it should change 723 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 724 for an example of this. */ 725 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 726 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 727 #endif 728 729 /* Nonzero if move instructions will actually fail to work 730 when given unaligned data. */ 731 #define STRICT_ALIGNMENT 1 732 733 /* wchar_t is unsigned under the AAPCS. */ 734 #ifndef WCHAR_TYPE 735 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 736 737 #define WCHAR_TYPE_SIZE BITS_PER_WORD 738 #endif 739 740 /* Sized for fixed-point types. */ 741 742 #define SHORT_FRACT_TYPE_SIZE 8 743 #define FRACT_TYPE_SIZE 16 744 #define LONG_FRACT_TYPE_SIZE 32 745 #define LONG_LONG_FRACT_TYPE_SIZE 64 746 747 #define SHORT_ACCUM_TYPE_SIZE 16 748 #define ACCUM_TYPE_SIZE 32 749 #define LONG_ACCUM_TYPE_SIZE 64 750 #define LONG_LONG_ACCUM_TYPE_SIZE 64 751 752 #define MAX_FIXED_MODE_SIZE 64 753 754 #ifndef SIZE_TYPE 755 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 756 #endif 757 758 #ifndef PTRDIFF_TYPE 759 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 760 #endif 761 762 /* AAPCS requires that structure alignment is affected by bitfields. */ 763 #ifndef PCC_BITFIELD_TYPE_MATTERS 764 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 765 #endif 766 767 /* The maximum size of the sync library functions supported. */ 768 #ifndef MAX_SYNC_LIBFUNC_SIZE 769 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 770 #endif 771 772 773 /* Standard register usage. */ 775 776 /* Register allocation in ARM Procedure Call Standard 777 (S - saved over call, F - Frame-related). 778 779 r0 * argument word/integer result 780 r1-r3 argument word 781 782 r4-r8 S register variable 783 r9 S (rfp) register variable (real frame pointer) 784 785 r10 F S (sl) stack limit (used by -mapcs-stack-check) 786 r11 F S (fp) argument pointer 787 r12 (ip) temp workspace 788 r13 F S (sp) lower end of current stack frame 789 r14 (lr) link address/workspace 790 r15 F (pc) program counter 791 792 cc This is NOT a real register, but is used internally 793 to represent things that use or set the condition 794 codes. 795 sfp This isn't either. It is used during rtl generation 796 since the offset between the frame pointer and the 797 auto's isn't known until after register allocation. 798 afp Nor this, we only need this because of non-local 799 goto. Without it fp appears to be used and the 800 elimination code won't get rid of sfp. It tracks 801 fp exactly at all times. 802 apsrq Nor this, it is used to track operations on the Q bit 803 of APSR by ACLE saturating intrinsics. 804 apsrge Nor this, it is used to track operations on the GE bits 805 of APSR by ACLE SIMD32 intrinsics 806 807 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 808 809 /* s0-s15 VFP scratch (aka d0-d7). 810 s16-s31 S VFP variable (aka d8-d15). 811 vfpcc Not a real register. Represents the VFP condition 812 code flags. 813 vpr Used to represent MVE VPR predication. */ 814 815 /* The stack backtrace structure is as follows: 816 fp points to here: | save code pointer | [fp] 817 | return link value | [fp, #-4] 818 | return sp value | [fp, #-8] 819 | return fp value | [fp, #-12] 820 [| saved r10 value |] 821 [| saved r9 value |] 822 [| saved r8 value |] 823 [| saved r7 value |] 824 [| saved r6 value |] 825 [| saved r5 value |] 826 [| saved r4 value |] 827 [| saved r3 value |] 828 [| saved r2 value |] 829 [| saved r1 value |] 830 [| saved r0 value |] 831 r0-r3 are not normally saved in a C function. */ 832 833 /* 1 for registers that have pervasive standard uses 834 and are not available for the register allocator. */ 835 #define FIXED_REGISTERS \ 836 { \ 837 /* Core regs. */ \ 838 0,0,0,0,0,0,0,0, \ 839 0,0,0,0,0,1,0,1, \ 840 /* VFP regs. */ \ 841 1,1,1,1,1,1,1,1, \ 842 1,1,1,1,1,1,1,1, \ 843 1,1,1,1,1,1,1,1, \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1,1,1,1,1, \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1,1,1,1,1, \ 849 /* IWMMXT regs. */ \ 850 1,1,1,1,1,1,1,1, \ 851 1,1,1,1,1,1,1,1, \ 852 1,1,1,1, \ 853 /* Specials. */ \ 854 1,1,1,1,1,1,1 \ 855 } 856 857 /* 1 for registers not available across function calls. 858 These must include the FIXED_REGISTERS and also any 859 registers that can be used without being saved. 860 The latter must include the registers where values are returned 861 and the register where structure-value addresses are passed. 862 Aside from that, you can include as many other registers as you like. 863 The CC is not preserved over function calls on the ARM 6, so it is 864 easier to assume this for all. SFP is preserved, since FP is. */ 865 #define CALL_USED_REGISTERS \ 866 { \ 867 /* Core regs. */ \ 868 1,1,1,1,0,0,0,0, \ 869 0,0,0,0,1,1,1,1, \ 870 /* VFP Regs. */ \ 871 1,1,1,1,1,1,1,1, \ 872 1,1,1,1,1,1,1,1, \ 873 1,1,1,1,1,1,1,1, \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1,1,1,1,1, \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1,1,1,1,1, \ 879 /* IWMMXT regs. */ \ 880 1,1,1,1,1,1,1,1, \ 881 1,1,1,1,1,1,1,1, \ 882 1,1,1,1, \ 883 /* Specials. */ \ 884 1,1,1,1,1,1,1 \ 885 } 886 887 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 888 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 889 #endif 890 891 /* These are a couple of extensions to the formats accepted 892 by asm_fprintf: 893 %@ prints out ASM_COMMENT_START 894 %r prints out REGISTER_PREFIX reg_names[arg] */ 895 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 896 case '@': \ 897 fputs (ASM_COMMENT_START, FILE); \ 898 break; \ 899 \ 900 case 'r': \ 901 fputs (REGISTER_PREFIX, FILE); \ 902 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 903 break; 904 905 /* Round X up to the nearest word. */ 906 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 907 908 /* Convert fron bytes to ints. */ 909 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 910 911 /* The number of (integer) registers required to hold a quantity of type MODE. 912 Also used for VFP registers. */ 913 #define ARM_NUM_REGS(MODE) \ 914 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 915 916 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 917 #define ARM_NUM_REGS2(MODE, TYPE) \ 918 ARM_NUM_INTS ((MODE) == BLKmode ? \ 919 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 920 921 /* The number of (integer) argument register available. */ 922 #define NUM_ARG_REGS 4 923 924 /* And similarly for the VFP. */ 925 #define NUM_VFP_ARG_REGS 16 926 927 /* Return the register number of the N'th (integer) argument. */ 928 #define ARG_REGISTER(N) (N - 1) 929 930 /* Specify the registers used for certain standard purposes. 931 The values of these macros are register numbers. */ 932 933 /* The number of the last argument register. */ 934 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 935 936 /* The numbers of the Thumb register ranges. */ 937 #define FIRST_LO_REGNUM 0 938 #define LAST_LO_REGNUM 7 939 #define FIRST_HI_REGNUM 8 940 #define LAST_HI_REGNUM 11 941 942 /* Overridden by config/arm/bpabi.h. */ 943 #ifndef ARM_UNWIND_INFO 944 #define ARM_UNWIND_INFO 0 945 #endif 946 947 /* Overriden by config/arm/netbsd-eabi.h. */ 948 #ifndef ARM_DWARF_UNWIND_TABLES 949 #define ARM_DWARF_UNWIND_TABLES 0 950 #endif 951 952 /* Use r0 and r1 to pass exception handling information. */ 953 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 954 955 /* The register that holds the return address in exception handlers. */ 956 #define ARM_EH_STACKADJ_REGNUM 2 957 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 958 959 #ifndef ARM_TARGET2_DWARF_FORMAT 960 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 961 #endif 962 963 #if ARM_DWARF_UNWIND_TABLES 964 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 965 for 32bit platforms. */ 966 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 967 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 968 : DW_EH_PE_absptr) 969 #else 970 /* ttype entries (the only interesting data references used) 971 use TARGET2 relocations. */ 972 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 973 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 974 : DW_EH_PE_absptr) 975 #endif 976 977 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 978 as an invisible last argument (possible since varargs don't exist in 979 Pascal), so the following is not true. */ 980 #define STATIC_CHAIN_REGNUM 12 981 982 /* r9 is the FDPIC register (base register for GOT and FUNCDESC accesses). */ 983 #define FDPIC_REGNUM 9 984 985 /* Define this to be where the real frame pointer is if it is not possible to 986 work out the offset between the frame pointer and the automatic variables 987 until after register allocation has taken place. FRAME_POINTER_REGNUM 988 should point to a special register that we will make sure is eliminated. 989 990 For the Thumb we have another problem. The TPCS defines the frame pointer 991 as r11, and GCC believes that it is always possible to use the frame pointer 992 as base register for addressing purposes. (See comments in 993 find_reloads_address()). But - the Thumb does not allow high registers, 994 including r11, to be used as base address registers. Hence our problem. 995 996 The solution used here, and in the old thumb port is to use r7 instead of 997 r11 as the hard frame pointer and to have special code to generate 998 backtrace structures on the stack (if required to do so via a command line 999 option) using r11. This is the only 'user visible' use of r11 as a frame 1000 pointer. */ 1001 #define ARM_HARD_FRAME_POINTER_REGNUM 11 1002 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 1003 1004 #define HARD_FRAME_POINTER_REGNUM \ 1005 (TARGET_ARM \ 1006 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1007 : THUMB_HARD_FRAME_POINTER_REGNUM) 1008 1009 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1010 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1011 1012 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1013 1014 /* Register to use for pushing function arguments. */ 1015 #define STACK_POINTER_REGNUM SP_REGNUM 1016 1017 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1018 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1019 1020 /* Need to sync with WCGR in iwmmxt.md. */ 1021 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1022 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1023 1024 #define IS_IWMMXT_REGNUM(REGNUM) \ 1025 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1026 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1027 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1028 1029 /* Base register for access to local variables of the function. */ 1030 #define FRAME_POINTER_REGNUM 102 1031 1032 /* Base register for access to arguments of the function. */ 1033 #define ARG_POINTER_REGNUM 103 1034 1035 #define FIRST_VFP_REGNUM 16 1036 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1037 #define LAST_VFP_REGNUM \ 1038 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1039 1040 #define IS_VFP_REGNUM(REGNUM) \ 1041 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1042 1043 /* VFP registers are split into two types: those defined by VFP versions < 3 1044 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1045 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1046 in various parts of the backend, we implement as "fake" single-precision 1047 registers (which would be S32-S63, but cannot be used in that way). The 1048 following macros define these ranges of registers. */ 1049 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1050 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1051 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1052 1053 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1054 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1055 1056 /* DFmode values are only valid in even register pairs. */ 1057 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1058 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1059 1060 /* Neon Quad values must start at a multiple of four registers. */ 1061 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1062 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1063 1064 /* Neon structures of vectors must be in even register pairs and there 1065 must be enough registers available. Because of various patterns 1066 requiring quad registers, we require them to start at a multiple of 1067 four. */ 1068 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1069 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1070 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1071 1072 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP 1073 + 1 APSRQ + 1 APSRGE + 1 VPR. */ 1074 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1075 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1076 #define FIRST_PSEUDO_REGISTER 107 1077 1078 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1079 1080 /* Value should be nonzero if functions must have frame pointers. 1081 Zero means the frame pointer need not be set up (and parms may be accessed 1082 via the stack pointer) in functions that seem suitable. 1083 If we have to have a frame pointer we might as well make use of it. 1084 APCS says that the frame pointer does not need to be pushed in leaf 1085 functions, or simple tail call functions. */ 1086 1087 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1088 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1089 #endif 1090 1091 #define VALID_IWMMXT_REG_MODE(MODE) \ 1092 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1093 1094 /* Modes valid for Neon D registers. */ 1095 #define VALID_NEON_DREG_MODE(MODE) \ 1096 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1097 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode \ 1098 || (MODE) == V4BFmode) 1099 1100 /* Modes valid for Neon Q registers. */ 1101 #define VALID_NEON_QREG_MODE(MODE) \ 1102 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1103 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode \ 1104 || (MODE) == V8BFmode) 1105 1106 #define VALID_MVE_MODE(MODE) \ 1107 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1108 || (MODE) == V16QImode || (MODE) == V8HFmode || (MODE) == V4SFmode \ 1109 || (MODE) == V2DFmode) 1110 1111 #define VALID_MVE_SI_MODE(MODE) \ 1112 ((MODE) == V2DImode ||(MODE) == V4SImode || (MODE) == V8HImode \ 1113 || (MODE) == V16QImode) 1114 1115 /* Modes used in MVE's narrowing stores or widening loads. */ 1116 #define MVE_STN_LDW_MODE(MODE) \ 1117 ((MODE) == V4QImode || (MODE) == V8QImode || (MODE) == V4HImode) 1118 1119 #define VALID_MVE_SF_MODE(MODE) \ 1120 ((MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DFmode) 1121 1122 /* Structure modes valid for Neon registers. */ 1123 #define VALID_NEON_STRUCT_MODE(MODE) \ 1124 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1125 || (MODE) == CImode || (MODE) == XImode) 1126 1127 #define VALID_MVE_STRUCT_MODE(MODE) \ 1128 ((MODE) == TImode || (MODE) == OImode || (MODE) == XImode) 1129 1130 /* The conditions under which vector modes are supported for general 1131 arithmetic using Neon. */ 1132 1133 #define ARM_HAVE_NEON_V8QI_ARITH TARGET_NEON 1134 #define ARM_HAVE_NEON_V4HI_ARITH TARGET_NEON 1135 #define ARM_HAVE_NEON_V2SI_ARITH TARGET_NEON 1136 1137 #define ARM_HAVE_NEON_V16QI_ARITH TARGET_NEON 1138 #define ARM_HAVE_NEON_V8HI_ARITH TARGET_NEON 1139 #define ARM_HAVE_NEON_V4SI_ARITH TARGET_NEON 1140 #define ARM_HAVE_NEON_V2DI_ARITH TARGET_NEON 1141 1142 /* HF operations have their own flush-to-zero control (FPSCR.FZ16). */ 1143 #define ARM_HAVE_NEON_V4HF_ARITH TARGET_NEON_FP16INST 1144 #define ARM_HAVE_NEON_V8HF_ARITH TARGET_NEON_FP16INST 1145 1146 /* SF operations always flush to zero, regardless of FPSCR.FZ, so we can 1147 only use them for general arithmetic when -funsafe-math-optimizations 1148 is in effect. */ 1149 #define ARM_HAVE_NEON_V2SF_ARITH \ 1150 (TARGET_NEON && flag_unsafe_math_optimizations) 1151 #define ARM_HAVE_NEON_V4SF_ARITH ARM_HAVE_NEON_V2SF_ARITH 1152 1153 /* The conditions under which vector modes are supported for general 1154 arithmetic by any vector extension. */ 1155 1156 #define ARM_HAVE_V8QI_ARITH (ARM_HAVE_NEON_V8QI_ARITH || TARGET_REALLY_IWMMXT) 1157 #define ARM_HAVE_V4HI_ARITH (ARM_HAVE_NEON_V4HI_ARITH || TARGET_REALLY_IWMMXT) 1158 #define ARM_HAVE_V2SI_ARITH (ARM_HAVE_NEON_V2SI_ARITH || TARGET_REALLY_IWMMXT) 1159 1160 #define ARM_HAVE_V16QI_ARITH (ARM_HAVE_NEON_V16QI_ARITH || TARGET_HAVE_MVE) 1161 #define ARM_HAVE_V8HI_ARITH (ARM_HAVE_NEON_V8HI_ARITH || TARGET_HAVE_MVE) 1162 #define ARM_HAVE_V4SI_ARITH (ARM_HAVE_NEON_V4SI_ARITH || TARGET_HAVE_MVE) 1163 #define ARM_HAVE_V2DI_ARITH ARM_HAVE_NEON_V2DI_ARITH 1164 1165 #define ARM_HAVE_V4HF_ARITH ARM_HAVE_NEON_V4HF_ARITH 1166 #define ARM_HAVE_V2SF_ARITH ARM_HAVE_NEON_V2SF_ARITH 1167 1168 #define ARM_HAVE_V8HF_ARITH (ARM_HAVE_NEON_V8HF_ARITH || TARGET_HAVE_MVE_FLOAT) 1169 #define ARM_HAVE_V4SF_ARITH (ARM_HAVE_NEON_V4SF_ARITH || TARGET_HAVE_MVE_FLOAT) 1170 1171 /* The conditions under which vector modes are supported by load/store 1172 instructions using Neon. */ 1173 1174 #define ARM_HAVE_NEON_V8QI_LDST TARGET_NEON 1175 #define ARM_HAVE_NEON_V16QI_LDST TARGET_NEON 1176 #define ARM_HAVE_NEON_V4HI_LDST TARGET_NEON 1177 #define ARM_HAVE_NEON_V8HI_LDST TARGET_NEON 1178 #define ARM_HAVE_NEON_V2SI_LDST TARGET_NEON 1179 #define ARM_HAVE_NEON_V4SI_LDST TARGET_NEON 1180 #define ARM_HAVE_NEON_V4HF_LDST TARGET_NEON_FP16INST 1181 #define ARM_HAVE_NEON_V8HF_LDST TARGET_NEON_FP16INST 1182 #define ARM_HAVE_NEON_V4BF_LDST TARGET_BF16_SIMD 1183 #define ARM_HAVE_NEON_V8BF_LDST TARGET_BF16_SIMD 1184 #define ARM_HAVE_NEON_V2SF_LDST TARGET_NEON 1185 #define ARM_HAVE_NEON_V4SF_LDST TARGET_NEON 1186 #define ARM_HAVE_NEON_DI_LDST TARGET_NEON 1187 #define ARM_HAVE_NEON_V2DI_LDST TARGET_NEON 1188 1189 /* The conditions under which vector modes are supported by load/store 1190 instructions by any vector extension. */ 1191 1192 #define ARM_HAVE_V8QI_LDST (ARM_HAVE_NEON_V8QI_LDST || TARGET_REALLY_IWMMXT) 1193 #define ARM_HAVE_V4HI_LDST (ARM_HAVE_NEON_V4HI_LDST || TARGET_REALLY_IWMMXT) 1194 #define ARM_HAVE_V2SI_LDST (ARM_HAVE_NEON_V2SI_LDST || TARGET_REALLY_IWMMXT) 1195 1196 #define ARM_HAVE_V16QI_LDST (ARM_HAVE_NEON_V16QI_LDST || TARGET_HAVE_MVE) 1197 #define ARM_HAVE_V8HI_LDST (ARM_HAVE_NEON_V8HI_LDST || TARGET_HAVE_MVE) 1198 #define ARM_HAVE_V4SI_LDST (ARM_HAVE_NEON_V4SI_LDST || TARGET_HAVE_MVE) 1199 #define ARM_HAVE_DI_LDST ARM_HAVE_NEON_DI_LDST 1200 #define ARM_HAVE_V2DI_LDST ARM_HAVE_NEON_V2DI_LDST 1201 1202 #define ARM_HAVE_V4HF_LDST ARM_HAVE_NEON_V4HF_LDST 1203 #define ARM_HAVE_V2SF_LDST ARM_HAVE_NEON_V2SF_LDST 1204 1205 #define ARM_HAVE_V4BF_LDST ARM_HAVE_NEON_V4BF_LDST 1206 #define ARM_HAVE_V8BF_LDST ARM_HAVE_NEON_V8BF_LDST 1207 1208 #define ARM_HAVE_V8HF_LDST (ARM_HAVE_NEON_V8HF_LDST || TARGET_HAVE_MVE_FLOAT) 1209 #define ARM_HAVE_V4SF_LDST (ARM_HAVE_NEON_V4SF_LDST || TARGET_HAVE_MVE_FLOAT) 1210 1211 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1212 extern int arm_regs_in_sequence[]; 1213 1214 /* The order in which register should be allocated. It is good to use ip 1215 since no saving is required (though calls clobber it) and it never contains 1216 function parameters. It is quite good to use lr since other calls may 1217 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1218 least likely to contain a function parameter; in addition results are 1219 returned in r0. 1220 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1221 then D8-D15. The reason for doing this is to attempt to reduce register 1222 pressure when both single- and double-precision registers are used in a 1223 function. */ 1224 1225 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1226 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1227 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1228 1229 #define REG_ALLOC_ORDER \ 1230 { \ 1231 /* General registers. */ \ 1232 3, 2, 1, 0, 12, 14, 4, 5, \ 1233 6, 7, 8, 9, 10, 11, \ 1234 /* High VFP registers. */ \ 1235 VREG(32), VREG(33), VREG(34), VREG(35), \ 1236 VREG(36), VREG(37), VREG(38), VREG(39), \ 1237 VREG(40), VREG(41), VREG(42), VREG(43), \ 1238 VREG(44), VREG(45), VREG(46), VREG(47), \ 1239 VREG(48), VREG(49), VREG(50), VREG(51), \ 1240 VREG(52), VREG(53), VREG(54), VREG(55), \ 1241 VREG(56), VREG(57), VREG(58), VREG(59), \ 1242 VREG(60), VREG(61), VREG(62), VREG(63), \ 1243 /* VFP argument registers. */ \ 1244 VREG(15), VREG(14), VREG(13), VREG(12), \ 1245 VREG(11), VREG(10), VREG(9), VREG(8), \ 1246 VREG(7), VREG(6), VREG(5), VREG(4), \ 1247 VREG(3), VREG(2), VREG(1), VREG(0), \ 1248 /* VFP call-saved registers. */ \ 1249 VREG(16), VREG(17), VREG(18), VREG(19), \ 1250 VREG(20), VREG(21), VREG(22), VREG(23), \ 1251 VREG(24), VREG(25), VREG(26), VREG(27), \ 1252 VREG(28), VREG(29), VREG(30), VREG(31), \ 1253 /* IWMMX registers. */ \ 1254 WREG(0), WREG(1), WREG(2), WREG(3), \ 1255 WREG(4), WREG(5), WREG(6), WREG(7), \ 1256 WREG(8), WREG(9), WREG(10), WREG(11), \ 1257 WREG(12), WREG(13), WREG(14), WREG(15), \ 1258 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1259 /* Registers not for general use. */ \ 1260 CC_REGNUM, VFPCC_REGNUM, \ 1261 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1262 SP_REGNUM, PC_REGNUM, APSRQ_REGNUM, \ 1263 APSRGE_REGNUM, VPR_REGNUM \ 1264 } 1265 1266 #define IS_VPR_REGNUM(REGNUM) \ 1267 ((REGNUM) == VPR_REGNUM) 1268 1269 /* Use different register alloc ordering for Thumb. */ 1270 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1271 1272 /* Tell IRA to use the order we define when optimizing for size. */ 1273 #define HONOR_REG_ALLOC_ORDER optimize_function_for_size_p (cfun) 1274 1275 /* Interrupt functions can only use registers that have already been 1276 saved by the prologue, even if they would normally be 1277 call-clobbered. */ 1278 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1279 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1280 df_regs_ever_live_p (DST)) 1281 1282 /* Register and constant classes. */ 1284 1285 /* Register classes. */ 1286 enum reg_class 1287 { 1288 NO_REGS, 1289 LO_REGS, 1290 STACK_REG, 1291 BASE_REGS, 1292 HI_REGS, 1293 CALLER_SAVE_REGS, 1294 EVEN_REG, 1295 GENERAL_REGS, 1296 CORE_REGS, 1297 VFP_D0_D7_REGS, 1298 VFP_LO_REGS, 1299 VFP_HI_REGS, 1300 VFP_REGS, 1301 IWMMXT_REGS, 1302 IWMMXT_GR_REGS, 1303 CC_REG, 1304 VFPCC_REG, 1305 SFP_REG, 1306 AFP_REG, 1307 VPR_REG, 1308 GENERAL_AND_VPR_REGS, 1309 ALL_REGS, 1310 LIM_REG_CLASSES 1311 }; 1312 1313 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1314 1315 /* Give names of register classes as strings for dump file. */ 1316 #define REG_CLASS_NAMES \ 1317 { \ 1318 "NO_REGS", \ 1319 "LO_REGS", \ 1320 "STACK_REG", \ 1321 "BASE_REGS", \ 1322 "HI_REGS", \ 1323 "CALLER_SAVE_REGS", \ 1324 "EVEN_REG", \ 1325 "GENERAL_REGS", \ 1326 "CORE_REGS", \ 1327 "VFP_D0_D7_REGS", \ 1328 "VFP_LO_REGS", \ 1329 "VFP_HI_REGS", \ 1330 "VFP_REGS", \ 1331 "IWMMXT_REGS", \ 1332 "IWMMXT_GR_REGS", \ 1333 "CC_REG", \ 1334 "VFPCC_REG", \ 1335 "SFP_REG", \ 1336 "AFP_REG", \ 1337 "VPR_REG", \ 1338 "GENERAL_AND_VPR_REGS", \ 1339 "ALL_REGS" \ 1340 } 1341 1342 /* Define which registers fit in which classes. 1343 This is an initializer for a vector of HARD_REG_SET 1344 of length N_REG_CLASSES. */ 1345 #define REG_CLASS_CONTENTS \ 1346 { \ 1347 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1348 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1349 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1350 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1351 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1352 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1353 { 0x00005555, 0x00000000, 0x00000000, 0x00000000 }, /* EVEN_REGS. */ \ 1354 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1355 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1356 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1357 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1358 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1359 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1360 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1361 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1362 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1363 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1364 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1365 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1366 { 0x00000000, 0x00000000, 0x00000000, 0x00000400 }, /* VPR_REG. */ \ 1367 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000400 }, /* GENERAL_AND_VPR_REGS. */ \ 1368 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000040F } /* ALL_REGS. */ \ 1369 } 1370 1371 #define FP_SYSREGS \ 1372 DEF_FP_SYSREG (FPSCR) \ 1373 DEF_FP_SYSREG (FPSCR_nzcvqc) \ 1374 DEF_FP_SYSREG (VPR) \ 1375 DEF_FP_SYSREG (P0) \ 1376 DEF_FP_SYSREG (FPCXTNS) \ 1377 DEF_FP_SYSREG (FPCXTS) 1378 1379 #define DEF_FP_SYSREG(reg) reg ## _ENUM, 1380 enum vfp_sysregs_encoding { 1381 FP_SYSREGS 1382 NB_FP_SYSREGS 1383 }; 1384 #undef DEF_FP_SYSREG 1385 extern const char *fp_sysreg_names[NB_FP_SYSREGS]; 1386 1387 /* Any of the VFP register classes. */ 1388 #define IS_VFP_CLASS(X) \ 1389 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1390 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1391 1392 /* The same information, inverted: 1393 Return the class number of the smallest class containing 1394 reg number REGNO. This could be a conditional expression 1395 or could index an array. */ 1396 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1397 1398 /* The class value for index registers, and the one for base regs. */ 1399 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1400 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1401 1402 /* For the Thumb the high registers cannot be used as base registers 1403 when addressing quantities in QI or HI mode; if we don't know the 1404 mode, then we must be conservative. For MVE we need to load from 1405 memory to low regs based on given modes i.e [Rn], Rn <= LO_REGS. */ 1406 #define MODE_BASE_REG_CLASS(MODE) \ 1407 (TARGET_HAVE_MVE ? arm_mode_base_reg_class (MODE) \ 1408 :(TARGET_32BIT ? CORE_REGS \ 1409 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1410 : LO_REGS)) 1411 1412 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1413 instead of BASE_REGS. */ 1414 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1415 1416 /* When this hook returns true for MODE, the compiler allows 1417 registers explicitly used in the rtl to be used as spill registers 1418 but prevents the compiler from extending the lifetime of these 1419 registers. */ 1420 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1421 arm_small_register_classes_for_mode_p 1422 1423 /* Must leave BASE_REGS reloads alone */ 1424 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1425 (lra_in_progress ? NO_REGS \ 1426 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1427 ? ((true_regnum (X) == -1 ? LO_REGS \ 1428 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1429 : NO_REGS)) \ 1430 : NO_REGS)) 1431 1432 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1433 (lra_in_progress ? NO_REGS \ 1434 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1435 ? ((true_regnum (X) == -1 ? LO_REGS \ 1436 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1437 : NO_REGS)) \ 1438 : NO_REGS) 1439 1440 /* Return the register class of a scratch register needed to copy IN into 1441 or out of a register in CLASS in MODE. If it can be done directly, 1442 NO_REGS is returned. */ 1443 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1444 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1445 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1446 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1447 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1448 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1449 : TARGET_32BIT \ 1450 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1451 ? GENERAL_REGS : NO_REGS) \ 1452 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1453 1454 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1455 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1456 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1457 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1458 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1459 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1460 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1461 (TARGET_32BIT ? \ 1462 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1463 && CONSTANT_P (X)) \ 1464 ? GENERAL_REGS : \ 1465 (((MODE) == HImode && ! arm_arch4 \ 1466 && (MEM_P (X) \ 1467 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1468 && true_regnum (X) == -1))) \ 1469 ? GENERAL_REGS : NO_REGS) \ 1470 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1471 1472 /* Return the maximum number of consecutive registers 1473 needed to represent mode MODE in a register of class CLASS. 1474 ARM regs are UNITS_PER_WORD bits. 1475 FIXME: Is this true for iWMMX? */ 1476 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1477 (CLASS == VPR_REG) \ 1478 ? CEIL (GET_MODE_SIZE (MODE), 2) \ 1479 : (ARM_NUM_REGS (MODE)) 1480 1481 /* If defined, gives a class of registers that cannot be used as the 1482 operand of a SUBREG that changes the mode of the object illegally. */ 1483 1484 /* Stack layout; function entry, exit and calling. */ 1486 1487 /* Define this if pushing a word on the stack 1488 makes the stack pointer a smaller address. */ 1489 #define STACK_GROWS_DOWNWARD 1 1490 1491 /* Define this to nonzero if the nominal address of the stack frame 1492 is at the high-address end of the local variables; 1493 that is, each additional local variable allocated 1494 goes at a more negative offset in the frame. */ 1495 #define FRAME_GROWS_DOWNWARD 1 1496 1497 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1498 When present, it is one word in size, and sits at the top of the frame, 1499 between the soft frame pointer and either r7 or r11. 1500 1501 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1502 and only then if some outgoing arguments are passed on the stack. It would 1503 be tempting to also check whether the stack arguments are passed by indirect 1504 calls, but there seems to be no reason in principle why a post-reload pass 1505 couldn't convert a direct call into an indirect one. */ 1506 #define CALLER_INTERWORKING_SLOT_SIZE \ 1507 (TARGET_CALLER_INTERWORKING \ 1508 && maybe_ne (crtl->outgoing_args_size, 0) \ 1509 ? UNITS_PER_WORD : 0) 1510 1511 /* If we generate an insn to push BYTES bytes, 1512 this says how many the stack pointer really advances by. */ 1513 /* The push insns do not do this rounding implicitly. 1514 So don't define this. */ 1515 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1516 1517 /* Define this if the maximum size of all the outgoing args is to be 1518 accumulated and pushed during the prologue. The amount can be 1519 found in the variable crtl->outgoing_args_size. */ 1520 #define ACCUMULATE_OUTGOING_ARGS 1 1521 1522 /* Offset of first parameter from the argument pointer register value. */ 1523 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1524 1525 /* Amount of memory needed for an untyped call to save all possible return 1526 registers. */ 1527 #define APPLY_RESULT_SIZE arm_apply_result_size() 1528 1529 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1530 values must be in memory. On the ARM, they need only do so if larger 1531 than a word, or if they contain elements offset from zero in the struct. */ 1532 #define DEFAULT_PCC_STRUCT_RETURN 0 1533 1534 /* These bits describe the different types of function supported 1535 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1536 normal function and an interworked function, for example. Knowing the 1537 type of a function is important for determining its prologue and 1538 epilogue sequences. 1539 Note value 7 is currently unassigned. Also note that the interrupt 1540 function types all have bit 2 set, so that they can be tested for easily. 1541 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1542 machine_function structure is initialized (to zero) func_type will 1543 default to unknown. This will force the first use of arm_current_func_type 1544 to call arm_compute_func_type. */ 1545 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1546 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1547 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1548 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1549 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1550 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1551 1552 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1553 1554 /* In addition functions can have several type modifiers, 1555 outlined by these bit masks: */ 1556 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1557 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1558 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1559 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1560 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1561 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1562 1563 /* Some macros to test these flags. */ 1564 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1565 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1566 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1567 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1568 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1569 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1570 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1571 1572 1573 /* Structure used to hold the function stack frame layout. Offsets are 1574 relative to the stack pointer on function entry. Positive offsets are 1575 in the direction of stack growth. 1576 Only soft_frame is used in thumb mode. */ 1577 1578 typedef struct GTY(()) arm_stack_offsets 1579 { 1580 int saved_args; /* ARG_POINTER_REGNUM. */ 1581 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1582 int saved_regs; 1583 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1584 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1585 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1586 unsigned int saved_regs_mask; 1587 } 1588 arm_stack_offsets; 1589 1590 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1591 /* A C structure for machine-specific, per-function data. 1592 This is added to the cfun structure. */ 1593 typedef struct GTY(()) machine_function 1594 { 1595 /* Additional stack adjustment in __builtin_eh_throw. */ 1596 rtx eh_epilogue_sp_ofs; 1597 /* Records if LR has to be saved for far jumps. */ 1598 int far_jump_used; 1599 /* Records if ARG_POINTER was ever live. */ 1600 int arg_pointer_live; 1601 /* Records if the save of LR has been eliminated. */ 1602 int lr_save_eliminated; 1603 /* The size of the stack frame. Only valid after reload. */ 1604 arm_stack_offsets stack_offsets; 1605 /* Records the type of the current function. */ 1606 unsigned long func_type; 1607 /* Record if the function has a variable argument list. */ 1608 int uses_anonymous_args; 1609 /* Records if sibcalls are blocked because an argument 1610 register is needed to preserve stack alignment. */ 1611 int sibcall_blocked; 1612 /* The PIC register for this function. This might be a pseudo. */ 1613 rtx pic_reg; 1614 /* Labels for per-function Thumb call-via stubs. One per potential calling 1615 register. We can never call via LR or PC. We can call via SP if a 1616 trampoline happens to be on the top of the stack. */ 1617 rtx call_via[14]; 1618 /* Set to 1 when a return insn is output, this means that the epilogue 1619 is not needed. */ 1620 int return_used_this_function; 1621 /* When outputting Thumb-1 code, record the last insn that provides 1622 information about condition codes, and the comparison operands. */ 1623 rtx thumb1_cc_insn; 1624 rtx thumb1_cc_op0; 1625 rtx thumb1_cc_op1; 1626 /* Also record the CC mode that is supported. */ 1627 machine_mode thumb1_cc_mode; 1628 /* Set to 1 after arm_reorg has started. */ 1629 int after_arm_reorg; 1630 /* The number of bytes used to store the static chain register on the 1631 stack, above the stack frame. */ 1632 int static_chain_stack_bytes; 1633 } 1634 machine_function; 1635 #endif 1636 1637 #define ARM_Q_BIT_READ (arm_q_bit_access ()) 1638 #define ARM_GE_BITS_READ (arm_ge_bits_access ()) 1639 1640 /* As in the machine_function, a global set of call-via labels, for code 1641 that is in text_section. */ 1642 extern GTY(()) rtx thumb_call_via_label[14]; 1643 1644 /* The number of potential ways of assigning to a co-processor. */ 1645 #define ARM_NUM_COPROC_SLOTS 1 1646 1647 /* Enumeration of procedure calling standard variants. We don't really 1648 support all of these yet. */ 1649 enum arm_pcs 1650 { 1651 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1652 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1653 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1654 /* This must be the last AAPCS variant. */ 1655 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1656 ARM_PCS_ATPCS, /* ATPCS. */ 1657 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1658 ARM_PCS_UNKNOWN 1659 }; 1660 1661 /* Default procedure calling standard of current compilation unit. */ 1662 extern enum arm_pcs arm_pcs_default; 1663 1664 #if !defined (USED_FOR_TARGET) 1665 /* A C type for declaring a variable that is used as the first argument of 1666 `FUNCTION_ARG' and other related values. */ 1667 typedef struct 1668 { 1669 /* This is the number of registers of arguments scanned so far. */ 1670 int nregs; 1671 /* This is the number of iWMMXt register arguments scanned so far. */ 1672 int iwmmxt_nregs; 1673 int named_count; 1674 int nargs; 1675 /* Which procedure call variant to use for this call. */ 1676 enum arm_pcs pcs_variant; 1677 1678 /* AAPCS related state tracking. */ 1679 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1680 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1681 this argument, or -1 if using core 1682 registers. */ 1683 int aapcs_ncrn; 1684 int aapcs_next_ncrn; 1685 rtx aapcs_reg; /* Register assigned to this argument. */ 1686 int aapcs_partial; /* How many bytes are passed in regs (if 1687 split between core regs and stack. 1688 Zero otherwise. */ 1689 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1690 int can_split; /* Argument can be split between core regs 1691 and the stack. */ 1692 /* Private data for tracking VFP register allocation */ 1693 unsigned aapcs_vfp_regs_free; 1694 unsigned aapcs_vfp_reg_alloc; 1695 int aapcs_vfp_rcount; 1696 MACHMODE aapcs_vfp_rmode; 1697 } CUMULATIVE_ARGS; 1698 #endif 1699 1700 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1701 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1702 1703 /* For AAPCS, padding should never be below the argument. For other ABIs, 1704 * mimic the default. */ 1705 #define PAD_VARARGS_DOWN \ 1706 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1707 1708 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1709 for a call to a function whose data type is FNTYPE. 1710 For a library call, FNTYPE is 0. 1711 On the ARM, the offset starts at 0. */ 1712 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1713 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1714 1715 /* 1 if N is a possible register number for function argument passing. 1716 On the ARM, r0-r3 are used to pass args. */ 1717 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1718 (IN_RANGE ((REGNO), 0, 3) \ 1719 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1720 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1721 || (TARGET_IWMMXT_ABI \ 1722 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1723 1724 1725 /* If your target environment doesn't prefix user functions with an 1727 underscore, you may wish to re-define this to prevent any conflicts. */ 1728 #ifndef ARM_MCOUNT_NAME 1729 #define ARM_MCOUNT_NAME "*mcount" 1730 #endif 1731 1732 /* Call the function profiler with a given profile label. The Acorn 1733 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1734 On the ARM the full profile code will look like: 1735 .data 1736 LP1 1737 .word 0 1738 .text 1739 mov ip, lr 1740 bl mcount 1741 .word LP1 1742 1743 profile_function() in final.cc outputs the .data section, FUNCTION_PROFILER 1744 will output the .text section. 1745 1746 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1747 ``prof'' doesn't seem to mind about this! 1748 1749 Note - this version of the code is designed to work in both ARM and 1750 Thumb modes. */ 1751 #ifndef ARM_FUNCTION_PROFILER 1752 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1753 { \ 1754 char temp[20]; \ 1755 rtx sym; \ 1756 \ 1757 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1758 IP_REGNUM, LR_REGNUM); \ 1759 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1760 fputc ('\n', STREAM); \ 1761 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1762 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1763 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1764 } 1765 #endif 1766 1767 #ifdef THUMB_FUNCTION_PROFILER 1768 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1769 if (TARGET_ARM) \ 1770 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1771 else \ 1772 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1773 #else 1774 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1775 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1776 #endif 1777 1778 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1779 the stack pointer does not matter. The value is tested only in 1780 functions that have frame pointers. 1781 No definition is equivalent to always zero. 1782 1783 On the ARM, the function epilogue recovers the stack pointer from the 1784 frame. */ 1785 #define EXIT_IGNORE_STACK 1 1786 1787 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1788 1789 /* Determine if the epilogue should be output as RTL. 1790 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1791 #define USE_RETURN_INSN(ISCOND) \ 1792 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1793 1794 /* Definitions for register eliminations. 1795 1796 This is an array of structures. Each structure initializes one pair 1797 of eliminable registers. The "from" register number is given first, 1798 followed by "to". Eliminations of the same "from" register are listed 1799 in order of preference. 1800 1801 We have two registers that can be eliminated on the ARM. First, the 1802 arg pointer register can often be eliminated in favor of the stack 1803 pointer register. Secondly, the pseudo frame pointer register can always 1804 be eliminated; it is replaced with either the stack or the real frame 1805 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1806 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1807 1808 #define ELIMINABLE_REGS \ 1809 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1810 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1811 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1812 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1813 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1814 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1815 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1816 1817 /* Define the offset between two registers, one to be eliminated, and the 1818 other its replacement, at the start of a routine. */ 1819 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1820 if (TARGET_ARM) \ 1821 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1822 else \ 1823 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1824 1825 /* Special case handling of the location of arguments passed on the stack. */ 1826 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1827 1828 /* Initialize data used by insn expanders. This is called from insn_emit, 1829 once for every function before code is generated. */ 1830 #define INIT_EXPANDERS arm_init_expanders () 1831 1832 /* Length in units of the trampoline for entering a nested function. */ 1833 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 32 : (TARGET_32BIT ? 16 : 20)) 1834 1835 /* Alignment required for a trampoline in bits. */ 1836 #define TRAMPOLINE_ALIGNMENT 32 1837 1838 /* Addressing modes, and classification of registers for them. */ 1840 #define HAVE_POST_INCREMENT 1 1841 #define HAVE_PRE_INCREMENT TARGET_32BIT 1842 #define HAVE_POST_DECREMENT TARGET_32BIT 1843 #define HAVE_PRE_DECREMENT TARGET_32BIT 1844 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1845 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1846 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1847 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1848 1849 enum arm_auto_incmodes 1850 { 1851 ARM_POST_INC, 1852 ARM_PRE_INC, 1853 ARM_POST_DEC, 1854 ARM_PRE_DEC 1855 }; 1856 1857 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1858 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1859 #define USE_LOAD_POST_INCREMENT(mode) \ 1860 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1861 #define USE_LOAD_PRE_INCREMENT(mode) \ 1862 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1863 #define USE_LOAD_POST_DECREMENT(mode) \ 1864 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1865 #define USE_LOAD_PRE_DECREMENT(mode) \ 1866 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1867 1868 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1869 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1870 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1871 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1872 1873 /* Macros to check register numbers against specific register classes. */ 1874 1875 /* These assume that REGNO is a hard or pseudo reg number. 1876 They give nonzero only if REGNO is a hard reg of the suitable class 1877 or a pseudo reg currently allocated to a suitable hard reg. */ 1878 #define TEST_REGNO(R, TEST, VALUE) \ 1879 ((R TEST VALUE) \ 1880 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1881 1882 /* Don't allow the pc to be used. */ 1883 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1884 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1885 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1886 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1887 1888 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1889 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1890 || (GET_MODE_SIZE (MODE) >= 4 \ 1891 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1892 1893 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1894 (TARGET_THUMB1 \ 1895 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1896 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1897 1898 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1899 For Thumb, we cannot use SP + reg, so reject SP. */ 1900 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1901 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1902 1903 /* For ARM code, we don't care about the mode, but for Thumb, the index 1904 must be suitable for use in a QImode load. */ 1905 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1906 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1907 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1908 1909 /* Maximum number of registers that can appear in a valid memory address. 1910 Shifts in addresses can't be by a register. */ 1911 #define MAX_REGS_PER_ADDRESS 2 1912 1913 /* Recognize any constant value that is a valid address. */ 1914 /* XXX We can address any constant, eventually... */ 1915 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1916 #define CONSTANT_ADDRESS_P(X) \ 1917 (GET_CODE (X) == SYMBOL_REF \ 1918 && (CONSTANT_POOL_ADDRESS_P (X) \ 1919 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1920 1921 /* True if SYMBOL + OFFSET constants must refer to something within 1922 SYMBOL's section. */ 1923 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1924 1925 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1926 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1927 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1928 #endif 1929 1930 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1931 #define SUBTARGET_NAME_ENCODING_LENGTHS 1932 #endif 1933 1934 /* This is a C fragment for the inside of a switch statement. 1935 Each case label should return the number of characters to 1936 be stripped from the start of a function's name, if that 1937 name starts with the indicated character. */ 1938 #define ARM_NAME_ENCODING_LENGTHS \ 1939 case '*': return 1; \ 1940 SUBTARGET_NAME_ENCODING_LENGTHS 1941 1942 /* This is how to output a reference to a user-level label named NAME. 1943 `assemble_name' uses this. */ 1944 #undef ASM_OUTPUT_LABELREF 1945 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1946 arm_asm_output_labelref (FILE, NAME) 1947 1948 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1949 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1950 if (TARGET_THUMB2) \ 1951 thumb2_asm_output_opcode (STREAM); 1952 1953 /* The EABI specifies that constructors should go in .init_array. 1954 Other targets use .ctors for compatibility. */ 1955 #ifndef ARM_EABI_CTORS_SECTION_OP 1956 #define ARM_EABI_CTORS_SECTION_OP \ 1957 "\t.section\t.init_array,\"aw\",%init_array" 1958 #endif 1959 #ifndef ARM_EABI_DTORS_SECTION_OP 1960 #define ARM_EABI_DTORS_SECTION_OP \ 1961 "\t.section\t.fini_array,\"aw\",%fini_array" 1962 #endif 1963 #define ARM_CTORS_SECTION_OP \ 1964 "\t.section\t.ctors,\"aw\",%progbits" 1965 #define ARM_DTORS_SECTION_OP \ 1966 "\t.section\t.dtors,\"aw\",%progbits" 1967 1968 /* Define CTORS_SECTION_ASM_OP. */ 1969 #undef CTORS_SECTION_ASM_OP 1970 #undef DTORS_SECTION_ASM_OP 1971 #ifndef IN_LIBGCC2 1972 # define CTORS_SECTION_ASM_OP \ 1973 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1974 # define DTORS_SECTION_ASM_OP \ 1975 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1976 #else /* !defined (IN_LIBGCC2) */ 1977 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1978 so we cannot use the definition above. */ 1979 # ifdef __ARM_EABI__ 1980 /* The .ctors section is not part of the EABI, so we do not define 1981 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1982 from trying to use it. We do define it when doing normal 1983 compilation, as .init_array can be used instead of .ctors. */ 1984 /* There is no need to emit begin or end markers when using 1985 init_array; the dynamic linker will compute the size of the 1986 array itself based on special symbols created by the static 1987 linker. However, we do need to arrange to set up 1988 exception-handling here. */ 1989 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1990 # define CTOR_LIST_END /* empty */ 1991 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1992 # define DTOR_LIST_END /* empty */ 1993 # else /* !defined (__ARM_EABI__) */ 1994 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1995 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1996 # endif /* !defined (__ARM_EABI__) */ 1997 #endif /* !defined (IN_LIBCC2) */ 1998 1999 /* True if the operating system can merge entities with vague linkage 2000 (e.g., symbols in COMDAT group) during dynamic linking. */ 2001 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 2002 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 2003 #endif 2004 2005 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 2006 2007 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2008 and check its validity for a certain class. 2009 We have two alternate definitions for each of them. 2010 The usual definition accepts all pseudo regs; the other rejects 2011 them unless they have been allocated suitable hard regs. 2012 The symbol REG_OK_STRICT causes the latter definition to be used. 2013 Thumb-2 has the same restrictions as arm. */ 2014 #ifndef REG_OK_STRICT 2015 2016 #define ARM_REG_OK_FOR_BASE_P(X) \ 2017 (REGNO (X) <= LAST_ARM_REGNUM \ 2018 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2019 || REGNO (X) == FRAME_POINTER_REGNUM \ 2020 || REGNO (X) == ARG_POINTER_REGNUM) 2021 2022 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2023 ((REGNO (X) <= LAST_ARM_REGNUM \ 2024 && REGNO (X) != STACK_POINTER_REGNUM) \ 2025 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2026 || REGNO (X) == FRAME_POINTER_REGNUM \ 2027 || REGNO (X) == ARG_POINTER_REGNUM) 2028 2029 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2030 (REGNO (X) <= LAST_LO_REGNUM \ 2031 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2032 || (GET_MODE_SIZE (MODE) >= 4 \ 2033 && (REGNO (X) == STACK_POINTER_REGNUM \ 2034 || (X) == hard_frame_pointer_rtx \ 2035 || (X) == arg_pointer_rtx))) 2036 2037 #define REG_STRICT_P 0 2038 2039 #else /* REG_OK_STRICT */ 2040 2041 #define ARM_REG_OK_FOR_BASE_P(X) \ 2042 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2043 2044 #define ARM_REG_OK_FOR_INDEX_P(X) \ 2045 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2046 2047 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2048 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2049 2050 #define REG_STRICT_P 1 2051 2052 #endif /* REG_OK_STRICT */ 2053 2054 /* Now define some helpers in terms of the above. */ 2055 2056 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2057 (TARGET_THUMB1 \ 2058 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2059 : ARM_REG_OK_FOR_BASE_P (X)) 2060 2061 /* For 16-bit Thumb, a valid index register is anything that can be used in 2062 a byte load instruction. */ 2063 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2064 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2065 2066 /* Nonzero if X is a hard reg that can be used as an index 2067 or if it is a pseudo reg. On the Thumb, the stack pointer 2068 is not suitable. */ 2069 #define REG_OK_FOR_INDEX_P(X) \ 2070 (TARGET_THUMB1 \ 2071 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2072 : ARM_REG_OK_FOR_INDEX_P (X)) 2073 2074 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2075 For Thumb, we cannot use SP + reg, so reject SP. */ 2076 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2077 REG_OK_FOR_INDEX_P (X) 2078 2079 #define ARM_BASE_REGISTER_RTX_P(X) \ 2081 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2082 2083 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2084 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2085 2086 /* Specify the machine mode that this machine uses 2088 for the index in the tablejump instruction. */ 2089 #define CASE_VECTOR_MODE Pmode 2090 2091 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 2092 || (TARGET_THUMB1 \ 2093 && (optimize_size || flag_pic))) \ 2094 && (!target_pure_code)) 2095 2096 2097 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2098 (TARGET_THUMB1 \ 2099 ? (min >= 0 && max < 512 \ 2100 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2101 : min >= -256 && max < 256 \ 2102 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2103 : min >= 0 && max < 8192 \ 2104 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2105 : min >= -4096 && max < 4096 \ 2106 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2107 : SImode) \ 2108 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2109 : (max >= 0x200) ? HImode \ 2110 : QImode)) 2111 2112 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2113 unsigned is probably best, but may break some code. */ 2114 #ifndef DEFAULT_SIGNED_CHAR 2115 #define DEFAULT_SIGNED_CHAR 0 2116 #endif 2117 2118 /* Max number of bytes we can move from memory to memory 2119 in one reasonably fast instruction. */ 2120 #define MOVE_MAX 4 2121 2122 #undef MOVE_RATIO 2123 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2124 2125 /* Define if operations between registers always perform the operation 2126 on the full register even if a narrower mode is specified. */ 2127 #define WORD_REGISTER_OPERATIONS 1 2128 2129 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2130 will either zero-extend or sign-extend. The value of this macro should 2131 be the code that says which one of the two operations is implicitly 2132 done, UNKNOWN if none. */ 2133 #define LOAD_EXTEND_OP(MODE) \ 2134 (TARGET_THUMB ? ZERO_EXTEND : \ 2135 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2136 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2137 2138 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2139 #define SLOW_BYTE_ACCESS 0 2140 2141 /* Immediate shift counts are truncated by the output routines (or was it 2142 the assembler?). Shift counts in a register are truncated by ARM. Note 2143 that the native compiler puts too large (> 32) immediate shift counts 2144 into a register and shifts by the register, letting the ARM decide what 2145 to do instead of doing that itself. */ 2146 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2147 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2148 On the arm, Y in a register is used modulo 256 for the shift. Only for 2149 rotates is modulo 32 used. */ 2150 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2151 2152 /* Calling from registers is a massive pain. */ 2153 #define NO_FUNCTION_CSE 1 2154 2155 /* The machine modes of pointers and functions */ 2156 #define Pmode SImode 2157 #define FUNCTION_MODE Pmode 2158 2159 #define ARM_FRAME_RTX(X) \ 2160 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2161 || (X) == arg_pointer_rtx) 2162 2163 /* Try to generate sequences that don't involve branches, we can then use 2164 conditional instructions. */ 2165 #define BRANCH_COST(speed_p, predictable_p) \ 2166 ((arm_branch_cost != -1) ? arm_branch_cost : \ 2167 (current_tune->branch_cost (speed_p, predictable_p))) 2168 2169 /* False if short circuit operation is preferred. */ 2170 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2171 ((optimize_size) \ 2172 ? (TARGET_THUMB ? false : true) \ 2173 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 2174 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 2175 2176 2177 /* Position Independent Code. */ 2179 /* We decide which register to use based on the compilation options and 2180 the assembler in use; this is more general than the APCS restriction of 2181 using sb (r9) all the time. */ 2182 extern unsigned arm_pic_register; 2183 2184 /* The register number of the register used to address a table of static 2185 data addresses in memory. */ 2186 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2187 2188 /* For FDPIC, the FDPIC register is call-clobbered (otherwise PLT 2189 entries would need to handle saving and restoring it). */ 2190 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED TARGET_FDPIC 2191 2192 /* We can't directly access anything that contains a symbol, 2193 nor can we indirect via the constant pool. One exception is 2194 UNSPEC_TLS, which is always PIC. */ 2195 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2196 (!(symbol_mentioned_p (X) \ 2197 || label_mentioned_p (X) \ 2198 || (GET_CODE (X) == SYMBOL_REF \ 2199 && CONSTANT_POOL_ADDRESS_P (X) \ 2200 && (symbol_mentioned_p (get_pool_constant (X)) \ 2201 || label_mentioned_p (get_pool_constant (X))))) \ 2202 || tls_mentioned_p (X)) 2203 2204 /* We may want to save the PIC register if it is a dedicated one. */ 2205 #define PIC_REGISTER_MAY_NEED_SAVING \ 2206 (flag_pic \ 2207 && !TARGET_SINGLE_PIC_BASE \ 2208 && !TARGET_FDPIC \ 2209 && arm_pic_register != INVALID_REGNUM) 2210 2211 /* We need to know when we are making a constant pool; this determines 2212 whether data needs to be in the GOT or can be referenced via a GOT 2213 offset. */ 2214 extern int making_const_table; 2215 2216 /* Handle pragmas for compatibility with Intel's compilers. */ 2218 /* Also abuse this to register additional C specific EABI attributes. */ 2219 #define REGISTER_TARGET_PRAGMAS() do { \ 2220 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2221 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2222 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2223 arm_lang_object_attributes_init(); \ 2224 arm_register_target_pragmas(); \ 2225 } while (0) 2226 2227 /* Condition code information. */ 2228 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2229 return the mode to be used for the comparison. */ 2230 2231 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2232 2233 #define REVERSIBLE_CC_MODE(MODE) 1 2234 2235 #define REVERSE_CONDITION(CODE,MODE) \ 2236 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2237 ? reverse_condition_maybe_unordered (code) \ 2238 : reverse_condition (code)) 2239 2240 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2241 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2242 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2243 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2244 2245 #define CC_STATUS_INIT \ 2247 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2248 2249 #undef ASM_APP_ON 2250 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2251 "\t.syntax divided\n") 2252 2253 #undef ASM_APP_OFF 2254 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2255 "\t.thumb\n\t.syntax unified\n") 2256 2257 /* Output a push or a pop instruction (only used when profiling). 2258 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2259 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2260 that r7 isn't used by the function profiler, so we can use it as a 2261 scratch reg. WARNING: This isn't safe in the general case! It may be 2262 sensitive to future changes in final.cc:profile_function. */ 2263 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2264 do \ 2265 { \ 2266 if (TARGET_THUMB1 \ 2267 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2268 { \ 2269 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2270 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2271 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2272 } \ 2273 else \ 2274 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2275 } while (0) 2276 2277 2278 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2279 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2280 do \ 2281 { \ 2282 if (TARGET_THUMB1 \ 2283 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2284 { \ 2285 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2286 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2287 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2288 } \ 2289 else \ 2290 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2291 } while (0) 2292 2293 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2294 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2295 2296 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2297 default alignment from elfos.h. */ 2298 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2299 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2300 2301 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2302 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2303 ? 1 : 0) 2304 2305 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2306 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2307 2308 /* For aliases of functions we use .thumb_set instead. */ 2309 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2310 do \ 2311 { \ 2312 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2313 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2314 \ 2315 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2316 { \ 2317 fprintf (FILE, "\t.thumb_set "); \ 2318 assemble_name (FILE, LABEL1); \ 2319 fprintf (FILE, ","); \ 2320 assemble_name (FILE, LABEL2); \ 2321 fprintf (FILE, "\n"); \ 2322 } \ 2323 else \ 2324 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2325 } \ 2326 while (0) 2327 2328 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2329 /* To support -falign-* switches we need to use .p2align so 2330 that alignment directives in code sections will be padded 2331 with no-op instructions, rather than zeroes. */ 2332 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2333 if ((LOG) != 0) \ 2334 { \ 2335 if ((MAX_SKIP) == 0) \ 2336 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2337 else \ 2338 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2339 (int) (LOG), (int) (MAX_SKIP)); \ 2340 } 2341 #endif 2342 2343 /* Add two bytes to the length of conditionally executed Thumb-2 2345 instructions for the IT instruction. */ 2346 #define ADJUST_INSN_LENGTH(insn, length) \ 2347 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2348 length += 2; 2349 2350 /* Only perform branch elimination (by making instructions conditional) if 2351 we're optimizing. For Thumb-2 check if any IT instructions need 2352 outputting. */ 2353 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2354 if (TARGET_ARM && optimize) \ 2355 arm_final_prescan_insn (INSN); \ 2356 else if (TARGET_THUMB2) \ 2357 thumb2_final_prescan_insn (INSN); \ 2358 else if (TARGET_THUMB1) \ 2359 thumb1_final_prescan_insn (INSN) 2360 2361 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2362 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2363 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2364 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2365 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2366 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2367 : 0)))) 2368 2369 /* A C expression whose value is RTL representing the value of the return 2370 address for the frame COUNT steps up from the current frame. */ 2371 2372 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2373 arm_return_addr (COUNT, FRAME) 2374 2375 /* Mask of the bits in the PC that contain the real return address 2376 when running in 26-bit mode. */ 2377 #define RETURN_ADDR_MASK26 (0x03fffffc) 2378 2379 /* Pick up the return address upon entry to a procedure. Used for 2380 dwarf2 unwind information. This also enables the table driven 2381 mechanism. */ 2382 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2383 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2384 2385 /* Used to mask out junk bits from the return address, such as 2386 processor state, interrupt status, condition codes and the like. */ 2387 #define MASK_RETURN_ADDR \ 2388 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2389 in 26 bit mode, the condition codes must be masked out of the \ 2390 return address. This does not apply to ARM6 and later processors \ 2391 when running in 32 bit mode. */ \ 2392 ((arm_arch4 || TARGET_THUMB) \ 2393 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2394 : arm_gen_return_addr_mask ()) 2395 2396 2397 /* Do not emit .note.GNU-stack by default. */ 2399 #ifndef NEED_INDICATE_EXEC_STACK 2400 #define NEED_INDICATE_EXEC_STACK 0 2401 #endif 2402 2403 #define TARGET_ARM_ARCH \ 2404 (arm_base_arch) \ 2405 2406 /* The highest Thumb instruction set version supported by the chip. */ 2407 #define TARGET_ARM_ARCH_ISA_THUMB \ 2408 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2409 2410 /* Expands to an upper-case char of the target's architectural 2411 profile. */ 2412 #define TARGET_ARM_ARCH_PROFILE \ 2413 (arm_active_target.profile) 2414 2415 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2416 Bit 0 for bytes, up to bit 3 for double-words. */ 2417 #define TARGET_ARM_FEATURE_LDREX \ 2418 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2419 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2420 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2421 2422 /* Set as a bit mask indicating the available widths of hardware floating 2423 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2424 32-bit support, bit 3 indicates 64-bit support. */ 2425 #define TARGET_ARM_FP \ 2426 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2427 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2428 : 0) 2429 2430 2431 /* Set as a bit mask indicating the available widths of floating point 2432 types for hardware NEON floating point. This is the same as 2433 TARGET_ARM_FP without the 64-bit bit set. */ 2434 #define TARGET_NEON_FP \ 2435 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2436 : 0) 2437 2438 /* Name of the automatic fpu-selection option. */ 2439 #define FPUTYPE_AUTO "auto" 2440 2441 /* The maximum number of parallel loads or stores we support in an ldm/stm 2442 instruction. */ 2443 #define MAX_LDM_STM_OPS 4 2444 2445 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2446 extern const char *arm_rewrite_march (int argc, const char **argv); 2447 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2448 #define ASM_CPU_SPEC_FUNCTIONS \ 2449 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2450 { "rewrite_march", arm_rewrite_march }, \ 2451 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2452 2453 #define ASM_CPU_SPEC \ 2454 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2455 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2456 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2457 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2458 " }" 2459 2460 extern const char *arm_target_mode (int argc, const char **argv); 2461 #define TARGET_MODE_SPEC_FUNCTIONS \ 2462 { "target_mode_check", arm_target_mode }, 2463 2464 /* -mcpu=native handling only makes sense with compiler running on 2465 an ARM chip. */ 2466 #if defined(__arm__) && defined(__linux__) 2467 extern const char *host_detect_local_cpu (int argc, const char **argv); 2468 #define HAVE_LOCAL_CPU_DETECT 2469 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2470 { "local_cpu_detect", host_detect_local_cpu }, 2471 # define MCPU_MTUNE_NATIVE_SPECS \ 2472 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2473 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2474 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2475 #else 2476 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2477 # define MCPU_MTUNE_NATIVE_SPECS "" 2478 #endif 2479 2480 const char *arm_canon_arch_option (int argc, const char **argv); 2481 const char *arm_canon_arch_multilib_option (int argc, const char **argv); 2482 2483 #define CANON_ARCH_SPEC_FUNCTION \ 2484 { "canon_arch", arm_canon_arch_option }, 2485 2486 #define CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2487 { "canon_arch_multilib", arm_canon_arch_multilib_option }, 2488 2489 const char *arm_be8_option (int argc, const char **argv); 2490 #define BE8_SPEC_FUNCTION \ 2491 { "be8_linkopt", arm_be8_option }, 2492 2493 # define EXTRA_SPEC_FUNCTIONS \ 2494 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2495 ASM_CPU_SPEC_FUNCTIONS \ 2496 CANON_ARCH_SPEC_FUNCTION \ 2497 CANON_ARCH_MULTILIB_SPEC_FUNCTION \ 2498 TARGET_MODE_SPEC_FUNCTIONS \ 2499 BE8_SPEC_FUNCTION 2500 2501 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2502 via the configuration option --with-mode or via the command line. The 2503 function target_mode_check is called to do the check with either: 2504 - an array of -march values if any is given; 2505 - an array of -mcpu values if any is given; 2506 - an empty array. */ 2507 #define TARGET_MODE_SPECS \ 2508 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2509 2510 /* Generate a canonical string to represent the architecture selected. */ 2511 #define ARCH_CANONICAL_SPECS \ 2512 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2513 " %{march=*: arch %*} " \ 2514 " %{mfpu=*: fpu %*} " \ 2515 " %{mfloat-abi=*: abi %*}" \ 2516 " %<march=*) " 2517 2518 /* Generate a canonical string to represent the architecture selected ignoring 2519 the options not required for multilib linking. */ 2520 #define MULTILIB_ARCH_CANONICAL_SPECS \ 2521 "-mlibarch=%:canon_arch_multilib(%{mcpu=*: cpu %*} " \ 2522 " %{march=*: arch %*} " \ 2523 " %{mfpu=*: fpu %*} " \ 2524 " %{mfloat-abi=*: abi %*}" \ 2525 " %<mlibarch=*) " 2526 2527 /* Complete set of specs for the driver. Commas separate the 2528 individual rules so that any option suppression (%<opt...)is 2529 completed before starting subsequent rules. */ 2530 #define DRIVER_SELF_SPECS \ 2531 MCPU_MTUNE_NATIVE_SPECS, \ 2532 TARGET_MODE_SPECS, \ 2533 MULTILIB_ARCH_CANONICAL_SPECS, \ 2534 ARCH_CANONICAL_SPECS 2535 2536 #define TARGET_SUPPORTS_WIDE_INT 1 2537 2538 /* For switching between functions with different target attributes. */ 2539 #define SWITCHABLE_TARGET 1 2540 2541 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2542 representation for SHF_ARM_PURECODE in GCC. */ 2543 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2544 2545 #endif /* ! GCC_ARM_H */ 2546
Indexes created Wed Apr 15 00:22:22 UTC 2026