arm.h revision 1.1.1.2
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2013 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING3. If not see 22 <http://www.gnu.org/licenses/>. */ 23 24 #ifndef GCC_ARM_H 25 #define GCC_ARM_H 26 27 /* We can't use enum machine_mode inside a generator file because it 28 hasn't been created yet; we shouldn't be using any code that 29 needs the real definition though, so this ought to be safe. */ 30 #ifdef GENERATOR_FILE 31 #define MACHMODE int 32 #else 33 #include "insn-modes.h" 34 #define MACHMODE enum machine_mode 35 #endif 36 37 #include "config/vxworks-dummy.h" 38 39 /* The architecture define. */ 40 extern char arm_arch_name[]; 41 42 /* Target CPU builtins. */ 43 #define TARGET_CPU_CPP_BUILTINS() \ 44 do \ 45 { \ 46 if (TARGET_DSP_MULTIPLY) \ 47 builtin_define ("__ARM_FEATURE_DSP"); \ 48 if (TARGET_ARM_QBIT) \ 49 builtin_define ("__ARM_FEATURE_QBIT"); \ 50 if (TARGET_ARM_SAT) \ 51 builtin_define ("__ARM_FEATURE_SAT"); \ 52 if (unaligned_access) \ 53 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 54 if (TARGET_ARM_FEATURE_LDREX) \ 55 builtin_define_with_int_value ( \ 56 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ 57 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ 58 || TARGET_ARM_ARCH_ISA_THUMB >=2) \ 59 builtin_define ("__ARM_FEATURE_CLZ"); \ 60 if (TARGET_INT_SIMD) \ 61 builtin_define ("__ARM_FEATURE_SIMD32"); \ 62 \ 63 builtin_define_with_int_value ( \ 64 "__ARM_SIZEOF_MINIMAL_ENUM", \ 65 flag_short_enums ? 1 : 4); \ 66 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ 67 wchar_type_node); \ 68 if (TARGET_ARM_ARCH_PROFILE) \ 69 builtin_define_with_int_value ( \ 70 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ 71 \ 72 /* Define __arm__ even when in thumb mode, for \ 73 consistency with armcc. */ \ 74 builtin_define ("__arm__"); \ 75 if (TARGET_ARM_ARCH) \ 76 builtin_define_with_int_value ( \ 77 "__ARM_ARCH", TARGET_ARM_ARCH); \ 78 if (arm_arch_notm) \ 79 builtin_define ("__ARM_ARCH_ISA_ARM"); \ 80 builtin_define ("__APCS_32__"); \ 81 if (TARGET_THUMB) \ 82 builtin_define ("__thumb__"); \ 83 if (TARGET_THUMB2) \ 84 builtin_define ("__thumb2__"); \ 85 if (TARGET_ARM_ARCH_ISA_THUMB) \ 86 builtin_define_with_int_value ( \ 87 "__ARM_ARCH_ISA_THUMB", \ 88 TARGET_ARM_ARCH_ISA_THUMB); \ 89 \ 90 if (TARGET_BIG_END) \ 91 { \ 92 builtin_define ("__ARMEB__"); \ 93 builtin_define ("__ARM_BIG_ENDIAN"); \ 94 if (TARGET_THUMB) \ 95 builtin_define ("__THUMBEB__"); \ 96 if (TARGET_LITTLE_WORDS) \ 97 builtin_define ("__ARMWEL__"); \ 98 } \ 99 else \ 100 { \ 101 builtin_define ("__ARMEL__"); \ 102 if (TARGET_THUMB) \ 103 builtin_define ("__THUMBEL__"); \ 104 } \ 105 \ 106 if (TARGET_SOFT_FLOAT) \ 107 builtin_define ("__SOFTFP__"); \ 108 \ 109 if (TARGET_VFP) \ 110 builtin_define ("__VFP_FP__"); \ 111 \ 112 if (TARGET_ARM_FP) \ 113 builtin_define_with_int_value ( \ 114 "__ARM_FP", TARGET_ARM_FP); \ 115 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ 116 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ 117 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ 118 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ 119 if (TARGET_FMA) \ 120 builtin_define ("__ARM_FEATURE_FMA"); \ 121 \ 122 if (TARGET_NEON) \ 123 { \ 124 builtin_define ("__ARM_NEON__"); \ 125 builtin_define ("__ARM_NEON"); \ 126 } \ 127 if (TARGET_NEON_FP) \ 128 builtin_define_with_int_value ( \ 129 "__ARM_NEON_FP", TARGET_NEON_FP); \ 130 \ 131 /* Add a define for interworking. \ 132 Needed when building libgcc.a. */ \ 133 if (arm_cpp_interwork) \ 134 builtin_define ("__THUMB_INTERWORK__"); \ 135 \ 136 builtin_assert ("cpu=arm"); \ 137 builtin_assert ("machine=arm"); \ 138 \ 139 builtin_define (arm_arch_name); \ 140 if (arm_arch_xscale) \ 141 builtin_define ("__XSCALE__"); \ 142 if (arm_arch_iwmmxt) \ 143 { \ 144 builtin_define ("__IWMMXT__"); \ 145 builtin_define ("__ARM_WMMX"); \ 146 } \ 147 if (arm_arch_iwmmxt2) \ 148 builtin_define ("__IWMMXT2__"); \ 149 if (TARGET_AAPCS_BASED) \ 150 { \ 151 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 152 builtin_define ("__ARM_PCS_VFP"); \ 153 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 154 builtin_define ("__ARM_PCS"); \ 155 builtin_define ("__ARM_EABI__"); \ 156 } \ 157 if (TARGET_IDIV) \ 158 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 159 } while (0) 160 161 #include "config/arm/arm-opts.h" 162 163 enum target_cpus 164 { 165 #define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 166 TARGET_CPU_##IDENT, 167 #include "arm-cores.def" 168 #undef ARM_CORE 169 TARGET_CPU_generic 170 }; 171 172 /* The processor for which instructions should be scheduled. */ 173 extern enum processor_type arm_tune; 174 175 typedef enum arm_cond_code 176 { 177 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 178 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 179 } 180 arm_cc; 181 182 extern arm_cc arm_current_cc; 183 184 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 185 186 extern int arm_target_label; 187 extern int arm_ccfsm_state; 188 extern GTY(()) rtx arm_target_insn; 189 /* The label of the current constant pool. */ 190 extern rtx pool_vector_label; 191 /* Set to 1 when a return insn is output, this means that the epilogue 192 is not needed. */ 193 extern int return_used_this_function; 194 /* Callback to output language specific object attributes. */ 195 extern void (*arm_lang_output_object_attributes_hook)(void); 196 197 /* Just in case configure has failed to define anything. */ 199 #ifndef TARGET_CPU_DEFAULT 200 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 201 #endif 202 203 204 #undef CPP_SPEC 205 #define CPP_SPEC "%(subtarget_cpp_spec) \ 206 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 207 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 208 %{mbig-endian:%{mlittle-endian: \ 209 %e-mbig-endian and -mlittle-endian may not be used together}}" 210 211 #ifndef CC1_SPEC 212 #define CC1_SPEC "" 213 #endif 214 215 /* This macro defines names of additional specifications to put in the specs 216 that can be used in various specifications like CC1_SPEC. Its definition 217 is an initializer with a subgrouping for each command option. 218 219 Each subgrouping contains a string constant, that defines the 220 specification name, and a string constant that used by the GCC driver 221 program. 222 223 Do not define this macro if it does not need to do anything. */ 224 #define EXTRA_SPECS \ 225 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 226 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 227 SUBTARGET_EXTRA_SPECS 228 229 #ifndef SUBTARGET_EXTRA_SPECS 230 #define SUBTARGET_EXTRA_SPECS 231 #endif 232 233 #ifndef SUBTARGET_CPP_SPEC 234 #define SUBTARGET_CPP_SPEC "" 235 #endif 236 237 /* Run-time Target Specification. */ 239 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 240 /* Use hardware floating point instructions. */ 241 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 242 /* Use hardware floating point calling convention. */ 243 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 244 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 245 #define TARGET_IWMMXT (arm_arch_iwmmxt) 246 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 247 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 248 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 249 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 250 #define TARGET_ARM (! TARGET_THUMB) 251 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 252 #define TARGET_BACKTRACE (leaf_function_p () \ 253 ? TARGET_TPCS_LEAF_FRAME \ 254 : TARGET_TPCS_FRAME) 255 #define TARGET_AAPCS_BASED \ 256 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 257 258 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 259 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 260 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 261 262 /* Only 16-bit thumb code. */ 263 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 264 /* Arm or Thumb-2 32-bit code. */ 265 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 266 /* 32-bit Thumb-2 code. */ 267 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 268 /* Thumb-1 only. */ 269 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 270 271 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 272 && !TARGET_THUMB1) 273 274 /* The following two macros concern the ability to execute coprocessor 275 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 276 only ever tested when we know we are generating for VFP hardware; we need 277 to be more careful with TARGET_NEON as noted below. */ 278 279 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 280 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 281 282 /* FPU supports VFPv3 instructions. */ 283 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 284 285 /* FPU only supports VFP single-precision instructions. */ 286 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 287 288 /* FPU supports VFP double-precision instructions. */ 289 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 290 291 /* FPU supports half-precision floating-point with NEON element load/store. */ 292 #define TARGET_NEON_FP16 \ 293 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 294 295 /* FPU supports VFP half-precision floating-point. */ 296 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 297 298 /* FPU supports fused-multiply-add operations. */ 299 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) 300 301 /* FPU is ARMv8 compatible. */ 302 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) 303 304 /* FPU supports Crypto extensions. */ 305 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) 306 307 /* FPU supports Neon instructions. The setting of this macro gets 308 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 309 and TARGET_HARD_FLOAT to ensure that NEON instructions are 310 available. */ 311 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 312 && TARGET_VFP && arm_fpu_desc->neon) 313 314 /* Q-bit is present. */ 315 #define TARGET_ARM_QBIT \ 316 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 317 /* Saturation operation, e.g. SSAT. */ 318 #define TARGET_ARM_SAT \ 319 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 320 /* "DSP" multiply instructions, eg. SMULxy. */ 321 #define TARGET_DSP_MULTIPLY \ 322 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 323 /* Integer SIMD instructions, and extend-accumulate instructions. */ 324 #define TARGET_INT_SIMD \ 325 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 326 327 /* Should MOVW/MOVT be used in preference to a constant pool. */ 328 #define TARGET_USE_MOVT \ 329 (arm_arch_thumb2 && !optimize_size && !current_tune->prefer_constant_pool) 330 331 /* We could use unified syntax for arm mode, but for now we just use it 332 for Thumb-2. */ 333 #define TARGET_UNIFIED_ASM TARGET_THUMB2 334 335 /* Nonzero if this chip provides the DMB instruction. */ 336 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 337 338 /* Nonzero if this chip implements a memory barrier via CP15. */ 339 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 340 && ! TARGET_THUMB1) 341 342 /* Nonzero if this chip implements a memory barrier instruction. */ 343 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 344 345 /* Nonzero if this chip supports ldrex and strex */ 346 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 347 348 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 349 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 350 351 /* Nonzero if this chip supports ldrexd and strexd. */ 352 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ 353 && arm_arch_notm) 354 355 /* Nonzero if integer division instructions supported. */ 356 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 357 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 358 359 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 360 then TARGET_AAPCS_BASED must be true -- but the converse does not 361 hold. TARGET_BPABI implies the use of the BPABI runtime library, 362 etc., in addition to just the AAPCS calling conventions. */ 363 #ifndef TARGET_BPABI 364 #define TARGET_BPABI false 365 #endif 366 367 /* Support for a compile-time default CPU, et cetera. The rules are: 368 --with-arch is ignored if -march or -mcpu are specified. 369 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 370 by --with-arch. 371 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 372 by -march). 373 --with-float is ignored if -mfloat-abi is specified. 374 --with-fpu is ignored if -mfpu is specified. 375 --with-abi is ignored if -mabi is specified. 376 --with-tls is ignored if -mtls-dialect is specified. */ 377 #define OPTION_DEFAULT_SPECS \ 378 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 379 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 380 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 381 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 382 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 383 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 384 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 385 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 386 387 /* Which floating point model to use. */ 388 enum arm_fp_model 389 { 390 ARM_FP_MODEL_UNKNOWN, 391 /* VFP floating point model. */ 392 ARM_FP_MODEL_VFP 393 }; 394 395 enum vfp_reg_type 396 { 397 VFP_NONE = 0, 398 VFP_REG_D16, 399 VFP_REG_D32, 400 VFP_REG_SINGLE 401 }; 402 403 extern const struct arm_fpu_desc 404 { 405 const char *name; 406 enum arm_fp_model model; 407 int rev; 408 enum vfp_reg_type regs; 409 int neon; 410 int fp16; 411 int crypto; 412 } *arm_fpu_desc; 413 414 /* Which floating point hardware to schedule for. */ 415 extern int arm_fpu_attr; 416 417 #ifndef TARGET_DEFAULT_FLOAT_ABI 418 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 419 #endif 420 421 #define LARGEST_EXPONENT_IS_NORMAL(bits) \ 422 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) 423 424 #ifndef ARM_DEFAULT_ABI 425 #define ARM_DEFAULT_ABI ARM_ABI_APCS 426 #endif 427 428 /* Map each of the micro-architecture variants to their corresponding 429 major architecture revision. */ 430 431 enum base_architecture 432 { 433 BASE_ARCH_0 = 0, 434 BASE_ARCH_2 = 2, 435 BASE_ARCH_3 = 3, 436 BASE_ARCH_3M = 3, 437 BASE_ARCH_4 = 4, 438 BASE_ARCH_4T = 4, 439 BASE_ARCH_5 = 5, 440 BASE_ARCH_5E = 5, 441 BASE_ARCH_5T = 5, 442 BASE_ARCH_5TE = 5, 443 BASE_ARCH_5TEJ = 5, 444 BASE_ARCH_6 = 6, 445 BASE_ARCH_6J = 6, 446 BASE_ARCH_6ZK = 6, 447 BASE_ARCH_6K = 6, 448 BASE_ARCH_6T2 = 6, 449 BASE_ARCH_6M = 6, 450 BASE_ARCH_6Z = 6, 451 BASE_ARCH_7 = 7, 452 BASE_ARCH_7A = 7, 453 BASE_ARCH_7R = 7, 454 BASE_ARCH_7M = 7, 455 BASE_ARCH_7EM = 7, 456 BASE_ARCH_8A = 8 457 }; 458 459 /* The major revision number of the ARM Architecture implemented by the target. */ 460 extern enum base_architecture arm_base_arch; 461 462 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 463 extern int arm_arch3m; 464 465 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 466 extern int arm_arch4; 467 468 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 469 extern int arm_arch4t; 470 471 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 472 extern int arm_arch5; 473 474 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 475 extern int arm_arch5e; 476 477 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 478 extern int arm_arch6; 479 480 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 481 extern int arm_arch6k; 482 483 /* Nonzero if instructions present in ARMv6-M can be used. */ 484 extern int arm_arch6m; 485 486 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 487 extern int arm_arch7; 488 489 /* Nonzero if instructions not present in the 'M' profile can be used. */ 490 extern int arm_arch_notm; 491 492 /* Nonzero if instructions present in ARMv7E-M can be used. */ 493 extern int arm_arch7em; 494 495 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 496 extern int arm_arch8; 497 498 /* Nonzero if this chip can benefit from load scheduling. */ 499 extern int arm_ld_sched; 500 501 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 502 extern int thumb_code; 503 504 /* Nonzero if generating Thumb-1 code. */ 505 extern int thumb1_code; 506 507 /* Nonzero if this chip is a StrongARM. */ 508 extern int arm_tune_strongarm; 509 510 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 511 extern int arm_arch_iwmmxt; 512 513 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 514 extern int arm_arch_iwmmxt2; 515 516 /* Nonzero if this chip is an XScale. */ 517 extern int arm_arch_xscale; 518 519 /* Nonzero if tuning for XScale. */ 520 extern int arm_tune_xscale; 521 522 /* Nonzero if tuning for stores via the write buffer. */ 523 extern int arm_tune_wbuf; 524 525 /* Nonzero if tuning for Cortex-A9. */ 526 extern int arm_tune_cortex_a9; 527 528 /* Nonzero if we should define __THUMB_INTERWORK__ in the 529 preprocessor. 530 XXX This is a bit of a hack, it's intended to help work around 531 problems in GLD which doesn't understand that armv5t code is 532 interworking clean. */ 533 extern int arm_cpp_interwork; 534 535 /* Nonzero if chip supports Thumb 2. */ 536 extern int arm_arch_thumb2; 537 538 /* Nonzero if chip supports integer division instruction in ARM mode. */ 539 extern int arm_arch_arm_hwdiv; 540 541 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 542 extern int arm_arch_thumb_hwdiv; 543 544 #ifndef TARGET_DEFAULT 545 #define TARGET_DEFAULT (MASK_APCS_FRAME) 546 #endif 547 548 /* Nonzero if PIC code requires explicit qualifiers to generate 549 PLT and GOT relocs rather than the assembler doing so implicitly. 550 Subtargets can override these if required. */ 551 #ifndef NEED_GOT_RELOC 552 #define NEED_GOT_RELOC 0 553 #endif 554 #ifndef NEED_PLT_RELOC 555 #define NEED_PLT_RELOC 0 556 #endif 557 558 /* Nonzero if we need to refer to the GOT with a PC-relative 559 offset. In other words, generate 560 561 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 562 563 rather than 564 565 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 566 567 The default is true, which matches NetBSD. Subtargets can 568 override this if required. */ 569 #ifndef GOT_PCREL 570 #define GOT_PCREL 1 571 #endif 572 573 /* Target machine storage Layout. */ 575 576 577 /* Define this macro if it is advisable to hold scalars in registers 578 in a wider mode than that declared by the program. In such cases, 579 the value is constrained to be within the bounds of the declared 580 type, but kept valid in the wider mode. The signedness of the 581 extension may differ from that of the type. */ 582 583 /* It is far faster to zero extend chars than to sign extend them */ 584 585 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 586 if (GET_MODE_CLASS (MODE) == MODE_INT \ 587 && GET_MODE_SIZE (MODE) < 4) \ 588 { \ 589 if (MODE == QImode) \ 590 UNSIGNEDP = 1; \ 591 else if (MODE == HImode) \ 592 UNSIGNEDP = 1; \ 593 (MODE) = SImode; \ 594 } 595 596 /* Define this if most significant bit is lowest numbered 597 in instructions that operate on numbered bit-fields. */ 598 #define BITS_BIG_ENDIAN 0 599 600 /* Define this if most significant byte of a word is the lowest numbered. 601 Most ARM processors are run in little endian mode, so that is the default. 602 If you want to have it run-time selectable, change the definition in a 603 cover file to be TARGET_BIG_ENDIAN. */ 604 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 605 606 /* Define this if most significant word of a multiword number is the lowest 607 numbered. 608 This is always false, even when in big-endian mode. */ 609 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 610 611 #define UNITS_PER_WORD 4 612 613 /* True if natural alignment is used for doubleword types. */ 614 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 615 616 #define DOUBLEWORD_ALIGNMENT 64 617 618 #define PARM_BOUNDARY 32 619 620 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 621 622 #define PREFERRED_STACK_BOUNDARY \ 623 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 624 625 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 626 627 /* The lowest bit is used to indicate Thumb-mode functions, so the 628 vbit must go into the delta field of pointers to member 629 functions. */ 630 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 631 632 #define EMPTY_FIELD_BOUNDARY 32 633 634 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 635 636 /* XXX Blah -- this macro is used directly by libobjc. Since it 637 supports no vector modes, cut out the complexity and fall back 638 on BIGGEST_FIELD_ALIGNMENT. */ 639 #ifdef IN_TARGET_LIBS 640 #define BIGGEST_FIELD_ALIGNMENT 64 641 #endif 642 643 /* Make strings word-aligned so strcpy from constants will be faster. */ 644 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 645 646 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 647 ((TREE_CODE (EXP) == STRING_CST \ 648 && !optimize_size \ 649 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 650 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 651 652 /* Align definitions of arrays, unions and structures so that 653 initializations and copies can be made more efficient. This is not 654 ABI-changing, so it only affects places where we can see the 655 definition. Increasing the alignment tends to introduce padding, 656 so don't do this when optimizing for size/conserving stack space. */ 657 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 658 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 659 && (TREE_CODE (EXP) == ARRAY_TYPE \ 660 || TREE_CODE (EXP) == UNION_TYPE \ 661 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 662 663 /* Align global data. */ 664 #define DATA_ALIGNMENT(EXP, ALIGN) \ 665 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 666 667 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 668 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 669 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 670 671 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 672 value set in previous versions of this toolchain was 8, which produces more 673 compact structures. The command line option -mstructure_size_boundary=<n> 674 can be used to change this value. For compatibility with the ARM SDK 675 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 676 0020D) page 2-20 says "Structures are aligned on word boundaries". 677 The AAPCS specifies a value of 8. */ 678 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 679 680 /* This is the value used to initialize arm_structure_size_boundary. If a 681 particular arm target wants to change the default value it should change 682 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 683 for an example of this. */ 684 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 685 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 686 #endif 687 688 /* Nonzero if move instructions will actually fail to work 689 when given unaligned data. */ 690 #define STRICT_ALIGNMENT 1 691 692 /* wchar_t is unsigned under the AAPCS. */ 693 #ifndef WCHAR_TYPE 694 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 695 696 #define WCHAR_TYPE_SIZE BITS_PER_WORD 697 #endif 698 699 /* Sized for fixed-point types. */ 700 701 #define SHORT_FRACT_TYPE_SIZE 8 702 #define FRACT_TYPE_SIZE 16 703 #define LONG_FRACT_TYPE_SIZE 32 704 #define LONG_LONG_FRACT_TYPE_SIZE 64 705 706 #define SHORT_ACCUM_TYPE_SIZE 16 707 #define ACCUM_TYPE_SIZE 32 708 #define LONG_ACCUM_TYPE_SIZE 64 709 #define LONG_LONG_ACCUM_TYPE_SIZE 64 710 711 #define MAX_FIXED_MODE_SIZE 64 712 713 #ifndef SIZE_TYPE 714 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 715 #endif 716 717 #ifndef PTRDIFF_TYPE 718 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 719 #endif 720 721 /* AAPCS requires that structure alignment is affected by bitfields. */ 722 #ifndef PCC_BITFIELD_TYPE_MATTERS 723 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 724 #endif 725 726 727 /* Standard register usage. */ 729 730 /* Register allocation in ARM Procedure Call Standard 731 (S - saved over call). 732 733 r0 * argument word/integer result 734 r1-r3 argument word 735 736 r4-r8 S register variable 737 r9 S (rfp) register variable (real frame pointer) 738 739 r10 F S (sl) stack limit (used by -mapcs-stack-check) 740 r11 F S (fp) argument pointer 741 r12 (ip) temp workspace 742 r13 F S (sp) lower end of current stack frame 743 r14 (lr) link address/workspace 744 r15 F (pc) program counter 745 746 cc This is NOT a real register, but is used internally 747 to represent things that use or set the condition 748 codes. 749 sfp This isn't either. It is used during rtl generation 750 since the offset between the frame pointer and the 751 auto's isn't known until after register allocation. 752 afp Nor this, we only need this because of non-local 753 goto. Without it fp appears to be used and the 754 elimination code won't get rid of sfp. It tracks 755 fp exactly at all times. 756 757 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 758 759 /* s0-s15 VFP scratch (aka d0-d7). 760 s16-s31 S VFP variable (aka d8-d15). 761 vfpcc Not a real register. Represents the VFP condition 762 code flags. */ 763 764 /* The stack backtrace structure is as follows: 765 fp points to here: | save code pointer | [fp] 766 | return link value | [fp, #-4] 767 | return sp value | [fp, #-8] 768 | return fp value | [fp, #-12] 769 [| saved r10 value |] 770 [| saved r9 value |] 771 [| saved r8 value |] 772 [| saved r7 value |] 773 [| saved r6 value |] 774 [| saved r5 value |] 775 [| saved r4 value |] 776 [| saved r3 value |] 777 [| saved r2 value |] 778 [| saved r1 value |] 779 [| saved r0 value |] 780 r0-r3 are not normally saved in a C function. */ 781 782 /* 1 for registers that have pervasive standard uses 783 and are not available for the register allocator. */ 784 #define FIXED_REGISTERS \ 785 { \ 786 /* Core regs. */ \ 787 0,0,0,0,0,0,0,0, \ 788 0,0,0,0,0,1,0,1, \ 789 /* VFP regs. */ \ 790 1,1,1,1,1,1,1,1, \ 791 1,1,1,1,1,1,1,1, \ 792 1,1,1,1,1,1,1,1, \ 793 1,1,1,1,1,1,1,1, \ 794 1,1,1,1,1,1,1,1, \ 795 1,1,1,1,1,1,1,1, \ 796 1,1,1,1,1,1,1,1, \ 797 1,1,1,1,1,1,1,1, \ 798 /* IWMMXT regs. */ \ 799 1,1,1,1,1,1,1,1, \ 800 1,1,1,1,1,1,1,1, \ 801 1,1,1,1, \ 802 /* Specials. */ \ 803 1,1,1,1 \ 804 } 805 806 /* 1 for registers not available across function calls. 807 These must include the FIXED_REGISTERS and also any 808 registers that can be used without being saved. 809 The latter must include the registers where values are returned 810 and the register where structure-value addresses are passed. 811 Aside from that, you can include as many other registers as you like. 812 The CC is not preserved over function calls on the ARM 6, so it is 813 easier to assume this for all. SFP is preserved, since FP is. */ 814 #define CALL_USED_REGISTERS \ 815 { \ 816 /* Core regs. */ \ 817 1,1,1,1,0,0,0,0, \ 818 0,0,0,0,1,1,1,1, \ 819 /* VFP Regs. */ \ 820 1,1,1,1,1,1,1,1, \ 821 1,1,1,1,1,1,1,1, \ 822 1,1,1,1,1,1,1,1, \ 823 1,1,1,1,1,1,1,1, \ 824 1,1,1,1,1,1,1,1, \ 825 1,1,1,1,1,1,1,1, \ 826 1,1,1,1,1,1,1,1, \ 827 1,1,1,1,1,1,1,1, \ 828 /* IWMMXT regs. */ \ 829 1,1,1,1,1,1,1,1, \ 830 1,1,1,1,1,1,1,1, \ 831 1,1,1,1, \ 832 /* Specials. */ \ 833 1,1,1,1 \ 834 } 835 836 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 837 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 838 #endif 839 840 /* These are a couple of extensions to the formats accepted 841 by asm_fprintf: 842 %@ prints out ASM_COMMENT_START 843 %r prints out REGISTER_PREFIX reg_names[arg] */ 844 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 845 case '@': \ 846 fputs (ASM_COMMENT_START, FILE); \ 847 break; \ 848 \ 849 case 'r': \ 850 fputs (REGISTER_PREFIX, FILE); \ 851 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 852 break; 853 854 /* Round X up to the nearest word. */ 855 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 856 857 /* Convert fron bytes to ints. */ 858 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 859 860 /* The number of (integer) registers required to hold a quantity of type MODE. 861 Also used for VFP registers. */ 862 #define ARM_NUM_REGS(MODE) \ 863 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 864 865 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 866 #define ARM_NUM_REGS2(MODE, TYPE) \ 867 ARM_NUM_INTS ((MODE) == BLKmode ? \ 868 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 869 870 /* The number of (integer) argument register available. */ 871 #define NUM_ARG_REGS 4 872 873 /* And similarly for the VFP. */ 874 #define NUM_VFP_ARG_REGS 16 875 876 /* Return the register number of the N'th (integer) argument. */ 877 #define ARG_REGISTER(N) (N - 1) 878 879 /* Specify the registers used for certain standard purposes. 880 The values of these macros are register numbers. */ 881 882 /* The number of the last argument register. */ 883 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 884 885 /* The numbers of the Thumb register ranges. */ 886 #define FIRST_LO_REGNUM 0 887 #define LAST_LO_REGNUM 7 888 #define FIRST_HI_REGNUM 8 889 #define LAST_HI_REGNUM 11 890 891 /* Overridden by config/arm/bpabi.h. */ 892 #ifndef ARM_UNWIND_INFO 893 #define ARM_UNWIND_INFO 0 894 #endif 895 896 /* Overriden by config/arm/netbsd-eabi.h. */ 897 #ifndef ARM_DWARF_UNWIND_TABLES 898 #define ARM_DWARF_UNWIND_TABLES 0 899 #endif 900 901 /* Use r0 and r1 to pass exception handling information. */ 902 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 903 904 /* The register that holds the return address in exception handlers. */ 905 #define ARM_EH_STACKADJ_REGNUM 2 906 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 907 908 #ifndef ARM_TARGET2_DWARF_FORMAT 909 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 910 911 # if ARM_DWARF_UNWIND_TABLES 912 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 913 for 32bit platforms. */ 914 # define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 915 ((flag_pic \ 916 && ((GLOBAL) || (CODE))) \ 917 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 918 : DW_EH_PE_absptr) 919 # else 920 /* ttype entries (the only interesting data references used) 921 use TARGET2 relocations. */ 922 # define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 923 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 924 : DW_EH_PE_absptr) 925 # endif 926 #endif 927 928 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 929 as an invisible last argument (possible since varargs don't exist in 930 Pascal), so the following is not true. */ 931 #define STATIC_CHAIN_REGNUM 12 932 933 /* Define this to be where the real frame pointer is if it is not possible to 934 work out the offset between the frame pointer and the automatic variables 935 until after register allocation has taken place. FRAME_POINTER_REGNUM 936 should point to a special register that we will make sure is eliminated. 937 938 For the Thumb we have another problem. The TPCS defines the frame pointer 939 as r11, and GCC believes that it is always possible to use the frame pointer 940 as base register for addressing purposes. (See comments in 941 find_reloads_address()). But - the Thumb does not allow high registers, 942 including r11, to be used as base address registers. Hence our problem. 943 944 The solution used here, and in the old thumb port is to use r7 instead of 945 r11 as the hard frame pointer and to have special code to generate 946 backtrace structures on the stack (if required to do so via a command line 947 option) using r11. This is the only 'user visible' use of r11 as a frame 948 pointer. */ 949 #define ARM_HARD_FRAME_POINTER_REGNUM 11 950 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 951 952 #define HARD_FRAME_POINTER_REGNUM \ 953 (TARGET_ARM \ 954 ? ARM_HARD_FRAME_POINTER_REGNUM \ 955 : THUMB_HARD_FRAME_POINTER_REGNUM) 956 957 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 958 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 959 960 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 961 962 /* Register to use for pushing function arguments. */ 963 #define STACK_POINTER_REGNUM SP_REGNUM 964 965 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 966 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 967 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 968 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 969 970 #define IS_IWMMXT_REGNUM(REGNUM) \ 971 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 972 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 973 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 974 975 /* Base register for access to local variables of the function. */ 976 #define FRAME_POINTER_REGNUM 102 977 978 /* Base register for access to arguments of the function. */ 979 #define ARG_POINTER_REGNUM 103 980 981 #define FIRST_VFP_REGNUM 16 982 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 983 #define LAST_VFP_REGNUM \ 984 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 985 986 #define IS_VFP_REGNUM(REGNUM) \ 987 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 988 989 /* VFP registers are split into two types: those defined by VFP versions < 3 990 have D registers overlaid on consecutive pairs of S registers. VFP version 3 991 defines 16 new D registers (d16-d31) which, for simplicity and correctness 992 in various parts of the backend, we implement as "fake" single-precision 993 registers (which would be S32-S63, but cannot be used in that way). The 994 following macros define these ranges of registers. */ 995 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 996 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 997 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 998 999 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1000 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1001 1002 /* DFmode values are only valid in even register pairs. */ 1003 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1004 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1005 1006 /* Neon Quad values must start at a multiple of four registers. */ 1007 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1008 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1009 1010 /* Neon structures of vectors must be in even register pairs and there 1011 must be enough registers available. Because of various patterns 1012 requiring quad registers, we require them to start at a multiple of 1013 four. */ 1014 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1015 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1016 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1017 1018 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1019 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1020 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1021 #define FIRST_PSEUDO_REGISTER 104 1022 1023 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1024 1025 /* Value should be nonzero if functions must have frame pointers. 1026 Zero means the frame pointer need not be set up (and parms may be accessed 1027 via the stack pointer) in functions that seem suitable. 1028 If we have to have a frame pointer we might as well make use of it. 1029 APCS says that the frame pointer does not need to be pushed in leaf 1030 functions, or simple tail call functions. */ 1031 1032 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1033 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1034 #endif 1035 1036 /* Return number of consecutive hard regs needed starting at reg REGNO 1037 to hold something of mode MODE. 1038 This is ordinarily the length in words of a value of mode MODE 1039 but can be less for certain modes in special long registers. 1040 1041 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1042 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1043 ((TARGET_32BIT \ 1044 && REGNO > PC_REGNUM \ 1045 && REGNO != FRAME_POINTER_REGNUM \ 1046 && REGNO != ARG_POINTER_REGNUM) \ 1047 && !IS_VFP_REGNUM (REGNO) \ 1048 ? 1 : ARM_NUM_REGS (MODE)) 1049 1050 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1051 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1052 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1053 1054 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1055 1056 #define VALID_IWMMXT_REG_MODE(MODE) \ 1057 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1058 1059 /* Modes valid for Neon D registers. */ 1060 #define VALID_NEON_DREG_MODE(MODE) \ 1061 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1062 || (MODE) == V2SFmode || (MODE) == DImode) 1063 1064 /* Modes valid for Neon Q registers. */ 1065 #define VALID_NEON_QREG_MODE(MODE) \ 1066 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1067 || (MODE) == V4SFmode || (MODE) == V2DImode) 1068 1069 /* Structure modes valid for Neon registers. */ 1070 #define VALID_NEON_STRUCT_MODE(MODE) \ 1071 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1072 || (MODE) == CImode || (MODE) == XImode) 1073 1074 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1075 extern int arm_regs_in_sequence[]; 1076 1077 /* The order in which register should be allocated. It is good to use ip 1078 since no saving is required (though calls clobber it) and it never contains 1079 function parameters. It is quite good to use lr since other calls may 1080 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1081 least likely to contain a function parameter; in addition results are 1082 returned in r0. 1083 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1084 then D8-D15. The reason for doing this is to attempt to reduce register 1085 pressure when both single- and double-precision registers are used in a 1086 function. */ 1087 1088 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1089 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1090 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1091 1092 #define REG_ALLOC_ORDER \ 1093 { \ 1094 /* General registers. */ \ 1095 3, 2, 1, 0, 12, 14, 4, 5, \ 1096 6, 7, 8, 9, 10, 11, \ 1097 /* High VFP registers. */ \ 1098 VREG(32), VREG(33), VREG(34), VREG(35), \ 1099 VREG(36), VREG(37), VREG(38), VREG(39), \ 1100 VREG(40), VREG(41), VREG(42), VREG(43), \ 1101 VREG(44), VREG(45), VREG(46), VREG(47), \ 1102 VREG(48), VREG(49), VREG(50), VREG(51), \ 1103 VREG(52), VREG(53), VREG(54), VREG(55), \ 1104 VREG(56), VREG(57), VREG(58), VREG(59), \ 1105 VREG(60), VREG(61), VREG(62), VREG(63), \ 1106 /* VFP argument registers. */ \ 1107 VREG(15), VREG(14), VREG(13), VREG(12), \ 1108 VREG(11), VREG(10), VREG(9), VREG(8), \ 1109 VREG(7), VREG(6), VREG(5), VREG(4), \ 1110 VREG(3), VREG(2), VREG(1), VREG(0), \ 1111 /* VFP call-saved registers. */ \ 1112 VREG(16), VREG(17), VREG(18), VREG(19), \ 1113 VREG(20), VREG(21), VREG(22), VREG(23), \ 1114 VREG(24), VREG(25), VREG(26), VREG(27), \ 1115 VREG(28), VREG(29), VREG(30), VREG(31), \ 1116 /* IWMMX registers. */ \ 1117 WREG(0), WREG(1), WREG(2), WREG(3), \ 1118 WREG(4), WREG(5), WREG(6), WREG(7), \ 1119 WREG(8), WREG(9), WREG(10), WREG(11), \ 1120 WREG(12), WREG(13), WREG(14), WREG(15), \ 1121 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1122 /* Registers not for general use. */ \ 1123 CC_REGNUM, VFPCC_REGNUM, \ 1124 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1125 SP_REGNUM, PC_REGNUM \ 1126 } 1127 1128 /* Use different register alloc ordering for Thumb. */ 1129 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1130 1131 /* Tell IRA to use the order we define rather than messing it up with its 1132 own cost calculations. */ 1133 #define HONOR_REG_ALLOC_ORDER 1134 1135 /* Interrupt functions can only use registers that have already been 1136 saved by the prologue, even if they would normally be 1137 call-clobbered. */ 1138 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1139 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1140 df_regs_ever_live_p (DST)) 1141 1142 /* Register and constant classes. */ 1144 1145 /* Register classes. */ 1146 enum reg_class 1147 { 1148 NO_REGS, 1149 LO_REGS, 1150 STACK_REG, 1151 BASE_REGS, 1152 HI_REGS, 1153 GENERAL_REGS, 1154 CORE_REGS, 1155 VFP_D0_D7_REGS, 1156 VFP_LO_REGS, 1157 VFP_HI_REGS, 1158 VFP_REGS, 1159 IWMMXT_REGS, 1160 IWMMXT_GR_REGS, 1161 CC_REG, 1162 VFPCC_REG, 1163 SFP_REG, 1164 AFP_REG, 1165 ALL_REGS, 1166 LIM_REG_CLASSES 1167 }; 1168 1169 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1170 1171 /* Give names of register classes as strings for dump file. */ 1172 #define REG_CLASS_NAMES \ 1173 { \ 1174 "NO_REGS", \ 1175 "LO_REGS", \ 1176 "STACK_REG", \ 1177 "BASE_REGS", \ 1178 "HI_REGS", \ 1179 "GENERAL_REGS", \ 1180 "CORE_REGS", \ 1181 "VFP_D0_D7_REGS", \ 1182 "VFP_LO_REGS", \ 1183 "VFP_HI_REGS", \ 1184 "VFP_REGS", \ 1185 "IWMMXT_REGS", \ 1186 "IWMMXT_GR_REGS", \ 1187 "CC_REG", \ 1188 "VFPCC_REG", \ 1189 "SFP_REG", \ 1190 "AFP_REG", \ 1191 "ALL_REGS" \ 1192 } 1193 1194 /* Define which registers fit in which classes. 1195 This is an initializer for a vector of HARD_REG_SET 1196 of length N_REG_CLASSES. */ 1197 #define REG_CLASS_CONTENTS \ 1198 { \ 1199 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1200 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1201 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1202 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1203 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1204 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1205 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1206 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1207 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1208 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1209 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1210 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1211 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1212 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1213 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1214 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1215 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1216 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000 } /* ALL_REGS */ \ 1217 } 1218 1219 /* Any of the VFP register classes. */ 1220 #define IS_VFP_CLASS(X) \ 1221 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1222 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1223 1224 /* The same information, inverted: 1225 Return the class number of the smallest class containing 1226 reg number REGNO. This could be a conditional expression 1227 or could index an array. */ 1228 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1229 1230 /* In VFPv1, VFP registers could only be accessed in the mode they 1231 were set, so subregs would be invalid there. However, we don't 1232 support VFPv1 at the moment, and the restriction was lifted in 1233 VFPv2. 1234 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1235 VFP registers in little-endian order. We can't describe that accurately to 1236 GCC, so avoid taking subregs of such values. 1237 The only exception is going from a 128-bit to a 64-bit type. In that case 1238 the data layout happens to be consistent for big-endian, so we explicitly allow 1239 that case. */ 1240 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1241 (TARGET_VFP && TARGET_BIG_END \ 1242 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1243 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1244 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1245 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1246 1247 /* The class value for index registers, and the one for base regs. */ 1248 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1249 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1250 1251 /* For the Thumb the high registers cannot be used as base registers 1252 when addressing quantities in QI or HI mode; if we don't know the 1253 mode, then we must be conservative. */ 1254 #define MODE_BASE_REG_CLASS(MODE) \ 1255 (TARGET_ARM || (TARGET_THUMB2 && !optimize_size) ? CORE_REGS : \ 1256 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) 1257 1258 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1259 instead of BASE_REGS. */ 1260 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1261 1262 /* When this hook returns true for MODE, the compiler allows 1263 registers explicitly used in the rtl to be used as spill registers 1264 but prevents the compiler from extending the lifetime of these 1265 registers. */ 1266 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1267 arm_small_register_classes_for_mode_p 1268 1269 /* Must leave BASE_REGS reloads alone */ 1270 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1271 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1272 ? ((true_regnum (X) == -1 ? LO_REGS \ 1273 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1274 : NO_REGS)) \ 1275 : NO_REGS) 1276 1277 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1278 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1279 ? ((true_regnum (X) == -1 ? LO_REGS \ 1280 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1281 : NO_REGS)) \ 1282 : NO_REGS) 1283 1284 /* Return the register class of a scratch register needed to copy IN into 1285 or out of a register in CLASS in MODE. If it can be done directly, 1286 NO_REGS is returned. */ 1287 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1288 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1289 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1290 && IS_VFP_CLASS (CLASS)) \ 1291 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1292 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1293 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1294 : TARGET_32BIT \ 1295 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1296 ? GENERAL_REGS : NO_REGS) \ 1297 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1298 1299 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1300 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1301 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1302 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1303 && IS_VFP_CLASS (CLASS)) \ 1304 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1305 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1306 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1307 (TARGET_32BIT ? \ 1308 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1309 && CONSTANT_P (X)) \ 1310 ? GENERAL_REGS : \ 1311 (((MODE) == HImode && ! arm_arch4 \ 1312 && (MEM_P (X) \ 1313 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1314 && true_regnum (X) == -1))) \ 1315 ? GENERAL_REGS : NO_REGS) \ 1316 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1317 1318 /* Try a machine-dependent way of reloading an illegitimate address 1319 operand. If we find one, push the reload and jump to WIN. This 1320 macro is used in only one place: `find_reloads_address' in reload.c. 1321 1322 For the ARM, we wish to handle large displacements off a base 1323 register by splitting the addend across a MOV and the mem insn. 1324 This can cut the number of reloads needed. */ 1325 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1326 do \ 1327 { \ 1328 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1329 goto WIN; \ 1330 } \ 1331 while (0) 1332 1333 /* XXX If an HImode FP+large_offset address is converted to an HImode 1334 SP+large_offset address, then reload won't know how to fix it. It sees 1335 only that SP isn't valid for HImode, and so reloads the SP into an index 1336 register, but the resulting address is still invalid because the offset 1337 is too big. We fix it here instead by reloading the entire address. */ 1338 /* We could probably achieve better results by defining PROMOTE_MODE to help 1339 cope with the variances between the Thumb's signed and unsigned byte and 1340 halfword load instructions. */ 1341 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1342 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1343 do { \ 1344 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1345 if (new_x) \ 1346 { \ 1347 X = new_x; \ 1348 goto WIN; \ 1349 } \ 1350 } while (0) 1351 1352 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1353 if (TARGET_ARM) \ 1354 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1355 else \ 1356 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1357 1358 /* Return the maximum number of consecutive registers 1359 needed to represent mode MODE in a register of class CLASS. 1360 ARM regs are UNITS_PER_WORD bits. 1361 FIXME: Is this true for iWMMX? */ 1362 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1363 (ARM_NUM_REGS (MODE)) 1364 1365 /* If defined, gives a class of registers that cannot be used as the 1366 operand of a SUBREG that changes the mode of the object illegally. */ 1367 1368 /* Stack layout; function entry, exit and calling. */ 1370 1371 /* Define this if pushing a word on the stack 1372 makes the stack pointer a smaller address. */ 1373 #define STACK_GROWS_DOWNWARD 1 1374 1375 /* Define this to nonzero if the nominal address of the stack frame 1376 is at the high-address end of the local variables; 1377 that is, each additional local variable allocated 1378 goes at a more negative offset in the frame. */ 1379 #define FRAME_GROWS_DOWNWARD 1 1380 1381 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1382 When present, it is one word in size, and sits at the top of the frame, 1383 between the soft frame pointer and either r7 or r11. 1384 1385 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1386 and only then if some outgoing arguments are passed on the stack. It would 1387 be tempting to also check whether the stack arguments are passed by indirect 1388 calls, but there seems to be no reason in principle why a post-reload pass 1389 couldn't convert a direct call into an indirect one. */ 1390 #define CALLER_INTERWORKING_SLOT_SIZE \ 1391 (TARGET_CALLER_INTERWORKING \ 1392 && crtl->outgoing_args_size != 0 \ 1393 ? UNITS_PER_WORD : 0) 1394 1395 /* Offset within stack frame to start allocating local variables at. 1396 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1397 first local allocated. Otherwise, it is the offset to the BEGINNING 1398 of the first local allocated. */ 1399 #define STARTING_FRAME_OFFSET 0 1400 1401 /* If we generate an insn to push BYTES bytes, 1402 this says how many the stack pointer really advances by. */ 1403 /* The push insns do not do this rounding implicitly. 1404 So don't define this. */ 1405 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1406 1407 /* Define this if the maximum size of all the outgoing args is to be 1408 accumulated and pushed during the prologue. The amount can be 1409 found in the variable crtl->outgoing_args_size. */ 1410 #define ACCUMULATE_OUTGOING_ARGS 1 1411 1412 /* Offset of first parameter from the argument pointer register value. */ 1413 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1414 1415 /* Amount of memory needed for an untyped call to save all possible return 1416 registers. */ 1417 #define APPLY_RESULT_SIZE arm_apply_result_size() 1418 1419 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1420 values must be in memory. On the ARM, they need only do so if larger 1421 than a word, or if they contain elements offset from zero in the struct. */ 1422 #define DEFAULT_PCC_STRUCT_RETURN 0 1423 1424 /* These bits describe the different types of function supported 1425 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1426 normal function and an interworked function, for example. Knowing the 1427 type of a function is important for determining its prologue and 1428 epilogue sequences. 1429 Note value 7 is currently unassigned. Also note that the interrupt 1430 function types all have bit 2 set, so that they can be tested for easily. 1431 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1432 machine_function structure is initialized (to zero) func_type will 1433 default to unknown. This will force the first use of arm_current_func_type 1434 to call arm_compute_func_type. */ 1435 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1436 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1437 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1438 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1439 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1440 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1441 1442 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1443 1444 /* In addition functions can have several type modifiers, 1445 outlined by these bit masks: */ 1446 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1447 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1448 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1449 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1450 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1451 1452 /* Some macros to test these flags. */ 1453 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1454 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1455 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1456 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1457 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1458 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1459 1460 1461 /* Structure used to hold the function stack frame layout. Offsets are 1462 relative to the stack pointer on function entry. Positive offsets are 1463 in the direction of stack growth. 1464 Only soft_frame is used in thumb mode. */ 1465 1466 typedef struct GTY(()) arm_stack_offsets 1467 { 1468 int saved_args; /* ARG_POINTER_REGNUM. */ 1469 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1470 int saved_regs; 1471 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1472 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1473 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1474 unsigned int saved_regs_mask; 1475 } 1476 arm_stack_offsets; 1477 1478 #ifndef GENERATOR_FILE 1479 /* A C structure for machine-specific, per-function data. 1480 This is added to the cfun structure. */ 1481 typedef struct GTY(()) machine_function 1482 { 1483 /* Additional stack adjustment in __builtin_eh_throw. */ 1484 rtx eh_epilogue_sp_ofs; 1485 /* Records if LR has to be saved for far jumps. */ 1486 int far_jump_used; 1487 /* Records if ARG_POINTER was ever live. */ 1488 int arg_pointer_live; 1489 /* Records if the save of LR has been eliminated. */ 1490 int lr_save_eliminated; 1491 /* The size of the stack frame. Only valid after reload. */ 1492 arm_stack_offsets stack_offsets; 1493 /* Records the type of the current function. */ 1494 unsigned long func_type; 1495 /* Record if the function has a variable argument list. */ 1496 int uses_anonymous_args; 1497 /* Records if sibcalls are blocked because an argument 1498 register is needed to preserve stack alignment. */ 1499 int sibcall_blocked; 1500 /* The PIC register for this function. This might be a pseudo. */ 1501 rtx pic_reg; 1502 /* Labels for per-function Thumb call-via stubs. One per potential calling 1503 register. We can never call via LR or PC. We can call via SP if a 1504 trampoline happens to be on the top of the stack. */ 1505 rtx call_via[14]; 1506 /* Set to 1 when a return insn is output, this means that the epilogue 1507 is not needed. */ 1508 int return_used_this_function; 1509 /* When outputting Thumb-1 code, record the last insn that provides 1510 information about condition codes, and the comparison operands. */ 1511 rtx thumb1_cc_insn; 1512 rtx thumb1_cc_op0; 1513 rtx thumb1_cc_op1; 1514 /* Also record the CC mode that is supported. */ 1515 enum machine_mode thumb1_cc_mode; 1516 } 1517 machine_function; 1518 #endif 1519 1520 /* As in the machine_function, a global set of call-via labels, for code 1521 that is in text_section. */ 1522 extern GTY(()) rtx thumb_call_via_label[14]; 1523 1524 /* The number of potential ways of assigning to a co-processor. */ 1525 #define ARM_NUM_COPROC_SLOTS 1 1526 1527 /* Enumeration of procedure calling standard variants. We don't really 1528 support all of these yet. */ 1529 enum arm_pcs 1530 { 1531 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1532 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1533 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1534 /* This must be the last AAPCS variant. */ 1535 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1536 ARM_PCS_ATPCS, /* ATPCS. */ 1537 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1538 ARM_PCS_UNKNOWN 1539 }; 1540 1541 /* Default procedure calling standard of current compilation unit. */ 1542 extern enum arm_pcs arm_pcs_default; 1543 1544 /* A C type for declaring a variable that is used as the first argument of 1545 `FUNCTION_ARG' and other related values. */ 1546 typedef struct 1547 { 1548 /* This is the number of registers of arguments scanned so far. */ 1549 int nregs; 1550 /* This is the number of iWMMXt register arguments scanned so far. */ 1551 int iwmmxt_nregs; 1552 int named_count; 1553 int nargs; 1554 /* Which procedure call variant to use for this call. */ 1555 enum arm_pcs pcs_variant; 1556 1557 /* AAPCS related state tracking. */ 1558 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1559 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1560 this argument, or -1 if using core 1561 registers. */ 1562 int aapcs_ncrn; 1563 int aapcs_next_ncrn; 1564 rtx aapcs_reg; /* Register assigned to this argument. */ 1565 int aapcs_partial; /* How many bytes are passed in regs (if 1566 split between core regs and stack. 1567 Zero otherwise. */ 1568 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1569 int can_split; /* Argument can be split between core regs 1570 and the stack. */ 1571 /* Private data for tracking VFP register allocation */ 1572 unsigned aapcs_vfp_regs_free; 1573 unsigned aapcs_vfp_reg_alloc; 1574 int aapcs_vfp_rcount; 1575 MACHMODE aapcs_vfp_rmode; 1576 } CUMULATIVE_ARGS; 1577 1578 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1579 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1580 1581 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1582 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1583 1584 /* For AAPCS, padding should never be below the argument. For other ABIs, 1585 * mimic the default. */ 1586 #define PAD_VARARGS_DOWN \ 1587 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1588 1589 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1590 for a call to a function whose data type is FNTYPE. 1591 For a library call, FNTYPE is 0. 1592 On the ARM, the offset starts at 0. */ 1593 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1594 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1595 1596 /* 1 if N is a possible register number for function argument passing. 1597 On the ARM, r0-r3 are used to pass args. */ 1598 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1599 (IN_RANGE ((REGNO), 0, 3) \ 1600 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1601 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1602 || (TARGET_IWMMXT_ABI \ 1603 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1604 1605 1606 /* If your target environment doesn't prefix user functions with an 1608 underscore, you may wish to re-define this to prevent any conflicts. */ 1609 #ifndef ARM_MCOUNT_NAME 1610 #define ARM_MCOUNT_NAME "*mcount" 1611 #endif 1612 1613 /* Call the function profiler with a given profile label. The Acorn 1614 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1615 On the ARM the full profile code will look like: 1616 .data 1617 LP1 1618 .word 0 1619 .text 1620 mov ip, lr 1621 bl mcount 1622 .word LP1 1623 1624 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1625 will output the .text section. 1626 1627 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1628 ``prof'' doesn't seem to mind about this! 1629 1630 Note - this version of the code is designed to work in both ARM and 1631 Thumb modes. */ 1632 #ifndef ARM_FUNCTION_PROFILER 1633 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1634 { \ 1635 char temp[20]; \ 1636 rtx sym; \ 1637 \ 1638 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1639 IP_REGNUM, LR_REGNUM); \ 1640 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1641 fputc ('\n', STREAM); \ 1642 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1643 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1644 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1645 } 1646 #endif 1647 1648 #ifdef THUMB_FUNCTION_PROFILER 1649 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1650 if (TARGET_ARM) \ 1651 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1652 else \ 1653 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1654 #else 1655 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1656 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1657 #endif 1658 1659 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1660 the stack pointer does not matter. The value is tested only in 1661 functions that have frame pointers. 1662 No definition is equivalent to always zero. 1663 1664 On the ARM, the function epilogue recovers the stack pointer from the 1665 frame. */ 1666 #define EXIT_IGNORE_STACK 1 1667 1668 #define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) 1669 1670 /* Determine if the epilogue should be output as RTL. 1671 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1672 #define USE_RETURN_INSN(ISCOND) \ 1673 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1674 1675 /* Definitions for register eliminations. 1676 1677 This is an array of structures. Each structure initializes one pair 1678 of eliminable registers. The "from" register number is given first, 1679 followed by "to". Eliminations of the same "from" register are listed 1680 in order of preference. 1681 1682 We have two registers that can be eliminated on the ARM. First, the 1683 arg pointer register can often be eliminated in favor of the stack 1684 pointer register. Secondly, the pseudo frame pointer register can always 1685 be eliminated; it is replaced with either the stack or the real frame 1686 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1687 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1688 1689 #define ELIMINABLE_REGS \ 1690 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1691 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1692 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1693 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1694 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1695 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1696 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1697 1698 /* Define the offset between two registers, one to be eliminated, and the 1699 other its replacement, at the start of a routine. */ 1700 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1701 if (TARGET_ARM) \ 1702 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1703 else \ 1704 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1705 1706 /* Special case handling of the location of arguments passed on the stack. */ 1707 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1708 1709 /* Initialize data used by insn expanders. This is called from insn_emit, 1710 once for every function before code is generated. */ 1711 #define INIT_EXPANDERS arm_init_expanders () 1712 1713 /* Length in units of the trampoline for entering a nested function. */ 1714 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1715 1716 /* Alignment required for a trampoline in bits. */ 1717 #define TRAMPOLINE_ALIGNMENT 32 1718 1719 /* Addressing modes, and classification of registers for them. */ 1721 #define HAVE_POST_INCREMENT 1 1722 #define HAVE_PRE_INCREMENT TARGET_32BIT 1723 #define HAVE_POST_DECREMENT TARGET_32BIT 1724 #define HAVE_PRE_DECREMENT TARGET_32BIT 1725 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1726 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1727 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1728 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1729 1730 enum arm_auto_incmodes 1731 { 1732 ARM_POST_INC, 1733 ARM_PRE_INC, 1734 ARM_POST_DEC, 1735 ARM_PRE_DEC 1736 }; 1737 1738 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1739 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1740 #define USE_LOAD_POST_INCREMENT(mode) \ 1741 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1742 #define USE_LOAD_PRE_INCREMENT(mode) \ 1743 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1744 #define USE_LOAD_POST_DECREMENT(mode) \ 1745 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1746 #define USE_LOAD_PRE_DECREMENT(mode) \ 1747 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1748 1749 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1750 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1751 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1752 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1753 1754 /* Macros to check register numbers against specific register classes. */ 1755 1756 /* These assume that REGNO is a hard or pseudo reg number. 1757 They give nonzero only if REGNO is a hard reg of the suitable class 1758 or a pseudo reg currently allocated to a suitable hard reg. 1759 Since they use reg_renumber, they are safe only once reg_renumber 1760 has been allocated, which happens in reginfo.c during register 1761 allocation. */ 1762 #define TEST_REGNO(R, TEST, VALUE) \ 1763 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1764 1765 /* Don't allow the pc to be used. */ 1766 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1767 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1768 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1769 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1770 1771 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1772 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1773 || (GET_MODE_SIZE (MODE) >= 4 \ 1774 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1775 1776 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1777 (TARGET_THUMB1 \ 1778 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1779 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1780 1781 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1782 For Thumb, we can not use SP + reg, so reject SP. */ 1783 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1784 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1785 1786 /* For ARM code, we don't care about the mode, but for Thumb, the index 1787 must be suitable for use in a QImode load. */ 1788 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1789 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1790 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1791 1792 /* Maximum number of registers that can appear in a valid memory address. 1793 Shifts in addresses can't be by a register. */ 1794 #define MAX_REGS_PER_ADDRESS 2 1795 1796 /* Recognize any constant value that is a valid address. */ 1797 /* XXX We can address any constant, eventually... */ 1798 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1799 #define CONSTANT_ADDRESS_P(X) \ 1800 (GET_CODE (X) == SYMBOL_REF \ 1801 && (CONSTANT_POOL_ADDRESS_P (X) \ 1802 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1803 1804 /* True if SYMBOL + OFFSET constants must refer to something within 1805 SYMBOL's section. */ 1806 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1807 1808 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1809 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1810 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1811 #endif 1812 1813 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1814 #define SUBTARGET_NAME_ENCODING_LENGTHS 1815 #endif 1816 1817 /* This is a C fragment for the inside of a switch statement. 1818 Each case label should return the number of characters to 1819 be stripped from the start of a function's name, if that 1820 name starts with the indicated character. */ 1821 #define ARM_NAME_ENCODING_LENGTHS \ 1822 case '*': return 1; \ 1823 SUBTARGET_NAME_ENCODING_LENGTHS 1824 1825 /* This is how to output a reference to a user-level label named NAME. 1826 `assemble_name' uses this. */ 1827 #undef ASM_OUTPUT_LABELREF 1828 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1829 arm_asm_output_labelref (FILE, NAME) 1830 1831 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1832 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1833 if (TARGET_THUMB2) \ 1834 thumb2_asm_output_opcode (STREAM); 1835 1836 /* The EABI specifies that constructors should go in .init_array. 1837 Other targets use .ctors for compatibility. */ 1838 #ifndef ARM_EABI_CTORS_SECTION_OP 1839 #define ARM_EABI_CTORS_SECTION_OP \ 1840 "\t.section\t.init_array,\"aw\",%init_array" 1841 #endif 1842 #ifndef ARM_EABI_DTORS_SECTION_OP 1843 #define ARM_EABI_DTORS_SECTION_OP \ 1844 "\t.section\t.fini_array,\"aw\",%fini_array" 1845 #endif 1846 #define ARM_CTORS_SECTION_OP \ 1847 "\t.section\t.ctors,\"aw\",%progbits" 1848 #define ARM_DTORS_SECTION_OP \ 1849 "\t.section\t.dtors,\"aw\",%progbits" 1850 1851 /* Define CTORS_SECTION_ASM_OP. */ 1852 #undef CTORS_SECTION_ASM_OP 1853 #undef DTORS_SECTION_ASM_OP 1854 #ifndef IN_LIBGCC2 1855 # define CTORS_SECTION_ASM_OP \ 1856 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1857 # define DTORS_SECTION_ASM_OP \ 1858 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1859 #else /* !defined (IN_LIBGCC2) */ 1860 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1861 so we cannot use the definition above. */ 1862 # ifdef __ARM_EABI__ 1863 /* The .ctors section is not part of the EABI, so we do not define 1864 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1865 from trying to use it. We do define it when doing normal 1866 compilation, as .init_array can be used instead of .ctors. */ 1867 /* There is no need to emit begin or end markers when using 1868 init_array; the dynamic linker will compute the size of the 1869 array itself based on special symbols created by the static 1870 linker. However, we do need to arrange to set up 1871 exception-handling here. */ 1872 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1873 # define CTOR_LIST_END /* empty */ 1874 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1875 # define DTOR_LIST_END /* empty */ 1876 # else /* !defined (__ARM_EABI__) */ 1877 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1878 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1879 # endif /* !defined (__ARM_EABI__) */ 1880 #endif /* !defined (IN_LIBCC2) */ 1881 1882 /* True if the operating system can merge entities with vague linkage 1883 (e.g., symbols in COMDAT group) during dynamic linking. */ 1884 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1885 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1886 #endif 1887 1888 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1889 1890 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1891 and check its validity for a certain class. 1892 We have two alternate definitions for each of them. 1893 The usual definition accepts all pseudo regs; the other rejects 1894 them unless they have been allocated suitable hard regs. 1895 The symbol REG_OK_STRICT causes the latter definition to be used. 1896 Thumb-2 has the same restrictions as arm. */ 1897 #ifndef REG_OK_STRICT 1898 1899 #define ARM_REG_OK_FOR_BASE_P(X) \ 1900 (REGNO (X) <= LAST_ARM_REGNUM \ 1901 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1902 || REGNO (X) == FRAME_POINTER_REGNUM \ 1903 || REGNO (X) == ARG_POINTER_REGNUM) 1904 1905 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1906 ((REGNO (X) <= LAST_ARM_REGNUM \ 1907 && REGNO (X) != STACK_POINTER_REGNUM) \ 1908 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1909 || REGNO (X) == FRAME_POINTER_REGNUM \ 1910 || REGNO (X) == ARG_POINTER_REGNUM) 1911 1912 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1913 (REGNO (X) <= LAST_LO_REGNUM \ 1914 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1915 || (GET_MODE_SIZE (MODE) >= 4 \ 1916 && (REGNO (X) == STACK_POINTER_REGNUM \ 1917 || (X) == hard_frame_pointer_rtx \ 1918 || (X) == arg_pointer_rtx))) 1919 1920 #define REG_STRICT_P 0 1921 1922 #else /* REG_OK_STRICT */ 1923 1924 #define ARM_REG_OK_FOR_BASE_P(X) \ 1925 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1926 1927 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1928 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1929 1930 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1931 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1932 1933 #define REG_STRICT_P 1 1934 1935 #endif /* REG_OK_STRICT */ 1936 1937 /* Now define some helpers in terms of the above. */ 1938 1939 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1940 (TARGET_THUMB1 \ 1941 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1942 : ARM_REG_OK_FOR_BASE_P (X)) 1943 1944 /* For 16-bit Thumb, a valid index register is anything that can be used in 1945 a byte load instruction. */ 1946 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1947 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1948 1949 /* Nonzero if X is a hard reg that can be used as an index 1950 or if it is a pseudo reg. On the Thumb, the stack pointer 1951 is not suitable. */ 1952 #define REG_OK_FOR_INDEX_P(X) \ 1953 (TARGET_THUMB1 \ 1954 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1955 : ARM_REG_OK_FOR_INDEX_P (X)) 1956 1957 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1958 For Thumb, we can not use SP + reg, so reject SP. */ 1959 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1960 REG_OK_FOR_INDEX_P (X) 1961 1962 #define ARM_BASE_REGISTER_RTX_P(X) \ 1964 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1965 1966 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1967 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1968 1969 /* Specify the machine mode that this machine uses 1971 for the index in the tablejump instruction. */ 1972 #define CASE_VECTOR_MODE Pmode 1973 1974 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 1975 || (TARGET_THUMB1 \ 1976 && (optimize_size || flag_pic))) 1977 1978 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1979 (TARGET_THUMB1 \ 1980 ? (min >= 0 && max < 512 \ 1981 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1982 : min >= -256 && max < 256 \ 1983 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1984 : min >= 0 && max < 8192 \ 1985 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1986 : min >= -4096 && max < 4096 \ 1987 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1988 : SImode) \ 1989 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1990 : (max >= 0x200) ? HImode \ 1991 : QImode)) 1992 1993 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1994 unsigned is probably best, but may break some code. */ 1995 #ifndef DEFAULT_SIGNED_CHAR 1996 #define DEFAULT_SIGNED_CHAR 0 1997 #endif 1998 1999 /* Max number of bytes we can move from memory to memory 2000 in one reasonably fast instruction. */ 2001 #define MOVE_MAX 4 2002 2003 #undef MOVE_RATIO 2004 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2005 2006 /* Define if operations between registers always perform the operation 2007 on the full register even if a narrower mode is specified. */ 2008 #define WORD_REGISTER_OPERATIONS 2009 2010 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2011 will either zero-extend or sign-extend. The value of this macro should 2012 be the code that says which one of the two operations is implicitly 2013 done, UNKNOWN if none. */ 2014 #define LOAD_EXTEND_OP(MODE) \ 2015 (TARGET_THUMB ? ZERO_EXTEND : \ 2016 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2017 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2018 2019 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2020 #define SLOW_BYTE_ACCESS 0 2021 2022 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2023 2024 /* Immediate shift counts are truncated by the output routines (or was it 2025 the assembler?). Shift counts in a register are truncated by ARM. Note 2026 that the native compiler puts too large (> 32) immediate shift counts 2027 into a register and shifts by the register, letting the ARM decide what 2028 to do instead of doing that itself. */ 2029 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2030 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2031 On the arm, Y in a register is used modulo 256 for the shift. Only for 2032 rotates is modulo 32 used. */ 2033 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2034 2035 /* All integers have the same format so truncation is easy. */ 2036 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2037 2038 /* Calling from registers is a massive pain. */ 2039 #define NO_FUNCTION_CSE 1 2040 2041 /* The machine modes of pointers and functions */ 2042 #define Pmode SImode 2043 #define FUNCTION_MODE Pmode 2044 2045 #define ARM_FRAME_RTX(X) \ 2046 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2047 || (X) == arg_pointer_rtx) 2048 2049 /* Try to generate sequences that don't involve branches, we can then use 2050 conditional instructions. */ 2051 #define BRANCH_COST(speed_p, predictable_p) \ 2052 (current_tune->branch_cost (speed_p, predictable_p)) 2053 2054 /* False if short circuit operation is preferred. */ 2055 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2056 ((optimize_size) \ 2057 ? (TARGET_THUMB ? false : true) \ 2058 : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) 2059 2060 2061 /* Position Independent Code. */ 2063 /* We decide which register to use based on the compilation options and 2064 the assembler in use; this is more general than the APCS restriction of 2065 using sb (r9) all the time. */ 2066 extern unsigned arm_pic_register; 2067 2068 /* The register number of the register used to address a table of static 2069 data addresses in memory. */ 2070 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2071 2072 /* We can't directly access anything that contains a symbol, 2073 nor can we indirect via the constant pool. One exception is 2074 UNSPEC_TLS, which is always PIC. */ 2075 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2076 (!(symbol_mentioned_p (X) \ 2077 || label_mentioned_p (X) \ 2078 || (GET_CODE (X) == SYMBOL_REF \ 2079 && CONSTANT_POOL_ADDRESS_P (X) \ 2080 && (symbol_mentioned_p (get_pool_constant (X)) \ 2081 || label_mentioned_p (get_pool_constant (X))))) \ 2082 || tls_mentioned_p (X)) 2083 2084 /* We need to know when we are making a constant pool; this determines 2085 whether data needs to be in the GOT or can be referenced via a GOT 2086 offset. */ 2087 extern int making_const_table; 2088 2089 /* Handle pragmas for compatibility with Intel's compilers. */ 2091 /* Also abuse this to register additional C specific EABI attributes. */ 2092 #define REGISTER_TARGET_PRAGMAS() do { \ 2093 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2094 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2095 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2096 arm_lang_object_attributes_init(); \ 2097 } while (0) 2098 2099 /* Condition code information. */ 2100 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2101 return the mode to be used for the comparison. */ 2102 2103 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2104 2105 #define REVERSIBLE_CC_MODE(MODE) 1 2106 2107 #define REVERSE_CONDITION(CODE,MODE) \ 2108 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2109 ? reverse_condition_maybe_unordered (code) \ 2110 : reverse_condition (code)) 2111 2112 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2113 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) 2114 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2115 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE)) 2116 2117 #define CC_STATUS_INIT \ 2119 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2120 2121 #undef ASM_APP_OFF 2122 #define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2123 TARGET_THUMB2 ? "\t.thumb\n" : "") 2124 2125 /* Output a push or a pop instruction (only used when profiling). 2126 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2127 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2128 that r7 isn't used by the function profiler, so we can use it as a 2129 scratch reg. WARNING: This isn't safe in the general case! It may be 2130 sensitive to future changes in final.c:profile_function. */ 2131 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2132 do \ 2133 { \ 2134 if (TARGET_ARM) \ 2135 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2136 STACK_POINTER_REGNUM, REGNO); \ 2137 else if (TARGET_THUMB1 \ 2138 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2139 { \ 2140 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2141 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2142 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2143 } \ 2144 else \ 2145 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2146 } while (0) 2147 2148 2149 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2150 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2151 do \ 2152 { \ 2153 if (TARGET_ARM) \ 2154 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2155 STACK_POINTER_REGNUM, REGNO); \ 2156 else if (TARGET_THUMB1 \ 2157 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2158 { \ 2159 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2160 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2161 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2162 } \ 2163 else \ 2164 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2165 } while (0) 2166 2167 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2168 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2169 2170 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2171 default alignment from elfos.h. */ 2172 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2173 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2174 2175 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2176 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2177 ? 1 : 0) 2178 2179 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2180 do \ 2181 { \ 2182 if (TARGET_THUMB) \ 2183 { \ 2184 if (is_called_in_ARM_mode (DECL) \ 2185 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2186 && cfun->is_thunk)) \ 2187 fprintf (STREAM, "\t.code 32\n") ; \ 2188 else if (TARGET_THUMB1) \ 2189 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2190 else \ 2191 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2192 } \ 2193 if (TARGET_POKE_FUNCTION_NAME) \ 2194 arm_poke_function_name (STREAM, (const char *) NAME); \ 2195 } \ 2196 while (0) 2197 2198 /* For aliases of functions we use .thumb_set instead. */ 2199 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2200 do \ 2201 { \ 2202 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2203 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2204 \ 2205 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2206 { \ 2207 fprintf (FILE, "\t.thumb_set "); \ 2208 assemble_name (FILE, LABEL1); \ 2209 fprintf (FILE, ","); \ 2210 assemble_name (FILE, LABEL2); \ 2211 fprintf (FILE, "\n"); \ 2212 } \ 2213 else \ 2214 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2215 } \ 2216 while (0) 2217 2218 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2219 /* To support -falign-* switches we need to use .p2align so 2220 that alignment directives in code sections will be padded 2221 with no-op instructions, rather than zeroes. */ 2222 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2223 if ((LOG) != 0) \ 2224 { \ 2225 if ((MAX_SKIP) == 0) \ 2226 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2227 else \ 2228 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2229 (int) (LOG), (int) (MAX_SKIP)); \ 2230 } 2231 #endif 2232 2233 /* Add two bytes to the length of conditionally executed Thumb-2 2235 instructions for the IT instruction. */ 2236 #define ADJUST_INSN_LENGTH(insn, length) \ 2237 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2238 length += 2; 2239 2240 /* Only perform branch elimination (by making instructions conditional) if 2241 we're optimizing. For Thumb-2 check if any IT instructions need 2242 outputting. */ 2243 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2244 if (TARGET_ARM && optimize) \ 2245 arm_final_prescan_insn (INSN); \ 2246 else if (TARGET_THUMB2) \ 2247 thumb2_final_prescan_insn (INSN); \ 2248 else if (TARGET_THUMB1) \ 2249 thumb1_final_prescan_insn (INSN) 2250 2251 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2252 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2253 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2254 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2255 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2256 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2257 : 0)))) 2258 2259 /* A C expression whose value is RTL representing the value of the return 2260 address for the frame COUNT steps up from the current frame. */ 2261 2262 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2263 arm_return_addr (COUNT, FRAME) 2264 2265 /* Mask of the bits in the PC that contain the real return address 2266 when running in 26-bit mode. */ 2267 #define RETURN_ADDR_MASK26 (0x03fffffc) 2268 2269 /* Pick up the return address upon entry to a procedure. Used for 2270 dwarf2 unwind information. This also enables the table driven 2271 mechanism. */ 2272 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2273 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2274 2275 /* Used to mask out junk bits from the return address, such as 2276 processor state, interrupt status, condition codes and the like. */ 2277 #define MASK_RETURN_ADDR \ 2278 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2279 in 26 bit mode, the condition codes must be masked out of the \ 2280 return address. This does not apply to ARM6 and later processors \ 2281 when running in 32 bit mode. */ \ 2282 ((arm_arch4 || TARGET_THUMB) \ 2283 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2284 : arm_gen_return_addr_mask ()) 2285 2286 2287 /* Do not emit .note.GNU-stack by default. */ 2289 #ifndef NEED_INDICATE_EXEC_STACK 2290 #define NEED_INDICATE_EXEC_STACK 0 2291 #endif 2292 2293 #define TARGET_ARM_ARCH \ 2294 (arm_base_arch) \ 2295 2296 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2297 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2298 2299 /* The highest Thumb instruction set version supported by the chip. */ 2300 #define TARGET_ARM_ARCH_ISA_THUMB \ 2301 (arm_arch_thumb2 ? 2 \ 2302 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2303 2304 /* Expands to an upper-case char of the target's architectural 2305 profile. */ 2306 #define TARGET_ARM_ARCH_PROFILE \ 2307 (!arm_arch_notm \ 2308 ? 'M' \ 2309 : (arm_arch7 \ 2310 ? (strlen (arm_arch_name) >=3 \ 2311 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2312 : 0) \ 2313 : 0)) 2314 2315 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2316 Bit 0 for bytes, up to bit 3 for double-words. */ 2317 #define TARGET_ARM_FEATURE_LDREX \ 2318 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2319 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2320 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2321 2322 /* Set as a bit mask indicating the available widths of hardware floating 2323 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2324 32-bit support, bit 3 indicates 64-bit support. */ 2325 #define TARGET_ARM_FP \ 2326 (TARGET_VFP_SINGLE ? 4 \ 2327 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) 2328 2329 2330 /* Set as a bit mask indicating the available widths of floating point 2331 types for hardware NEON floating point. This is the same as 2332 TARGET_ARM_FP without the 64-bit bit set. */ 2333 #ifdef TARGET_NEON 2334 #define TARGET_NEON_FP \ 2335 (TARGET_ARM_FP & (0xff ^ 0x08)) 2336 #endif 2337 2338 /* The maximum number of parallel loads or stores we support in an ldm/stm 2339 instruction. */ 2340 #define MAX_LDM_STM_OPS 4 2341 2342 #define ASM_CPU_SPEC \ 2343 " %{mcpu=generic-*:-march=%*;" \ 2344 " :%{mcpu=*:-mcpu=%*} %{march=*:-march=%*}}" 2345 2346 /* -mcpu=native handling only makes sense with compiler running on 2347 an ARM chip. */ 2348 #if defined(__arm__) && defined(__linux__) 2349 extern const char *host_detect_local_cpu (int argc, const char **argv); 2350 # define EXTRA_SPEC_FUNCTIONS \ 2351 { "local_cpu_detect", host_detect_local_cpu }, 2352 2353 # define MCPU_MTUNE_NATIVE_SPECS \ 2354 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2355 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2356 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2357 #else 2358 # define MCPU_MTUNE_NATIVE_SPECS "" 2359 #endif 2360 2361 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2362 2363 #endif /* ! GCC_ARM_H */ 2364
Indexes created Sun Apr 19 00:22:55 UTC 2026