arm.h revision 1.1.1.3
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2015 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() \ 49 do \ 50 { \ 51 if (TARGET_DSP_MULTIPLY) \ 52 builtin_define ("__ARM_FEATURE_DSP"); \ 53 if (TARGET_ARM_QBIT) \ 54 builtin_define ("__ARM_FEATURE_QBIT"); \ 55 if (TARGET_ARM_SAT) \ 56 builtin_define ("__ARM_FEATURE_SAT"); \ 57 if (TARGET_CRYPTO) \ 58 builtin_define ("__ARM_FEATURE_CRYPTO"); \ 59 if (unaligned_access) \ 60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 61 if (TARGET_CRC32) \ 62 builtin_define ("__ARM_FEATURE_CRC32"); \ 63 if (TARGET_32BIT) \ 64 builtin_define ("__ARM_32BIT_STATE"); \ 65 if (TARGET_ARM_FEATURE_LDREX) \ 66 builtin_define_with_int_value ( \ 67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ 68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ 69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \ 70 builtin_define ("__ARM_FEATURE_CLZ"); \ 71 if (TARGET_INT_SIMD) \ 72 builtin_define ("__ARM_FEATURE_SIMD32"); \ 73 \ 74 builtin_define_with_int_value ( \ 75 "__ARM_SIZEOF_MINIMAL_ENUM", \ 76 flag_short_enums ? 1 : 4); \ 77 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ 78 wchar_type_node); \ 79 if (TARGET_ARM_ARCH_PROFILE) \ 80 builtin_define_with_int_value ( \ 81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ 82 \ 83 /* Define __arm__ even when in thumb mode, for \ 84 consistency with armcc. */ \ 85 builtin_define ("__arm__"); \ 86 if (TARGET_ARM_ARCH) \ 87 builtin_define_with_int_value ( \ 88 "__ARM_ARCH", TARGET_ARM_ARCH); \ 89 if (arm_arch_notm) \ 90 builtin_define ("__ARM_ARCH_ISA_ARM"); \ 91 builtin_define ("__APCS_32__"); \ 92 if (TARGET_THUMB) \ 93 builtin_define ("__thumb__"); \ 94 if (TARGET_THUMB2) \ 95 builtin_define ("__thumb2__"); \ 96 if (TARGET_ARM_ARCH_ISA_THUMB) \ 97 builtin_define_with_int_value ( \ 98 "__ARM_ARCH_ISA_THUMB", \ 99 TARGET_ARM_ARCH_ISA_THUMB); \ 100 \ 101 if (TARGET_BIG_END) \ 102 { \ 103 builtin_define ("__ARMEB__"); \ 104 builtin_define ("__ARM_BIG_ENDIAN"); \ 105 if (TARGET_THUMB) \ 106 builtin_define ("__THUMBEB__"); \ 107 } \ 108 else \ 109 { \ 110 builtin_define ("__ARMEL__"); \ 111 if (TARGET_THUMB) \ 112 builtin_define ("__THUMBEL__"); \ 113 } \ 114 \ 115 if (TARGET_SOFT_FLOAT) \ 116 builtin_define ("__SOFTFP__"); \ 117 \ 118 if (TARGET_VFP) \ 119 builtin_define ("__VFP_FP__"); \ 120 \ 121 if (TARGET_ARM_FP) \ 122 builtin_define_with_int_value ( \ 123 "__ARM_FP", TARGET_ARM_FP); \ 124 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ 125 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ 126 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ 127 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ 128 if (TARGET_FMA) \ 129 builtin_define ("__ARM_FEATURE_FMA"); \ 130 \ 131 if (TARGET_NEON) \ 132 { \ 133 builtin_define ("__ARM_NEON__"); \ 134 builtin_define ("__ARM_NEON"); \ 135 } \ 136 if (TARGET_NEON_FP) \ 137 builtin_define_with_int_value ( \ 138 "__ARM_NEON_FP", TARGET_NEON_FP); \ 139 \ 140 /* Add a define for interworking. \ 141 Needed when building libgcc.a. */ \ 142 if (arm_cpp_interwork) \ 143 builtin_define ("__THUMB_INTERWORK__"); \ 144 \ 145 builtin_assert ("cpu=arm"); \ 146 builtin_assert ("machine=arm"); \ 147 \ 148 builtin_define (arm_arch_name); \ 149 if (arm_arch_xscale) \ 150 builtin_define ("__XSCALE__"); \ 151 if (arm_arch_iwmmxt) \ 152 { \ 153 builtin_define ("__IWMMXT__"); \ 154 builtin_define ("__ARM_WMMX"); \ 155 } \ 156 if (arm_arch_iwmmxt2) \ 157 builtin_define ("__IWMMXT2__"); \ 158 if (TARGET_AAPCS_BASED) \ 159 { \ 160 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 161 builtin_define ("__ARM_PCS_VFP"); \ 162 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 163 builtin_define ("__ARM_PCS"); \ 164 builtin_define ("__ARM_EABI__"); \ 165 } \ 166 if (TARGET_IDIV) \ 167 { \ 168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 169 builtin_define ("__ARM_FEATURE_IDIV"); \ 170 } \ 171 if (inline_asm_unified) \ 172 builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");\ 173 } while (0) 174 175 #include "config/arm/arm-opts.h" 176 177 enum target_cpus 178 { 179 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ 180 TARGET_CPU_##INTERNAL_IDENT, 181 #include "arm-cores.def" 182 #undef ARM_CORE 183 TARGET_CPU_generic 184 }; 185 186 /* The processor for which instructions should be scheduled. */ 187 extern enum processor_type arm_tune; 188 189 typedef enum arm_cond_code 190 { 191 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 192 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 193 } 194 arm_cc; 195 196 extern arm_cc arm_current_cc; 197 198 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 199 200 /* The maximum number of instructions that is beneficial to 201 conditionally execute. */ 202 #undef MAX_CONDITIONAL_EXECUTE 203 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 204 205 extern int arm_target_label; 206 extern int arm_ccfsm_state; 207 extern GTY(()) rtx arm_target_insn; 208 /* The label of the current constant pool. */ 209 extern rtx pool_vector_label; 210 /* Set to 1 when a return insn is output, this means that the epilogue 211 is not needed. */ 212 extern int return_used_this_function; 213 /* Callback to output language specific object attributes. */ 214 extern void (*arm_lang_output_object_attributes_hook)(void); 215 216 /* Just in case configure has failed to define anything. */ 218 #ifndef TARGET_CPU_DEFAULT 219 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 220 #endif 221 222 223 #undef CPP_SPEC 224 #define CPP_SPEC "%(subtarget_cpp_spec) \ 225 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 226 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 227 %{mbig-endian:%{mlittle-endian: \ 228 %e-mbig-endian and -mlittle-endian may not be used together}}" 229 230 #ifndef CC1_SPEC 231 #define CC1_SPEC "" 232 #endif 233 234 /* This macro defines names of additional specifications to put in the specs 235 that can be used in various specifications like CC1_SPEC. Its definition 236 is an initializer with a subgrouping for each command option. 237 238 Each subgrouping contains a string constant, that defines the 239 specification name, and a string constant that used by the GCC driver 240 program. 241 242 Do not define this macro if it does not need to do anything. */ 243 #define EXTRA_SPECS \ 244 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 245 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 246 SUBTARGET_EXTRA_SPECS 247 248 #ifndef SUBTARGET_EXTRA_SPECS 249 #define SUBTARGET_EXTRA_SPECS 250 #endif 251 252 #ifndef SUBTARGET_CPP_SPEC 253 #define SUBTARGET_CPP_SPEC "" 254 #endif 255 256 /* Run-time Target Specification. */ 258 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 259 /* Use hardware floating point instructions. */ 260 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 261 /* Use hardware floating point calling convention. */ 262 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 263 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 264 #define TARGET_IWMMXT (arm_arch_iwmmxt) 265 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 266 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 267 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 268 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 269 #define TARGET_ARM (! TARGET_THUMB) 270 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 271 #define TARGET_BACKTRACE (leaf_function_p () \ 272 ? TARGET_TPCS_LEAF_FRAME \ 273 : TARGET_TPCS_FRAME) 274 #define TARGET_AAPCS_BASED \ 275 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 276 277 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 278 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 279 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 280 281 /* Only 16-bit thumb code. */ 282 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 283 /* Arm or Thumb-2 32-bit code. */ 284 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 285 /* 32-bit Thumb-2 code. */ 286 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 287 /* Thumb-1 only. */ 288 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 289 290 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 291 && !TARGET_THUMB1) 292 293 #define TARGET_CRC32 (arm_arch_crc) 294 295 /* The following two macros concern the ability to execute coprocessor 296 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 297 only ever tested when we know we are generating for VFP hardware; we need 298 to be more careful with TARGET_NEON as noted below. */ 299 300 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 301 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 302 303 /* FPU supports VFPv3 instructions. */ 304 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 305 306 /* FPU supports FPv5 instructions. */ 307 #define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5) 308 309 /* FPU only supports VFP single-precision instructions. */ 310 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 311 312 /* FPU supports VFP double-precision instructions. */ 313 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 314 315 /* FPU supports half-precision floating-point with NEON element load/store. */ 316 #define TARGET_NEON_FP16 \ 317 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 318 319 /* FPU supports VFP half-precision floating-point. */ 320 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 321 322 /* FPU supports fused-multiply-add operations. */ 323 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) 324 325 /* FPU is ARMv8 compatible. */ 326 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) 327 328 /* FPU supports Crypto extensions. */ 329 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) 330 331 /* FPU supports Neon instructions. The setting of this macro gets 332 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 333 and TARGET_HARD_FLOAT to ensure that NEON instructions are 334 available. */ 335 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 336 && TARGET_VFP && arm_fpu_desc->neon) 337 338 /* Q-bit is present. */ 339 #define TARGET_ARM_QBIT \ 340 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 341 /* Saturation operation, e.g. SSAT. */ 342 #define TARGET_ARM_SAT \ 343 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 344 /* "DSP" multiply instructions, eg. SMULxy. */ 345 #define TARGET_DSP_MULTIPLY \ 346 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 347 /* Integer SIMD instructions, and extend-accumulate instructions. */ 348 #define TARGET_INT_SIMD \ 349 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 350 351 /* Should MOVW/MOVT be used in preference to a constant pool. */ 352 #define TARGET_USE_MOVT \ 353 (arm_arch_thumb2 \ 354 && (arm_disable_literal_pool \ 355 || (!optimize_size && !current_tune->prefer_constant_pool))) 356 357 /* We could use unified syntax for arm mode, but for now we just use it 358 for thumb mode. */ 359 #define TARGET_UNIFIED_ASM (TARGET_THUMB) 360 361 /* Nonzero if this chip provides the DMB instruction. */ 362 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 363 364 /* Nonzero if this chip implements a memory barrier via CP15. */ 365 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 366 && ! TARGET_THUMB1) 367 368 /* Nonzero if this chip implements a memory barrier instruction. */ 369 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 370 371 /* Nonzero if this chip supports ldrex and strex */ 372 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 373 374 /* Nonzero if this chip supports LPAE. */ 375 #define TARGET_HAVE_LPAE \ 376 (arm_arch7 && ((insn_flags & FL_FOR_ARCH7VE) == FL_FOR_ARCH7VE)) 377 378 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 379 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 380 381 /* Nonzero if this chip supports ldrexd and strexd. */ 382 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ 383 && arm_arch_notm) 384 385 /* Nonzero if this chip supports load-acquire and store-release. */ 386 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 387 388 /* Nonzero if integer division instructions supported. */ 389 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 390 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 391 392 /* Nonzero if disallow volatile memory access in IT block. */ 393 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 394 395 /* Should NEON be used for 64-bits bitops. */ 396 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 397 398 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 399 then TARGET_AAPCS_BASED must be true -- but the converse does not 400 hold. TARGET_BPABI implies the use of the BPABI runtime library, 401 etc., in addition to just the AAPCS calling conventions. */ 402 #ifndef TARGET_BPABI 403 #define TARGET_BPABI false 404 #endif 405 406 /* Support for a compile-time default CPU, et cetera. The rules are: 407 --with-arch is ignored if -march or -mcpu are specified. 408 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 409 by --with-arch. 410 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 411 by -march). 412 --with-float is ignored if -mfloat-abi is specified. 413 --with-fpu is ignored if -mfpu is specified. 414 --with-abi is ignored if -mabi is specified. 415 --with-tls is ignored if -mtls-dialect is specified. */ 416 #define OPTION_DEFAULT_SPECS \ 417 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 418 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 419 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 420 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 421 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 422 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 423 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 424 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 425 426 /* Which floating point model to use. */ 427 enum arm_fp_model 428 { 429 ARM_FP_MODEL_UNKNOWN, 430 /* VFP floating point model. */ 431 ARM_FP_MODEL_VFP 432 }; 433 434 enum vfp_reg_type 435 { 436 VFP_NONE = 0, 437 VFP_REG_D16, 438 VFP_REG_D32, 439 VFP_REG_SINGLE 440 }; 441 442 extern const struct arm_fpu_desc 443 { 444 const char *name; 445 enum arm_fp_model model; 446 int rev; 447 enum vfp_reg_type regs; 448 int neon; 449 int fp16; 450 int crypto; 451 } *arm_fpu_desc; 452 453 /* Which floating point hardware to schedule for. */ 454 extern int arm_fpu_attr; 455 456 #ifndef TARGET_DEFAULT_FLOAT_ABI 457 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 458 #endif 459 460 #ifndef ARM_DEFAULT_ABI 461 #define ARM_DEFAULT_ABI ARM_ABI_APCS 462 #endif 463 464 /* Map each of the micro-architecture variants to their corresponding 465 major architecture revision. */ 466 467 enum base_architecture 468 { 469 BASE_ARCH_0 = 0, 470 BASE_ARCH_2 = 2, 471 BASE_ARCH_3 = 3, 472 BASE_ARCH_3M = 3, 473 BASE_ARCH_4 = 4, 474 BASE_ARCH_4T = 4, 475 BASE_ARCH_5 = 5, 476 BASE_ARCH_5E = 5, 477 BASE_ARCH_5T = 5, 478 BASE_ARCH_5TE = 5, 479 BASE_ARCH_5TEJ = 5, 480 BASE_ARCH_6 = 6, 481 BASE_ARCH_6J = 6, 482 BASE_ARCH_6ZK = 6, 483 BASE_ARCH_6K = 6, 484 BASE_ARCH_6T2 = 6, 485 BASE_ARCH_6M = 6, 486 BASE_ARCH_6Z = 6, 487 BASE_ARCH_7 = 7, 488 BASE_ARCH_7A = 7, 489 BASE_ARCH_7R = 7, 490 BASE_ARCH_7M = 7, 491 BASE_ARCH_7EM = 7, 492 BASE_ARCH_8A = 8 493 }; 494 495 /* The major revision number of the ARM Architecture implemented by the target. */ 496 extern enum base_architecture arm_base_arch; 497 498 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 499 extern int arm_arch3m; 500 501 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 502 extern int arm_arch4; 503 504 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 505 extern int arm_arch4t; 506 507 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 508 extern int arm_arch5; 509 510 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 511 extern int arm_arch5e; 512 513 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 514 extern int arm_arch6; 515 516 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 517 extern int arm_arch6k; 518 519 /* Nonzero if instructions present in ARMv6-M can be used. */ 520 extern int arm_arch6m; 521 522 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 523 extern int arm_arch7; 524 525 /* Nonzero if instructions not present in the 'M' profile can be used. */ 526 extern int arm_arch_notm; 527 528 /* Nonzero if instructions present in ARMv7E-M can be used. */ 529 extern int arm_arch7em; 530 531 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 532 extern int arm_arch8; 533 534 /* Nonzero if this chip can benefit from load scheduling. */ 535 extern int arm_ld_sched; 536 537 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 538 extern int thumb_code; 539 540 /* Nonzero if generating Thumb-1 code. */ 541 extern int thumb1_code; 542 543 /* Nonzero if this chip is a StrongARM. */ 544 extern int arm_tune_strongarm; 545 546 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 547 extern int arm_arch_iwmmxt; 548 549 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 550 extern int arm_arch_iwmmxt2; 551 552 /* Nonzero if this chip is an XScale. */ 553 extern int arm_arch_xscale; 554 555 /* Nonzero if tuning for XScale. */ 556 extern int arm_tune_xscale; 557 558 /* Nonzero if tuning for stores via the write buffer. */ 559 extern int arm_tune_wbuf; 560 561 /* Nonzero if tuning for Cortex-A9. */ 562 extern int arm_tune_cortex_a9; 563 564 /* Nonzero if we should define __THUMB_INTERWORK__ in the 565 preprocessor. 566 XXX This is a bit of a hack, it's intended to help work around 567 problems in GLD which doesn't understand that armv5t code is 568 interworking clean. */ 569 extern int arm_cpp_interwork; 570 571 /* Nonzero if chip supports Thumb 2. */ 572 extern int arm_arch_thumb2; 573 574 /* Nonzero if chip supports integer division instruction in ARM mode. */ 575 extern int arm_arch_arm_hwdiv; 576 577 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 578 extern int arm_arch_thumb_hwdiv; 579 580 /* Nonzero if chip disallows volatile memory access in IT block. */ 581 extern int arm_arch_no_volatile_ce; 582 583 /* Nonzero if we should use Neon to handle 64-bits operations rather 584 than core registers. */ 585 extern int prefer_neon_for_64bits; 586 587 /* Nonzero if we shouldn't use literal pools. */ 588 #ifndef USED_FOR_TARGET 589 extern bool arm_disable_literal_pool; 590 #endif 591 592 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 593 extern int arm_arch_crc; 594 595 #ifndef TARGET_DEFAULT 596 #define TARGET_DEFAULT (MASK_APCS_FRAME) 597 #endif 598 599 /* Nonzero if PIC code requires explicit qualifiers to generate 600 PLT and GOT relocs rather than the assembler doing so implicitly. 601 Subtargets can override these if required. */ 602 #ifndef NEED_GOT_RELOC 603 #define NEED_GOT_RELOC 0 604 #endif 605 #ifndef NEED_PLT_RELOC 606 #define NEED_PLT_RELOC 0 607 #endif 608 609 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 610 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 611 #endif 612 613 /* Nonzero if we need to refer to the GOT with a PC-relative 614 offset. In other words, generate 615 616 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 617 618 rather than 619 620 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 621 622 The default is true, which matches NetBSD. Subtargets can 623 override this if required. */ 624 #ifndef GOT_PCREL 625 #define GOT_PCREL 1 626 #endif 627 628 /* Target machine storage Layout. */ 630 631 632 /* Define this macro if it is advisable to hold scalars in registers 633 in a wider mode than that declared by the program. In such cases, 634 the value is constrained to be within the bounds of the declared 635 type, but kept valid in the wider mode. The signedness of the 636 extension may differ from that of the type. */ 637 638 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 639 if (GET_MODE_CLASS (MODE) == MODE_INT \ 640 && GET_MODE_SIZE (MODE) < 4) \ 641 { \ 642 (MODE) = SImode; \ 643 } 644 645 /* Define this if most significant bit is lowest numbered 646 in instructions that operate on numbered bit-fields. */ 647 #define BITS_BIG_ENDIAN 0 648 649 /* Define this if most significant byte of a word is the lowest numbered. 650 Most ARM processors are run in little endian mode, so that is the default. 651 If you want to have it run-time selectable, change the definition in a 652 cover file to be TARGET_BIG_ENDIAN. */ 653 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 654 655 /* Define this if most significant word of a multiword number is the lowest 656 numbered. */ 657 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 658 659 #define UNITS_PER_WORD 4 660 661 /* True if natural alignment is used for doubleword types. */ 662 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 663 664 #define DOUBLEWORD_ALIGNMENT 64 665 666 #define PARM_BOUNDARY 32 667 668 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 669 670 #define PREFERRED_STACK_BOUNDARY \ 671 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 672 673 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 674 675 /* The lowest bit is used to indicate Thumb-mode functions, so the 676 vbit must go into the delta field of pointers to member 677 functions. */ 678 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 679 680 #define EMPTY_FIELD_BOUNDARY 32 681 682 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 683 684 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 685 686 /* XXX Blah -- this macro is used directly by libobjc. Since it 687 supports no vector modes, cut out the complexity and fall back 688 on BIGGEST_FIELD_ALIGNMENT. */ 689 #ifdef IN_TARGET_LIBS 690 #define BIGGEST_FIELD_ALIGNMENT 64 691 #endif 692 693 /* Make strings word-aligned so strcpy from constants will be faster. */ 694 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 695 696 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 697 ((TREE_CODE (EXP) == STRING_CST \ 698 && !optimize_size \ 699 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 700 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 701 702 /* Align definitions of arrays, unions and structures so that 703 initializations and copies can be made more efficient. This is not 704 ABI-changing, so it only affects places where we can see the 705 definition. Increasing the alignment tends to introduce padding, 706 so don't do this when optimizing for size/conserving stack space. */ 707 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 708 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 709 && (TREE_CODE (EXP) == ARRAY_TYPE \ 710 || TREE_CODE (EXP) == UNION_TYPE \ 711 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 712 713 /* Align global data. */ 714 #define DATA_ALIGNMENT(EXP, ALIGN) \ 715 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 716 717 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 718 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 719 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 720 721 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 722 value set in previous versions of this toolchain was 8, which produces more 723 compact structures. The command line option -mstructure_size_boundary=<n> 724 can be used to change this value. For compatibility with the ARM SDK 725 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 726 0020D) page 2-20 says "Structures are aligned on word boundaries". 727 The AAPCS specifies a value of 8. */ 728 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 729 730 /* This is the value used to initialize arm_structure_size_boundary. If a 731 particular arm target wants to change the default value it should change 732 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 733 for an example of this. */ 734 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 735 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 736 #endif 737 738 /* Nonzero if move instructions will actually fail to work 739 when given unaligned data. */ 740 #define STRICT_ALIGNMENT 1 741 742 /* wchar_t is unsigned under the AAPCS. */ 743 #ifndef WCHAR_TYPE 744 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 745 746 #define WCHAR_TYPE_SIZE BITS_PER_WORD 747 #endif 748 749 /* Sized for fixed-point types. */ 750 751 #define SHORT_FRACT_TYPE_SIZE 8 752 #define FRACT_TYPE_SIZE 16 753 #define LONG_FRACT_TYPE_SIZE 32 754 #define LONG_LONG_FRACT_TYPE_SIZE 64 755 756 #define SHORT_ACCUM_TYPE_SIZE 16 757 #define ACCUM_TYPE_SIZE 32 758 #define LONG_ACCUM_TYPE_SIZE 64 759 #define LONG_LONG_ACCUM_TYPE_SIZE 64 760 761 #define MAX_FIXED_MODE_SIZE 64 762 763 #ifndef SIZE_TYPE 764 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 765 #endif 766 767 #ifndef PTRDIFF_TYPE 768 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 769 #endif 770 771 /* AAPCS requires that structure alignment is affected by bitfields. */ 772 #ifndef PCC_BITFIELD_TYPE_MATTERS 773 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 774 #endif 775 776 /* The maximum size of the sync library functions supported. */ 777 #ifndef MAX_SYNC_LIBFUNC_SIZE 778 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 779 #endif 780 781 782 /* Standard register usage. */ 784 785 /* Register allocation in ARM Procedure Call Standard 786 (S - saved over call). 787 788 r0 * argument word/integer result 789 r1-r3 argument word 790 791 r4-r8 S register variable 792 r9 S (rfp) register variable (real frame pointer) 793 794 r10 F S (sl) stack limit (used by -mapcs-stack-check) 795 r11 F S (fp) argument pointer 796 r12 (ip) temp workspace 797 r13 F S (sp) lower end of current stack frame 798 r14 (lr) link address/workspace 799 r15 F (pc) program counter 800 801 cc This is NOT a real register, but is used internally 802 to represent things that use or set the condition 803 codes. 804 sfp This isn't either. It is used during rtl generation 805 since the offset between the frame pointer and the 806 auto's isn't known until after register allocation. 807 afp Nor this, we only need this because of non-local 808 goto. Without it fp appears to be used and the 809 elimination code won't get rid of sfp. It tracks 810 fp exactly at all times. 811 812 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 813 814 /* s0-s15 VFP scratch (aka d0-d7). 815 s16-s31 S VFP variable (aka d8-d15). 816 vfpcc Not a real register. Represents the VFP condition 817 code flags. */ 818 819 /* The stack backtrace structure is as follows: 820 fp points to here: | save code pointer | [fp] 821 | return link value | [fp, #-4] 822 | return sp value | [fp, #-8] 823 | return fp value | [fp, #-12] 824 [| saved r10 value |] 825 [| saved r9 value |] 826 [| saved r8 value |] 827 [| saved r7 value |] 828 [| saved r6 value |] 829 [| saved r5 value |] 830 [| saved r4 value |] 831 [| saved r3 value |] 832 [| saved r2 value |] 833 [| saved r1 value |] 834 [| saved r0 value |] 835 r0-r3 are not normally saved in a C function. */ 836 837 /* 1 for registers that have pervasive standard uses 838 and are not available for the register allocator. */ 839 #define FIXED_REGISTERS \ 840 { \ 841 /* Core regs. */ \ 842 0,0,0,0,0,0,0,0, \ 843 0,0,0,0,0,1,0,1, \ 844 /* VFP regs. */ \ 845 1,1,1,1,1,1,1,1, \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1,1,1,1,1, \ 849 1,1,1,1,1,1,1,1, \ 850 1,1,1,1,1,1,1,1, \ 851 1,1,1,1,1,1,1,1, \ 852 1,1,1,1,1,1,1,1, \ 853 /* IWMMXT regs. */ \ 854 1,1,1,1,1,1,1,1, \ 855 1,1,1,1,1,1,1,1, \ 856 1,1,1,1, \ 857 /* Specials. */ \ 858 1,1,1,1 \ 859 } 860 861 /* 1 for registers not available across function calls. 862 These must include the FIXED_REGISTERS and also any 863 registers that can be used without being saved. 864 The latter must include the registers where values are returned 865 and the register where structure-value addresses are passed. 866 Aside from that, you can include as many other registers as you like. 867 The CC is not preserved over function calls on the ARM 6, so it is 868 easier to assume this for all. SFP is preserved, since FP is. */ 869 #define CALL_USED_REGISTERS \ 870 { \ 871 /* Core regs. */ \ 872 1,1,1,1,0,0,0,0, \ 873 0,0,0,0,1,1,1,1, \ 874 /* VFP Regs. */ \ 875 1,1,1,1,1,1,1,1, \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1,1,1,1,1, \ 879 1,1,1,1,1,1,1,1, \ 880 1,1,1,1,1,1,1,1, \ 881 1,1,1,1,1,1,1,1, \ 882 1,1,1,1,1,1,1,1, \ 883 /* IWMMXT regs. */ \ 884 1,1,1,1,1,1,1,1, \ 885 1,1,1,1,1,1,1,1, \ 886 1,1,1,1, \ 887 /* Specials. */ \ 888 1,1,1,1 \ 889 } 890 891 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 892 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 893 #endif 894 895 /* These are a couple of extensions to the formats accepted 896 by asm_fprintf: 897 %@ prints out ASM_COMMENT_START 898 %r prints out REGISTER_PREFIX reg_names[arg] */ 899 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 900 case '@': \ 901 fputs (ASM_COMMENT_START, FILE); \ 902 break; \ 903 \ 904 case 'r': \ 905 fputs (REGISTER_PREFIX, FILE); \ 906 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 907 break; 908 909 /* Round X up to the nearest word. */ 910 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 911 912 /* Convert fron bytes to ints. */ 913 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 914 915 /* The number of (integer) registers required to hold a quantity of type MODE. 916 Also used for VFP registers. */ 917 #define ARM_NUM_REGS(MODE) \ 918 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 919 920 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 921 #define ARM_NUM_REGS2(MODE, TYPE) \ 922 ARM_NUM_INTS ((MODE) == BLKmode ? \ 923 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 924 925 /* The number of (integer) argument register available. */ 926 #define NUM_ARG_REGS 4 927 928 /* And similarly for the VFP. */ 929 #define NUM_VFP_ARG_REGS 16 930 931 /* Return the register number of the N'th (integer) argument. */ 932 #define ARG_REGISTER(N) (N - 1) 933 934 /* Specify the registers used for certain standard purposes. 935 The values of these macros are register numbers. */ 936 937 /* The number of the last argument register. */ 938 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 939 940 /* The numbers of the Thumb register ranges. */ 941 #define FIRST_LO_REGNUM 0 942 #define LAST_LO_REGNUM 7 943 #define FIRST_HI_REGNUM 8 944 #define LAST_HI_REGNUM 11 945 946 /* Overridden by config/arm/bpabi.h. */ 947 #ifndef ARM_UNWIND_INFO 948 #define ARM_UNWIND_INFO 0 949 #endif 950 951 /* Overriden by config/arm/netbsd-eabi.h. */ 952 #ifndef ARM_DWARF_UNWIND_TABLES 953 #define ARM_DWARF_UNWIND_TABLES 0 954 #endif 955 956 /* Use r0 and r1 to pass exception handling information. */ 957 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 958 959 /* The register that holds the return address in exception handlers. */ 960 #define ARM_EH_STACKADJ_REGNUM 2 961 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 962 963 #ifndef ARM_TARGET2_DWARF_FORMAT 964 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 965 #endif 966 967 #if ARM_DWARF_UNWIND_TABLES 968 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 969 for 32bit platforms. */ 970 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 971 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 972 : DW_EH_PE_absptr) 973 #else 974 /* ttype entries (the only interesting data references used) 975 use TARGET2 relocations. */ 976 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 977 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 978 : DW_EH_PE_absptr) 979 #endif 980 981 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 982 as an invisible last argument (possible since varargs don't exist in 983 Pascal), so the following is not true. */ 984 #define STATIC_CHAIN_REGNUM 12 985 986 /* Define this to be where the real frame pointer is if it is not possible to 987 work out the offset between the frame pointer and the automatic variables 988 until after register allocation has taken place. FRAME_POINTER_REGNUM 989 should point to a special register that we will make sure is eliminated. 990 991 For the Thumb we have another problem. The TPCS defines the frame pointer 992 as r11, and GCC believes that it is always possible to use the frame pointer 993 as base register for addressing purposes. (See comments in 994 find_reloads_address()). But - the Thumb does not allow high registers, 995 including r11, to be used as base address registers. Hence our problem. 996 997 The solution used here, and in the old thumb port is to use r7 instead of 998 r11 as the hard frame pointer and to have special code to generate 999 backtrace structures on the stack (if required to do so via a command line 1000 option) using r11. This is the only 'user visible' use of r11 as a frame 1001 pointer. */ 1002 #define ARM_HARD_FRAME_POINTER_REGNUM 11 1003 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 1004 1005 #define HARD_FRAME_POINTER_REGNUM \ 1006 (TARGET_ARM \ 1007 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1008 : THUMB_HARD_FRAME_POINTER_REGNUM) 1009 1010 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1011 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1012 1013 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1014 1015 /* Register to use for pushing function arguments. */ 1016 #define STACK_POINTER_REGNUM SP_REGNUM 1017 1018 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1019 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1020 1021 /* Need to sync with WCGR in iwmmxt.md. */ 1022 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1023 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1024 1025 #define IS_IWMMXT_REGNUM(REGNUM) \ 1026 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1027 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1028 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1029 1030 /* Base register for access to local variables of the function. */ 1031 #define FRAME_POINTER_REGNUM 102 1032 1033 /* Base register for access to arguments of the function. */ 1034 #define ARG_POINTER_REGNUM 103 1035 1036 #define FIRST_VFP_REGNUM 16 1037 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1038 #define LAST_VFP_REGNUM \ 1039 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1040 1041 #define IS_VFP_REGNUM(REGNUM) \ 1042 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1043 1044 /* VFP registers are split into two types: those defined by VFP versions < 3 1045 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1046 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1047 in various parts of the backend, we implement as "fake" single-precision 1048 registers (which would be S32-S63, but cannot be used in that way). The 1049 following macros define these ranges of registers. */ 1050 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1051 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1052 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1053 1054 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1055 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1056 1057 /* DFmode values are only valid in even register pairs. */ 1058 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1059 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1060 1061 /* Neon Quad values must start at a multiple of four registers. */ 1062 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1063 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1064 1065 /* Neon structures of vectors must be in even register pairs and there 1066 must be enough registers available. Because of various patterns 1067 requiring quad registers, we require them to start at a multiple of 1068 four. */ 1069 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1070 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1071 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1072 1073 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1074 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1075 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1076 #define FIRST_PSEUDO_REGISTER 104 1077 1078 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1079 1080 /* Value should be nonzero if functions must have frame pointers. 1081 Zero means the frame pointer need not be set up (and parms may be accessed 1082 via the stack pointer) in functions that seem suitable. 1083 If we have to have a frame pointer we might as well make use of it. 1084 APCS says that the frame pointer does not need to be pushed in leaf 1085 functions, or simple tail call functions. */ 1086 1087 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1088 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1089 #endif 1090 1091 /* Return number of consecutive hard regs needed starting at reg REGNO 1092 to hold something of mode MODE. 1093 This is ordinarily the length in words of a value of mode MODE 1094 but can be less for certain modes in special long registers. 1095 1096 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1097 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1098 ((TARGET_32BIT \ 1099 && REGNO > PC_REGNUM \ 1100 && REGNO != FRAME_POINTER_REGNUM \ 1101 && REGNO != ARG_POINTER_REGNUM) \ 1102 && !IS_VFP_REGNUM (REGNO) \ 1103 ? 1 : ARM_NUM_REGS (MODE)) 1104 1105 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1106 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1107 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1108 1109 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1110 1111 #define VALID_IWMMXT_REG_MODE(MODE) \ 1112 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1113 1114 /* Modes valid for Neon D registers. */ 1115 #define VALID_NEON_DREG_MODE(MODE) \ 1116 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1117 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1118 1119 /* Modes valid for Neon Q registers. */ 1120 #define VALID_NEON_QREG_MODE(MODE) \ 1121 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1122 || (MODE) == V4SFmode || (MODE) == V2DImode) 1123 1124 /* Structure modes valid for Neon registers. */ 1125 #define VALID_NEON_STRUCT_MODE(MODE) \ 1126 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1127 || (MODE) == CImode || (MODE) == XImode) 1128 1129 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1130 extern int arm_regs_in_sequence[]; 1131 1132 /* The order in which register should be allocated. It is good to use ip 1133 since no saving is required (though calls clobber it) and it never contains 1134 function parameters. It is quite good to use lr since other calls may 1135 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1136 least likely to contain a function parameter; in addition results are 1137 returned in r0. 1138 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1139 then D8-D15. The reason for doing this is to attempt to reduce register 1140 pressure when both single- and double-precision registers are used in a 1141 function. */ 1142 1143 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1144 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1145 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1146 1147 #define REG_ALLOC_ORDER \ 1148 { \ 1149 /* General registers. */ \ 1150 3, 2, 1, 0, 12, 14, 4, 5, \ 1151 6, 7, 8, 9, 10, 11, \ 1152 /* High VFP registers. */ \ 1153 VREG(32), VREG(33), VREG(34), VREG(35), \ 1154 VREG(36), VREG(37), VREG(38), VREG(39), \ 1155 VREG(40), VREG(41), VREG(42), VREG(43), \ 1156 VREG(44), VREG(45), VREG(46), VREG(47), \ 1157 VREG(48), VREG(49), VREG(50), VREG(51), \ 1158 VREG(52), VREG(53), VREG(54), VREG(55), \ 1159 VREG(56), VREG(57), VREG(58), VREG(59), \ 1160 VREG(60), VREG(61), VREG(62), VREG(63), \ 1161 /* VFP argument registers. */ \ 1162 VREG(15), VREG(14), VREG(13), VREG(12), \ 1163 VREG(11), VREG(10), VREG(9), VREG(8), \ 1164 VREG(7), VREG(6), VREG(5), VREG(4), \ 1165 VREG(3), VREG(2), VREG(1), VREG(0), \ 1166 /* VFP call-saved registers. */ \ 1167 VREG(16), VREG(17), VREG(18), VREG(19), \ 1168 VREG(20), VREG(21), VREG(22), VREG(23), \ 1169 VREG(24), VREG(25), VREG(26), VREG(27), \ 1170 VREG(28), VREG(29), VREG(30), VREG(31), \ 1171 /* IWMMX registers. */ \ 1172 WREG(0), WREG(1), WREG(2), WREG(3), \ 1173 WREG(4), WREG(5), WREG(6), WREG(7), \ 1174 WREG(8), WREG(9), WREG(10), WREG(11), \ 1175 WREG(12), WREG(13), WREG(14), WREG(15), \ 1176 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1177 /* Registers not for general use. */ \ 1178 CC_REGNUM, VFPCC_REGNUM, \ 1179 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1180 SP_REGNUM, PC_REGNUM \ 1181 } 1182 1183 /* Use different register alloc ordering for Thumb. */ 1184 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1185 1186 /* Tell IRA to use the order we define rather than messing it up with its 1187 own cost calculations. */ 1188 #define HONOR_REG_ALLOC_ORDER 1 1189 1190 /* Interrupt functions can only use registers that have already been 1191 saved by the prologue, even if they would normally be 1192 call-clobbered. */ 1193 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1194 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1195 df_regs_ever_live_p (DST)) 1196 1197 /* Register and constant classes. */ 1199 1200 /* Register classes. */ 1201 enum reg_class 1202 { 1203 NO_REGS, 1204 LO_REGS, 1205 STACK_REG, 1206 BASE_REGS, 1207 HI_REGS, 1208 CALLER_SAVE_REGS, 1209 GENERAL_REGS, 1210 CORE_REGS, 1211 VFP_D0_D7_REGS, 1212 VFP_LO_REGS, 1213 VFP_HI_REGS, 1214 VFP_REGS, 1215 IWMMXT_REGS, 1216 IWMMXT_GR_REGS, 1217 CC_REG, 1218 VFPCC_REG, 1219 SFP_REG, 1220 AFP_REG, 1221 ALL_REGS, 1222 LIM_REG_CLASSES 1223 }; 1224 1225 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1226 1227 /* Give names of register classes as strings for dump file. */ 1228 #define REG_CLASS_NAMES \ 1229 { \ 1230 "NO_REGS", \ 1231 "LO_REGS", \ 1232 "STACK_REG", \ 1233 "BASE_REGS", \ 1234 "HI_REGS", \ 1235 "CALLER_SAVE_REGS", \ 1236 "GENERAL_REGS", \ 1237 "CORE_REGS", \ 1238 "VFP_D0_D7_REGS", \ 1239 "VFP_LO_REGS", \ 1240 "VFP_HI_REGS", \ 1241 "VFP_REGS", \ 1242 "IWMMXT_REGS", \ 1243 "IWMMXT_GR_REGS", \ 1244 "CC_REG", \ 1245 "VFPCC_REG", \ 1246 "SFP_REG", \ 1247 "AFP_REG", \ 1248 "ALL_REGS" \ 1249 } 1250 1251 /* Define which registers fit in which classes. 1252 This is an initializer for a vector of HARD_REG_SET 1253 of length N_REG_CLASSES. */ 1254 #define REG_CLASS_CONTENTS \ 1255 { \ 1256 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1257 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1258 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1259 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1260 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1261 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1262 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1263 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1264 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1265 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1266 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1267 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1268 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1269 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1270 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1271 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1272 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1273 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1274 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1275 } 1276 1277 /* Any of the VFP register classes. */ 1278 #define IS_VFP_CLASS(X) \ 1279 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1280 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1281 1282 /* The same information, inverted: 1283 Return the class number of the smallest class containing 1284 reg number REGNO. This could be a conditional expression 1285 or could index an array. */ 1286 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1287 1288 /* In VFPv1, VFP registers could only be accessed in the mode they 1289 were set, so subregs would be invalid there. However, we don't 1290 support VFPv1 at the moment, and the restriction was lifted in 1291 VFPv2. 1292 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1293 VFP registers in little-endian order. We can't describe that accurately to 1294 GCC, so avoid taking subregs of such values. 1295 The only exception is going from a 128-bit to a 64-bit type. In that case 1296 the data layout happens to be consistent for big-endian, so we explicitly allow 1297 that case. */ 1298 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1299 (TARGET_VFP && TARGET_BIG_END \ 1300 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1301 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1302 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1303 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1304 1305 /* The class value for index registers, and the one for base regs. */ 1306 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1307 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1308 1309 /* For the Thumb the high registers cannot be used as base registers 1310 when addressing quantities in QI or HI mode; if we don't know the 1311 mode, then we must be conservative. */ 1312 #define MODE_BASE_REG_CLASS(MODE) \ 1313 (TARGET_32BIT ? CORE_REGS \ 1314 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1315 : LO_REGS) 1316 1317 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1318 instead of BASE_REGS. */ 1319 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1320 1321 /* When this hook returns true for MODE, the compiler allows 1322 registers explicitly used in the rtl to be used as spill registers 1323 but prevents the compiler from extending the lifetime of these 1324 registers. */ 1325 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1326 arm_small_register_classes_for_mode_p 1327 1328 /* Must leave BASE_REGS reloads alone */ 1329 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1330 (lra_in_progress ? NO_REGS \ 1331 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1332 ? ((true_regnum (X) == -1 ? LO_REGS \ 1333 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1334 : NO_REGS)) \ 1335 : NO_REGS)) 1336 1337 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1338 (lra_in_progress ? NO_REGS \ 1339 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1340 ? ((true_regnum (X) == -1 ? LO_REGS \ 1341 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1342 : NO_REGS)) \ 1343 : NO_REGS) 1344 1345 /* Return the register class of a scratch register needed to copy IN into 1346 or out of a register in CLASS in MODE. If it can be done directly, 1347 NO_REGS is returned. */ 1348 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1349 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1350 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1351 && IS_VFP_CLASS (CLASS)) \ 1352 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1353 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1354 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1355 : TARGET_32BIT \ 1356 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1357 ? GENERAL_REGS : NO_REGS) \ 1358 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1359 1360 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1361 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1362 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1363 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1364 && IS_VFP_CLASS (CLASS)) \ 1365 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1366 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1367 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1368 (TARGET_32BIT ? \ 1369 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1370 && CONSTANT_P (X)) \ 1371 ? GENERAL_REGS : \ 1372 (((MODE) == HImode && ! arm_arch4 \ 1373 && (MEM_P (X) \ 1374 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1375 && true_regnum (X) == -1))) \ 1376 ? GENERAL_REGS : NO_REGS) \ 1377 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1378 1379 /* Try a machine-dependent way of reloading an illegitimate address 1380 operand. If we find one, push the reload and jump to WIN. This 1381 macro is used in only one place: `find_reloads_address' in reload.c. 1382 1383 For the ARM, we wish to handle large displacements off a base 1384 register by splitting the addend across a MOV and the mem insn. 1385 This can cut the number of reloads needed. */ 1386 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1387 do \ 1388 { \ 1389 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1390 goto WIN; \ 1391 } \ 1392 while (0) 1393 1394 /* XXX If an HImode FP+large_offset address is converted to an HImode 1395 SP+large_offset address, then reload won't know how to fix it. It sees 1396 only that SP isn't valid for HImode, and so reloads the SP into an index 1397 register, but the resulting address is still invalid because the offset 1398 is too big. We fix it here instead by reloading the entire address. */ 1399 /* We could probably achieve better results by defining PROMOTE_MODE to help 1400 cope with the variances between the Thumb's signed and unsigned byte and 1401 halfword load instructions. */ 1402 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1403 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1404 do { \ 1405 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1406 if (new_x) \ 1407 { \ 1408 X = new_x; \ 1409 goto WIN; \ 1410 } \ 1411 } while (0) 1412 1413 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1414 if (TARGET_ARM) \ 1415 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1416 else \ 1417 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1418 1419 /* Return the maximum number of consecutive registers 1420 needed to represent mode MODE in a register of class CLASS. 1421 ARM regs are UNITS_PER_WORD bits. 1422 FIXME: Is this true for iWMMX? */ 1423 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1424 (ARM_NUM_REGS (MODE)) 1425 1426 /* If defined, gives a class of registers that cannot be used as the 1427 operand of a SUBREG that changes the mode of the object illegally. */ 1428 1429 /* Stack layout; function entry, exit and calling. */ 1431 1432 /* Define this if pushing a word on the stack 1433 makes the stack pointer a smaller address. */ 1434 #define STACK_GROWS_DOWNWARD 1 1435 1436 /* Define this to nonzero if the nominal address of the stack frame 1437 is at the high-address end of the local variables; 1438 that is, each additional local variable allocated 1439 goes at a more negative offset in the frame. */ 1440 #define FRAME_GROWS_DOWNWARD 1 1441 1442 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1443 When present, it is one word in size, and sits at the top of the frame, 1444 between the soft frame pointer and either r7 or r11. 1445 1446 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1447 and only then if some outgoing arguments are passed on the stack. It would 1448 be tempting to also check whether the stack arguments are passed by indirect 1449 calls, but there seems to be no reason in principle why a post-reload pass 1450 couldn't convert a direct call into an indirect one. */ 1451 #define CALLER_INTERWORKING_SLOT_SIZE \ 1452 (TARGET_CALLER_INTERWORKING \ 1453 && crtl->outgoing_args_size != 0 \ 1454 ? UNITS_PER_WORD : 0) 1455 1456 /* Offset within stack frame to start allocating local variables at. 1457 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1458 first local allocated. Otherwise, it is the offset to the BEGINNING 1459 of the first local allocated. */ 1460 #define STARTING_FRAME_OFFSET 0 1461 1462 /* If we generate an insn to push BYTES bytes, 1463 this says how many the stack pointer really advances by. */ 1464 /* The push insns do not do this rounding implicitly. 1465 So don't define this. */ 1466 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1467 1468 /* Define this if the maximum size of all the outgoing args is to be 1469 accumulated and pushed during the prologue. The amount can be 1470 found in the variable crtl->outgoing_args_size. */ 1471 #define ACCUMULATE_OUTGOING_ARGS 1 1472 1473 /* Offset of first parameter from the argument pointer register value. */ 1474 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1475 1476 /* Amount of memory needed for an untyped call to save all possible return 1477 registers. */ 1478 #define APPLY_RESULT_SIZE arm_apply_result_size() 1479 1480 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1481 values must be in memory. On the ARM, they need only do so if larger 1482 than a word, or if they contain elements offset from zero in the struct. */ 1483 #define DEFAULT_PCC_STRUCT_RETURN 0 1484 1485 /* These bits describe the different types of function supported 1486 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1487 normal function and an interworked function, for example. Knowing the 1488 type of a function is important for determining its prologue and 1489 epilogue sequences. 1490 Note value 7 is currently unassigned. Also note that the interrupt 1491 function types all have bit 2 set, so that they can be tested for easily. 1492 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1493 machine_function structure is initialized (to zero) func_type will 1494 default to unknown. This will force the first use of arm_current_func_type 1495 to call arm_compute_func_type. */ 1496 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1497 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1498 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1499 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1500 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1501 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1502 1503 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1504 1505 /* In addition functions can have several type modifiers, 1506 outlined by these bit masks: */ 1507 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1508 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1509 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1510 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1511 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1512 1513 /* Some macros to test these flags. */ 1514 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1515 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1516 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1517 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1518 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1519 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1520 1521 1522 /* Structure used to hold the function stack frame layout. Offsets are 1523 relative to the stack pointer on function entry. Positive offsets are 1524 in the direction of stack growth. 1525 Only soft_frame is used in thumb mode. */ 1526 1527 typedef struct GTY(()) arm_stack_offsets 1528 { 1529 int saved_args; /* ARG_POINTER_REGNUM. */ 1530 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1531 int saved_regs; 1532 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1533 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1534 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1535 unsigned int saved_regs_mask; 1536 } 1537 arm_stack_offsets; 1538 1539 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1540 /* A C structure for machine-specific, per-function data. 1541 This is added to the cfun structure. */ 1542 typedef struct GTY(()) machine_function 1543 { 1544 /* Additional stack adjustment in __builtin_eh_throw. */ 1545 rtx eh_epilogue_sp_ofs; 1546 /* Records if LR has to be saved for far jumps. */ 1547 int far_jump_used; 1548 /* Records if ARG_POINTER was ever live. */ 1549 int arg_pointer_live; 1550 /* Records if the save of LR has been eliminated. */ 1551 int lr_save_eliminated; 1552 /* The size of the stack frame. Only valid after reload. */ 1553 arm_stack_offsets stack_offsets; 1554 /* Records the type of the current function. */ 1555 unsigned long func_type; 1556 /* Record if the function has a variable argument list. */ 1557 int uses_anonymous_args; 1558 /* Records if sibcalls are blocked because an argument 1559 register is needed to preserve stack alignment. */ 1560 int sibcall_blocked; 1561 /* The PIC register for this function. This might be a pseudo. */ 1562 rtx pic_reg; 1563 /* Labels for per-function Thumb call-via stubs. One per potential calling 1564 register. We can never call via LR or PC. We can call via SP if a 1565 trampoline happens to be on the top of the stack. */ 1566 rtx call_via[14]; 1567 /* Set to 1 when a return insn is output, this means that the epilogue 1568 is not needed. */ 1569 int return_used_this_function; 1570 /* When outputting Thumb-1 code, record the last insn that provides 1571 information about condition codes, and the comparison operands. */ 1572 rtx thumb1_cc_insn; 1573 rtx thumb1_cc_op0; 1574 rtx thumb1_cc_op1; 1575 /* Also record the CC mode that is supported. */ 1576 machine_mode thumb1_cc_mode; 1577 /* Set to 1 after arm_reorg has started. */ 1578 int after_arm_reorg; 1579 } 1580 machine_function; 1581 #endif 1582 1583 /* As in the machine_function, a global set of call-via labels, for code 1584 that is in text_section. */ 1585 extern GTY(()) rtx thumb_call_via_label[14]; 1586 1587 /* The number of potential ways of assigning to a co-processor. */ 1588 #define ARM_NUM_COPROC_SLOTS 1 1589 1590 /* Enumeration of procedure calling standard variants. We don't really 1591 support all of these yet. */ 1592 enum arm_pcs 1593 { 1594 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1595 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1596 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1597 /* This must be the last AAPCS variant. */ 1598 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1599 ARM_PCS_ATPCS, /* ATPCS. */ 1600 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1601 ARM_PCS_UNKNOWN 1602 }; 1603 1604 /* Default procedure calling standard of current compilation unit. */ 1605 extern enum arm_pcs arm_pcs_default; 1606 1607 #if !defined (USED_FOR_TARGET) 1608 /* A C type for declaring a variable that is used as the first argument of 1609 `FUNCTION_ARG' and other related values. */ 1610 typedef struct 1611 { 1612 /* This is the number of registers of arguments scanned so far. */ 1613 int nregs; 1614 /* This is the number of iWMMXt register arguments scanned so far. */ 1615 int iwmmxt_nregs; 1616 int named_count; 1617 int nargs; 1618 /* Which procedure call variant to use for this call. */ 1619 enum arm_pcs pcs_variant; 1620 1621 /* AAPCS related state tracking. */ 1622 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1623 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1624 this argument, or -1 if using core 1625 registers. */ 1626 int aapcs_ncrn; 1627 int aapcs_next_ncrn; 1628 rtx aapcs_reg; /* Register assigned to this argument. */ 1629 int aapcs_partial; /* How many bytes are passed in regs (if 1630 split between core regs and stack. 1631 Zero otherwise. */ 1632 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1633 int can_split; /* Argument can be split between core regs 1634 and the stack. */ 1635 /* Private data for tracking VFP register allocation */ 1636 unsigned aapcs_vfp_regs_free; 1637 unsigned aapcs_vfp_reg_alloc; 1638 int aapcs_vfp_rcount; 1639 MACHMODE aapcs_vfp_rmode; 1640 } CUMULATIVE_ARGS; 1641 #endif 1642 1643 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1644 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1645 1646 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1647 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1648 1649 /* For AAPCS, padding should never be below the argument. For other ABIs, 1650 * mimic the default. */ 1651 #define PAD_VARARGS_DOWN \ 1652 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1653 1654 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1655 for a call to a function whose data type is FNTYPE. 1656 For a library call, FNTYPE is 0. 1657 On the ARM, the offset starts at 0. */ 1658 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1659 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1660 1661 /* 1 if N is a possible register number for function argument passing. 1662 On the ARM, r0-r3 are used to pass args. */ 1663 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1664 (IN_RANGE ((REGNO), 0, 3) \ 1665 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1666 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1667 || (TARGET_IWMMXT_ABI \ 1668 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1669 1670 1671 /* If your target environment doesn't prefix user functions with an 1673 underscore, you may wish to re-define this to prevent any conflicts. */ 1674 #ifndef ARM_MCOUNT_NAME 1675 #define ARM_MCOUNT_NAME "*mcount" 1676 #endif 1677 1678 /* Call the function profiler with a given profile label. The Acorn 1679 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1680 On the ARM the full profile code will look like: 1681 .data 1682 LP1 1683 .word 0 1684 .text 1685 mov ip, lr 1686 bl mcount 1687 .word LP1 1688 1689 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1690 will output the .text section. 1691 1692 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1693 ``prof'' doesn't seem to mind about this! 1694 1695 Note - this version of the code is designed to work in both ARM and 1696 Thumb modes. */ 1697 #ifndef ARM_FUNCTION_PROFILER 1698 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1699 { \ 1700 char temp[20]; \ 1701 rtx sym; \ 1702 \ 1703 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1704 IP_REGNUM, LR_REGNUM); \ 1705 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1706 fputc ('\n', STREAM); \ 1707 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1708 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1709 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1710 } 1711 #endif 1712 1713 #ifdef THUMB_FUNCTION_PROFILER 1714 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1715 if (TARGET_ARM) \ 1716 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1717 else \ 1718 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1719 #else 1720 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1721 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1722 #endif 1723 1724 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1725 the stack pointer does not matter. The value is tested only in 1726 functions that have frame pointers. 1727 No definition is equivalent to always zero. 1728 1729 On the ARM, the function epilogue recovers the stack pointer from the 1730 frame. */ 1731 #define EXIT_IGNORE_STACK 1 1732 1733 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1734 1735 /* Determine if the epilogue should be output as RTL. 1736 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1737 #define USE_RETURN_INSN(ISCOND) \ 1738 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1739 1740 /* Definitions for register eliminations. 1741 1742 This is an array of structures. Each structure initializes one pair 1743 of eliminable registers. The "from" register number is given first, 1744 followed by "to". Eliminations of the same "from" register are listed 1745 in order of preference. 1746 1747 We have two registers that can be eliminated on the ARM. First, the 1748 arg pointer register can often be eliminated in favor of the stack 1749 pointer register. Secondly, the pseudo frame pointer register can always 1750 be eliminated; it is replaced with either the stack or the real frame 1751 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1752 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1753 1754 #define ELIMINABLE_REGS \ 1755 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1756 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1757 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1758 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1759 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1760 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1761 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1762 1763 /* Define the offset between two registers, one to be eliminated, and the 1764 other its replacement, at the start of a routine. */ 1765 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1766 if (TARGET_ARM) \ 1767 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1768 else \ 1769 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1770 1771 /* Special case handling of the location of arguments passed on the stack. */ 1772 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1773 1774 /* Initialize data used by insn expanders. This is called from insn_emit, 1775 once for every function before code is generated. */ 1776 #define INIT_EXPANDERS arm_init_expanders () 1777 1778 /* Length in units of the trampoline for entering a nested function. */ 1779 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1780 1781 /* Alignment required for a trampoline in bits. */ 1782 #define TRAMPOLINE_ALIGNMENT 32 1783 1784 /* Addressing modes, and classification of registers for them. */ 1786 #define HAVE_POST_INCREMENT 1 1787 #define HAVE_PRE_INCREMENT TARGET_32BIT 1788 #define HAVE_POST_DECREMENT TARGET_32BIT 1789 #define HAVE_PRE_DECREMENT TARGET_32BIT 1790 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1791 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1792 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1793 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1794 1795 enum arm_auto_incmodes 1796 { 1797 ARM_POST_INC, 1798 ARM_PRE_INC, 1799 ARM_POST_DEC, 1800 ARM_PRE_DEC 1801 }; 1802 1803 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1804 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1805 #define USE_LOAD_POST_INCREMENT(mode) \ 1806 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1807 #define USE_LOAD_PRE_INCREMENT(mode) \ 1808 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1809 #define USE_LOAD_POST_DECREMENT(mode) \ 1810 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1811 #define USE_LOAD_PRE_DECREMENT(mode) \ 1812 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1813 1814 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1815 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1816 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1817 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1818 1819 /* Macros to check register numbers against specific register classes. */ 1820 1821 /* These assume that REGNO is a hard or pseudo reg number. 1822 They give nonzero only if REGNO is a hard reg of the suitable class 1823 or a pseudo reg currently allocated to a suitable hard reg. 1824 Since they use reg_renumber, they are safe only once reg_renumber 1825 has been allocated, which happens in reginfo.c during register 1826 allocation. */ 1827 #define TEST_REGNO(R, TEST, VALUE) \ 1828 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1829 1830 /* Don't allow the pc to be used. */ 1831 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1832 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1833 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1834 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1835 1836 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1837 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1838 || (GET_MODE_SIZE (MODE) >= 4 \ 1839 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1840 1841 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1842 (TARGET_THUMB1 \ 1843 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1844 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1845 1846 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1847 For Thumb, we can not use SP + reg, so reject SP. */ 1848 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1849 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1850 1851 /* For ARM code, we don't care about the mode, but for Thumb, the index 1852 must be suitable for use in a QImode load. */ 1853 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1854 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1855 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1856 1857 /* Maximum number of registers that can appear in a valid memory address. 1858 Shifts in addresses can't be by a register. */ 1859 #define MAX_REGS_PER_ADDRESS 2 1860 1861 /* Recognize any constant value that is a valid address. */ 1862 /* XXX We can address any constant, eventually... */ 1863 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1864 #define CONSTANT_ADDRESS_P(X) \ 1865 (GET_CODE (X) == SYMBOL_REF \ 1866 && (CONSTANT_POOL_ADDRESS_P (X) \ 1867 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1868 1869 /* True if SYMBOL + OFFSET constants must refer to something within 1870 SYMBOL's section. */ 1871 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1872 1873 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1874 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1875 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1876 #endif 1877 1878 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1879 #define SUBTARGET_NAME_ENCODING_LENGTHS 1880 #endif 1881 1882 /* This is a C fragment for the inside of a switch statement. 1883 Each case label should return the number of characters to 1884 be stripped from the start of a function's name, if that 1885 name starts with the indicated character. */ 1886 #define ARM_NAME_ENCODING_LENGTHS \ 1887 case '*': return 1; \ 1888 SUBTARGET_NAME_ENCODING_LENGTHS 1889 1890 /* This is how to output a reference to a user-level label named NAME. 1891 `assemble_name' uses this. */ 1892 #undef ASM_OUTPUT_LABELREF 1893 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1894 arm_asm_output_labelref (FILE, NAME) 1895 1896 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1897 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1898 if (TARGET_THUMB2) \ 1899 thumb2_asm_output_opcode (STREAM); 1900 1901 /* The EABI specifies that constructors should go in .init_array. 1902 Other targets use .ctors for compatibility. */ 1903 #ifndef ARM_EABI_CTORS_SECTION_OP 1904 #define ARM_EABI_CTORS_SECTION_OP \ 1905 "\t.section\t.init_array,\"aw\",%init_array" 1906 #endif 1907 #ifndef ARM_EABI_DTORS_SECTION_OP 1908 #define ARM_EABI_DTORS_SECTION_OP \ 1909 "\t.section\t.fini_array,\"aw\",%fini_array" 1910 #endif 1911 #define ARM_CTORS_SECTION_OP \ 1912 "\t.section\t.ctors,\"aw\",%progbits" 1913 #define ARM_DTORS_SECTION_OP \ 1914 "\t.section\t.dtors,\"aw\",%progbits" 1915 1916 /* Define CTORS_SECTION_ASM_OP. */ 1917 #undef CTORS_SECTION_ASM_OP 1918 #undef DTORS_SECTION_ASM_OP 1919 #ifndef IN_LIBGCC2 1920 # define CTORS_SECTION_ASM_OP \ 1921 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1922 # define DTORS_SECTION_ASM_OP \ 1923 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1924 #else /* !defined (IN_LIBGCC2) */ 1925 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1926 so we cannot use the definition above. */ 1927 # ifdef __ARM_EABI__ 1928 /* The .ctors section is not part of the EABI, so we do not define 1929 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1930 from trying to use it. We do define it when doing normal 1931 compilation, as .init_array can be used instead of .ctors. */ 1932 /* There is no need to emit begin or end markers when using 1933 init_array; the dynamic linker will compute the size of the 1934 array itself based on special symbols created by the static 1935 linker. However, we do need to arrange to set up 1936 exception-handling here. */ 1937 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1938 # define CTOR_LIST_END /* empty */ 1939 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1940 # define DTOR_LIST_END /* empty */ 1941 # else /* !defined (__ARM_EABI__) */ 1942 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1943 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1944 # endif /* !defined (__ARM_EABI__) */ 1945 #endif /* !defined (IN_LIBCC2) */ 1946 1947 /* True if the operating system can merge entities with vague linkage 1948 (e.g., symbols in COMDAT group) during dynamic linking. */ 1949 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1950 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1951 #endif 1952 1953 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1954 1955 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1956 and check its validity for a certain class. 1957 We have two alternate definitions for each of them. 1958 The usual definition accepts all pseudo regs; the other rejects 1959 them unless they have been allocated suitable hard regs. 1960 The symbol REG_OK_STRICT causes the latter definition to be used. 1961 Thumb-2 has the same restrictions as arm. */ 1962 #ifndef REG_OK_STRICT 1963 1964 #define ARM_REG_OK_FOR_BASE_P(X) \ 1965 (REGNO (X) <= LAST_ARM_REGNUM \ 1966 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1967 || REGNO (X) == FRAME_POINTER_REGNUM \ 1968 || REGNO (X) == ARG_POINTER_REGNUM) 1969 1970 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1971 ((REGNO (X) <= LAST_ARM_REGNUM \ 1972 && REGNO (X) != STACK_POINTER_REGNUM) \ 1973 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1974 || REGNO (X) == FRAME_POINTER_REGNUM \ 1975 || REGNO (X) == ARG_POINTER_REGNUM) 1976 1977 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1978 (REGNO (X) <= LAST_LO_REGNUM \ 1979 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1980 || (GET_MODE_SIZE (MODE) >= 4 \ 1981 && (REGNO (X) == STACK_POINTER_REGNUM \ 1982 || (X) == hard_frame_pointer_rtx \ 1983 || (X) == arg_pointer_rtx))) 1984 1985 #define REG_STRICT_P 0 1986 1987 #else /* REG_OK_STRICT */ 1988 1989 #define ARM_REG_OK_FOR_BASE_P(X) \ 1990 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1991 1992 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1993 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1994 1995 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1996 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1997 1998 #define REG_STRICT_P 1 1999 2000 #endif /* REG_OK_STRICT */ 2001 2002 /* Now define some helpers in terms of the above. */ 2003 2004 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2005 (TARGET_THUMB1 \ 2006 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2007 : ARM_REG_OK_FOR_BASE_P (X)) 2008 2009 /* For 16-bit Thumb, a valid index register is anything that can be used in 2010 a byte load instruction. */ 2011 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2012 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2013 2014 /* Nonzero if X is a hard reg that can be used as an index 2015 or if it is a pseudo reg. On the Thumb, the stack pointer 2016 is not suitable. */ 2017 #define REG_OK_FOR_INDEX_P(X) \ 2018 (TARGET_THUMB1 \ 2019 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2020 : ARM_REG_OK_FOR_INDEX_P (X)) 2021 2022 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2023 For Thumb, we can not use SP + reg, so reject SP. */ 2024 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2025 REG_OK_FOR_INDEX_P (X) 2026 2027 #define ARM_BASE_REGISTER_RTX_P(X) \ 2029 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2030 2031 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2032 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2033 2034 /* Specify the machine mode that this machine uses 2036 for the index in the tablejump instruction. */ 2037 #define CASE_VECTOR_MODE Pmode 2038 2039 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2040 || (TARGET_THUMB1 \ 2041 && (optimize_size || flag_pic))) 2042 2043 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2044 (TARGET_THUMB1 \ 2045 ? (min >= 0 && max < 512 \ 2046 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2047 : min >= -256 && max < 256 \ 2048 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2049 : min >= 0 && max < 8192 \ 2050 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2051 : min >= -4096 && max < 4096 \ 2052 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2053 : SImode) \ 2054 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2055 : (max >= 0x200) ? HImode \ 2056 : QImode)) 2057 2058 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2059 unsigned is probably best, but may break some code. */ 2060 #ifndef DEFAULT_SIGNED_CHAR 2061 #define DEFAULT_SIGNED_CHAR 0 2062 #endif 2063 2064 /* Max number of bytes we can move from memory to memory 2065 in one reasonably fast instruction. */ 2066 #define MOVE_MAX 4 2067 2068 #undef MOVE_RATIO 2069 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2070 2071 /* Define if operations between registers always perform the operation 2072 on the full register even if a narrower mode is specified. */ 2073 #define WORD_REGISTER_OPERATIONS 2074 2075 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2076 will either zero-extend or sign-extend. The value of this macro should 2077 be the code that says which one of the two operations is implicitly 2078 done, UNKNOWN if none. */ 2079 #define LOAD_EXTEND_OP(MODE) \ 2080 (TARGET_THUMB ? ZERO_EXTEND : \ 2081 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2082 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2083 2084 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2085 #define SLOW_BYTE_ACCESS 0 2086 2087 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2088 2089 /* Immediate shift counts are truncated by the output routines (or was it 2090 the assembler?). Shift counts in a register are truncated by ARM. Note 2091 that the native compiler puts too large (> 32) immediate shift counts 2092 into a register and shifts by the register, letting the ARM decide what 2093 to do instead of doing that itself. */ 2094 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2095 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2096 On the arm, Y in a register is used modulo 256 for the shift. Only for 2097 rotates is modulo 32 used. */ 2098 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2099 2100 /* All integers have the same format so truncation is easy. */ 2101 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2102 2103 /* Calling from registers is a massive pain. */ 2104 #define NO_FUNCTION_CSE 1 2105 2106 /* The machine modes of pointers and functions */ 2107 #define Pmode SImode 2108 #define FUNCTION_MODE Pmode 2109 2110 #define ARM_FRAME_RTX(X) \ 2111 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2112 || (X) == arg_pointer_rtx) 2113 2114 /* Try to generate sequences that don't involve branches, we can then use 2115 conditional instructions. */ 2116 #define BRANCH_COST(speed_p, predictable_p) \ 2117 (current_tune->branch_cost (speed_p, predictable_p)) 2118 2119 /* False if short circuit operation is preferred. */ 2120 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2121 ((optimize_size) \ 2122 ? (TARGET_THUMB ? false : true) \ 2123 : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) 2124 2125 2126 /* Position Independent Code. */ 2128 /* We decide which register to use based on the compilation options and 2129 the assembler in use; this is more general than the APCS restriction of 2130 using sb (r9) all the time. */ 2131 extern unsigned arm_pic_register; 2132 2133 /* The register number of the register used to address a table of static 2134 data addresses in memory. */ 2135 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2136 2137 /* We can't directly access anything that contains a symbol, 2138 nor can we indirect via the constant pool. One exception is 2139 UNSPEC_TLS, which is always PIC. */ 2140 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2141 (!(symbol_mentioned_p (X) \ 2142 || label_mentioned_p (X) \ 2143 || (GET_CODE (X) == SYMBOL_REF \ 2144 && CONSTANT_POOL_ADDRESS_P (X) \ 2145 && (symbol_mentioned_p (get_pool_constant (X)) \ 2146 || label_mentioned_p (get_pool_constant (X))))) \ 2147 || tls_mentioned_p (X)) 2148 2149 /* We need to know when we are making a constant pool; this determines 2150 whether data needs to be in the GOT or can be referenced via a GOT 2151 offset. */ 2152 extern int making_const_table; 2153 2154 /* Handle pragmas for compatibility with Intel's compilers. */ 2156 /* Also abuse this to register additional C specific EABI attributes. */ 2157 #define REGISTER_TARGET_PRAGMAS() do { \ 2158 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2159 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2160 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2161 arm_lang_object_attributes_init(); \ 2162 } while (0) 2163 2164 /* Condition code information. */ 2165 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2166 return the mode to be used for the comparison. */ 2167 2168 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2169 2170 #define REVERSIBLE_CC_MODE(MODE) 1 2171 2172 #define REVERSE_CONDITION(CODE,MODE) \ 2173 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2174 ? reverse_condition_maybe_unordered (code) \ 2175 : reverse_condition (code)) 2176 2177 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2178 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2179 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2180 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2181 2182 #define CC_STATUS_INIT \ 2184 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2185 2186 #undef ASM_APP_ON 2187 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2188 "\t.syntax divided\n") 2189 2190 #undef ASM_APP_OFF 2191 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \ 2192 "\t.thumb\n\t.syntax unified\n") 2193 2194 /* Output a push or a pop instruction (only used when profiling). 2195 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2196 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2197 that r7 isn't used by the function profiler, so we can use it as a 2198 scratch reg. WARNING: This isn't safe in the general case! It may be 2199 sensitive to future changes in final.c:profile_function. */ 2200 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2201 do \ 2202 { \ 2203 if (TARGET_ARM) \ 2204 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2205 STACK_POINTER_REGNUM, REGNO); \ 2206 else if (TARGET_THUMB1 \ 2207 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2208 { \ 2209 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2210 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2211 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2212 } \ 2213 else \ 2214 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2215 } while (0) 2216 2217 2218 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2219 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2220 do \ 2221 { \ 2222 if (TARGET_ARM) \ 2223 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2224 STACK_POINTER_REGNUM, REGNO); \ 2225 else if (TARGET_THUMB1 \ 2226 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2227 { \ 2228 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2229 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2230 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2231 } \ 2232 else \ 2233 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2234 } while (0) 2235 2236 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2237 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2238 2239 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2240 default alignment from elfos.h. */ 2241 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2242 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2243 2244 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2245 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2246 ? 1 : 0) 2247 2248 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2249 do \ 2250 { \ 2251 if (TARGET_THUMB) \ 2252 { \ 2253 if (is_called_in_ARM_mode (DECL) \ 2254 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2255 && cfun->is_thunk)) \ 2256 fprintf (STREAM, "\t.code 32\n") ; \ 2257 else if (TARGET_THUMB1) \ 2258 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2259 else \ 2260 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2261 } \ 2262 if (TARGET_POKE_FUNCTION_NAME) \ 2263 arm_poke_function_name (STREAM, (const char *) NAME); \ 2264 } \ 2265 while (0) 2266 2267 /* For aliases of functions we use .thumb_set instead. */ 2268 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2269 do \ 2270 { \ 2271 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2272 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2273 \ 2274 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2275 { \ 2276 fprintf (FILE, "\t.thumb_set "); \ 2277 assemble_name (FILE, LABEL1); \ 2278 fprintf (FILE, ","); \ 2279 assemble_name (FILE, LABEL2); \ 2280 fprintf (FILE, "\n"); \ 2281 } \ 2282 else \ 2283 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2284 } \ 2285 while (0) 2286 2287 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2288 /* To support -falign-* switches we need to use .p2align so 2289 that alignment directives in code sections will be padded 2290 with no-op instructions, rather than zeroes. */ 2291 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2292 if ((LOG) != 0) \ 2293 { \ 2294 if ((MAX_SKIP) == 0) \ 2295 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2296 else \ 2297 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2298 (int) (LOG), (int) (MAX_SKIP)); \ 2299 } 2300 #endif 2301 2302 /* Add two bytes to the length of conditionally executed Thumb-2 2304 instructions for the IT instruction. */ 2305 #define ADJUST_INSN_LENGTH(insn, length) \ 2306 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2307 length += 2; 2308 2309 /* Only perform branch elimination (by making instructions conditional) if 2310 we're optimizing. For Thumb-2 check if any IT instructions need 2311 outputting. */ 2312 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2313 if (TARGET_ARM && optimize) \ 2314 arm_final_prescan_insn (INSN); \ 2315 else if (TARGET_THUMB2) \ 2316 thumb2_final_prescan_insn (INSN); \ 2317 else if (TARGET_THUMB1) \ 2318 thumb1_final_prescan_insn (INSN) 2319 2320 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2321 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2322 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2323 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2324 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2325 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2326 : 0)))) 2327 2328 /* A C expression whose value is RTL representing the value of the return 2329 address for the frame COUNT steps up from the current frame. */ 2330 2331 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2332 arm_return_addr (COUNT, FRAME) 2333 2334 /* Mask of the bits in the PC that contain the real return address 2335 when running in 26-bit mode. */ 2336 #define RETURN_ADDR_MASK26 (0x03fffffc) 2337 2338 /* Pick up the return address upon entry to a procedure. Used for 2339 dwarf2 unwind information. This also enables the table driven 2340 mechanism. */ 2341 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2342 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2343 2344 /* Used to mask out junk bits from the return address, such as 2345 processor state, interrupt status, condition codes and the like. */ 2346 #define MASK_RETURN_ADDR \ 2347 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2348 in 26 bit mode, the condition codes must be masked out of the \ 2349 return address. This does not apply to ARM6 and later processors \ 2350 when running in 32 bit mode. */ \ 2351 ((arm_arch4 || TARGET_THUMB) \ 2352 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2353 : arm_gen_return_addr_mask ()) 2354 2355 2356 /* Do not emit .note.GNU-stack by default. */ 2358 #ifndef NEED_INDICATE_EXEC_STACK 2359 #define NEED_INDICATE_EXEC_STACK 0 2360 #endif 2361 2362 #define TARGET_ARM_ARCH \ 2363 (arm_base_arch) \ 2364 2365 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2366 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2367 2368 /* The highest Thumb instruction set version supported by the chip. */ 2369 #define TARGET_ARM_ARCH_ISA_THUMB \ 2370 (arm_arch_thumb2 ? 2 \ 2371 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2372 2373 /* Expands to an upper-case char of the target's architectural 2374 profile. */ 2375 #define TARGET_ARM_ARCH_PROFILE \ 2376 (!arm_arch_notm \ 2377 ? 'M' \ 2378 : (arm_arch7 \ 2379 ? (strlen (arm_arch_name) >=3 \ 2380 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2381 : 0) \ 2382 : 0)) 2383 2384 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2385 Bit 0 for bytes, up to bit 3 for double-words. */ 2386 #define TARGET_ARM_FEATURE_LDREX \ 2387 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2388 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2389 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2390 2391 /* Set as a bit mask indicating the available widths of hardware floating 2392 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2393 32-bit support, bit 3 indicates 64-bit support. */ 2394 #define TARGET_ARM_FP \ 2395 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2396 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2397 : 0) 2398 2399 2400 /* Set as a bit mask indicating the available widths of floating point 2401 types for hardware NEON floating point. This is the same as 2402 TARGET_ARM_FP without the 64-bit bit set. */ 2403 #define TARGET_NEON_FP \ 2404 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2405 : 0) 2406 2407 /* The maximum number of parallel loads or stores we support in an ldm/stm 2408 instruction. */ 2409 #define MAX_LDM_STM_OPS 4 2410 2411 #define BIG_LITTLE_SPEC \ 2412 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2413 2414 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2415 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2416 { "rewrite_mcpu", arm_rewrite_mcpu }, 2417 2418 #define ASM_CPU_SPEC \ 2419 " %{mcpu=generic-*:-march=%*;" \ 2420 " :%{march=*:-march=%*}}" \ 2421 BIG_LITTLE_SPEC 2422 2423 /* -mcpu=native handling only makes sense with compiler running on 2424 an ARM chip. */ 2425 #if defined(__arm__) && defined(__linux__) 2426 extern const char *host_detect_local_cpu (int argc, const char **argv); 2427 # define EXTRA_SPEC_FUNCTIONS \ 2428 { "local_cpu_detect", host_detect_local_cpu }, \ 2429 BIG_LITTLE_CPU_SPEC_FUNCTIONS 2430 2431 # define MCPU_MTUNE_NATIVE_SPECS \ 2432 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2433 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2434 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2435 #else 2436 # define MCPU_MTUNE_NATIVE_SPECS "" 2437 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 2438 #endif 2439 2440 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2441 #define TARGET_SUPPORTS_WIDE_INT 1 2442 #endif /* ! GCC_ARM_H */ 2443
Indexes created Tue Apr 21 00:23:25 UTC 2026