arm.h revision 1.1.1.4
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2015 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() \ 49 do \ 50 { \ 51 if (TARGET_DSP_MULTIPLY) \ 52 builtin_define ("__ARM_FEATURE_DSP"); \ 53 if (TARGET_ARM_QBIT) \ 54 builtin_define ("__ARM_FEATURE_QBIT"); \ 55 if (TARGET_ARM_SAT) \ 56 builtin_define ("__ARM_FEATURE_SAT"); \ 57 if (TARGET_CRYPTO) \ 58 builtin_define ("__ARM_FEATURE_CRYPTO"); \ 59 if (unaligned_access) \ 60 builtin_define ("__ARM_FEATURE_UNALIGNED"); \ 61 if (TARGET_CRC32) \ 62 builtin_define ("__ARM_FEATURE_CRC32"); \ 63 if (TARGET_32BIT) \ 64 builtin_define ("__ARM_32BIT_STATE"); \ 65 if (TARGET_ARM_FEATURE_LDREX) \ 66 builtin_define_with_int_value ( \ 67 "__ARM_FEATURE_LDREX", TARGET_ARM_FEATURE_LDREX); \ 68 if ((TARGET_ARM_ARCH >= 5 && !TARGET_THUMB) \ 69 || TARGET_ARM_ARCH_ISA_THUMB >=2) \ 70 builtin_define ("__ARM_FEATURE_CLZ"); \ 71 if (TARGET_INT_SIMD) \ 72 builtin_define ("__ARM_FEATURE_SIMD32"); \ 73 \ 74 builtin_define_with_int_value ( \ 75 "__ARM_SIZEOF_MINIMAL_ENUM", \ 76 flag_short_enums ? 1 : 4); \ 77 builtin_define_type_sizeof ("__ARM_SIZEOF_WCHAR_T", \ 78 wchar_type_node); \ 79 if (TARGET_ARM_ARCH_PROFILE) \ 80 builtin_define_with_int_value ( \ 81 "__ARM_ARCH_PROFILE", TARGET_ARM_ARCH_PROFILE); \ 82 \ 83 /* Define __arm__ even when in thumb mode, for \ 84 consistency with armcc. */ \ 85 builtin_define ("__arm__"); \ 86 if (TARGET_ARM_ARCH) \ 87 builtin_define_with_int_value ( \ 88 "__ARM_ARCH", TARGET_ARM_ARCH); \ 89 if (arm_arch_notm) \ 90 builtin_define ("__ARM_ARCH_ISA_ARM"); \ 91 builtin_define ("__APCS_32__"); \ 92 if (TARGET_THUMB) \ 93 builtin_define ("__thumb__"); \ 94 if (TARGET_THUMB2) \ 95 builtin_define ("__thumb2__"); \ 96 if (TARGET_ARM_ARCH_ISA_THUMB) \ 97 builtin_define_with_int_value ( \ 98 "__ARM_ARCH_ISA_THUMB", \ 99 TARGET_ARM_ARCH_ISA_THUMB); \ 100 \ 101 if (TARGET_BIG_END) \ 102 { \ 103 builtin_define ("__ARMEB__"); \ 104 builtin_define ("__ARM_BIG_ENDIAN"); \ 105 if (TARGET_THUMB) \ 106 builtin_define ("__THUMBEB__"); \ 107 } \ 108 else \ 109 { \ 110 builtin_define ("__ARMEL__"); \ 111 if (TARGET_THUMB) \ 112 builtin_define ("__THUMBEL__"); \ 113 } \ 114 \ 115 if (TARGET_SOFT_FLOAT) \ 116 builtin_define ("__SOFTFP__"); \ 117 \ 118 if (TARGET_VFP) \ 119 builtin_define ("__VFP_FP__"); \ 120 \ 121 if (TARGET_ARM_FP) \ 122 builtin_define_with_int_value ( \ 123 "__ARM_FP", TARGET_ARM_FP); \ 124 if (arm_fp16_format == ARM_FP16_FORMAT_IEEE) \ 125 builtin_define ("__ARM_FP16_FORMAT_IEEE"); \ 126 if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) \ 127 builtin_define ("__ARM_FP16_FORMAT_ALTERNATIVE"); \ 128 if (TARGET_FMA) \ 129 builtin_define ("__ARM_FEATURE_FMA"); \ 130 \ 131 if (TARGET_NEON) \ 132 { \ 133 builtin_define ("__ARM_NEON__"); \ 134 builtin_define ("__ARM_NEON"); \ 135 } \ 136 if (TARGET_NEON_FP) \ 137 builtin_define_with_int_value ( \ 138 "__ARM_NEON_FP", TARGET_NEON_FP); \ 139 \ 140 /* Add a define for interworking. \ 141 Needed when building libgcc.a. */ \ 142 if (arm_cpp_interwork) \ 143 builtin_define ("__THUMB_INTERWORK__"); \ 144 \ 145 builtin_assert ("cpu=arm"); \ 146 builtin_assert ("machine=arm"); \ 147 \ 148 builtin_define (arm_arch_name); \ 149 if (arm_arch_xscale) \ 150 builtin_define ("__XSCALE__"); \ 151 if (arm_arch_iwmmxt) \ 152 { \ 153 builtin_define ("__IWMMXT__"); \ 154 builtin_define ("__ARM_WMMX"); \ 155 } \ 156 if (arm_arch_iwmmxt2) \ 157 builtin_define ("__IWMMXT2__"); \ 158 if (TARGET_AAPCS_BASED) \ 159 { \ 160 if (arm_pcs_default == ARM_PCS_AAPCS_VFP) \ 161 builtin_define ("__ARM_PCS_VFP"); \ 162 else if (arm_pcs_default == ARM_PCS_AAPCS) \ 163 builtin_define ("__ARM_PCS"); \ 164 builtin_define ("__ARM_EABI__"); \ 165 } \ 166 if (TARGET_IDIV) \ 167 { \ 168 builtin_define ("__ARM_ARCH_EXT_IDIV__"); \ 169 builtin_define ("__ARM_FEATURE_IDIV"); \ 170 } \ 171 if (inline_asm_unified) \ 172 builtin_define ("__ARM_ASM_SYNTAX_UNIFIED__");\ 173 } while (0) 174 175 #include "config/arm/arm-opts.h" 176 177 enum target_cpus 178 { 179 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ 180 TARGET_CPU_##INTERNAL_IDENT, 181 #include "arm-cores.def" 182 #undef ARM_CORE 183 TARGET_CPU_generic 184 }; 185 186 /* The processor for which instructions should be scheduled. */ 187 extern enum processor_type arm_tune; 188 189 typedef enum arm_cond_code 190 { 191 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 192 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 193 } 194 arm_cc; 195 196 extern arm_cc arm_current_cc; 197 198 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 199 200 /* The maximum number of instructions that is beneficial to 201 conditionally execute. */ 202 #undef MAX_CONDITIONAL_EXECUTE 203 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 204 205 extern int arm_target_label; 206 extern int arm_ccfsm_state; 207 extern GTY(()) rtx arm_target_insn; 208 /* The label of the current constant pool. */ 209 extern rtx pool_vector_label; 210 /* Set to 1 when a return insn is output, this means that the epilogue 211 is not needed. */ 212 extern int return_used_this_function; 213 /* Callback to output language specific object attributes. */ 214 extern void (*arm_lang_output_object_attributes_hook)(void); 215 216 /* Just in case configure has failed to define anything. */ 218 #ifndef TARGET_CPU_DEFAULT 219 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 220 #endif 221 222 223 #undef CPP_SPEC 224 #define CPP_SPEC "%(subtarget_cpp_spec) \ 225 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 226 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 227 %{mbig-endian:%{mlittle-endian: \ 228 %e-mbig-endian and -mlittle-endian may not be used together}}" 229 230 #ifndef CC1_SPEC 231 #define CC1_SPEC "" 232 #endif 233 234 /* This macro defines names of additional specifications to put in the specs 235 that can be used in various specifications like CC1_SPEC. Its definition 236 is an initializer with a subgrouping for each command option. 237 238 Each subgrouping contains a string constant, that defines the 239 specification name, and a string constant that used by the GCC driver 240 program. 241 242 Do not define this macro if it does not need to do anything. */ 243 #define EXTRA_SPECS \ 244 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 245 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 246 SUBTARGET_EXTRA_SPECS 247 248 #ifndef SUBTARGET_EXTRA_SPECS 249 #define SUBTARGET_EXTRA_SPECS 250 #endif 251 252 #ifndef SUBTARGET_CPP_SPEC 253 #define SUBTARGET_CPP_SPEC "" 254 #endif 255 256 /* Run-time Target Specification. */ 258 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 259 /* Use hardware floating point instructions. */ 260 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 261 /* Use hardware floating point calling convention. */ 262 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 263 #define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 264 #define TARGET_IWMMXT (arm_arch_iwmmxt) 265 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 266 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 267 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 268 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 269 #define TARGET_ARM (! TARGET_THUMB) 270 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 271 #define TARGET_BACKTRACE (leaf_function_p () \ 272 ? TARGET_TPCS_LEAF_FRAME \ 273 : TARGET_TPCS_FRAME) 274 #define TARGET_AAPCS_BASED \ 275 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 276 277 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 278 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 279 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 280 281 /* Only 16-bit thumb code. */ 282 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 283 /* Arm or Thumb-2 32-bit code. */ 284 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 285 /* 32-bit Thumb-2 code. */ 286 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 287 /* Thumb-1 only. */ 288 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 289 290 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 291 && !TARGET_THUMB1) 292 293 #define TARGET_CRC32 (arm_arch_crc) 294 295 /* The following two macros concern the ability to execute coprocessor 296 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 297 only ever tested when we know we are generating for VFP hardware; we need 298 to be more careful with TARGET_NEON as noted below. */ 299 300 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 301 #define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 302 303 /* FPU supports VFPv3 instructions. */ 304 #define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 305 306 /* FPU supports FPv5 instructions. */ 307 #define TARGET_VFP5 (TARGET_VFP && arm_fpu_desc->rev >= 5) 308 309 /* FPU only supports VFP single-precision instructions. */ 310 #define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 311 312 /* FPU supports VFP double-precision instructions. */ 313 #define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 314 315 /* FPU supports half-precision floating-point with NEON element load/store. */ 316 #define TARGET_NEON_FP16 \ 317 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 318 319 /* FPU supports VFP half-precision floating-point. */ 320 #define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 321 322 /* FPU supports fused-multiply-add operations. */ 323 #define TARGET_FMA (TARGET_VFP && arm_fpu_desc->rev >= 4) 324 325 /* FPU is ARMv8 compatible. */ 326 #define TARGET_FPU_ARMV8 (TARGET_VFP && arm_fpu_desc->rev >= 8) 327 328 /* FPU supports Crypto extensions. */ 329 #define TARGET_CRYPTO (TARGET_VFP && arm_fpu_desc->crypto) 330 331 /* FPU supports Neon instructions. The setting of this macro gets 332 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 333 and TARGET_HARD_FLOAT to ensure that NEON instructions are 334 available. */ 335 #define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 336 && TARGET_VFP && arm_fpu_desc->neon) 337 338 /* Q-bit is present. */ 339 #define TARGET_ARM_QBIT \ 340 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 341 /* Saturation operation, e.g. SSAT. */ 342 #define TARGET_ARM_SAT \ 343 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 344 /* "DSP" multiply instructions, eg. SMULxy. */ 345 #define TARGET_DSP_MULTIPLY \ 346 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 347 /* Integer SIMD instructions, and extend-accumulate instructions. */ 348 #define TARGET_INT_SIMD \ 349 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 350 351 /* Should MOVW/MOVT be used in preference to a constant pool. */ 352 #define TARGET_USE_MOVT \ 353 (arm_arch_thumb2 \ 354 && (arm_disable_literal_pool \ 355 || (!optimize_size && !current_tune->prefer_constant_pool))) 356 357 /* We could use unified syntax for arm mode, but for now we just use it 358 for thumb mode. */ 359 #define TARGET_UNIFIED_ASM (TARGET_THUMB) 360 361 /* Nonzero if this chip provides the DMB instruction. */ 362 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 363 364 /* Nonzero if this chip implements a memory barrier via CP15. */ 365 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 366 && ! TARGET_THUMB1) 367 368 /* Nonzero if this chip implements a memory barrier instruction. */ 369 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 370 371 /* Nonzero if this chip supports ldrex and strex */ 372 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 373 374 /* Nonzero if this chip supports LPAE. */ 375 #define TARGET_HAVE_LPAE (arm_arch_lpae) 376 377 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 378 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 379 380 /* Nonzero if this chip supports ldrexd and strexd. */ 381 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) || arm_arch7) \ 382 && arm_arch_notm) 383 384 /* Nonzero if this chip supports load-acquire and store-release. */ 385 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 386 387 /* Nonzero if integer division instructions supported. */ 388 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 389 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 390 391 /* Nonzero if disallow volatile memory access in IT block. */ 392 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 393 394 /* Should NEON be used for 64-bits bitops. */ 395 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 396 397 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 398 then TARGET_AAPCS_BASED must be true -- but the converse does not 399 hold. TARGET_BPABI implies the use of the BPABI runtime library, 400 etc., in addition to just the AAPCS calling conventions. */ 401 #ifndef TARGET_BPABI 402 #define TARGET_BPABI false 403 #endif 404 405 /* Support for a compile-time default CPU, et cetera. The rules are: 406 --with-arch is ignored if -march or -mcpu are specified. 407 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 408 by --with-arch. 409 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 410 by -march). 411 --with-float is ignored if -mfloat-abi is specified. 412 --with-fpu is ignored if -mfpu is specified. 413 --with-abi is ignored if -mabi is specified. 414 --with-tls is ignored if -mtls-dialect is specified. */ 415 #define OPTION_DEFAULT_SPECS \ 416 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 417 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 418 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 419 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 420 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 421 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 422 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 423 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 424 425 /* Which floating point model to use. */ 426 enum arm_fp_model 427 { 428 ARM_FP_MODEL_UNKNOWN, 429 /* VFP floating point model. */ 430 ARM_FP_MODEL_VFP 431 }; 432 433 enum vfp_reg_type 434 { 435 VFP_NONE = 0, 436 VFP_REG_D16, 437 VFP_REG_D32, 438 VFP_REG_SINGLE 439 }; 440 441 extern const struct arm_fpu_desc 442 { 443 const char *name; 444 enum arm_fp_model model; 445 int rev; 446 enum vfp_reg_type regs; 447 int neon; 448 int fp16; 449 int crypto; 450 } *arm_fpu_desc; 451 452 /* Which floating point hardware to schedule for. */ 453 extern int arm_fpu_attr; 454 455 #ifndef TARGET_DEFAULT_FLOAT_ABI 456 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 457 #endif 458 459 #ifndef ARM_DEFAULT_ABI 460 #define ARM_DEFAULT_ABI ARM_ABI_APCS 461 #endif 462 463 /* Map each of the micro-architecture variants to their corresponding 464 major architecture revision. */ 465 466 enum base_architecture 467 { 468 BASE_ARCH_0 = 0, 469 BASE_ARCH_2 = 2, 470 BASE_ARCH_3 = 3, 471 BASE_ARCH_3M = 3, 472 BASE_ARCH_4 = 4, 473 BASE_ARCH_4T = 4, 474 BASE_ARCH_5 = 5, 475 BASE_ARCH_5E = 5, 476 BASE_ARCH_5T = 5, 477 BASE_ARCH_5TE = 5, 478 BASE_ARCH_5TEJ = 5, 479 BASE_ARCH_6 = 6, 480 BASE_ARCH_6J = 6, 481 BASE_ARCH_6ZK = 6, 482 BASE_ARCH_6K = 6, 483 BASE_ARCH_6T2 = 6, 484 BASE_ARCH_6M = 6, 485 BASE_ARCH_6Z = 6, 486 BASE_ARCH_7 = 7, 487 BASE_ARCH_7A = 7, 488 BASE_ARCH_7R = 7, 489 BASE_ARCH_7M = 7, 490 BASE_ARCH_7EM = 7, 491 BASE_ARCH_8A = 8 492 }; 493 494 /* The major revision number of the ARM Architecture implemented by the target. */ 495 extern enum base_architecture arm_base_arch; 496 497 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 498 extern int arm_arch3m; 499 500 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 501 extern int arm_arch4; 502 503 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 504 extern int arm_arch4t; 505 506 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 507 extern int arm_arch5; 508 509 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 510 extern int arm_arch5e; 511 512 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 513 extern int arm_arch6; 514 515 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 516 extern int arm_arch6k; 517 518 /* Nonzero if instructions present in ARMv6-M can be used. */ 519 extern int arm_arch6m; 520 521 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 522 extern int arm_arch7; 523 524 /* Nonzero if instructions not present in the 'M' profile can be used. */ 525 extern int arm_arch_notm; 526 527 /* Nonzero if instructions present in ARMv7E-M can be used. */ 528 extern int arm_arch7em; 529 530 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 531 extern int arm_arch8; 532 533 /* Nonzero if this chip can benefit from load scheduling. */ 534 extern int arm_ld_sched; 535 536 /* Nonzero if generating Thumb code, either Thumb-1 or Thumb-2. */ 537 extern int thumb_code; 538 539 /* Nonzero if generating Thumb-1 code. */ 540 extern int thumb1_code; 541 542 /* Nonzero if this chip is a StrongARM. */ 543 extern int arm_tune_strongarm; 544 545 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 546 extern int arm_arch_iwmmxt; 547 548 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 549 extern int arm_arch_iwmmxt2; 550 551 /* Nonzero if this chip is an XScale. */ 552 extern int arm_arch_xscale; 553 554 /* Nonzero if tuning for XScale. */ 555 extern int arm_tune_xscale; 556 557 /* Nonzero if tuning for stores via the write buffer. */ 558 extern int arm_tune_wbuf; 559 560 /* Nonzero if tuning for Cortex-A9. */ 561 extern int arm_tune_cortex_a9; 562 563 /* Nonzero if we should define __THUMB_INTERWORK__ in the 564 preprocessor. 565 XXX This is a bit of a hack, it's intended to help work around 566 problems in GLD which doesn't understand that armv5t code is 567 interworking clean. */ 568 extern int arm_cpp_interwork; 569 570 /* Nonzero if chip supports Thumb 2. */ 571 extern int arm_arch_thumb2; 572 573 /* Nonzero if chip supports integer division instruction in ARM mode. */ 574 extern int arm_arch_arm_hwdiv; 575 576 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 577 extern int arm_arch_thumb_hwdiv; 578 579 /* Nonzero if chip disallows volatile memory access in IT block. */ 580 extern int arm_arch_no_volatile_ce; 581 582 /* Nonzero if we should use Neon to handle 64-bits operations rather 583 than core registers. */ 584 extern int prefer_neon_for_64bits; 585 586 /* Nonzero if we shouldn't use literal pools. */ 587 #ifndef USED_FOR_TARGET 588 extern bool arm_disable_literal_pool; 589 #endif 590 591 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 592 extern int arm_arch_crc; 593 594 #ifndef TARGET_DEFAULT 595 #define TARGET_DEFAULT (MASK_APCS_FRAME) 596 #endif 597 598 /* Nonzero if PIC code requires explicit qualifiers to generate 599 PLT and GOT relocs rather than the assembler doing so implicitly. 600 Subtargets can override these if required. */ 601 #ifndef NEED_GOT_RELOC 602 #define NEED_GOT_RELOC 0 603 #endif 604 #ifndef NEED_PLT_RELOC 605 #define NEED_PLT_RELOC 0 606 #endif 607 608 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 609 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 610 #endif 611 612 /* Nonzero if we need to refer to the GOT with a PC-relative 613 offset. In other words, generate 614 615 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 616 617 rather than 618 619 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 620 621 The default is true, which matches NetBSD. Subtargets can 622 override this if required. */ 623 #ifndef GOT_PCREL 624 #define GOT_PCREL 1 625 #endif 626 627 /* Target machine storage Layout. */ 629 630 631 /* Define this macro if it is advisable to hold scalars in registers 632 in a wider mode than that declared by the program. In such cases, 633 the value is constrained to be within the bounds of the declared 634 type, but kept valid in the wider mode. The signedness of the 635 extension may differ from that of the type. */ 636 637 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 638 if (GET_MODE_CLASS (MODE) == MODE_INT \ 639 && GET_MODE_SIZE (MODE) < 4) \ 640 { \ 641 (MODE) = SImode; \ 642 } 643 644 /* Define this if most significant bit is lowest numbered 645 in instructions that operate on numbered bit-fields. */ 646 #define BITS_BIG_ENDIAN 0 647 648 /* Define this if most significant byte of a word is the lowest numbered. 649 Most ARM processors are run in little endian mode, so that is the default. 650 If you want to have it run-time selectable, change the definition in a 651 cover file to be TARGET_BIG_ENDIAN. */ 652 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 653 654 /* Define this if most significant word of a multiword number is the lowest 655 numbered. */ 656 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 657 658 #define UNITS_PER_WORD 4 659 660 /* True if natural alignment is used for doubleword types. */ 661 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 662 663 #define DOUBLEWORD_ALIGNMENT 64 664 665 #define PARM_BOUNDARY 32 666 667 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 668 669 #define PREFERRED_STACK_BOUNDARY \ 670 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 671 672 #define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 673 674 /* The lowest bit is used to indicate Thumb-mode functions, so the 675 vbit must go into the delta field of pointers to member 676 functions. */ 677 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 678 679 #define EMPTY_FIELD_BOUNDARY 32 680 681 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 682 683 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 684 685 /* XXX Blah -- this macro is used directly by libobjc. Since it 686 supports no vector modes, cut out the complexity and fall back 687 on BIGGEST_FIELD_ALIGNMENT. */ 688 #ifdef IN_TARGET_LIBS 689 #define BIGGEST_FIELD_ALIGNMENT 64 690 #endif 691 692 /* Make strings word-aligned so strcpy from constants will be faster. */ 693 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 694 695 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 696 ((TREE_CODE (EXP) == STRING_CST \ 697 && !optimize_size \ 698 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 699 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 700 701 /* Align definitions of arrays, unions and structures so that 702 initializations and copies can be made more efficient. This is not 703 ABI-changing, so it only affects places where we can see the 704 definition. Increasing the alignment tends to introduce padding, 705 so don't do this when optimizing for size/conserving stack space. */ 706 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 707 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 708 && (TREE_CODE (EXP) == ARRAY_TYPE \ 709 || TREE_CODE (EXP) == UNION_TYPE \ 710 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 711 712 /* Align global data. */ 713 #define DATA_ALIGNMENT(EXP, ALIGN) \ 714 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 715 716 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 717 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 718 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 719 720 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 721 value set in previous versions of this toolchain was 8, which produces more 722 compact structures. The command line option -mstructure_size_boundary=<n> 723 can be used to change this value. For compatibility with the ARM SDK 724 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 725 0020D) page 2-20 says "Structures are aligned on word boundaries". 726 The AAPCS specifies a value of 8. */ 727 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 728 729 /* This is the value used to initialize arm_structure_size_boundary. If a 730 particular arm target wants to change the default value it should change 731 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 732 for an example of this. */ 733 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 734 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 735 #endif 736 737 /* Nonzero if move instructions will actually fail to work 738 when given unaligned data. */ 739 #define STRICT_ALIGNMENT 1 740 741 /* wchar_t is unsigned under the AAPCS. */ 742 #ifndef WCHAR_TYPE 743 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 744 745 #define WCHAR_TYPE_SIZE BITS_PER_WORD 746 #endif 747 748 /* Sized for fixed-point types. */ 749 750 #define SHORT_FRACT_TYPE_SIZE 8 751 #define FRACT_TYPE_SIZE 16 752 #define LONG_FRACT_TYPE_SIZE 32 753 #define LONG_LONG_FRACT_TYPE_SIZE 64 754 755 #define SHORT_ACCUM_TYPE_SIZE 16 756 #define ACCUM_TYPE_SIZE 32 757 #define LONG_ACCUM_TYPE_SIZE 64 758 #define LONG_LONG_ACCUM_TYPE_SIZE 64 759 760 #define MAX_FIXED_MODE_SIZE 64 761 762 #ifndef SIZE_TYPE 763 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 764 #endif 765 766 #ifndef PTRDIFF_TYPE 767 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 768 #endif 769 770 /* AAPCS requires that structure alignment is affected by bitfields. */ 771 #ifndef PCC_BITFIELD_TYPE_MATTERS 772 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 773 #endif 774 775 /* The maximum size of the sync library functions supported. */ 776 #ifndef MAX_SYNC_LIBFUNC_SIZE 777 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 778 #endif 779 780 781 /* Standard register usage. */ 783 784 /* Register allocation in ARM Procedure Call Standard 785 (S - saved over call). 786 787 r0 * argument word/integer result 788 r1-r3 argument word 789 790 r4-r8 S register variable 791 r9 S (rfp) register variable (real frame pointer) 792 793 r10 F S (sl) stack limit (used by -mapcs-stack-check) 794 r11 F S (fp) argument pointer 795 r12 (ip) temp workspace 796 r13 F S (sp) lower end of current stack frame 797 r14 (lr) link address/workspace 798 r15 F (pc) program counter 799 800 cc This is NOT a real register, but is used internally 801 to represent things that use or set the condition 802 codes. 803 sfp This isn't either. It is used during rtl generation 804 since the offset between the frame pointer and the 805 auto's isn't known until after register allocation. 806 afp Nor this, we only need this because of non-local 807 goto. Without it fp appears to be used and the 808 elimination code won't get rid of sfp. It tracks 809 fp exactly at all times. 810 811 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 812 813 /* s0-s15 VFP scratch (aka d0-d7). 814 s16-s31 S VFP variable (aka d8-d15). 815 vfpcc Not a real register. Represents the VFP condition 816 code flags. */ 817 818 /* The stack backtrace structure is as follows: 819 fp points to here: | save code pointer | [fp] 820 | return link value | [fp, #-4] 821 | return sp value | [fp, #-8] 822 | return fp value | [fp, #-12] 823 [| saved r10 value |] 824 [| saved r9 value |] 825 [| saved r8 value |] 826 [| saved r7 value |] 827 [| saved r6 value |] 828 [| saved r5 value |] 829 [| saved r4 value |] 830 [| saved r3 value |] 831 [| saved r2 value |] 832 [| saved r1 value |] 833 [| saved r0 value |] 834 r0-r3 are not normally saved in a C function. */ 835 836 /* 1 for registers that have pervasive standard uses 837 and are not available for the register allocator. */ 838 #define FIXED_REGISTERS \ 839 { \ 840 /* Core regs. */ \ 841 0,0,0,0,0,0,0,0, \ 842 0,0,0,0,0,1,0,1, \ 843 /* VFP regs. */ \ 844 1,1,1,1,1,1,1,1, \ 845 1,1,1,1,1,1,1,1, \ 846 1,1,1,1,1,1,1,1, \ 847 1,1,1,1,1,1,1,1, \ 848 1,1,1,1,1,1,1,1, \ 849 1,1,1,1,1,1,1,1, \ 850 1,1,1,1,1,1,1,1, \ 851 1,1,1,1,1,1,1,1, \ 852 /* IWMMXT regs. */ \ 853 1,1,1,1,1,1,1,1, \ 854 1,1,1,1,1,1,1,1, \ 855 1,1,1,1, \ 856 /* Specials. */ \ 857 1,1,1,1 \ 858 } 859 860 /* 1 for registers not available across function calls. 861 These must include the FIXED_REGISTERS and also any 862 registers that can be used without being saved. 863 The latter must include the registers where values are returned 864 and the register where structure-value addresses are passed. 865 Aside from that, you can include as many other registers as you like. 866 The CC is not preserved over function calls on the ARM 6, so it is 867 easier to assume this for all. SFP is preserved, since FP is. */ 868 #define CALL_USED_REGISTERS \ 869 { \ 870 /* Core regs. */ \ 871 1,1,1,1,0,0,0,0, \ 872 0,0,0,0,1,1,1,1, \ 873 /* VFP Regs. */ \ 874 1,1,1,1,1,1,1,1, \ 875 1,1,1,1,1,1,1,1, \ 876 1,1,1,1,1,1,1,1, \ 877 1,1,1,1,1,1,1,1, \ 878 1,1,1,1,1,1,1,1, \ 879 1,1,1,1,1,1,1,1, \ 880 1,1,1,1,1,1,1,1, \ 881 1,1,1,1,1,1,1,1, \ 882 /* IWMMXT regs. */ \ 883 1,1,1,1,1,1,1,1, \ 884 1,1,1,1,1,1,1,1, \ 885 1,1,1,1, \ 886 /* Specials. */ \ 887 1,1,1,1 \ 888 } 889 890 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 891 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 892 #endif 893 894 /* These are a couple of extensions to the formats accepted 895 by asm_fprintf: 896 %@ prints out ASM_COMMENT_START 897 %r prints out REGISTER_PREFIX reg_names[arg] */ 898 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 899 case '@': \ 900 fputs (ASM_COMMENT_START, FILE); \ 901 break; \ 902 \ 903 case 'r': \ 904 fputs (REGISTER_PREFIX, FILE); \ 905 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 906 break; 907 908 /* Round X up to the nearest word. */ 909 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 910 911 /* Convert fron bytes to ints. */ 912 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 913 914 /* The number of (integer) registers required to hold a quantity of type MODE. 915 Also used for VFP registers. */ 916 #define ARM_NUM_REGS(MODE) \ 917 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 918 919 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 920 #define ARM_NUM_REGS2(MODE, TYPE) \ 921 ARM_NUM_INTS ((MODE) == BLKmode ? \ 922 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 923 924 /* The number of (integer) argument register available. */ 925 #define NUM_ARG_REGS 4 926 927 /* And similarly for the VFP. */ 928 #define NUM_VFP_ARG_REGS 16 929 930 /* Return the register number of the N'th (integer) argument. */ 931 #define ARG_REGISTER(N) (N - 1) 932 933 /* Specify the registers used for certain standard purposes. 934 The values of these macros are register numbers. */ 935 936 /* The number of the last argument register. */ 937 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 938 939 /* The numbers of the Thumb register ranges. */ 940 #define FIRST_LO_REGNUM 0 941 #define LAST_LO_REGNUM 7 942 #define FIRST_HI_REGNUM 8 943 #define LAST_HI_REGNUM 11 944 945 /* Overridden by config/arm/bpabi.h. */ 946 #ifndef ARM_UNWIND_INFO 947 #define ARM_UNWIND_INFO 0 948 #endif 949 950 /* Overriden by config/arm/netbsd-eabi.h. */ 951 #ifndef ARM_DWARF_UNWIND_TABLES 952 #define ARM_DWARF_UNWIND_TABLES 0 953 #endif 954 955 /* Use r0 and r1 to pass exception handling information. */ 956 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 957 958 /* The register that holds the return address in exception handlers. */ 959 #define ARM_EH_STACKADJ_REGNUM 2 960 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 961 962 #ifndef ARM_TARGET2_DWARF_FORMAT 963 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 964 #endif 965 966 #if ARM_DWARF_UNWIND_TABLES 967 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 968 for 32bit platforms. */ 969 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 970 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 971 : DW_EH_PE_absptr) 972 #else 973 /* ttype entries (the only interesting data references used) 974 use TARGET2 relocations. */ 975 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 976 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 977 : DW_EH_PE_absptr) 978 #endif 979 980 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 981 as an invisible last argument (possible since varargs don't exist in 982 Pascal), so the following is not true. */ 983 #define STATIC_CHAIN_REGNUM 12 984 985 /* Define this to be where the real frame pointer is if it is not possible to 986 work out the offset between the frame pointer and the automatic variables 987 until after register allocation has taken place. FRAME_POINTER_REGNUM 988 should point to a special register that we will make sure is eliminated. 989 990 For the Thumb we have another problem. The TPCS defines the frame pointer 991 as r11, and GCC believes that it is always possible to use the frame pointer 992 as base register for addressing purposes. (See comments in 993 find_reloads_address()). But - the Thumb does not allow high registers, 994 including r11, to be used as base address registers. Hence our problem. 995 996 The solution used here, and in the old thumb port is to use r7 instead of 997 r11 as the hard frame pointer and to have special code to generate 998 backtrace structures on the stack (if required to do so via a command line 999 option) using r11. This is the only 'user visible' use of r11 as a frame 1000 pointer. */ 1001 #define ARM_HARD_FRAME_POINTER_REGNUM 11 1002 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 1003 1004 #define HARD_FRAME_POINTER_REGNUM \ 1005 (TARGET_ARM \ 1006 ? ARM_HARD_FRAME_POINTER_REGNUM \ 1007 : THUMB_HARD_FRAME_POINTER_REGNUM) 1008 1009 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 1010 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 1011 1012 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 1013 1014 /* Register to use for pushing function arguments. */ 1015 #define STACK_POINTER_REGNUM SP_REGNUM 1016 1017 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 1018 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 1019 1020 /* Need to sync with WCGR in iwmmxt.md. */ 1021 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 1022 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 1023 1024 #define IS_IWMMXT_REGNUM(REGNUM) \ 1025 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 1026 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 1027 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 1028 1029 /* Base register for access to local variables of the function. */ 1030 #define FRAME_POINTER_REGNUM 102 1031 1032 /* Base register for access to arguments of the function. */ 1033 #define ARG_POINTER_REGNUM 103 1034 1035 #define FIRST_VFP_REGNUM 16 1036 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 1037 #define LAST_VFP_REGNUM \ 1038 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 1039 1040 #define IS_VFP_REGNUM(REGNUM) \ 1041 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 1042 1043 /* VFP registers are split into two types: those defined by VFP versions < 3 1044 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1045 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1046 in various parts of the backend, we implement as "fake" single-precision 1047 registers (which would be S32-S63, but cannot be used in that way). The 1048 following macros define these ranges of registers. */ 1049 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 1050 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 1051 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 1052 1053 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1054 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1055 1056 /* DFmode values are only valid in even register pairs. */ 1057 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1058 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1059 1060 /* Neon Quad values must start at a multiple of four registers. */ 1061 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1062 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1063 1064 /* Neon structures of vectors must be in even register pairs and there 1065 must be enough registers available. Because of various patterns 1066 requiring quad registers, we require them to start at a multiple of 1067 four. */ 1068 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1069 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1070 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1071 1072 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1073 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1074 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1075 #define FIRST_PSEUDO_REGISTER 104 1076 1077 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1078 1079 /* Value should be nonzero if functions must have frame pointers. 1080 Zero means the frame pointer need not be set up (and parms may be accessed 1081 via the stack pointer) in functions that seem suitable. 1082 If we have to have a frame pointer we might as well make use of it. 1083 APCS says that the frame pointer does not need to be pushed in leaf 1084 functions, or simple tail call functions. */ 1085 1086 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1087 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1088 #endif 1089 1090 /* Return number of consecutive hard regs needed starting at reg REGNO 1091 to hold something of mode MODE. 1092 This is ordinarily the length in words of a value of mode MODE 1093 but can be less for certain modes in special long registers. 1094 1095 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1096 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1097 ((TARGET_32BIT \ 1098 && REGNO > PC_REGNUM \ 1099 && REGNO != FRAME_POINTER_REGNUM \ 1100 && REGNO != ARG_POINTER_REGNUM) \ 1101 && !IS_VFP_REGNUM (REGNO) \ 1102 ? 1 : ARM_NUM_REGS (MODE)) 1103 1104 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1105 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1106 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1107 1108 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1109 1110 #define VALID_IWMMXT_REG_MODE(MODE) \ 1111 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1112 1113 /* Modes valid for Neon D registers. */ 1114 #define VALID_NEON_DREG_MODE(MODE) \ 1115 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1116 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1117 1118 /* Modes valid for Neon Q registers. */ 1119 #define VALID_NEON_QREG_MODE(MODE) \ 1120 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1121 || (MODE) == V4SFmode || (MODE) == V2DImode) 1122 1123 /* Structure modes valid for Neon registers. */ 1124 #define VALID_NEON_STRUCT_MODE(MODE) \ 1125 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1126 || (MODE) == CImode || (MODE) == XImode) 1127 1128 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1129 extern int arm_regs_in_sequence[]; 1130 1131 /* The order in which register should be allocated. It is good to use ip 1132 since no saving is required (though calls clobber it) and it never contains 1133 function parameters. It is quite good to use lr since other calls may 1134 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1135 least likely to contain a function parameter; in addition results are 1136 returned in r0. 1137 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1138 then D8-D15. The reason for doing this is to attempt to reduce register 1139 pressure when both single- and double-precision registers are used in a 1140 function. */ 1141 1142 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1143 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1144 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1145 1146 #define REG_ALLOC_ORDER \ 1147 { \ 1148 /* General registers. */ \ 1149 3, 2, 1, 0, 12, 14, 4, 5, \ 1150 6, 7, 8, 9, 10, 11, \ 1151 /* High VFP registers. */ \ 1152 VREG(32), VREG(33), VREG(34), VREG(35), \ 1153 VREG(36), VREG(37), VREG(38), VREG(39), \ 1154 VREG(40), VREG(41), VREG(42), VREG(43), \ 1155 VREG(44), VREG(45), VREG(46), VREG(47), \ 1156 VREG(48), VREG(49), VREG(50), VREG(51), \ 1157 VREG(52), VREG(53), VREG(54), VREG(55), \ 1158 VREG(56), VREG(57), VREG(58), VREG(59), \ 1159 VREG(60), VREG(61), VREG(62), VREG(63), \ 1160 /* VFP argument registers. */ \ 1161 VREG(15), VREG(14), VREG(13), VREG(12), \ 1162 VREG(11), VREG(10), VREG(9), VREG(8), \ 1163 VREG(7), VREG(6), VREG(5), VREG(4), \ 1164 VREG(3), VREG(2), VREG(1), VREG(0), \ 1165 /* VFP call-saved registers. */ \ 1166 VREG(16), VREG(17), VREG(18), VREG(19), \ 1167 VREG(20), VREG(21), VREG(22), VREG(23), \ 1168 VREG(24), VREG(25), VREG(26), VREG(27), \ 1169 VREG(28), VREG(29), VREG(30), VREG(31), \ 1170 /* IWMMX registers. */ \ 1171 WREG(0), WREG(1), WREG(2), WREG(3), \ 1172 WREG(4), WREG(5), WREG(6), WREG(7), \ 1173 WREG(8), WREG(9), WREG(10), WREG(11), \ 1174 WREG(12), WREG(13), WREG(14), WREG(15), \ 1175 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1176 /* Registers not for general use. */ \ 1177 CC_REGNUM, VFPCC_REGNUM, \ 1178 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1179 SP_REGNUM, PC_REGNUM \ 1180 } 1181 1182 /* Use different register alloc ordering for Thumb. */ 1183 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1184 1185 /* Tell IRA to use the order we define rather than messing it up with its 1186 own cost calculations. */ 1187 #define HONOR_REG_ALLOC_ORDER 1 1188 1189 /* Interrupt functions can only use registers that have already been 1190 saved by the prologue, even if they would normally be 1191 call-clobbered. */ 1192 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1193 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1194 df_regs_ever_live_p (DST)) 1195 1196 /* Register and constant classes. */ 1198 1199 /* Register classes. */ 1200 enum reg_class 1201 { 1202 NO_REGS, 1203 LO_REGS, 1204 STACK_REG, 1205 BASE_REGS, 1206 HI_REGS, 1207 CALLER_SAVE_REGS, 1208 GENERAL_REGS, 1209 CORE_REGS, 1210 VFP_D0_D7_REGS, 1211 VFP_LO_REGS, 1212 VFP_HI_REGS, 1213 VFP_REGS, 1214 IWMMXT_REGS, 1215 IWMMXT_GR_REGS, 1216 CC_REG, 1217 VFPCC_REG, 1218 SFP_REG, 1219 AFP_REG, 1220 ALL_REGS, 1221 LIM_REG_CLASSES 1222 }; 1223 1224 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1225 1226 /* Give names of register classes as strings for dump file. */ 1227 #define REG_CLASS_NAMES \ 1228 { \ 1229 "NO_REGS", \ 1230 "LO_REGS", \ 1231 "STACK_REG", \ 1232 "BASE_REGS", \ 1233 "HI_REGS", \ 1234 "CALLER_SAVE_REGS", \ 1235 "GENERAL_REGS", \ 1236 "CORE_REGS", \ 1237 "VFP_D0_D7_REGS", \ 1238 "VFP_LO_REGS", \ 1239 "VFP_HI_REGS", \ 1240 "VFP_REGS", \ 1241 "IWMMXT_REGS", \ 1242 "IWMMXT_GR_REGS", \ 1243 "CC_REG", \ 1244 "VFPCC_REG", \ 1245 "SFP_REG", \ 1246 "AFP_REG", \ 1247 "ALL_REGS" \ 1248 } 1249 1250 /* Define which registers fit in which classes. 1251 This is an initializer for a vector of HARD_REG_SET 1252 of length N_REG_CLASSES. */ 1253 #define REG_CLASS_CONTENTS \ 1254 { \ 1255 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1256 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1257 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1258 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1259 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1260 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1261 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1262 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1263 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1264 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1265 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1266 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1267 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1268 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1269 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1270 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1271 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1272 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1273 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1274 } 1275 1276 /* Any of the VFP register classes. */ 1277 #define IS_VFP_CLASS(X) \ 1278 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1279 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1280 1281 /* The same information, inverted: 1282 Return the class number of the smallest class containing 1283 reg number REGNO. This could be a conditional expression 1284 or could index an array. */ 1285 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1286 1287 /* In VFPv1, VFP registers could only be accessed in the mode they 1288 were set, so subregs would be invalid there. However, we don't 1289 support VFPv1 at the moment, and the restriction was lifted in 1290 VFPv2. 1291 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1292 VFP registers in little-endian order. We can't describe that accurately to 1293 GCC, so avoid taking subregs of such values. 1294 The only exception is going from a 128-bit to a 64-bit type. In that case 1295 the data layout happens to be consistent for big-endian, so we explicitly allow 1296 that case. */ 1297 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1298 (TARGET_VFP && TARGET_BIG_END \ 1299 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1300 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1301 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1302 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1303 1304 /* The class value for index registers, and the one for base regs. */ 1305 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1306 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1307 1308 /* For the Thumb the high registers cannot be used as base registers 1309 when addressing quantities in QI or HI mode; if we don't know the 1310 mode, then we must be conservative. */ 1311 #define MODE_BASE_REG_CLASS(MODE) \ 1312 (TARGET_32BIT ? CORE_REGS \ 1313 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1314 : LO_REGS) 1315 1316 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1317 instead of BASE_REGS. */ 1318 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1319 1320 /* When this hook returns true for MODE, the compiler allows 1321 registers explicitly used in the rtl to be used as spill registers 1322 but prevents the compiler from extending the lifetime of these 1323 registers. */ 1324 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1325 arm_small_register_classes_for_mode_p 1326 1327 /* Must leave BASE_REGS reloads alone */ 1328 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1329 (lra_in_progress ? NO_REGS \ 1330 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1331 ? ((true_regnum (X) == -1 ? LO_REGS \ 1332 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1333 : NO_REGS)) \ 1334 : NO_REGS)) 1335 1336 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1337 (lra_in_progress ? NO_REGS \ 1338 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1339 ? ((true_regnum (X) == -1 ? LO_REGS \ 1340 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1341 : NO_REGS)) \ 1342 : NO_REGS) 1343 1344 /* Return the register class of a scratch register needed to copy IN into 1345 or out of a register in CLASS in MODE. If it can be done directly, 1346 NO_REGS is returned. */ 1347 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1348 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1349 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1350 && IS_VFP_CLASS (CLASS)) \ 1351 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1352 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1353 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1354 : TARGET_32BIT \ 1355 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1356 ? GENERAL_REGS : NO_REGS) \ 1357 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1358 1359 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1360 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1361 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1362 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1363 && IS_VFP_CLASS (CLASS)) \ 1364 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1365 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1366 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1367 (TARGET_32BIT ? \ 1368 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1369 && CONSTANT_P (X)) \ 1370 ? GENERAL_REGS : \ 1371 (((MODE) == HImode && ! arm_arch4 \ 1372 && (MEM_P (X) \ 1373 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1374 && true_regnum (X) == -1))) \ 1375 ? GENERAL_REGS : NO_REGS) \ 1376 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1377 1378 /* Try a machine-dependent way of reloading an illegitimate address 1379 operand. If we find one, push the reload and jump to WIN. This 1380 macro is used in only one place: `find_reloads_address' in reload.c. 1381 1382 For the ARM, we wish to handle large displacements off a base 1383 register by splitting the addend across a MOV and the mem insn. 1384 This can cut the number of reloads needed. */ 1385 #define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1386 do \ 1387 { \ 1388 if (arm_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND)) \ 1389 goto WIN; \ 1390 } \ 1391 while (0) 1392 1393 /* XXX If an HImode FP+large_offset address is converted to an HImode 1394 SP+large_offset address, then reload won't know how to fix it. It sees 1395 only that SP isn't valid for HImode, and so reloads the SP into an index 1396 register, but the resulting address is still invalid because the offset 1397 is too big. We fix it here instead by reloading the entire address. */ 1398 /* We could probably achieve better results by defining PROMOTE_MODE to help 1399 cope with the variances between the Thumb's signed and unsigned byte and 1400 halfword load instructions. */ 1401 /* ??? This should be safe for thumb2, but we may be able to do better. */ 1402 #define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1403 do { \ 1404 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1405 if (new_x) \ 1406 { \ 1407 X = new_x; \ 1408 goto WIN; \ 1409 } \ 1410 } while (0) 1411 1412 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1413 if (TARGET_ARM) \ 1414 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1415 else \ 1416 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1417 1418 /* Return the maximum number of consecutive registers 1419 needed to represent mode MODE in a register of class CLASS. 1420 ARM regs are UNITS_PER_WORD bits. 1421 FIXME: Is this true for iWMMX? */ 1422 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1423 (ARM_NUM_REGS (MODE)) 1424 1425 /* If defined, gives a class of registers that cannot be used as the 1426 operand of a SUBREG that changes the mode of the object illegally. */ 1427 1428 /* Stack layout; function entry, exit and calling. */ 1430 1431 /* Define this if pushing a word on the stack 1432 makes the stack pointer a smaller address. */ 1433 #define STACK_GROWS_DOWNWARD 1 1434 1435 /* Define this to nonzero if the nominal address of the stack frame 1436 is at the high-address end of the local variables; 1437 that is, each additional local variable allocated 1438 goes at a more negative offset in the frame. */ 1439 #define FRAME_GROWS_DOWNWARD 1 1440 1441 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1442 When present, it is one word in size, and sits at the top of the frame, 1443 between the soft frame pointer and either r7 or r11. 1444 1445 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1446 and only then if some outgoing arguments are passed on the stack. It would 1447 be tempting to also check whether the stack arguments are passed by indirect 1448 calls, but there seems to be no reason in principle why a post-reload pass 1449 couldn't convert a direct call into an indirect one. */ 1450 #define CALLER_INTERWORKING_SLOT_SIZE \ 1451 (TARGET_CALLER_INTERWORKING \ 1452 && crtl->outgoing_args_size != 0 \ 1453 ? UNITS_PER_WORD : 0) 1454 1455 /* Offset within stack frame to start allocating local variables at. 1456 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1457 first local allocated. Otherwise, it is the offset to the BEGINNING 1458 of the first local allocated. */ 1459 #define STARTING_FRAME_OFFSET 0 1460 1461 /* If we generate an insn to push BYTES bytes, 1462 this says how many the stack pointer really advances by. */ 1463 /* The push insns do not do this rounding implicitly. 1464 So don't define this. */ 1465 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1466 1467 /* Define this if the maximum size of all the outgoing args is to be 1468 accumulated and pushed during the prologue. The amount can be 1469 found in the variable crtl->outgoing_args_size. */ 1470 #define ACCUMULATE_OUTGOING_ARGS 1 1471 1472 /* Offset of first parameter from the argument pointer register value. */ 1473 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1474 1475 /* Amount of memory needed for an untyped call to save all possible return 1476 registers. */ 1477 #define APPLY_RESULT_SIZE arm_apply_result_size() 1478 1479 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1480 values must be in memory. On the ARM, they need only do so if larger 1481 than a word, or if they contain elements offset from zero in the struct. */ 1482 #define DEFAULT_PCC_STRUCT_RETURN 0 1483 1484 /* These bits describe the different types of function supported 1485 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1486 normal function and an interworked function, for example. Knowing the 1487 type of a function is important for determining its prologue and 1488 epilogue sequences. 1489 Note value 7 is currently unassigned. Also note that the interrupt 1490 function types all have bit 2 set, so that they can be tested for easily. 1491 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1492 machine_function structure is initialized (to zero) func_type will 1493 default to unknown. This will force the first use of arm_current_func_type 1494 to call arm_compute_func_type. */ 1495 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1496 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1497 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1498 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1499 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1500 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1501 1502 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1503 1504 /* In addition functions can have several type modifiers, 1505 outlined by these bit masks: */ 1506 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1507 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1508 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1509 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1510 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1511 1512 /* Some macros to test these flags. */ 1513 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1514 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1515 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1516 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1517 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1518 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1519 1520 1521 /* Structure used to hold the function stack frame layout. Offsets are 1522 relative to the stack pointer on function entry. Positive offsets are 1523 in the direction of stack growth. 1524 Only soft_frame is used in thumb mode. */ 1525 1526 typedef struct GTY(()) arm_stack_offsets 1527 { 1528 int saved_args; /* ARG_POINTER_REGNUM. */ 1529 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1530 int saved_regs; 1531 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1532 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1533 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1534 unsigned int saved_regs_mask; 1535 } 1536 arm_stack_offsets; 1537 1538 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1539 /* A C structure for machine-specific, per-function data. 1540 This is added to the cfun structure. */ 1541 typedef struct GTY(()) machine_function 1542 { 1543 /* Additional stack adjustment in __builtin_eh_throw. */ 1544 rtx eh_epilogue_sp_ofs; 1545 /* Records if LR has to be saved for far jumps. */ 1546 int far_jump_used; 1547 /* Records if ARG_POINTER was ever live. */ 1548 int arg_pointer_live; 1549 /* Records if the save of LR has been eliminated. */ 1550 int lr_save_eliminated; 1551 /* The size of the stack frame. Only valid after reload. */ 1552 arm_stack_offsets stack_offsets; 1553 /* Records the type of the current function. */ 1554 unsigned long func_type; 1555 /* Record if the function has a variable argument list. */ 1556 int uses_anonymous_args; 1557 /* Records if sibcalls are blocked because an argument 1558 register is needed to preserve stack alignment. */ 1559 int sibcall_blocked; 1560 /* The PIC register for this function. This might be a pseudo. */ 1561 rtx pic_reg; 1562 /* Labels for per-function Thumb call-via stubs. One per potential calling 1563 register. We can never call via LR or PC. We can call via SP if a 1564 trampoline happens to be on the top of the stack. */ 1565 rtx call_via[14]; 1566 /* Set to 1 when a return insn is output, this means that the epilogue 1567 is not needed. */ 1568 int return_used_this_function; 1569 /* When outputting Thumb-1 code, record the last insn that provides 1570 information about condition codes, and the comparison operands. */ 1571 rtx thumb1_cc_insn; 1572 rtx thumb1_cc_op0; 1573 rtx thumb1_cc_op1; 1574 /* Also record the CC mode that is supported. */ 1575 machine_mode thumb1_cc_mode; 1576 /* Set to 1 after arm_reorg has started. */ 1577 int after_arm_reorg; 1578 } 1579 machine_function; 1580 #endif 1581 1582 /* As in the machine_function, a global set of call-via labels, for code 1583 that is in text_section. */ 1584 extern GTY(()) rtx thumb_call_via_label[14]; 1585 1586 /* The number of potential ways of assigning to a co-processor. */ 1587 #define ARM_NUM_COPROC_SLOTS 1 1588 1589 /* Enumeration of procedure calling standard variants. We don't really 1590 support all of these yet. */ 1591 enum arm_pcs 1592 { 1593 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1594 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1595 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1596 /* This must be the last AAPCS variant. */ 1597 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1598 ARM_PCS_ATPCS, /* ATPCS. */ 1599 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1600 ARM_PCS_UNKNOWN 1601 }; 1602 1603 /* Default procedure calling standard of current compilation unit. */ 1604 extern enum arm_pcs arm_pcs_default; 1605 1606 #if !defined (USED_FOR_TARGET) 1607 /* A C type for declaring a variable that is used as the first argument of 1608 `FUNCTION_ARG' and other related values. */ 1609 typedef struct 1610 { 1611 /* This is the number of registers of arguments scanned so far. */ 1612 int nregs; 1613 /* This is the number of iWMMXt register arguments scanned so far. */ 1614 int iwmmxt_nregs; 1615 int named_count; 1616 int nargs; 1617 /* Which procedure call variant to use for this call. */ 1618 enum arm_pcs pcs_variant; 1619 1620 /* AAPCS related state tracking. */ 1621 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1622 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1623 this argument, or -1 if using core 1624 registers. */ 1625 int aapcs_ncrn; 1626 int aapcs_next_ncrn; 1627 rtx aapcs_reg; /* Register assigned to this argument. */ 1628 int aapcs_partial; /* How many bytes are passed in regs (if 1629 split between core regs and stack. 1630 Zero otherwise. */ 1631 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1632 int can_split; /* Argument can be split between core regs 1633 and the stack. */ 1634 /* Private data for tracking VFP register allocation */ 1635 unsigned aapcs_vfp_regs_free; 1636 unsigned aapcs_vfp_reg_alloc; 1637 int aapcs_vfp_rcount; 1638 MACHMODE aapcs_vfp_rmode; 1639 } CUMULATIVE_ARGS; 1640 #endif 1641 1642 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1643 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1644 1645 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1646 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1647 1648 /* For AAPCS, padding should never be below the argument. For other ABIs, 1649 * mimic the default. */ 1650 #define PAD_VARARGS_DOWN \ 1651 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1652 1653 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1654 for a call to a function whose data type is FNTYPE. 1655 For a library call, FNTYPE is 0. 1656 On the ARM, the offset starts at 0. */ 1657 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1658 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1659 1660 /* 1 if N is a possible register number for function argument passing. 1661 On the ARM, r0-r3 are used to pass args. */ 1662 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1663 (IN_RANGE ((REGNO), 0, 3) \ 1664 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1665 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1666 || (TARGET_IWMMXT_ABI \ 1667 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1668 1669 1670 /* If your target environment doesn't prefix user functions with an 1672 underscore, you may wish to re-define this to prevent any conflicts. */ 1673 #ifndef ARM_MCOUNT_NAME 1674 #define ARM_MCOUNT_NAME "*mcount" 1675 #endif 1676 1677 /* Call the function profiler with a given profile label. The Acorn 1678 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1679 On the ARM the full profile code will look like: 1680 .data 1681 LP1 1682 .word 0 1683 .text 1684 mov ip, lr 1685 bl mcount 1686 .word LP1 1687 1688 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1689 will output the .text section. 1690 1691 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1692 ``prof'' doesn't seem to mind about this! 1693 1694 Note - this version of the code is designed to work in both ARM and 1695 Thumb modes. */ 1696 #ifndef ARM_FUNCTION_PROFILER 1697 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1698 { \ 1699 char temp[20]; \ 1700 rtx sym; \ 1701 \ 1702 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1703 IP_REGNUM, LR_REGNUM); \ 1704 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1705 fputc ('\n', STREAM); \ 1706 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1707 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1708 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1709 } 1710 #endif 1711 1712 #ifdef THUMB_FUNCTION_PROFILER 1713 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1714 if (TARGET_ARM) \ 1715 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1716 else \ 1717 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1718 #else 1719 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1720 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1721 #endif 1722 1723 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1724 the stack pointer does not matter. The value is tested only in 1725 functions that have frame pointers. 1726 No definition is equivalent to always zero. 1727 1728 On the ARM, the function epilogue recovers the stack pointer from the 1729 frame. */ 1730 #define EXIT_IGNORE_STACK 1 1731 1732 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1733 1734 /* Determine if the epilogue should be output as RTL. 1735 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1736 #define USE_RETURN_INSN(ISCOND) \ 1737 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1738 1739 /* Definitions for register eliminations. 1740 1741 This is an array of structures. Each structure initializes one pair 1742 of eliminable registers. The "from" register number is given first, 1743 followed by "to". Eliminations of the same "from" register are listed 1744 in order of preference. 1745 1746 We have two registers that can be eliminated on the ARM. First, the 1747 arg pointer register can often be eliminated in favor of the stack 1748 pointer register. Secondly, the pseudo frame pointer register can always 1749 be eliminated; it is replaced with either the stack or the real frame 1750 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1751 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1752 1753 #define ELIMINABLE_REGS \ 1754 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1755 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1756 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1757 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1758 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1759 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1760 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1761 1762 /* Define the offset between two registers, one to be eliminated, and the 1763 other its replacement, at the start of a routine. */ 1764 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1765 if (TARGET_ARM) \ 1766 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1767 else \ 1768 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1769 1770 /* Special case handling of the location of arguments passed on the stack. */ 1771 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1772 1773 /* Initialize data used by insn expanders. This is called from insn_emit, 1774 once for every function before code is generated. */ 1775 #define INIT_EXPANDERS arm_init_expanders () 1776 1777 /* Length in units of the trampoline for entering a nested function. */ 1778 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1779 1780 /* Alignment required for a trampoline in bits. */ 1781 #define TRAMPOLINE_ALIGNMENT 32 1782 1783 /* Addressing modes, and classification of registers for them. */ 1785 #define HAVE_POST_INCREMENT 1 1786 #define HAVE_PRE_INCREMENT TARGET_32BIT 1787 #define HAVE_POST_DECREMENT TARGET_32BIT 1788 #define HAVE_PRE_DECREMENT TARGET_32BIT 1789 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1790 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1791 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1792 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1793 1794 enum arm_auto_incmodes 1795 { 1796 ARM_POST_INC, 1797 ARM_PRE_INC, 1798 ARM_POST_DEC, 1799 ARM_PRE_DEC 1800 }; 1801 1802 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1803 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1804 #define USE_LOAD_POST_INCREMENT(mode) \ 1805 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1806 #define USE_LOAD_PRE_INCREMENT(mode) \ 1807 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1808 #define USE_LOAD_POST_DECREMENT(mode) \ 1809 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1810 #define USE_LOAD_PRE_DECREMENT(mode) \ 1811 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1812 1813 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1814 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1815 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1816 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1817 1818 /* Macros to check register numbers against specific register classes. */ 1819 1820 /* These assume that REGNO is a hard or pseudo reg number. 1821 They give nonzero only if REGNO is a hard reg of the suitable class 1822 or a pseudo reg currently allocated to a suitable hard reg. 1823 Since they use reg_renumber, they are safe only once reg_renumber 1824 has been allocated, which happens in reginfo.c during register 1825 allocation. */ 1826 #define TEST_REGNO(R, TEST, VALUE) \ 1827 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1828 1829 /* Don't allow the pc to be used. */ 1830 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1831 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1832 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1833 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1834 1835 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1836 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1837 || (GET_MODE_SIZE (MODE) >= 4 \ 1838 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1839 1840 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1841 (TARGET_THUMB1 \ 1842 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1843 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1844 1845 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1846 For Thumb, we can not use SP + reg, so reject SP. */ 1847 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1848 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1849 1850 /* For ARM code, we don't care about the mode, but for Thumb, the index 1851 must be suitable for use in a QImode load. */ 1852 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1853 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1854 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1855 1856 /* Maximum number of registers that can appear in a valid memory address. 1857 Shifts in addresses can't be by a register. */ 1858 #define MAX_REGS_PER_ADDRESS 2 1859 1860 /* Recognize any constant value that is a valid address. */ 1861 /* XXX We can address any constant, eventually... */ 1862 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1863 #define CONSTANT_ADDRESS_P(X) \ 1864 (GET_CODE (X) == SYMBOL_REF \ 1865 && (CONSTANT_POOL_ADDRESS_P (X) \ 1866 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1867 1868 /* True if SYMBOL + OFFSET constants must refer to something within 1869 SYMBOL's section. */ 1870 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1871 1872 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1873 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1874 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1875 #endif 1876 1877 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1878 #define SUBTARGET_NAME_ENCODING_LENGTHS 1879 #endif 1880 1881 /* This is a C fragment for the inside of a switch statement. 1882 Each case label should return the number of characters to 1883 be stripped from the start of a function's name, if that 1884 name starts with the indicated character. */ 1885 #define ARM_NAME_ENCODING_LENGTHS \ 1886 case '*': return 1; \ 1887 SUBTARGET_NAME_ENCODING_LENGTHS 1888 1889 /* This is how to output a reference to a user-level label named NAME. 1890 `assemble_name' uses this. */ 1891 #undef ASM_OUTPUT_LABELREF 1892 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1893 arm_asm_output_labelref (FILE, NAME) 1894 1895 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1896 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1897 if (TARGET_THUMB2) \ 1898 thumb2_asm_output_opcode (STREAM); 1899 1900 /* The EABI specifies that constructors should go in .init_array. 1901 Other targets use .ctors for compatibility. */ 1902 #ifndef ARM_EABI_CTORS_SECTION_OP 1903 #define ARM_EABI_CTORS_SECTION_OP \ 1904 "\t.section\t.init_array,\"aw\",%init_array" 1905 #endif 1906 #ifndef ARM_EABI_DTORS_SECTION_OP 1907 #define ARM_EABI_DTORS_SECTION_OP \ 1908 "\t.section\t.fini_array,\"aw\",%fini_array" 1909 #endif 1910 #define ARM_CTORS_SECTION_OP \ 1911 "\t.section\t.ctors,\"aw\",%progbits" 1912 #define ARM_DTORS_SECTION_OP \ 1913 "\t.section\t.dtors,\"aw\",%progbits" 1914 1915 /* Define CTORS_SECTION_ASM_OP. */ 1916 #undef CTORS_SECTION_ASM_OP 1917 #undef DTORS_SECTION_ASM_OP 1918 #ifndef IN_LIBGCC2 1919 # define CTORS_SECTION_ASM_OP \ 1920 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1921 # define DTORS_SECTION_ASM_OP \ 1922 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1923 #else /* !defined (IN_LIBGCC2) */ 1924 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1925 so we cannot use the definition above. */ 1926 # ifdef __ARM_EABI__ 1927 /* The .ctors section is not part of the EABI, so we do not define 1928 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1929 from trying to use it. We do define it when doing normal 1930 compilation, as .init_array can be used instead of .ctors. */ 1931 /* There is no need to emit begin or end markers when using 1932 init_array; the dynamic linker will compute the size of the 1933 array itself based on special symbols created by the static 1934 linker. However, we do need to arrange to set up 1935 exception-handling here. */ 1936 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1937 # define CTOR_LIST_END /* empty */ 1938 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1939 # define DTOR_LIST_END /* empty */ 1940 # else /* !defined (__ARM_EABI__) */ 1941 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1942 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1943 # endif /* !defined (__ARM_EABI__) */ 1944 #endif /* !defined (IN_LIBCC2) */ 1945 1946 /* True if the operating system can merge entities with vague linkage 1947 (e.g., symbols in COMDAT group) during dynamic linking. */ 1948 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1949 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1950 #endif 1951 1952 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1953 1954 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1955 and check its validity for a certain class. 1956 We have two alternate definitions for each of them. 1957 The usual definition accepts all pseudo regs; the other rejects 1958 them unless they have been allocated suitable hard regs. 1959 The symbol REG_OK_STRICT causes the latter definition to be used. 1960 Thumb-2 has the same restrictions as arm. */ 1961 #ifndef REG_OK_STRICT 1962 1963 #define ARM_REG_OK_FOR_BASE_P(X) \ 1964 (REGNO (X) <= LAST_ARM_REGNUM \ 1965 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1966 || REGNO (X) == FRAME_POINTER_REGNUM \ 1967 || REGNO (X) == ARG_POINTER_REGNUM) 1968 1969 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1970 ((REGNO (X) <= LAST_ARM_REGNUM \ 1971 && REGNO (X) != STACK_POINTER_REGNUM) \ 1972 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1973 || REGNO (X) == FRAME_POINTER_REGNUM \ 1974 || REGNO (X) == ARG_POINTER_REGNUM) 1975 1976 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1977 (REGNO (X) <= LAST_LO_REGNUM \ 1978 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1979 || (GET_MODE_SIZE (MODE) >= 4 \ 1980 && (REGNO (X) == STACK_POINTER_REGNUM \ 1981 || (X) == hard_frame_pointer_rtx \ 1982 || (X) == arg_pointer_rtx))) 1983 1984 #define REG_STRICT_P 0 1985 1986 #else /* REG_OK_STRICT */ 1987 1988 #define ARM_REG_OK_FOR_BASE_P(X) \ 1989 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1990 1991 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1992 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1993 1994 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1995 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1996 1997 #define REG_STRICT_P 1 1998 1999 #endif /* REG_OK_STRICT */ 2000 2001 /* Now define some helpers in terms of the above. */ 2002 2003 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2004 (TARGET_THUMB1 \ 2005 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2006 : ARM_REG_OK_FOR_BASE_P (X)) 2007 2008 /* For 16-bit Thumb, a valid index register is anything that can be used in 2009 a byte load instruction. */ 2010 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2011 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2012 2013 /* Nonzero if X is a hard reg that can be used as an index 2014 or if it is a pseudo reg. On the Thumb, the stack pointer 2015 is not suitable. */ 2016 #define REG_OK_FOR_INDEX_P(X) \ 2017 (TARGET_THUMB1 \ 2018 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2019 : ARM_REG_OK_FOR_INDEX_P (X)) 2020 2021 /* Nonzero if X can be the base register in a reg+reg addressing mode. 2022 For Thumb, we can not use SP + reg, so reject SP. */ 2023 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2024 REG_OK_FOR_INDEX_P (X) 2025 2026 #define ARM_BASE_REGISTER_RTX_P(X) \ 2028 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 2029 2030 #define ARM_INDEX_REGISTER_RTX_P(X) \ 2031 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 2032 2033 /* Specify the machine mode that this machine uses 2035 for the index in the tablejump instruction. */ 2036 #define CASE_VECTOR_MODE Pmode 2037 2038 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2039 || (TARGET_THUMB1 \ 2040 && (optimize_size || flag_pic))) 2041 2042 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2043 (TARGET_THUMB1 \ 2044 ? (min >= 0 && max < 512 \ 2045 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2046 : min >= -256 && max < 256 \ 2047 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2048 : min >= 0 && max < 8192 \ 2049 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2050 : min >= -4096 && max < 4096 \ 2051 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2052 : SImode) \ 2053 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 2054 : (max >= 0x200) ? HImode \ 2055 : QImode)) 2056 2057 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 2058 unsigned is probably best, but may break some code. */ 2059 #ifndef DEFAULT_SIGNED_CHAR 2060 #define DEFAULT_SIGNED_CHAR 0 2061 #endif 2062 2063 /* Max number of bytes we can move from memory to memory 2064 in one reasonably fast instruction. */ 2065 #define MOVE_MAX 4 2066 2067 #undef MOVE_RATIO 2068 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2069 2070 /* Define if operations between registers always perform the operation 2071 on the full register even if a narrower mode is specified. */ 2072 #define WORD_REGISTER_OPERATIONS 2073 2074 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2075 will either zero-extend or sign-extend. The value of this macro should 2076 be the code that says which one of the two operations is implicitly 2077 done, UNKNOWN if none. */ 2078 #define LOAD_EXTEND_OP(MODE) \ 2079 (TARGET_THUMB ? ZERO_EXTEND : \ 2080 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2081 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2082 2083 /* Nonzero if access to memory by bytes is slow and undesirable. */ 2084 #define SLOW_BYTE_ACCESS 0 2085 2086 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2087 2088 /* Immediate shift counts are truncated by the output routines (or was it 2089 the assembler?). Shift counts in a register are truncated by ARM. Note 2090 that the native compiler puts too large (> 32) immediate shift counts 2091 into a register and shifts by the register, letting the ARM decide what 2092 to do instead of doing that itself. */ 2093 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2094 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2095 On the arm, Y in a register is used modulo 256 for the shift. Only for 2096 rotates is modulo 32 used. */ 2097 /* #define SHIFT_COUNT_TRUNCATED 1 */ 2098 2099 /* All integers have the same format so truncation is easy. */ 2100 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2101 2102 /* Calling from registers is a massive pain. */ 2103 #define NO_FUNCTION_CSE 1 2104 2105 /* The machine modes of pointers and functions */ 2106 #define Pmode SImode 2107 #define FUNCTION_MODE Pmode 2108 2109 #define ARM_FRAME_RTX(X) \ 2110 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2111 || (X) == arg_pointer_rtx) 2112 2113 /* Try to generate sequences that don't involve branches, we can then use 2114 conditional instructions. */ 2115 #define BRANCH_COST(speed_p, predictable_p) \ 2116 (current_tune->branch_cost (speed_p, predictable_p)) 2117 2118 /* False if short circuit operation is preferred. */ 2119 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2120 ((optimize_size) \ 2121 ? (TARGET_THUMB ? false : true) \ 2122 : (current_tune->logical_op_non_short_circuit[TARGET_ARM])) 2123 2124 2125 /* Position Independent Code. */ 2127 /* We decide which register to use based on the compilation options and 2128 the assembler in use; this is more general than the APCS restriction of 2129 using sb (r9) all the time. */ 2130 extern unsigned arm_pic_register; 2131 2132 /* The register number of the register used to address a table of static 2133 data addresses in memory. */ 2134 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2135 2136 /* We can't directly access anything that contains a symbol, 2137 nor can we indirect via the constant pool. One exception is 2138 UNSPEC_TLS, which is always PIC. */ 2139 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2140 (!(symbol_mentioned_p (X) \ 2141 || label_mentioned_p (X) \ 2142 || (GET_CODE (X) == SYMBOL_REF \ 2143 && CONSTANT_POOL_ADDRESS_P (X) \ 2144 && (symbol_mentioned_p (get_pool_constant (X)) \ 2145 || label_mentioned_p (get_pool_constant (X))))) \ 2146 || tls_mentioned_p (X)) 2147 2148 /* We need to know when we are making a constant pool; this determines 2149 whether data needs to be in the GOT or can be referenced via a GOT 2150 offset. */ 2151 extern int making_const_table; 2152 2153 /* Handle pragmas for compatibility with Intel's compilers. */ 2155 /* Also abuse this to register additional C specific EABI attributes. */ 2156 #define REGISTER_TARGET_PRAGMAS() do { \ 2157 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2158 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2159 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2160 arm_lang_object_attributes_init(); \ 2161 } while (0) 2162 2163 /* Condition code information. */ 2164 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2165 return the mode to be used for the comparison. */ 2166 2167 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2168 2169 #define REVERSIBLE_CC_MODE(MODE) 1 2170 2171 #define REVERSE_CONDITION(CODE,MODE) \ 2172 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2173 ? reverse_condition_maybe_unordered (code) \ 2174 : reverse_condition (code)) 2175 2176 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2177 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2178 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2179 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2180 2181 #define CC_STATUS_INIT \ 2183 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2184 2185 #undef ASM_APP_ON 2186 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2187 "\t.syntax divided\n") 2188 2189 #undef ASM_APP_OFF 2190 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax divided\n" : \ 2191 "\t.thumb\n\t.syntax unified\n") 2192 2193 /* Output a push or a pop instruction (only used when profiling). 2194 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2195 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2196 that r7 isn't used by the function profiler, so we can use it as a 2197 scratch reg. WARNING: This isn't safe in the general case! It may be 2198 sensitive to future changes in final.c:profile_function. */ 2199 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2200 do \ 2201 { \ 2202 if (TARGET_ARM) \ 2203 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2204 STACK_POINTER_REGNUM, REGNO); \ 2205 else if (TARGET_THUMB1 \ 2206 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2207 { \ 2208 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2209 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2210 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2211 } \ 2212 else \ 2213 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2214 } while (0) 2215 2216 2217 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2218 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2219 do \ 2220 { \ 2221 if (TARGET_ARM) \ 2222 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2223 STACK_POINTER_REGNUM, REGNO); \ 2224 else if (TARGET_THUMB1 \ 2225 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2226 { \ 2227 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2228 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2229 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2230 } \ 2231 else \ 2232 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2233 } while (0) 2234 2235 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2236 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2237 2238 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2239 default alignment from elfos.h. */ 2240 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2241 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2242 2243 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2244 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2245 ? 1 : 0) 2246 2247 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2248 do \ 2249 { \ 2250 if (TARGET_THUMB) \ 2251 { \ 2252 if (is_called_in_ARM_mode (DECL) \ 2253 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2254 && cfun->is_thunk)) \ 2255 fprintf (STREAM, "\t.code 32\n") ; \ 2256 else if (TARGET_THUMB1) \ 2257 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2258 else \ 2259 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2260 } \ 2261 if (TARGET_POKE_FUNCTION_NAME) \ 2262 arm_poke_function_name (STREAM, (const char *) NAME); \ 2263 } \ 2264 while (0) 2265 2266 /* For aliases of functions we use .thumb_set instead. */ 2267 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2268 do \ 2269 { \ 2270 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2271 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2272 \ 2273 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2274 { \ 2275 fprintf (FILE, "\t.thumb_set "); \ 2276 assemble_name (FILE, LABEL1); \ 2277 fprintf (FILE, ","); \ 2278 assemble_name (FILE, LABEL2); \ 2279 fprintf (FILE, "\n"); \ 2280 } \ 2281 else \ 2282 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2283 } \ 2284 while (0) 2285 2286 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2287 /* To support -falign-* switches we need to use .p2align so 2288 that alignment directives in code sections will be padded 2289 with no-op instructions, rather than zeroes. */ 2290 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2291 if ((LOG) != 0) \ 2292 { \ 2293 if ((MAX_SKIP) == 0) \ 2294 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2295 else \ 2296 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2297 (int) (LOG), (int) (MAX_SKIP)); \ 2298 } 2299 #endif 2300 2301 /* Add two bytes to the length of conditionally executed Thumb-2 2303 instructions for the IT instruction. */ 2304 #define ADJUST_INSN_LENGTH(insn, length) \ 2305 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2306 length += 2; 2307 2308 /* Only perform branch elimination (by making instructions conditional) if 2309 we're optimizing. For Thumb-2 check if any IT instructions need 2310 outputting. */ 2311 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2312 if (TARGET_ARM && optimize) \ 2313 arm_final_prescan_insn (INSN); \ 2314 else if (TARGET_THUMB2) \ 2315 thumb2_final_prescan_insn (INSN); \ 2316 else if (TARGET_THUMB1) \ 2317 thumb1_final_prescan_insn (INSN) 2318 2319 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2320 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2321 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2322 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2323 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2324 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2325 : 0)))) 2326 2327 /* A C expression whose value is RTL representing the value of the return 2328 address for the frame COUNT steps up from the current frame. */ 2329 2330 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2331 arm_return_addr (COUNT, FRAME) 2332 2333 /* Mask of the bits in the PC that contain the real return address 2334 when running in 26-bit mode. */ 2335 #define RETURN_ADDR_MASK26 (0x03fffffc) 2336 2337 /* Pick up the return address upon entry to a procedure. Used for 2338 dwarf2 unwind information. This also enables the table driven 2339 mechanism. */ 2340 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2341 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2342 2343 /* Used to mask out junk bits from the return address, such as 2344 processor state, interrupt status, condition codes and the like. */ 2345 #define MASK_RETURN_ADDR \ 2346 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2347 in 26 bit mode, the condition codes must be masked out of the \ 2348 return address. This does not apply to ARM6 and later processors \ 2349 when running in 32 bit mode. */ \ 2350 ((arm_arch4 || TARGET_THUMB) \ 2351 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2352 : arm_gen_return_addr_mask ()) 2353 2354 2355 /* Do not emit .note.GNU-stack by default. */ 2357 #ifndef NEED_INDICATE_EXEC_STACK 2358 #define NEED_INDICATE_EXEC_STACK 0 2359 #endif 2360 2361 #define TARGET_ARM_ARCH \ 2362 (arm_base_arch) \ 2363 2364 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2365 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2366 2367 /* The highest Thumb instruction set version supported by the chip. */ 2368 #define TARGET_ARM_ARCH_ISA_THUMB \ 2369 (arm_arch_thumb2 ? 2 \ 2370 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2371 2372 /* Expands to an upper-case char of the target's architectural 2373 profile. */ 2374 #define TARGET_ARM_ARCH_PROFILE \ 2375 (!arm_arch_notm \ 2376 ? 'M' \ 2377 : (arm_arch7 \ 2378 ? (strlen (arm_arch_name) >=3 \ 2379 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2380 : 0) \ 2381 : 0)) 2382 2383 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2384 Bit 0 for bytes, up to bit 3 for double-words. */ 2385 #define TARGET_ARM_FEATURE_LDREX \ 2386 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2387 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2388 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2389 2390 /* Set as a bit mask indicating the available widths of hardware floating 2391 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2392 32-bit support, bit 3 indicates 64-bit support. */ 2393 #define TARGET_ARM_FP \ 2394 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2395 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2396 : 0) 2397 2398 2399 /* Set as a bit mask indicating the available widths of floating point 2400 types for hardware NEON floating point. This is the same as 2401 TARGET_ARM_FP without the 64-bit bit set. */ 2402 #define TARGET_NEON_FP \ 2403 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2404 : 0) 2405 2406 /* The maximum number of parallel loads or stores we support in an ldm/stm 2407 instruction. */ 2408 #define MAX_LDM_STM_OPS 4 2409 2410 #define BIG_LITTLE_SPEC \ 2411 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2412 2413 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2414 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2415 { "rewrite_mcpu", arm_rewrite_mcpu }, 2416 2417 #define ASM_CPU_SPEC \ 2418 " %{mcpu=generic-*:-march=%*;" \ 2419 " :%{march=*:-march=%*}}" \ 2420 BIG_LITTLE_SPEC 2421 2422 /* -mcpu=native handling only makes sense with compiler running on 2423 an ARM chip. */ 2424 #if defined(__arm__) && defined(__linux__) 2425 extern const char *host_detect_local_cpu (int argc, const char **argv); 2426 # define EXTRA_SPEC_FUNCTIONS \ 2427 { "local_cpu_detect", host_detect_local_cpu }, \ 2428 BIG_LITTLE_CPU_SPEC_FUNCTIONS 2429 2430 # define MCPU_MTUNE_NATIVE_SPECS \ 2431 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2432 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2433 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2434 #else 2435 # define MCPU_MTUNE_NATIVE_SPECS "" 2436 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 2437 #endif 2438 2439 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2440 #define TARGET_SUPPORTS_WIDE_INT 1 2441 #endif /* ! GCC_ARM_H */ 2442
Indexes created Wed Apr 15 00:22:22 UTC 2026