arm.h revision 1.1.1.6
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2016 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 #include "config/arm/arm-opts.h" 51 52 enum target_cpus 53 { 54 #define ARM_CORE(NAME, INTERNAL_IDENT, IDENT, ARCH, FLAGS, COSTS) \ 55 TARGET_CPU_##INTERNAL_IDENT, 56 #include "arm-cores.def" 57 #undef ARM_CORE 58 TARGET_CPU_generic 59 }; 60 61 /* The processor for which instructions should be scheduled. */ 62 extern enum processor_type arm_tune; 63 64 typedef enum arm_cond_code 65 { 66 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 67 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 68 } 69 arm_cc; 70 71 extern arm_cc arm_current_cc; 72 73 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 74 75 /* The maximum number of instructions that is beneficial to 76 conditionally execute. */ 77 #undef MAX_CONDITIONAL_EXECUTE 78 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 79 80 extern int arm_target_label; 81 extern int arm_ccfsm_state; 82 extern GTY(()) rtx arm_target_insn; 83 /* The label of the current constant pool. */ 84 extern rtx pool_vector_label; 85 /* Set to 1 when a return insn is output, this means that the epilogue 86 is not needed. */ 87 extern int return_used_this_function; 88 /* Callback to output language specific object attributes. */ 89 extern void (*arm_lang_output_object_attributes_hook)(void); 90 91 /* Just in case configure has failed to define anything. */ 93 #ifndef TARGET_CPU_DEFAULT 94 #define TARGET_CPU_DEFAULT TARGET_CPU_generic 95 #endif 96 97 98 #undef CPP_SPEC 99 #define CPP_SPEC "%(subtarget_cpp_spec) \ 100 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 101 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 102 %{mbig-endian:%{mlittle-endian: \ 103 %e-mbig-endian and -mlittle-endian may not be used together}}" 104 105 #ifndef CC1_SPEC 106 #define CC1_SPEC "" 107 #endif 108 109 /* This macro defines names of additional specifications to put in the specs 110 that can be used in various specifications like CC1_SPEC. Its definition 111 is an initializer with a subgrouping for each command option. 112 113 Each subgrouping contains a string constant, that defines the 114 specification name, and a string constant that used by the GCC driver 115 program. 116 117 Do not define this macro if it does not need to do anything. */ 118 #define EXTRA_SPECS \ 119 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 120 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 121 SUBTARGET_EXTRA_SPECS 122 123 #ifndef SUBTARGET_EXTRA_SPECS 124 #define SUBTARGET_EXTRA_SPECS 125 #endif 126 127 #ifndef SUBTARGET_CPP_SPEC 128 #define SUBTARGET_CPP_SPEC "" 129 #endif 130 131 /* Tree Target Specification. */ 133 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 134 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 135 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 136 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 137 138 /* Run-time Target Specification. */ 139 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 140 /* Use hardware floating point instructions. */ 141 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 142 /* Use hardware floating point calling convention. */ 143 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 144 #define TARGET_VFP (TARGET_FPU_MODEL == ARM_FP_MODEL_VFP) 145 #define TARGET_IWMMXT (arm_arch_iwmmxt) 146 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 147 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 148 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 149 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 150 #define TARGET_ARM (! TARGET_THUMB) 151 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 152 #define TARGET_BACKTRACE (leaf_function_p () \ 153 ? TARGET_TPCS_LEAF_FRAME \ 154 : TARGET_TPCS_FRAME) 155 #define TARGET_AAPCS_BASED \ 156 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 157 158 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 159 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 160 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 161 162 /* Only 16-bit thumb code. */ 163 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 164 /* Arm or Thumb-2 32-bit code. */ 165 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 166 /* 32-bit Thumb-2 code. */ 167 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 168 /* Thumb-1 only. */ 169 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 170 171 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 172 && !TARGET_THUMB1) 173 174 #define TARGET_CRC32 (arm_arch_crc) 175 176 /* The following two macros concern the ability to execute coprocessor 177 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 178 only ever tested when we know we are generating for VFP hardware; we need 179 to be more careful with TARGET_NEON as noted below. */ 180 181 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 182 #define TARGET_VFPD32 (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_D32) 183 184 /* FPU supports VFPv3 instructions. */ 185 #define TARGET_VFP3 (TARGET_VFP && TARGET_FPU_REV >= 3) 186 187 /* FPU supports FPv5 instructions. */ 188 #define TARGET_VFP5 (TARGET_VFP && TARGET_FPU_REV >= 5) 189 190 /* FPU only supports VFP single-precision instructions. */ 191 #define TARGET_VFP_SINGLE (TARGET_VFP && TARGET_FPU_REGS == VFP_REG_SINGLE) 192 193 /* FPU supports VFP double-precision instructions. */ 194 #define TARGET_VFP_DOUBLE (TARGET_VFP && TARGET_FPU_REGS != VFP_REG_SINGLE) 195 196 /* FPU supports half-precision floating-point with NEON element load/store. */ 197 #define TARGET_NEON_FP16 \ 198 (TARGET_VFP \ 199 && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON | FPU_FL_FP16)) 200 201 /* FPU supports VFP half-precision floating-point. */ 202 #define TARGET_FP16 \ 203 (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_FP16)) 204 205 /* FPU supports fused-multiply-add operations. */ 206 #define TARGET_FMA (TARGET_VFP && TARGET_FPU_REV >= 4) 207 208 /* FPU is ARMv8 compatible. */ 209 #define TARGET_FPU_ARMV8 (TARGET_VFP && TARGET_FPU_REV >= 8) 210 211 /* FPU supports Crypto extensions. */ 212 #define TARGET_CRYPTO \ 213 (TARGET_VFP && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_CRYPTO)) 214 215 /* FPU supports Neon instructions. The setting of this macro gets 216 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 217 and TARGET_HARD_FLOAT to ensure that NEON instructions are 218 available. */ 219 #define TARGET_NEON \ 220 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP \ 221 && ARM_FPU_FSET_HAS (TARGET_FPU_FEATURES, FPU_FL_NEON)) 222 223 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 224 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 225 226 /* Q-bit is present. */ 227 #define TARGET_ARM_QBIT \ 228 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 229 /* Saturation operation, e.g. SSAT. */ 230 #define TARGET_ARM_SAT \ 231 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 232 /* "DSP" multiply instructions, eg. SMULxy. */ 233 #define TARGET_DSP_MULTIPLY \ 234 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 235 /* Integer SIMD instructions, and extend-accumulate instructions. */ 236 #define TARGET_INT_SIMD \ 237 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 238 239 /* Should MOVW/MOVT be used in preference to a constant pool. */ 240 #define TARGET_USE_MOVT \ 241 (arm_arch_thumb2 \ 242 && (arm_disable_literal_pool \ 243 || (!optimize_size && !current_tune->prefer_constant_pool))) 244 245 /* Nonzero if this chip provides the DMB instruction. */ 246 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 247 248 /* Nonzero if this chip implements a memory barrier via CP15. */ 249 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 250 && ! TARGET_THUMB1) 251 252 /* Nonzero if this chip implements a memory barrier instruction. */ 253 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 254 255 /* Nonzero if this chip supports ldrex and strex */ 256 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) || arm_arch7) 257 258 /* Nonzero if this chip supports LPAE. */ 259 #define TARGET_HAVE_LPAE (arm_arch_lpae) 260 261 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 262 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) || arm_arch7) 263 264 /* Nonzero if this chip supports ldrexd and strexd. */ 265 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 266 || arm_arch7) && arm_arch_notm) 267 268 /* Nonzero if this chip supports load-acquire and store-release. */ 269 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 270 271 /* Nonzero if integer division instructions supported. */ 272 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 273 || (TARGET_THUMB2 && arm_arch_thumb_hwdiv)) 274 275 /* Nonzero if disallow volatile memory access in IT block. */ 276 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 277 278 /* Should NEON be used for 64-bits bitops. */ 279 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 280 281 /* Should constant I be slplit for OP. */ 282 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 283 ((optimize >= 2) \ 284 && can_create_pseudo_p () \ 285 && !const_ok_for_op (i, op)) 286 287 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 288 then TARGET_AAPCS_BASED must be true -- but the converse does not 289 hold. TARGET_BPABI implies the use of the BPABI runtime library, 290 etc., in addition to just the AAPCS calling conventions. */ 291 #ifndef TARGET_BPABI 292 #define TARGET_BPABI false 293 #endif 294 295 /* Transform lane numbers on big endian targets. This is used to allow for the 296 endianness difference between NEON architectural lane numbers and those 297 used in RTL */ 298 #define NEON_ENDIAN_LANE_N(mode, n) \ 299 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 300 301 /* Support for a compile-time default CPU, et cetera. The rules are: 302 --with-arch is ignored if -march or -mcpu are specified. 303 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 304 by --with-arch. 305 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 306 by -march). 307 --with-float is ignored if -mfloat-abi is specified. 308 --with-fpu is ignored if -mfpu is specified. 309 --with-abi is ignored if -mabi is specified. 310 --with-tls is ignored if -mtls-dialect is specified. */ 311 #define OPTION_DEFAULT_SPECS \ 312 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 313 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 314 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 315 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 316 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 317 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 318 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 319 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 320 321 /* FPU feature sets. */ 322 323 typedef unsigned long arm_fpu_feature_set; 324 325 /* Test for an FPU feature. */ 326 #define ARM_FPU_FSET_HAS(S,F) (((S) & (F)) == (F)) 327 328 /* FPU Features. */ 329 #define FPU_FL_NONE (0) 330 #define FPU_FL_NEON (1 << 0) /* NEON instructions. */ 331 #define FPU_FL_FP16 (1 << 1) /* Half-precision. */ 332 #define FPU_FL_CRYPTO (1 << 2) /* Crypto extensions. */ 333 334 /* Which floating point model to use. */ 335 enum arm_fp_model 336 { 337 ARM_FP_MODEL_UNKNOWN, 338 /* VFP floating point model. */ 339 ARM_FP_MODEL_VFP 340 }; 341 342 enum vfp_reg_type 343 { 344 VFP_NONE = 0, 345 VFP_REG_D16, 346 VFP_REG_D32, 347 VFP_REG_SINGLE 348 }; 349 350 extern const struct arm_fpu_desc 351 { 352 const char *name; 353 enum arm_fp_model model; 354 int rev; 355 enum vfp_reg_type regs; 356 arm_fpu_feature_set features; 357 } all_fpus[]; 358 359 /* Accessors. */ 360 361 #define TARGET_FPU_NAME (all_fpus[arm_fpu_index].name) 362 #define TARGET_FPU_MODEL (all_fpus[arm_fpu_index].model) 363 #define TARGET_FPU_REV (all_fpus[arm_fpu_index].rev) 364 #define TARGET_FPU_REGS (all_fpus[arm_fpu_index].regs) 365 #define TARGET_FPU_FEATURES (all_fpus[arm_fpu_index].features) 366 367 /* Which floating point hardware to schedule for. */ 368 extern int arm_fpu_attr; 369 370 #ifndef TARGET_DEFAULT_FLOAT_ABI 371 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 372 #endif 373 374 #ifndef ARM_DEFAULT_ABI 375 #define ARM_DEFAULT_ABI ARM_ABI_APCS 376 #endif 377 378 /* AAPCS based ABIs use short enums by default. */ 379 #ifndef ARM_DEFAULT_SHORT_ENUMS 380 #define ARM_DEFAULT_SHORT_ENUMS \ 381 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 382 #endif 383 384 /* Map each of the micro-architecture variants to their corresponding 385 major architecture revision. */ 386 387 enum base_architecture 388 { 389 BASE_ARCH_0 = 0, 390 BASE_ARCH_2 = 2, 391 BASE_ARCH_3 = 3, 392 BASE_ARCH_3M = 3, 393 BASE_ARCH_4 = 4, 394 BASE_ARCH_4T = 4, 395 BASE_ARCH_5 = 5, 396 BASE_ARCH_5E = 5, 397 BASE_ARCH_5T = 5, 398 BASE_ARCH_5TE = 5, 399 BASE_ARCH_5TEJ = 5, 400 BASE_ARCH_6 = 6, 401 BASE_ARCH_6J = 6, 402 BASE_ARCH_6KZ = 6, 403 BASE_ARCH_6K = 6, 404 BASE_ARCH_6T2 = 6, 405 BASE_ARCH_6M = 6, 406 BASE_ARCH_6Z = 6, 407 BASE_ARCH_7 = 7, 408 BASE_ARCH_7A = 7, 409 BASE_ARCH_7R = 7, 410 BASE_ARCH_7M = 7, 411 BASE_ARCH_7EM = 7, 412 BASE_ARCH_8A = 8 413 }; 414 415 /* The major revision number of the ARM Architecture implemented by the target. */ 416 extern enum base_architecture arm_base_arch; 417 418 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 419 extern int arm_arch3m; 420 421 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 422 extern int arm_arch4; 423 424 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 425 extern int arm_arch4t; 426 427 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 428 extern int arm_arch5; 429 430 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 431 extern int arm_arch5e; 432 433 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 434 extern int arm_arch6; 435 436 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 437 extern int arm_arch6k; 438 439 /* Nonzero if instructions present in ARMv6-M can be used. */ 440 extern int arm_arch6m; 441 442 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 443 extern int arm_arch7; 444 445 /* Nonzero if instructions not present in the 'M' profile can be used. */ 446 extern int arm_arch_notm; 447 448 /* Nonzero if instructions present in ARMv7E-M can be used. */ 449 extern int arm_arch7em; 450 451 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 452 extern int arm_arch8; 453 454 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 455 extern int arm_arch8_1; 456 457 /* Nonzero if this chip can benefit from load scheduling. */ 458 extern int arm_ld_sched; 459 460 /* Nonzero if this chip is a StrongARM. */ 461 extern int arm_tune_strongarm; 462 463 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 464 extern int arm_arch_iwmmxt; 465 466 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 467 extern int arm_arch_iwmmxt2; 468 469 /* Nonzero if this chip is an XScale. */ 470 extern int arm_arch_xscale; 471 472 /* Nonzero if tuning for XScale. */ 473 extern int arm_tune_xscale; 474 475 /* Nonzero if tuning for stores via the write buffer. */ 476 extern int arm_tune_wbuf; 477 478 /* Nonzero if tuning for Cortex-A9. */ 479 extern int arm_tune_cortex_a9; 480 481 /* Nonzero if we should define __THUMB_INTERWORK__ in the 482 preprocessor. 483 XXX This is a bit of a hack, it's intended to help work around 484 problems in GLD which doesn't understand that armv5t code is 485 interworking clean. */ 486 extern int arm_cpp_interwork; 487 488 /* Nonzero if chip supports Thumb 2. */ 489 extern int arm_arch_thumb2; 490 491 /* Nonzero if chip supports integer division instruction in ARM mode. */ 492 extern int arm_arch_arm_hwdiv; 493 494 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 495 extern int arm_arch_thumb_hwdiv; 496 497 /* Nonzero if chip disallows volatile memory access in IT block. */ 498 extern int arm_arch_no_volatile_ce; 499 500 /* Nonzero if we should use Neon to handle 64-bits operations rather 501 than core registers. */ 502 extern int prefer_neon_for_64bits; 503 504 /* Nonzero if we shouldn't use literal pools. */ 505 #ifndef USED_FOR_TARGET 506 extern bool arm_disable_literal_pool; 507 #endif 508 509 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 510 extern int arm_arch_crc; 511 512 #ifndef TARGET_DEFAULT 513 #define TARGET_DEFAULT (MASK_APCS_FRAME) 514 #endif 515 516 /* Nonzero if PIC code requires explicit qualifiers to generate 517 PLT and GOT relocs rather than the assembler doing so implicitly. 518 Subtargets can override these if required. */ 519 #ifndef NEED_GOT_RELOC 520 #define NEED_GOT_RELOC 0 521 #endif 522 #ifndef NEED_PLT_RELOC 523 #define NEED_PLT_RELOC 0 524 #endif 525 526 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 527 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 528 #endif 529 530 /* Nonzero if we need to refer to the GOT with a PC-relative 531 offset. In other words, generate 532 533 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 534 535 rather than 536 537 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 538 539 The default is true, which matches NetBSD. Subtargets can 540 override this if required. */ 541 #ifndef GOT_PCREL 542 #define GOT_PCREL 1 543 #endif 544 545 /* Target machine storage Layout. */ 547 548 549 /* Define this macro if it is advisable to hold scalars in registers 550 in a wider mode than that declared by the program. In such cases, 551 the value is constrained to be within the bounds of the declared 552 type, but kept valid in the wider mode. The signedness of the 553 extension may differ from that of the type. */ 554 555 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 556 if (GET_MODE_CLASS (MODE) == MODE_INT \ 557 && GET_MODE_SIZE (MODE) < 4) \ 558 { \ 559 (MODE) = SImode; \ 560 } 561 562 /* Define this if most significant bit is lowest numbered 563 in instructions that operate on numbered bit-fields. */ 564 #define BITS_BIG_ENDIAN 0 565 566 /* Define this if most significant byte of a word is the lowest numbered. 567 Most ARM processors are run in little endian mode, so that is the default. 568 If you want to have it run-time selectable, change the definition in a 569 cover file to be TARGET_BIG_ENDIAN. */ 570 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 571 572 /* Define this if most significant word of a multiword number is the lowest 573 numbered. */ 574 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 575 576 #define UNITS_PER_WORD 4 577 578 /* True if natural alignment is used for doubleword types. */ 579 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 580 581 #define DOUBLEWORD_ALIGNMENT 64 582 583 #define PARM_BOUNDARY 32 584 585 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 586 587 #define PREFERRED_STACK_BOUNDARY \ 588 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 589 590 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 591 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 592 593 /* The lowest bit is used to indicate Thumb-mode functions, so the 594 vbit must go into the delta field of pointers to member 595 functions. */ 596 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 597 598 #define EMPTY_FIELD_BOUNDARY 32 599 600 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 601 602 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 603 604 /* XXX Blah -- this macro is used directly by libobjc. Since it 605 supports no vector modes, cut out the complexity and fall back 606 on BIGGEST_FIELD_ALIGNMENT. */ 607 #ifdef IN_TARGET_LIBS 608 #define BIGGEST_FIELD_ALIGNMENT 64 609 #endif 610 611 /* Make strings word-aligned so strcpy from constants will be faster. */ 612 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 613 614 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 615 ((TREE_CODE (EXP) == STRING_CST \ 616 && !optimize_size \ 617 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 618 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 619 620 /* Align definitions of arrays, unions and structures so that 621 initializations and copies can be made more efficient. This is not 622 ABI-changing, so it only affects places where we can see the 623 definition. Increasing the alignment tends to introduce padding, 624 so don't do this when optimizing for size/conserving stack space. */ 625 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 626 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 627 && (TREE_CODE (EXP) == ARRAY_TYPE \ 628 || TREE_CODE (EXP) == UNION_TYPE \ 629 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 630 631 /* Align global data. */ 632 #define DATA_ALIGNMENT(EXP, ALIGN) \ 633 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 634 635 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 636 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 637 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 638 639 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 640 value set in previous versions of this toolchain was 8, which produces more 641 compact structures. The command line option -mstructure_size_boundary=<n> 642 can be used to change this value. For compatibility with the ARM SDK 643 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 644 0020D) page 2-20 says "Structures are aligned on word boundaries". 645 The AAPCS specifies a value of 8. */ 646 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 647 648 /* This is the value used to initialize arm_structure_size_boundary. If a 649 particular arm target wants to change the default value it should change 650 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 651 for an example of this. */ 652 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 653 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 654 #endif 655 656 /* Nonzero if move instructions will actually fail to work 657 when given unaligned data. */ 658 #define STRICT_ALIGNMENT 1 659 660 /* wchar_t is unsigned under the AAPCS. */ 661 #ifndef WCHAR_TYPE 662 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 663 664 #define WCHAR_TYPE_SIZE BITS_PER_WORD 665 #endif 666 667 /* Sized for fixed-point types. */ 668 669 #define SHORT_FRACT_TYPE_SIZE 8 670 #define FRACT_TYPE_SIZE 16 671 #define LONG_FRACT_TYPE_SIZE 32 672 #define LONG_LONG_FRACT_TYPE_SIZE 64 673 674 #define SHORT_ACCUM_TYPE_SIZE 16 675 #define ACCUM_TYPE_SIZE 32 676 #define LONG_ACCUM_TYPE_SIZE 64 677 #define LONG_LONG_ACCUM_TYPE_SIZE 64 678 679 #define MAX_FIXED_MODE_SIZE 64 680 681 #ifndef SIZE_TYPE 682 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 683 #endif 684 685 #ifndef PTRDIFF_TYPE 686 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 687 #endif 688 689 /* AAPCS requires that structure alignment is affected by bitfields. */ 690 #ifndef PCC_BITFIELD_TYPE_MATTERS 691 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 692 #endif 693 694 /* The maximum size of the sync library functions supported. */ 695 #ifndef MAX_SYNC_LIBFUNC_SIZE 696 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 697 #endif 698 699 700 /* Standard register usage. */ 702 703 /* Register allocation in ARM Procedure Call Standard 704 (S - saved over call). 705 706 r0 * argument word/integer result 707 r1-r3 argument word 708 709 r4-r8 S register variable 710 r9 S (rfp) register variable (real frame pointer) 711 712 r10 F S (sl) stack limit (used by -mapcs-stack-check) 713 r11 F S (fp) argument pointer 714 r12 (ip) temp workspace 715 r13 F S (sp) lower end of current stack frame 716 r14 (lr) link address/workspace 717 r15 F (pc) program counter 718 719 cc This is NOT a real register, but is used internally 720 to represent things that use or set the condition 721 codes. 722 sfp This isn't either. It is used during rtl generation 723 since the offset between the frame pointer and the 724 auto's isn't known until after register allocation. 725 afp Nor this, we only need this because of non-local 726 goto. Without it fp appears to be used and the 727 elimination code won't get rid of sfp. It tracks 728 fp exactly at all times. 729 730 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 731 732 /* s0-s15 VFP scratch (aka d0-d7). 733 s16-s31 S VFP variable (aka d8-d15). 734 vfpcc Not a real register. Represents the VFP condition 735 code flags. */ 736 737 /* The stack backtrace structure is as follows: 738 fp points to here: | save code pointer | [fp] 739 | return link value | [fp, #-4] 740 | return sp value | [fp, #-8] 741 | return fp value | [fp, #-12] 742 [| saved r10 value |] 743 [| saved r9 value |] 744 [| saved r8 value |] 745 [| saved r7 value |] 746 [| saved r6 value |] 747 [| saved r5 value |] 748 [| saved r4 value |] 749 [| saved r3 value |] 750 [| saved r2 value |] 751 [| saved r1 value |] 752 [| saved r0 value |] 753 r0-r3 are not normally saved in a C function. */ 754 755 /* 1 for registers that have pervasive standard uses 756 and are not available for the register allocator. */ 757 #define FIXED_REGISTERS \ 758 { \ 759 /* Core regs. */ \ 760 0,0,0,0,0,0,0,0, \ 761 0,0,0,0,0,1,0,1, \ 762 /* VFP regs. */ \ 763 1,1,1,1,1,1,1,1, \ 764 1,1,1,1,1,1,1,1, \ 765 1,1,1,1,1,1,1,1, \ 766 1,1,1,1,1,1,1,1, \ 767 1,1,1,1,1,1,1,1, \ 768 1,1,1,1,1,1,1,1, \ 769 1,1,1,1,1,1,1,1, \ 770 1,1,1,1,1,1,1,1, \ 771 /* IWMMXT regs. */ \ 772 1,1,1,1,1,1,1,1, \ 773 1,1,1,1,1,1,1,1, \ 774 1,1,1,1, \ 775 /* Specials. */ \ 776 1,1,1,1 \ 777 } 778 779 /* 1 for registers not available across function calls. 780 These must include the FIXED_REGISTERS and also any 781 registers that can be used without being saved. 782 The latter must include the registers where values are returned 783 and the register where structure-value addresses are passed. 784 Aside from that, you can include as many other registers as you like. 785 The CC is not preserved over function calls on the ARM 6, so it is 786 easier to assume this for all. SFP is preserved, since FP is. */ 787 #define CALL_USED_REGISTERS \ 788 { \ 789 /* Core regs. */ \ 790 1,1,1,1,0,0,0,0, \ 791 0,0,0,0,1,1,1,1, \ 792 /* VFP Regs. */ \ 793 1,1,1,1,1,1,1,1, \ 794 1,1,1,1,1,1,1,1, \ 795 1,1,1,1,1,1,1,1, \ 796 1,1,1,1,1,1,1,1, \ 797 1,1,1,1,1,1,1,1, \ 798 1,1,1,1,1,1,1,1, \ 799 1,1,1,1,1,1,1,1, \ 800 1,1,1,1,1,1,1,1, \ 801 /* IWMMXT regs. */ \ 802 1,1,1,1,1,1,1,1, \ 803 1,1,1,1,1,1,1,1, \ 804 1,1,1,1, \ 805 /* Specials. */ \ 806 1,1,1,1 \ 807 } 808 809 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 810 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 811 #endif 812 813 /* These are a couple of extensions to the formats accepted 814 by asm_fprintf: 815 %@ prints out ASM_COMMENT_START 816 %r prints out REGISTER_PREFIX reg_names[arg] */ 817 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 818 case '@': \ 819 fputs (ASM_COMMENT_START, FILE); \ 820 break; \ 821 \ 822 case 'r': \ 823 fputs (REGISTER_PREFIX, FILE); \ 824 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 825 break; 826 827 /* Round X up to the nearest word. */ 828 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 829 830 /* Convert fron bytes to ints. */ 831 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 832 833 /* The number of (integer) registers required to hold a quantity of type MODE. 834 Also used for VFP registers. */ 835 #define ARM_NUM_REGS(MODE) \ 836 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 837 838 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 839 #define ARM_NUM_REGS2(MODE, TYPE) \ 840 ARM_NUM_INTS ((MODE) == BLKmode ? \ 841 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 842 843 /* The number of (integer) argument register available. */ 844 #define NUM_ARG_REGS 4 845 846 /* And similarly for the VFP. */ 847 #define NUM_VFP_ARG_REGS 16 848 849 /* Return the register number of the N'th (integer) argument. */ 850 #define ARG_REGISTER(N) (N - 1) 851 852 /* Specify the registers used for certain standard purposes. 853 The values of these macros are register numbers. */ 854 855 /* The number of the last argument register. */ 856 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 857 858 /* The numbers of the Thumb register ranges. */ 859 #define FIRST_LO_REGNUM 0 860 #define LAST_LO_REGNUM 7 861 #define FIRST_HI_REGNUM 8 862 #define LAST_HI_REGNUM 11 863 864 /* Overridden by config/arm/bpabi.h. */ 865 #ifndef ARM_UNWIND_INFO 866 #define ARM_UNWIND_INFO 0 867 #endif 868 869 /* Overriden by config/arm/netbsd-eabi.h. */ 870 #ifndef ARM_DWARF_UNWIND_TABLES 871 #define ARM_DWARF_UNWIND_TABLES 0 872 #endif 873 874 /* Use r0 and r1 to pass exception handling information. */ 875 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 876 877 /* The register that holds the return address in exception handlers. */ 878 #define ARM_EH_STACKADJ_REGNUM 2 879 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 880 881 #ifndef ARM_TARGET2_DWARF_FORMAT 882 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 883 #endif 884 885 #if ARM_DWARF_UNWIND_TABLES 886 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 887 for 32bit platforms. */ 888 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 889 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 890 : DW_EH_PE_absptr) 891 #else 892 /* ttype entries (the only interesting data references used) 893 use TARGET2 relocations. */ 894 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 895 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 896 : DW_EH_PE_absptr) 897 #endif 898 899 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 900 as an invisible last argument (possible since varargs don't exist in 901 Pascal), so the following is not true. */ 902 #define STATIC_CHAIN_REGNUM 12 903 904 /* Define this to be where the real frame pointer is if it is not possible to 905 work out the offset between the frame pointer and the automatic variables 906 until after register allocation has taken place. FRAME_POINTER_REGNUM 907 should point to a special register that we will make sure is eliminated. 908 909 For the Thumb we have another problem. The TPCS defines the frame pointer 910 as r11, and GCC believes that it is always possible to use the frame pointer 911 as base register for addressing purposes. (See comments in 912 find_reloads_address()). But - the Thumb does not allow high registers, 913 including r11, to be used as base address registers. Hence our problem. 914 915 The solution used here, and in the old thumb port is to use r7 instead of 916 r11 as the hard frame pointer and to have special code to generate 917 backtrace structures on the stack (if required to do so via a command line 918 option) using r11. This is the only 'user visible' use of r11 as a frame 919 pointer. */ 920 #define ARM_HARD_FRAME_POINTER_REGNUM 11 921 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 922 923 #define HARD_FRAME_POINTER_REGNUM \ 924 (TARGET_ARM \ 925 ? ARM_HARD_FRAME_POINTER_REGNUM \ 926 : THUMB_HARD_FRAME_POINTER_REGNUM) 927 928 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 929 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 930 931 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 932 933 /* Register to use for pushing function arguments. */ 934 #define STACK_POINTER_REGNUM SP_REGNUM 935 936 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 937 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 938 939 /* Need to sync with WCGR in iwmmxt.md. */ 940 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 941 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 942 943 #define IS_IWMMXT_REGNUM(REGNUM) \ 944 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 945 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 946 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 947 948 /* Base register for access to local variables of the function. */ 949 #define FRAME_POINTER_REGNUM 102 950 951 /* Base register for access to arguments of the function. */ 952 #define ARG_POINTER_REGNUM 103 953 954 #define FIRST_VFP_REGNUM 16 955 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 956 #define LAST_VFP_REGNUM \ 957 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 958 959 #define IS_VFP_REGNUM(REGNUM) \ 960 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 961 962 /* VFP registers are split into two types: those defined by VFP versions < 3 963 have D registers overlaid on consecutive pairs of S registers. VFP version 3 964 defines 16 new D registers (d16-d31) which, for simplicity and correctness 965 in various parts of the backend, we implement as "fake" single-precision 966 registers (which would be S32-S63, but cannot be used in that way). The 967 following macros define these ranges of registers. */ 968 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 969 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 970 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 971 972 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 973 ((REGNUM) <= LAST_LO_VFP_REGNUM) 974 975 /* DFmode values are only valid in even register pairs. */ 976 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 977 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 978 979 /* Neon Quad values must start at a multiple of four registers. */ 980 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 981 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 982 983 /* Neon structures of vectors must be in even register pairs and there 984 must be enough registers available. Because of various patterns 985 requiring quad registers, we require them to start at a multiple of 986 four. */ 987 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 988 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 989 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 990 991 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 992 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 993 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 994 #define FIRST_PSEUDO_REGISTER 104 995 996 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 997 998 /* Value should be nonzero if functions must have frame pointers. 999 Zero means the frame pointer need not be set up (and parms may be accessed 1000 via the stack pointer) in functions that seem suitable. 1001 If we have to have a frame pointer we might as well make use of it. 1002 APCS says that the frame pointer does not need to be pushed in leaf 1003 functions, or simple tail call functions. */ 1004 1005 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1006 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1007 #endif 1008 1009 /* Return number of consecutive hard regs needed starting at reg REGNO 1010 to hold something of mode MODE. 1011 This is ordinarily the length in words of a value of mode MODE 1012 but can be less for certain modes in special long registers. 1013 1014 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1015 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1016 ((TARGET_32BIT \ 1017 && REGNO > PC_REGNUM \ 1018 && REGNO != FRAME_POINTER_REGNUM \ 1019 && REGNO != ARG_POINTER_REGNUM) \ 1020 && !IS_VFP_REGNUM (REGNO) \ 1021 ? 1 : ARM_NUM_REGS (MODE)) 1022 1023 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1024 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1025 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1026 1027 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1028 1029 #define VALID_IWMMXT_REG_MODE(MODE) \ 1030 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1031 1032 /* Modes valid for Neon D registers. */ 1033 #define VALID_NEON_DREG_MODE(MODE) \ 1034 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1035 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1036 1037 /* Modes valid for Neon Q registers. */ 1038 #define VALID_NEON_QREG_MODE(MODE) \ 1039 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1040 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode) 1041 1042 /* Structure modes valid for Neon registers. */ 1043 #define VALID_NEON_STRUCT_MODE(MODE) \ 1044 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1045 || (MODE) == CImode || (MODE) == XImode) 1046 1047 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1048 extern int arm_regs_in_sequence[]; 1049 1050 /* The order in which register should be allocated. It is good to use ip 1051 since no saving is required (though calls clobber it) and it never contains 1052 function parameters. It is quite good to use lr since other calls may 1053 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1054 least likely to contain a function parameter; in addition results are 1055 returned in r0. 1056 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1057 then D8-D15. The reason for doing this is to attempt to reduce register 1058 pressure when both single- and double-precision registers are used in a 1059 function. */ 1060 1061 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1062 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1063 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1064 1065 #define REG_ALLOC_ORDER \ 1066 { \ 1067 /* General registers. */ \ 1068 3, 2, 1, 0, 12, 14, 4, 5, \ 1069 6, 7, 8, 9, 10, 11, \ 1070 /* High VFP registers. */ \ 1071 VREG(32), VREG(33), VREG(34), VREG(35), \ 1072 VREG(36), VREG(37), VREG(38), VREG(39), \ 1073 VREG(40), VREG(41), VREG(42), VREG(43), \ 1074 VREG(44), VREG(45), VREG(46), VREG(47), \ 1075 VREG(48), VREG(49), VREG(50), VREG(51), \ 1076 VREG(52), VREG(53), VREG(54), VREG(55), \ 1077 VREG(56), VREG(57), VREG(58), VREG(59), \ 1078 VREG(60), VREG(61), VREG(62), VREG(63), \ 1079 /* VFP argument registers. */ \ 1080 VREG(15), VREG(14), VREG(13), VREG(12), \ 1081 VREG(11), VREG(10), VREG(9), VREG(8), \ 1082 VREG(7), VREG(6), VREG(5), VREG(4), \ 1083 VREG(3), VREG(2), VREG(1), VREG(0), \ 1084 /* VFP call-saved registers. */ \ 1085 VREG(16), VREG(17), VREG(18), VREG(19), \ 1086 VREG(20), VREG(21), VREG(22), VREG(23), \ 1087 VREG(24), VREG(25), VREG(26), VREG(27), \ 1088 VREG(28), VREG(29), VREG(30), VREG(31), \ 1089 /* IWMMX registers. */ \ 1090 WREG(0), WREG(1), WREG(2), WREG(3), \ 1091 WREG(4), WREG(5), WREG(6), WREG(7), \ 1092 WREG(8), WREG(9), WREG(10), WREG(11), \ 1093 WREG(12), WREG(13), WREG(14), WREG(15), \ 1094 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1095 /* Registers not for general use. */ \ 1096 CC_REGNUM, VFPCC_REGNUM, \ 1097 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1098 SP_REGNUM, PC_REGNUM \ 1099 } 1100 1101 /* Use different register alloc ordering for Thumb. */ 1102 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1103 1104 /* Tell IRA to use the order we define rather than messing it up with its 1105 own cost calculations. */ 1106 #define HONOR_REG_ALLOC_ORDER 1 1107 1108 /* Interrupt functions can only use registers that have already been 1109 saved by the prologue, even if they would normally be 1110 call-clobbered. */ 1111 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1112 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1113 df_regs_ever_live_p (DST)) 1114 1115 /* Register and constant classes. */ 1117 1118 /* Register classes. */ 1119 enum reg_class 1120 { 1121 NO_REGS, 1122 LO_REGS, 1123 STACK_REG, 1124 BASE_REGS, 1125 HI_REGS, 1126 CALLER_SAVE_REGS, 1127 GENERAL_REGS, 1128 CORE_REGS, 1129 VFP_D0_D7_REGS, 1130 VFP_LO_REGS, 1131 VFP_HI_REGS, 1132 VFP_REGS, 1133 IWMMXT_REGS, 1134 IWMMXT_GR_REGS, 1135 CC_REG, 1136 VFPCC_REG, 1137 SFP_REG, 1138 AFP_REG, 1139 ALL_REGS, 1140 LIM_REG_CLASSES 1141 }; 1142 1143 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1144 1145 /* Give names of register classes as strings for dump file. */ 1146 #define REG_CLASS_NAMES \ 1147 { \ 1148 "NO_REGS", \ 1149 "LO_REGS", \ 1150 "STACK_REG", \ 1151 "BASE_REGS", \ 1152 "HI_REGS", \ 1153 "CALLER_SAVE_REGS", \ 1154 "GENERAL_REGS", \ 1155 "CORE_REGS", \ 1156 "VFP_D0_D7_REGS", \ 1157 "VFP_LO_REGS", \ 1158 "VFP_HI_REGS", \ 1159 "VFP_REGS", \ 1160 "IWMMXT_REGS", \ 1161 "IWMMXT_GR_REGS", \ 1162 "CC_REG", \ 1163 "VFPCC_REG", \ 1164 "SFP_REG", \ 1165 "AFP_REG", \ 1166 "ALL_REGS" \ 1167 } 1168 1169 /* Define which registers fit in which classes. 1170 This is an initializer for a vector of HARD_REG_SET 1171 of length N_REG_CLASSES. */ 1172 #define REG_CLASS_CONTENTS \ 1173 { \ 1174 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1175 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1176 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1177 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1178 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1179 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1180 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1181 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1182 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1183 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1184 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1185 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1186 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1187 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1188 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1189 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1190 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1191 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1192 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1193 } 1194 1195 /* Any of the VFP register classes. */ 1196 #define IS_VFP_CLASS(X) \ 1197 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1198 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1199 1200 /* The same information, inverted: 1201 Return the class number of the smallest class containing 1202 reg number REGNO. This could be a conditional expression 1203 or could index an array. */ 1204 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1205 1206 /* In VFPv1, VFP registers could only be accessed in the mode they 1207 were set, so subregs would be invalid there. However, we don't 1208 support VFPv1 at the moment, and the restriction was lifted in 1209 VFPv2. 1210 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1211 VFP registers in little-endian order. We can't describe that accurately to 1212 GCC, so avoid taking subregs of such values. 1213 The only exception is going from a 128-bit to a 64-bit type. In that case 1214 the data layout happens to be consistent for big-endian, so we explicitly allow 1215 that case. */ 1216 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1217 (TARGET_VFP && TARGET_BIG_END \ 1218 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1219 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1220 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1221 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1222 1223 /* The class value for index registers, and the one for base regs. */ 1224 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1225 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1226 1227 /* For the Thumb the high registers cannot be used as base registers 1228 when addressing quantities in QI or HI mode; if we don't know the 1229 mode, then we must be conservative. */ 1230 #define MODE_BASE_REG_CLASS(MODE) \ 1231 (TARGET_32BIT ? CORE_REGS \ 1232 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1233 : LO_REGS) 1234 1235 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1236 instead of BASE_REGS. */ 1237 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1238 1239 /* When this hook returns true for MODE, the compiler allows 1240 registers explicitly used in the rtl to be used as spill registers 1241 but prevents the compiler from extending the lifetime of these 1242 registers. */ 1243 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1244 arm_small_register_classes_for_mode_p 1245 1246 /* Must leave BASE_REGS reloads alone */ 1247 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1248 (lra_in_progress ? NO_REGS \ 1249 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1250 ? ((true_regnum (X) == -1 ? LO_REGS \ 1251 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1252 : NO_REGS)) \ 1253 : NO_REGS)) 1254 1255 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1256 (lra_in_progress ? NO_REGS \ 1257 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1258 ? ((true_regnum (X) == -1 ? LO_REGS \ 1259 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1260 : NO_REGS)) \ 1261 : NO_REGS) 1262 1263 /* Return the register class of a scratch register needed to copy IN into 1264 or out of a register in CLASS in MODE. If it can be done directly, 1265 NO_REGS is returned. */ 1266 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1267 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1268 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1269 && IS_VFP_CLASS (CLASS)) \ 1270 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1271 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1272 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1273 : TARGET_32BIT \ 1274 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1275 ? GENERAL_REGS : NO_REGS) \ 1276 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1277 1278 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1279 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1280 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1281 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1282 && IS_VFP_CLASS (CLASS)) \ 1283 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1284 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1285 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1286 (TARGET_32BIT ? \ 1287 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1288 && CONSTANT_P (X)) \ 1289 ? GENERAL_REGS : \ 1290 (((MODE) == HImode && ! arm_arch4 \ 1291 && (MEM_P (X) \ 1292 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1293 && true_regnum (X) == -1))) \ 1294 ? GENERAL_REGS : NO_REGS) \ 1295 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1296 1297 /* Return the maximum number of consecutive registers 1298 needed to represent mode MODE in a register of class CLASS. 1299 ARM regs are UNITS_PER_WORD bits. 1300 FIXME: Is this true for iWMMX? */ 1301 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1302 (ARM_NUM_REGS (MODE)) 1303 1304 /* If defined, gives a class of registers that cannot be used as the 1305 operand of a SUBREG that changes the mode of the object illegally. */ 1306 1307 /* Stack layout; function entry, exit and calling. */ 1309 1310 /* Define this if pushing a word on the stack 1311 makes the stack pointer a smaller address. */ 1312 #define STACK_GROWS_DOWNWARD 1 1313 1314 /* Define this to nonzero if the nominal address of the stack frame 1315 is at the high-address end of the local variables; 1316 that is, each additional local variable allocated 1317 goes at a more negative offset in the frame. */ 1318 #define FRAME_GROWS_DOWNWARD 1 1319 1320 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1321 When present, it is one word in size, and sits at the top of the frame, 1322 between the soft frame pointer and either r7 or r11. 1323 1324 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1325 and only then if some outgoing arguments are passed on the stack. It would 1326 be tempting to also check whether the stack arguments are passed by indirect 1327 calls, but there seems to be no reason in principle why a post-reload pass 1328 couldn't convert a direct call into an indirect one. */ 1329 #define CALLER_INTERWORKING_SLOT_SIZE \ 1330 (TARGET_CALLER_INTERWORKING \ 1331 && crtl->outgoing_args_size != 0 \ 1332 ? UNITS_PER_WORD : 0) 1333 1334 /* Offset within stack frame to start allocating local variables at. 1335 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1336 first local allocated. Otherwise, it is the offset to the BEGINNING 1337 of the first local allocated. */ 1338 #define STARTING_FRAME_OFFSET 0 1339 1340 /* If we generate an insn to push BYTES bytes, 1341 this says how many the stack pointer really advances by. */ 1342 /* The push insns do not do this rounding implicitly. 1343 So don't define this. */ 1344 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1345 1346 /* Define this if the maximum size of all the outgoing args is to be 1347 accumulated and pushed during the prologue. The amount can be 1348 found in the variable crtl->outgoing_args_size. */ 1349 #define ACCUMULATE_OUTGOING_ARGS 1 1350 1351 /* Offset of first parameter from the argument pointer register value. */ 1352 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1353 1354 /* Amount of memory needed for an untyped call to save all possible return 1355 registers. */ 1356 #define APPLY_RESULT_SIZE arm_apply_result_size() 1357 1358 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1359 values must be in memory. On the ARM, they need only do so if larger 1360 than a word, or if they contain elements offset from zero in the struct. */ 1361 #define DEFAULT_PCC_STRUCT_RETURN 0 1362 1363 /* These bits describe the different types of function supported 1364 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1365 normal function and an interworked function, for example. Knowing the 1366 type of a function is important for determining its prologue and 1367 epilogue sequences. 1368 Note value 7 is currently unassigned. Also note that the interrupt 1369 function types all have bit 2 set, so that they can be tested for easily. 1370 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1371 machine_function structure is initialized (to zero) func_type will 1372 default to unknown. This will force the first use of arm_current_func_type 1373 to call arm_compute_func_type. */ 1374 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1375 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1376 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1377 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1378 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1379 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1380 1381 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1382 1383 /* In addition functions can have several type modifiers, 1384 outlined by these bit masks: */ 1385 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1386 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1387 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1388 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1389 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1390 1391 /* Some macros to test these flags. */ 1392 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1393 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1394 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1395 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1396 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1397 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1398 1399 1400 /* Structure used to hold the function stack frame layout. Offsets are 1401 relative to the stack pointer on function entry. Positive offsets are 1402 in the direction of stack growth. 1403 Only soft_frame is used in thumb mode. */ 1404 1405 typedef struct GTY(()) arm_stack_offsets 1406 { 1407 int saved_args; /* ARG_POINTER_REGNUM. */ 1408 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1409 int saved_regs; 1410 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1411 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1412 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1413 unsigned int saved_regs_mask; 1414 } 1415 arm_stack_offsets; 1416 1417 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1418 /* A C structure for machine-specific, per-function data. 1419 This is added to the cfun structure. */ 1420 typedef struct GTY(()) machine_function 1421 { 1422 /* Additional stack adjustment in __builtin_eh_throw. */ 1423 rtx eh_epilogue_sp_ofs; 1424 /* Records if LR has to be saved for far jumps. */ 1425 int far_jump_used; 1426 /* Records if ARG_POINTER was ever live. */ 1427 int arg_pointer_live; 1428 /* Records if the save of LR has been eliminated. */ 1429 int lr_save_eliminated; 1430 /* The size of the stack frame. Only valid after reload. */ 1431 arm_stack_offsets stack_offsets; 1432 /* Records the type of the current function. */ 1433 unsigned long func_type; 1434 /* Record if the function has a variable argument list. */ 1435 int uses_anonymous_args; 1436 /* Records if sibcalls are blocked because an argument 1437 register is needed to preserve stack alignment. */ 1438 int sibcall_blocked; 1439 /* The PIC register for this function. This might be a pseudo. */ 1440 rtx pic_reg; 1441 /* Labels for per-function Thumb call-via stubs. One per potential calling 1442 register. We can never call via LR or PC. We can call via SP if a 1443 trampoline happens to be on the top of the stack. */ 1444 rtx call_via[14]; 1445 /* Set to 1 when a return insn is output, this means that the epilogue 1446 is not needed. */ 1447 int return_used_this_function; 1448 /* When outputting Thumb-1 code, record the last insn that provides 1449 information about condition codes, and the comparison operands. */ 1450 rtx thumb1_cc_insn; 1451 rtx thumb1_cc_op0; 1452 rtx thumb1_cc_op1; 1453 /* Also record the CC mode that is supported. */ 1454 machine_mode thumb1_cc_mode; 1455 /* Set to 1 after arm_reorg has started. */ 1456 int after_arm_reorg; 1457 /* The number of bytes used to store the static chain register on the 1458 stack, above the stack frame. */ 1459 int static_chain_stack_bytes; 1460 } 1461 machine_function; 1462 #endif 1463 1464 /* As in the machine_function, a global set of call-via labels, for code 1465 that is in text_section. */ 1466 extern GTY(()) rtx thumb_call_via_label[14]; 1467 1468 /* The number of potential ways of assigning to a co-processor. */ 1469 #define ARM_NUM_COPROC_SLOTS 1 1470 1471 /* Enumeration of procedure calling standard variants. We don't really 1472 support all of these yet. */ 1473 enum arm_pcs 1474 { 1475 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1476 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1477 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1478 /* This must be the last AAPCS variant. */ 1479 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1480 ARM_PCS_ATPCS, /* ATPCS. */ 1481 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1482 ARM_PCS_UNKNOWN 1483 }; 1484 1485 /* Default procedure calling standard of current compilation unit. */ 1486 extern enum arm_pcs arm_pcs_default; 1487 1488 #if !defined (USED_FOR_TARGET) 1489 /* A C type for declaring a variable that is used as the first argument of 1490 `FUNCTION_ARG' and other related values. */ 1491 typedef struct 1492 { 1493 /* This is the number of registers of arguments scanned so far. */ 1494 int nregs; 1495 /* This is the number of iWMMXt register arguments scanned so far. */ 1496 int iwmmxt_nregs; 1497 int named_count; 1498 int nargs; 1499 /* Which procedure call variant to use for this call. */ 1500 enum arm_pcs pcs_variant; 1501 1502 /* AAPCS related state tracking. */ 1503 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1504 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1505 this argument, or -1 if using core 1506 registers. */ 1507 int aapcs_ncrn; 1508 int aapcs_next_ncrn; 1509 rtx aapcs_reg; /* Register assigned to this argument. */ 1510 int aapcs_partial; /* How many bytes are passed in regs (if 1511 split between core regs and stack. 1512 Zero otherwise. */ 1513 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1514 int can_split; /* Argument can be split between core regs 1515 and the stack. */ 1516 /* Private data for tracking VFP register allocation */ 1517 unsigned aapcs_vfp_regs_free; 1518 unsigned aapcs_vfp_reg_alloc; 1519 int aapcs_vfp_rcount; 1520 MACHMODE aapcs_vfp_rmode; 1521 } CUMULATIVE_ARGS; 1522 #endif 1523 1524 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1525 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1526 1527 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1528 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1529 1530 /* For AAPCS, padding should never be below the argument. For other ABIs, 1531 * mimic the default. */ 1532 #define PAD_VARARGS_DOWN \ 1533 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1534 1535 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1536 for a call to a function whose data type is FNTYPE. 1537 For a library call, FNTYPE is 0. 1538 On the ARM, the offset starts at 0. */ 1539 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1540 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1541 1542 /* 1 if N is a possible register number for function argument passing. 1543 On the ARM, r0-r3 are used to pass args. */ 1544 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1545 (IN_RANGE ((REGNO), 0, 3) \ 1546 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1547 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1548 || (TARGET_IWMMXT_ABI \ 1549 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1550 1551 1552 /* If your target environment doesn't prefix user functions with an 1554 underscore, you may wish to re-define this to prevent any conflicts. */ 1555 #ifndef ARM_MCOUNT_NAME 1556 #define ARM_MCOUNT_NAME "*mcount" 1557 #endif 1558 1559 /* Call the function profiler with a given profile label. The Acorn 1560 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1561 On the ARM the full profile code will look like: 1562 .data 1563 LP1 1564 .word 0 1565 .text 1566 mov ip, lr 1567 bl mcount 1568 .word LP1 1569 1570 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1571 will output the .text section. 1572 1573 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1574 ``prof'' doesn't seem to mind about this! 1575 1576 Note - this version of the code is designed to work in both ARM and 1577 Thumb modes. */ 1578 #ifndef ARM_FUNCTION_PROFILER 1579 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1580 { \ 1581 char temp[20]; \ 1582 rtx sym; \ 1583 \ 1584 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1585 IP_REGNUM, LR_REGNUM); \ 1586 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1587 fputc ('\n', STREAM); \ 1588 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1589 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1590 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1591 } 1592 #endif 1593 1594 #ifdef THUMB_FUNCTION_PROFILER 1595 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1596 if (TARGET_ARM) \ 1597 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1598 else \ 1599 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1600 #else 1601 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1602 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1603 #endif 1604 1605 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1606 the stack pointer does not matter. The value is tested only in 1607 functions that have frame pointers. 1608 No definition is equivalent to always zero. 1609 1610 On the ARM, the function epilogue recovers the stack pointer from the 1611 frame. */ 1612 #define EXIT_IGNORE_STACK 1 1613 1614 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1615 1616 /* Determine if the epilogue should be output as RTL. 1617 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1618 #define USE_RETURN_INSN(ISCOND) \ 1619 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1620 1621 /* Definitions for register eliminations. 1622 1623 This is an array of structures. Each structure initializes one pair 1624 of eliminable registers. The "from" register number is given first, 1625 followed by "to". Eliminations of the same "from" register are listed 1626 in order of preference. 1627 1628 We have two registers that can be eliminated on the ARM. First, the 1629 arg pointer register can often be eliminated in favor of the stack 1630 pointer register. Secondly, the pseudo frame pointer register can always 1631 be eliminated; it is replaced with either the stack or the real frame 1632 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1633 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1634 1635 #define ELIMINABLE_REGS \ 1636 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1637 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1638 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1639 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1640 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1641 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1642 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1643 1644 /* Define the offset between two registers, one to be eliminated, and the 1645 other its replacement, at the start of a routine. */ 1646 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1647 if (TARGET_ARM) \ 1648 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1649 else \ 1650 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1651 1652 /* Special case handling of the location of arguments passed on the stack. */ 1653 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1654 1655 /* Initialize data used by insn expanders. This is called from insn_emit, 1656 once for every function before code is generated. */ 1657 #define INIT_EXPANDERS arm_init_expanders () 1658 1659 /* Length in units of the trampoline for entering a nested function. */ 1660 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1661 1662 /* Alignment required for a trampoline in bits. */ 1663 #define TRAMPOLINE_ALIGNMENT 32 1664 1665 /* Addressing modes, and classification of registers for them. */ 1667 #define HAVE_POST_INCREMENT 1 1668 #define HAVE_PRE_INCREMENT TARGET_32BIT 1669 #define HAVE_POST_DECREMENT TARGET_32BIT 1670 #define HAVE_PRE_DECREMENT TARGET_32BIT 1671 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1672 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1673 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1674 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1675 1676 enum arm_auto_incmodes 1677 { 1678 ARM_POST_INC, 1679 ARM_PRE_INC, 1680 ARM_POST_DEC, 1681 ARM_PRE_DEC 1682 }; 1683 1684 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1685 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1686 #define USE_LOAD_POST_INCREMENT(mode) \ 1687 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1688 #define USE_LOAD_PRE_INCREMENT(mode) \ 1689 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1690 #define USE_LOAD_POST_DECREMENT(mode) \ 1691 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1692 #define USE_LOAD_PRE_DECREMENT(mode) \ 1693 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1694 1695 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1696 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1697 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1698 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1699 1700 /* Macros to check register numbers against specific register classes. */ 1701 1702 /* These assume that REGNO is a hard or pseudo reg number. 1703 They give nonzero only if REGNO is a hard reg of the suitable class 1704 or a pseudo reg currently allocated to a suitable hard reg. */ 1705 #define TEST_REGNO(R, TEST, VALUE) \ 1706 ((R TEST VALUE) \ 1707 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1708 1709 /* Don't allow the pc to be used. */ 1710 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1711 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1712 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1713 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1714 1715 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1716 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1717 || (GET_MODE_SIZE (MODE) >= 4 \ 1718 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1719 1720 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1721 (TARGET_THUMB1 \ 1722 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1723 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1724 1725 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1726 For Thumb, we can not use SP + reg, so reject SP. */ 1727 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1728 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1729 1730 /* For ARM code, we don't care about the mode, but for Thumb, the index 1731 must be suitable for use in a QImode load. */ 1732 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1733 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1734 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1735 1736 /* Maximum number of registers that can appear in a valid memory address. 1737 Shifts in addresses can't be by a register. */ 1738 #define MAX_REGS_PER_ADDRESS 2 1739 1740 /* Recognize any constant value that is a valid address. */ 1741 /* XXX We can address any constant, eventually... */ 1742 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1743 #define CONSTANT_ADDRESS_P(X) \ 1744 (GET_CODE (X) == SYMBOL_REF \ 1745 && (CONSTANT_POOL_ADDRESS_P (X) \ 1746 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1747 1748 /* True if SYMBOL + OFFSET constants must refer to something within 1749 SYMBOL's section. */ 1750 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1751 1752 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1753 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1754 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1755 #endif 1756 1757 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1758 #define SUBTARGET_NAME_ENCODING_LENGTHS 1759 #endif 1760 1761 /* This is a C fragment for the inside of a switch statement. 1762 Each case label should return the number of characters to 1763 be stripped from the start of a function's name, if that 1764 name starts with the indicated character. */ 1765 #define ARM_NAME_ENCODING_LENGTHS \ 1766 case '*': return 1; \ 1767 SUBTARGET_NAME_ENCODING_LENGTHS 1768 1769 /* This is how to output a reference to a user-level label named NAME. 1770 `assemble_name' uses this. */ 1771 #undef ASM_OUTPUT_LABELREF 1772 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1773 arm_asm_output_labelref (FILE, NAME) 1774 1775 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1776 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1777 if (TARGET_THUMB2) \ 1778 thumb2_asm_output_opcode (STREAM); 1779 1780 /* The EABI specifies that constructors should go in .init_array. 1781 Other targets use .ctors for compatibility. */ 1782 #ifndef ARM_EABI_CTORS_SECTION_OP 1783 #define ARM_EABI_CTORS_SECTION_OP \ 1784 "\t.section\t.init_array,\"aw\",%init_array" 1785 #endif 1786 #ifndef ARM_EABI_DTORS_SECTION_OP 1787 #define ARM_EABI_DTORS_SECTION_OP \ 1788 "\t.section\t.fini_array,\"aw\",%fini_array" 1789 #endif 1790 #define ARM_CTORS_SECTION_OP \ 1791 "\t.section\t.ctors,\"aw\",%progbits" 1792 #define ARM_DTORS_SECTION_OP \ 1793 "\t.section\t.dtors,\"aw\",%progbits" 1794 1795 /* Define CTORS_SECTION_ASM_OP. */ 1796 #undef CTORS_SECTION_ASM_OP 1797 #undef DTORS_SECTION_ASM_OP 1798 #ifndef IN_LIBGCC2 1799 # define CTORS_SECTION_ASM_OP \ 1800 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1801 # define DTORS_SECTION_ASM_OP \ 1802 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1803 #else /* !defined (IN_LIBGCC2) */ 1804 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1805 so we cannot use the definition above. */ 1806 # ifdef __ARM_EABI__ 1807 /* The .ctors section is not part of the EABI, so we do not define 1808 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1809 from trying to use it. We do define it when doing normal 1810 compilation, as .init_array can be used instead of .ctors. */ 1811 /* There is no need to emit begin or end markers when using 1812 init_array; the dynamic linker will compute the size of the 1813 array itself based on special symbols created by the static 1814 linker. However, we do need to arrange to set up 1815 exception-handling here. */ 1816 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1817 # define CTOR_LIST_END /* empty */ 1818 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1819 # define DTOR_LIST_END /* empty */ 1820 # else /* !defined (__ARM_EABI__) */ 1821 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1822 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1823 # endif /* !defined (__ARM_EABI__) */ 1824 #endif /* !defined (IN_LIBCC2) */ 1825 1826 /* True if the operating system can merge entities with vague linkage 1827 (e.g., symbols in COMDAT group) during dynamic linking. */ 1828 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1829 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1830 #endif 1831 1832 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1833 1834 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1835 and check its validity for a certain class. 1836 We have two alternate definitions for each of them. 1837 The usual definition accepts all pseudo regs; the other rejects 1838 them unless they have been allocated suitable hard regs. 1839 The symbol REG_OK_STRICT causes the latter definition to be used. 1840 Thumb-2 has the same restrictions as arm. */ 1841 #ifndef REG_OK_STRICT 1842 1843 #define ARM_REG_OK_FOR_BASE_P(X) \ 1844 (REGNO (X) <= LAST_ARM_REGNUM \ 1845 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1846 || REGNO (X) == FRAME_POINTER_REGNUM \ 1847 || REGNO (X) == ARG_POINTER_REGNUM) 1848 1849 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1850 ((REGNO (X) <= LAST_ARM_REGNUM \ 1851 && REGNO (X) != STACK_POINTER_REGNUM) \ 1852 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1853 || REGNO (X) == FRAME_POINTER_REGNUM \ 1854 || REGNO (X) == ARG_POINTER_REGNUM) 1855 1856 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1857 (REGNO (X) <= LAST_LO_REGNUM \ 1858 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1859 || (GET_MODE_SIZE (MODE) >= 4 \ 1860 && (REGNO (X) == STACK_POINTER_REGNUM \ 1861 || (X) == hard_frame_pointer_rtx \ 1862 || (X) == arg_pointer_rtx))) 1863 1864 #define REG_STRICT_P 0 1865 1866 #else /* REG_OK_STRICT */ 1867 1868 #define ARM_REG_OK_FOR_BASE_P(X) \ 1869 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1870 1871 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1872 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1873 1874 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1875 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1876 1877 #define REG_STRICT_P 1 1878 1879 #endif /* REG_OK_STRICT */ 1880 1881 /* Now define some helpers in terms of the above. */ 1882 1883 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1884 (TARGET_THUMB1 \ 1885 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1886 : ARM_REG_OK_FOR_BASE_P (X)) 1887 1888 /* For 16-bit Thumb, a valid index register is anything that can be used in 1889 a byte load instruction. */ 1890 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1891 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1892 1893 /* Nonzero if X is a hard reg that can be used as an index 1894 or if it is a pseudo reg. On the Thumb, the stack pointer 1895 is not suitable. */ 1896 #define REG_OK_FOR_INDEX_P(X) \ 1897 (TARGET_THUMB1 \ 1898 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1899 : ARM_REG_OK_FOR_INDEX_P (X)) 1900 1901 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1902 For Thumb, we can not use SP + reg, so reject SP. */ 1903 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1904 REG_OK_FOR_INDEX_P (X) 1905 1906 #define ARM_BASE_REGISTER_RTX_P(X) \ 1908 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1909 1910 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1911 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1912 1913 /* Specify the machine mode that this machine uses 1915 for the index in the tablejump instruction. */ 1916 #define CASE_VECTOR_MODE Pmode 1917 1918 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 1919 || (TARGET_THUMB1 \ 1920 && (optimize_size || flag_pic))) 1921 1922 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1923 (TARGET_THUMB1 \ 1924 ? (min >= 0 && max < 512 \ 1925 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1926 : min >= -256 && max < 256 \ 1927 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1928 : min >= 0 && max < 8192 \ 1929 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1930 : min >= -4096 && max < 4096 \ 1931 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1932 : SImode) \ 1933 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1934 : (max >= 0x200) ? HImode \ 1935 : QImode)) 1936 1937 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1938 unsigned is probably best, but may break some code. */ 1939 #ifndef DEFAULT_SIGNED_CHAR 1940 #define DEFAULT_SIGNED_CHAR 0 1941 #endif 1942 1943 /* Max number of bytes we can move from memory to memory 1944 in one reasonably fast instruction. */ 1945 #define MOVE_MAX 4 1946 1947 #undef MOVE_RATIO 1948 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 1949 1950 /* Define if operations between registers always perform the operation 1951 on the full register even if a narrower mode is specified. */ 1952 #define WORD_REGISTER_OPERATIONS 1 1953 1954 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1955 will either zero-extend or sign-extend. The value of this macro should 1956 be the code that says which one of the two operations is implicitly 1957 done, UNKNOWN if none. */ 1958 #define LOAD_EXTEND_OP(MODE) \ 1959 (TARGET_THUMB ? ZERO_EXTEND : \ 1960 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 1961 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 1962 1963 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1964 #define SLOW_BYTE_ACCESS 0 1965 1966 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 1967 1968 /* Immediate shift counts are truncated by the output routines (or was it 1969 the assembler?). Shift counts in a register are truncated by ARM. Note 1970 that the native compiler puts too large (> 32) immediate shift counts 1971 into a register and shifts by the register, letting the ARM decide what 1972 to do instead of doing that itself. */ 1973 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1974 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1975 On the arm, Y in a register is used modulo 256 for the shift. Only for 1976 rotates is modulo 32 used. */ 1977 /* #define SHIFT_COUNT_TRUNCATED 1 */ 1978 1979 /* All integers have the same format so truncation is easy. */ 1980 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1981 1982 /* Calling from registers is a massive pain. */ 1983 #define NO_FUNCTION_CSE 1 1984 1985 /* The machine modes of pointers and functions */ 1986 #define Pmode SImode 1987 #define FUNCTION_MODE Pmode 1988 1989 #define ARM_FRAME_RTX(X) \ 1990 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1991 || (X) == arg_pointer_rtx) 1992 1993 /* Try to generate sequences that don't involve branches, we can then use 1994 conditional instructions. */ 1995 #define BRANCH_COST(speed_p, predictable_p) \ 1996 (current_tune->branch_cost (speed_p, predictable_p)) 1997 1998 /* False if short circuit operation is preferred. */ 1999 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 2000 ((optimize_size) \ 2001 ? (TARGET_THUMB ? false : true) \ 2002 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 2003 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 2004 2005 2006 /* Position Independent Code. */ 2008 /* We decide which register to use based on the compilation options and 2009 the assembler in use; this is more general than the APCS restriction of 2010 using sb (r9) all the time. */ 2011 extern unsigned arm_pic_register; 2012 2013 /* The register number of the register used to address a table of static 2014 data addresses in memory. */ 2015 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2016 2017 /* We can't directly access anything that contains a symbol, 2018 nor can we indirect via the constant pool. One exception is 2019 UNSPEC_TLS, which is always PIC. */ 2020 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2021 (!(symbol_mentioned_p (X) \ 2022 || label_mentioned_p (X) \ 2023 || (GET_CODE (X) == SYMBOL_REF \ 2024 && CONSTANT_POOL_ADDRESS_P (X) \ 2025 && (symbol_mentioned_p (get_pool_constant (X)) \ 2026 || label_mentioned_p (get_pool_constant (X))))) \ 2027 || tls_mentioned_p (X)) 2028 2029 /* We need to know when we are making a constant pool; this determines 2030 whether data needs to be in the GOT or can be referenced via a GOT 2031 offset. */ 2032 extern int making_const_table; 2033 2034 /* Handle pragmas for compatibility with Intel's compilers. */ 2036 /* Also abuse this to register additional C specific EABI attributes. */ 2037 #define REGISTER_TARGET_PRAGMAS() do { \ 2038 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2039 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2040 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2041 arm_lang_object_attributes_init(); \ 2042 arm_register_target_pragmas(); \ 2043 } while (0) 2044 2045 /* Condition code information. */ 2046 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2047 return the mode to be used for the comparison. */ 2048 2049 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2050 2051 #define REVERSIBLE_CC_MODE(MODE) 1 2052 2053 #define REVERSE_CONDITION(CODE,MODE) \ 2054 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2055 ? reverse_condition_maybe_unordered (code) \ 2056 : reverse_condition (code)) 2057 2058 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2059 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2060 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2061 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2062 2063 #define CC_STATUS_INIT \ 2065 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2066 2067 #undef ASM_APP_ON 2068 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2069 "\t.syntax divided\n") 2070 2071 #undef ASM_APP_OFF 2072 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2073 "\t.thumb\n\t.syntax unified\n") 2074 2075 /* Output a push or a pop instruction (only used when profiling). 2076 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2077 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2078 that r7 isn't used by the function profiler, so we can use it as a 2079 scratch reg. WARNING: This isn't safe in the general case! It may be 2080 sensitive to future changes in final.c:profile_function. */ 2081 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2082 do \ 2083 { \ 2084 if (TARGET_THUMB1 \ 2085 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2086 { \ 2087 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2088 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2089 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2090 } \ 2091 else \ 2092 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2093 } while (0) 2094 2095 2096 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2097 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2098 do \ 2099 { \ 2100 if (TARGET_THUMB1 \ 2101 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2102 { \ 2103 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2104 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2105 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2106 } \ 2107 else \ 2108 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2109 } while (0) 2110 2111 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2112 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2113 2114 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2115 default alignment from elfos.h. */ 2116 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2117 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2118 2119 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2120 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2121 ? 1 : 0) 2122 2123 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2124 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2125 2126 /* For aliases of functions we use .thumb_set instead. */ 2127 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2128 do \ 2129 { \ 2130 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2131 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2132 \ 2133 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2134 { \ 2135 fprintf (FILE, "\t.thumb_set "); \ 2136 assemble_name (FILE, LABEL1); \ 2137 fprintf (FILE, ","); \ 2138 assemble_name (FILE, LABEL2); \ 2139 fprintf (FILE, "\n"); \ 2140 } \ 2141 else \ 2142 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2143 } \ 2144 while (0) 2145 2146 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2147 /* To support -falign-* switches we need to use .p2align so 2148 that alignment directives in code sections will be padded 2149 with no-op instructions, rather than zeroes. */ 2150 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2151 if ((LOG) != 0) \ 2152 { \ 2153 if ((MAX_SKIP) == 0) \ 2154 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2155 else \ 2156 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2157 (int) (LOG), (int) (MAX_SKIP)); \ 2158 } 2159 #endif 2160 2161 /* Add two bytes to the length of conditionally executed Thumb-2 2163 instructions for the IT instruction. */ 2164 #define ADJUST_INSN_LENGTH(insn, length) \ 2165 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2166 length += 2; 2167 2168 /* Only perform branch elimination (by making instructions conditional) if 2169 we're optimizing. For Thumb-2 check if any IT instructions need 2170 outputting. */ 2171 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2172 if (TARGET_ARM && optimize) \ 2173 arm_final_prescan_insn (INSN); \ 2174 else if (TARGET_THUMB2) \ 2175 thumb2_final_prescan_insn (INSN); \ 2176 else if (TARGET_THUMB1) \ 2177 thumb1_final_prescan_insn (INSN) 2178 2179 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2180 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2181 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2182 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2183 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2184 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2185 : 0)))) 2186 2187 /* A C expression whose value is RTL representing the value of the return 2188 address for the frame COUNT steps up from the current frame. */ 2189 2190 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2191 arm_return_addr (COUNT, FRAME) 2192 2193 /* Mask of the bits in the PC that contain the real return address 2194 when running in 26-bit mode. */ 2195 #define RETURN_ADDR_MASK26 (0x03fffffc) 2196 2197 /* Pick up the return address upon entry to a procedure. Used for 2198 dwarf2 unwind information. This also enables the table driven 2199 mechanism. */ 2200 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2201 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2202 2203 /* Used to mask out junk bits from the return address, such as 2204 processor state, interrupt status, condition codes and the like. */ 2205 #define MASK_RETURN_ADDR \ 2206 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2207 in 26 bit mode, the condition codes must be masked out of the \ 2208 return address. This does not apply to ARM6 and later processors \ 2209 when running in 32 bit mode. */ \ 2210 ((arm_arch4 || TARGET_THUMB) \ 2211 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2212 : arm_gen_return_addr_mask ()) 2213 2214 2215 /* Do not emit .note.GNU-stack by default. */ 2217 #ifndef NEED_INDICATE_EXEC_STACK 2218 #define NEED_INDICATE_EXEC_STACK 0 2219 #endif 2220 2221 #define TARGET_ARM_ARCH \ 2222 (arm_base_arch) \ 2223 2224 #define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) 2225 #define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) 2226 2227 /* The highest Thumb instruction set version supported by the chip. */ 2228 #define TARGET_ARM_ARCH_ISA_THUMB \ 2229 (arm_arch_thumb2 ? 2 \ 2230 : ((TARGET_ARM_ARCH >= 5 || arm_arch4t) ? 1 : 0)) 2231 2232 /* Expands to an upper-case char of the target's architectural 2233 profile. */ 2234 #define TARGET_ARM_ARCH_PROFILE \ 2235 (!arm_arch_notm \ 2236 ? 'M' \ 2237 : (arm_arch7 \ 2238 ? (strlen (arm_arch_name) >=3 \ 2239 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2240 : 0) \ 2241 : 0)) 2242 2243 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2244 Bit 0 for bytes, up to bit 3 for double-words. */ 2245 #define TARGET_ARM_FEATURE_LDREX \ 2246 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2247 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2248 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2249 2250 /* Set as a bit mask indicating the available widths of hardware floating 2251 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2252 32-bit support, bit 3 indicates 64-bit support. */ 2253 #define TARGET_ARM_FP \ 2254 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2255 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2256 : 0) 2257 2258 2259 /* Set as a bit mask indicating the available widths of floating point 2260 types for hardware NEON floating point. This is the same as 2261 TARGET_ARM_FP without the 64-bit bit set. */ 2262 #define TARGET_NEON_FP \ 2263 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2264 : 0) 2265 2266 /* The maximum number of parallel loads or stores we support in an ldm/stm 2267 instruction. */ 2268 #define MAX_LDM_STM_OPS 4 2269 2270 #define BIG_LITTLE_SPEC \ 2271 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2272 2273 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2274 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2275 { "rewrite_mcpu", arm_rewrite_mcpu }, 2276 2277 #define ASM_CPU_SPEC \ 2278 " %{mcpu=generic-*:-march=%*;" \ 2279 " :%{march=*:-march=%*}}" \ 2280 BIG_LITTLE_SPEC 2281 2282 /* -mcpu=native handling only makes sense with compiler running on 2283 an ARM chip. */ 2284 #if defined(__arm__) && defined(__linux__) 2285 extern const char *host_detect_local_cpu (int argc, const char **argv); 2286 # define EXTRA_SPEC_FUNCTIONS \ 2287 { "local_cpu_detect", host_detect_local_cpu }, \ 2288 BIG_LITTLE_CPU_SPEC_FUNCTIONS 2289 2290 # define MCPU_MTUNE_NATIVE_SPECS \ 2291 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2292 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2293 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2294 #else 2295 # define MCPU_MTUNE_NATIVE_SPECS "" 2296 # define EXTRA_SPEC_FUNCTIONS BIG_LITTLE_CPU_SPEC_FUNCTIONS 2297 #endif 2298 2299 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS 2300 #define TARGET_SUPPORTS_WIDE_INT 1 2301 2302 /* For switching between functions with different target attributes. */ 2303 #define SWITCHABLE_TARGET 1 2304 2305 #endif /* ! GCC_ARM_H */ 2306
Indexes created Wed Apr 15 00:22:22 UTC 2026