arm.h revision 1.1.1.7
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2017 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 #include "config/arm/arm-opts.h" 51 52 /* The processor for which instructions should be scheduled. */ 53 extern enum processor_type arm_tune; 54 55 typedef enum arm_cond_code 56 { 57 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 58 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 59 } 60 arm_cc; 61 62 extern arm_cc arm_current_cc; 63 64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 65 66 /* The maximum number of instructions that is beneficial to 67 conditionally execute. */ 68 #undef MAX_CONDITIONAL_EXECUTE 69 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 70 71 extern int arm_target_label; 72 extern int arm_ccfsm_state; 73 extern GTY(()) rtx arm_target_insn; 74 /* Callback to output language specific object attributes. */ 75 extern void (*arm_lang_output_object_attributes_hook)(void); 76 77 /* This type is the user-visible __fp16. We need it in a few places in 78 the backend. Defined in arm-builtins.c. */ 79 extern tree arm_fp16_type_node; 80 81 82 #undef CPP_SPEC 84 #define CPP_SPEC "%(subtarget_cpp_spec) \ 85 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 86 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 87 %{mbig-endian:%{mlittle-endian: \ 88 %e-mbig-endian and -mlittle-endian may not be used together}}" 89 90 #ifndef CC1_SPEC 91 #define CC1_SPEC "" 92 #endif 93 94 /* This macro defines names of additional specifications to put in the specs 95 that can be used in various specifications like CC1_SPEC. Its definition 96 is an initializer with a subgrouping for each command option. 97 98 Each subgrouping contains a string constant, that defines the 99 specification name, and a string constant that used by the GCC driver 100 program. 101 102 Do not define this macro if it does not need to do anything. */ 103 #define EXTRA_SPECS \ 104 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 105 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 106 SUBTARGET_EXTRA_SPECS 107 108 #ifndef SUBTARGET_EXTRA_SPECS 109 #define SUBTARGET_EXTRA_SPECS 110 #endif 111 112 #ifndef SUBTARGET_CPP_SPEC 113 #define SUBTARGET_CPP_SPEC "" 114 #endif 115 116 /* Tree Target Specification. */ 118 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 119 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 120 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 121 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 122 123 /* Run-time Target Specification. */ 124 #define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 125 /* Use hardware floating point instructions. */ 126 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 127 /* Use hardware floating point calling convention. */ 128 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 129 #define TARGET_IWMMXT (arm_arch_iwmmxt) 130 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 131 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 132 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 133 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 134 #define TARGET_ARM (! TARGET_THUMB) 135 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 136 #define TARGET_BACKTRACE (crtl->is_leaf \ 137 ? TARGET_TPCS_LEAF_FRAME \ 138 : TARGET_TPCS_FRAME) 139 #define TARGET_AAPCS_BASED \ 140 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 141 142 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 143 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 144 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 145 146 /* Only 16-bit thumb code. */ 147 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 148 /* Arm or Thumb-2 32-bit code. */ 149 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 150 /* 32-bit Thumb-2 code. */ 151 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 152 /* Thumb-1 only. */ 153 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 154 155 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 156 && !TARGET_THUMB1) 157 158 #define TARGET_CRC32 (arm_arch_crc) 159 160 /* The following two macros concern the ability to execute coprocessor 161 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 162 only ever tested when we know we are generating for VFP hardware; we need 163 to be more careful with TARGET_NEON as noted below. */ 164 165 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 166 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 167 168 /* FPU supports VFPv3 instructions. */ 169 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv3)) 170 171 /* FPU supports FPv5 instructions. */ 172 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_FPv5)) 173 174 /* FPU only supports VFP single-precision instructions. */ 175 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 176 177 /* FPU supports VFP double-precision instructions. */ 178 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 179 180 /* FPU supports half-precision floating-point with NEON element load/store. */ 181 #define TARGET_NEON_FP16 \ 182 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 183 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 184 185 /* FPU supports VFP half-precision floating-point conversions. */ 186 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 187 188 /* FPU supports converting between HFmode and DFmode in a single hardware 189 step. */ 190 #define TARGET_FP16_TO_DOUBLE \ 191 (TARGET_HARD_FLOAT && (TARGET_FP16 && TARGET_VFP5)) 192 193 /* FPU supports fused-multiply-add operations. */ 194 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv4)) 195 196 /* FPU is ARMv8 compatible. */ 197 #define TARGET_FPU_ARMV8 \ 198 (bitmap_bit_p (arm_active_target.isa, isa_bit_FP_ARMv8)) 199 200 /* FPU supports Crypto extensions. */ 201 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 202 203 /* FPU supports Neon instructions. The setting of this macro gets 204 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 205 and TARGET_HARD_FLOAT to ensure that NEON instructions are 206 available. */ 207 #define TARGET_NEON \ 208 (TARGET_32BIT && TARGET_HARD_FLOAT \ 209 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 210 211 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 212 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 213 214 /* FPU supports the floating point FP16 instructions for ARMv8.2 and later. */ 215 #define TARGET_VFP_FP16INST \ 216 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_FPU_ARMV8 && arm_fp16_inst) 217 218 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 219 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 220 221 /* Q-bit is present. */ 222 #define TARGET_ARM_QBIT \ 223 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 224 /* Saturation operation, e.g. SSAT. */ 225 #define TARGET_ARM_SAT \ 226 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 227 /* "DSP" multiply instructions, eg. SMULxy. */ 228 #define TARGET_DSP_MULTIPLY \ 229 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 230 /* Integer SIMD instructions, and extend-accumulate instructions. */ 231 #define TARGET_INT_SIMD \ 232 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 233 234 /* Should MOVW/MOVT be used in preference to a constant pool. */ 235 #define TARGET_USE_MOVT \ 236 (TARGET_HAVE_MOVT \ 237 && (arm_disable_literal_pool \ 238 || (!optimize_size && !current_tune->prefer_constant_pool))) 239 240 /* Nonzero if this chip provides the DMB instruction. */ 241 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 242 243 /* Nonzero if this chip implements a memory barrier via CP15. */ 244 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 245 && ! TARGET_THUMB1) 246 247 /* Nonzero if this chip implements a memory barrier instruction. */ 248 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 249 250 /* Nonzero if this chip supports ldrex and strex */ 251 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 252 || arm_arch7 \ 253 || (arm_arch8 && !arm_arch_notm)) 254 255 /* Nonzero if this chip supports LPAE. */ 256 #define TARGET_HAVE_LPAE (arm_arch_lpae) 257 258 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 259 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 260 || arm_arch7 \ 261 || (arm_arch8 && !arm_arch_notm)) 262 263 /* Nonzero if this chip supports ldrexd and strexd. */ 264 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 265 || arm_arch7) && arm_arch_notm) 266 267 /* Nonzero if this chip supports load-acquire and store-release. */ 268 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 269 270 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 271 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 272 && TARGET_32BIT \ 273 && arm_arch_notm) 274 275 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 276 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 277 278 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 279 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 280 281 /* Nonzero if integer division instructions supported. */ 282 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 283 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 284 285 /* Nonzero if disallow volatile memory access in IT block. */ 286 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 287 288 /* Should NEON be used for 64-bits bitops. */ 289 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 290 291 /* Should constant I be slplit for OP. */ 292 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 293 ((optimize >= 2) \ 294 && can_create_pseudo_p () \ 295 && !const_ok_for_op (i, op)) 296 297 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 298 then TARGET_AAPCS_BASED must be true -- but the converse does not 299 hold. TARGET_BPABI implies the use of the BPABI runtime library, 300 etc., in addition to just the AAPCS calling conventions. */ 301 #ifndef TARGET_BPABI 302 #define TARGET_BPABI false 303 #endif 304 305 /* Transform lane numbers on big endian targets. This is used to allow for the 306 endianness difference between NEON architectural lane numbers and those 307 used in RTL */ 308 #define NEON_ENDIAN_LANE_N(mode, n) \ 309 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 310 311 /* Support for a compile-time default CPU, et cetera. The rules are: 312 --with-arch is ignored if -march or -mcpu are specified. 313 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 314 by --with-arch. 315 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 316 by -march). 317 --with-float is ignored if -mfloat-abi is specified. 318 --with-fpu is ignored if -mfpu is specified. 319 --with-abi is ignored if -mabi is specified. 320 --with-tls is ignored if -mtls-dialect is specified. */ 321 #define OPTION_DEFAULT_SPECS \ 322 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 323 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 324 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 325 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 326 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 327 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 328 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 329 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 330 331 extern const struct arm_fpu_desc 332 { 333 const char *name; 334 enum isa_feature isa_bits[isa_num_bits]; 335 } all_fpus[]; 336 337 /* Which floating point hardware to schedule for. */ 338 extern int arm_fpu_attr; 339 340 #ifndef TARGET_DEFAULT_FLOAT_ABI 341 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 342 #endif 343 344 #ifndef ARM_DEFAULT_ABI 345 #define ARM_DEFAULT_ABI ARM_ABI_APCS 346 #endif 347 348 /* AAPCS based ABIs use short enums by default. */ 349 #ifndef ARM_DEFAULT_SHORT_ENUMS 350 #define ARM_DEFAULT_SHORT_ENUMS \ 351 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 352 #endif 353 354 /* Map each of the micro-architecture variants to their corresponding 355 major architecture revision. */ 356 357 enum base_architecture 358 { 359 BASE_ARCH_0 = 0, 360 BASE_ARCH_2 = 2, 361 BASE_ARCH_3 = 3, 362 BASE_ARCH_3M = 3, 363 BASE_ARCH_4 = 4, 364 BASE_ARCH_4T = 4, 365 BASE_ARCH_5 = 5, 366 BASE_ARCH_5E = 5, 367 BASE_ARCH_5T = 5, 368 BASE_ARCH_5TE = 5, 369 BASE_ARCH_5TEJ = 5, 370 BASE_ARCH_6 = 6, 371 BASE_ARCH_6J = 6, 372 BASE_ARCH_6KZ = 6, 373 BASE_ARCH_6K = 6, 374 BASE_ARCH_6T2 = 6, 375 BASE_ARCH_6M = 6, 376 BASE_ARCH_6Z = 6, 377 BASE_ARCH_7 = 7, 378 BASE_ARCH_7A = 7, 379 BASE_ARCH_7R = 7, 380 BASE_ARCH_7M = 7, 381 BASE_ARCH_7EM = 7, 382 BASE_ARCH_8A = 8, 383 BASE_ARCH_8M_BASE = 8, 384 BASE_ARCH_8M_MAIN = 8 385 }; 386 387 /* The major revision number of the ARM Architecture implemented by the target. */ 388 extern enum base_architecture arm_base_arch; 389 390 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 391 extern int arm_arch3m; 392 393 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 394 extern int arm_arch4; 395 396 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 397 extern int arm_arch4t; 398 399 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 400 extern int arm_arch5; 401 402 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 403 extern int arm_arch5e; 404 405 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 406 extern int arm_arch6; 407 408 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 409 extern int arm_arch6k; 410 411 /* Nonzero if instructions present in ARMv6-M can be used. */ 412 extern int arm_arch6m; 413 414 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 415 extern int arm_arch7; 416 417 /* Nonzero if instructions not present in the 'M' profile can be used. */ 418 extern int arm_arch_notm; 419 420 /* Nonzero if instructions present in ARMv7E-M can be used. */ 421 extern int arm_arch7em; 422 423 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 424 extern int arm_arch8; 425 426 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 427 extern int arm_arch8_1; 428 429 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 430 extern int arm_arch8_2; 431 432 /* Nonzero if this chip supports the FP16 instructions extension of ARM 433 Architecture 8.2. */ 434 extern int arm_fp16_inst; 435 436 /* Nonzero if this chip can benefit from load scheduling. */ 437 extern int arm_ld_sched; 438 439 /* Nonzero if this chip is a StrongARM. */ 440 extern int arm_tune_strongarm; 441 442 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 443 extern int arm_arch_iwmmxt; 444 445 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 446 extern int arm_arch_iwmmxt2; 447 448 /* Nonzero if this chip is an XScale. */ 449 extern int arm_arch_xscale; 450 451 /* Nonzero if tuning for XScale. */ 452 extern int arm_tune_xscale; 453 454 /* Nonzero if tuning for stores via the write buffer. */ 455 extern int arm_tune_wbuf; 456 457 /* Nonzero if tuning for Cortex-A9. */ 458 extern int arm_tune_cortex_a9; 459 460 /* Nonzero if we should define __THUMB_INTERWORK__ in the 461 preprocessor. 462 XXX This is a bit of a hack, it's intended to help work around 463 problems in GLD which doesn't understand that armv5t code is 464 interworking clean. */ 465 extern int arm_cpp_interwork; 466 467 /* Nonzero if chip supports Thumb 1. */ 468 extern int arm_arch_thumb1; 469 470 /* Nonzero if chip supports Thumb 2. */ 471 extern int arm_arch_thumb2; 472 473 /* Nonzero if chip supports integer division instruction in ARM mode. */ 474 extern int arm_arch_arm_hwdiv; 475 476 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 477 extern int arm_arch_thumb_hwdiv; 478 479 /* Nonzero if chip disallows volatile memory access in IT block. */ 480 extern int arm_arch_no_volatile_ce; 481 482 /* Nonzero if we should use Neon to handle 64-bits operations rather 483 than core registers. */ 484 extern int prefer_neon_for_64bits; 485 486 /* Nonzero if we shouldn't use literal pools. */ 487 #ifndef USED_FOR_TARGET 488 extern bool arm_disable_literal_pool; 489 #endif 490 491 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 492 extern int arm_arch_crc; 493 494 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 495 extern int arm_arch_cmse; 496 497 #ifndef TARGET_DEFAULT 498 #define TARGET_DEFAULT (MASK_APCS_FRAME) 499 #endif 500 501 /* Nonzero if PIC code requires explicit qualifiers to generate 502 PLT and GOT relocs rather than the assembler doing so implicitly. 503 Subtargets can override these if required. */ 504 #ifndef NEED_GOT_RELOC 505 #define NEED_GOT_RELOC 0 506 #endif 507 #ifndef NEED_PLT_RELOC 508 #define NEED_PLT_RELOC 0 509 #endif 510 511 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 512 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 513 #endif 514 515 /* Nonzero if we need to refer to the GOT with a PC-relative 516 offset. In other words, generate 517 518 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 519 520 rather than 521 522 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 523 524 The default is true, which matches NetBSD. Subtargets can 525 override this if required. */ 526 #ifndef GOT_PCREL 527 #define GOT_PCREL 1 528 #endif 529 530 /* Target machine storage Layout. */ 532 533 534 /* Define this macro if it is advisable to hold scalars in registers 535 in a wider mode than that declared by the program. In such cases, 536 the value is constrained to be within the bounds of the declared 537 type, but kept valid in the wider mode. The signedness of the 538 extension may differ from that of the type. */ 539 540 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 541 if (GET_MODE_CLASS (MODE) == MODE_INT \ 542 && GET_MODE_SIZE (MODE) < 4) \ 543 { \ 544 (MODE) = SImode; \ 545 } 546 547 /* Define this if most significant bit is lowest numbered 548 in instructions that operate on numbered bit-fields. */ 549 #define BITS_BIG_ENDIAN 0 550 551 /* Define this if most significant byte of a word is the lowest numbered. 552 Most ARM processors are run in little endian mode, so that is the default. 553 If you want to have it run-time selectable, change the definition in a 554 cover file to be TARGET_BIG_ENDIAN. */ 555 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 556 557 /* Define this if most significant word of a multiword number is the lowest 558 numbered. */ 559 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 560 561 #define UNITS_PER_WORD 4 562 563 /* True if natural alignment is used for doubleword types. */ 564 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 565 566 #define DOUBLEWORD_ALIGNMENT 64 567 568 #define PARM_BOUNDARY 32 569 570 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 571 572 #define PREFERRED_STACK_BOUNDARY \ 573 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 574 575 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 576 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 577 578 /* The lowest bit is used to indicate Thumb-mode functions, so the 579 vbit must go into the delta field of pointers to member 580 functions. */ 581 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 582 583 #define EMPTY_FIELD_BOUNDARY 32 584 585 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 586 587 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 588 589 /* XXX Blah -- this macro is used directly by libobjc. Since it 590 supports no vector modes, cut out the complexity and fall back 591 on BIGGEST_FIELD_ALIGNMENT. */ 592 #ifdef IN_TARGET_LIBS 593 #define BIGGEST_FIELD_ALIGNMENT 64 594 #endif 595 596 /* Make strings word-aligned so strcpy from constants will be faster. */ 597 #define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 598 599 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 600 ((TREE_CODE (EXP) == STRING_CST \ 601 && !optimize_size \ 602 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 603 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 604 605 /* Align definitions of arrays, unions and structures so that 606 initializations and copies can be made more efficient. This is not 607 ABI-changing, so it only affects places where we can see the 608 definition. Increasing the alignment tends to introduce padding, 609 so don't do this when optimizing for size/conserving stack space. */ 610 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 611 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 612 && (TREE_CODE (EXP) == ARRAY_TYPE \ 613 || TREE_CODE (EXP) == UNION_TYPE \ 614 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 615 616 /* Align global data. */ 617 #define DATA_ALIGNMENT(EXP, ALIGN) \ 618 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 619 620 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 621 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 622 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 623 624 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 625 value set in previous versions of this toolchain was 8, which produces more 626 compact structures. The command line option -mstructure_size_boundary=<n> 627 can be used to change this value. For compatibility with the ARM SDK 628 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 629 0020D) page 2-20 says "Structures are aligned on word boundaries". 630 The AAPCS specifies a value of 8. */ 631 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 632 633 /* This is the value used to initialize arm_structure_size_boundary. If a 634 particular arm target wants to change the default value it should change 635 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 636 for an example of this. */ 637 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 638 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 639 #endif 640 641 /* Nonzero if move instructions will actually fail to work 642 when given unaligned data. */ 643 #define STRICT_ALIGNMENT 1 644 645 /* wchar_t is unsigned under the AAPCS. */ 646 #ifndef WCHAR_TYPE 647 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 648 649 #define WCHAR_TYPE_SIZE BITS_PER_WORD 650 #endif 651 652 /* Sized for fixed-point types. */ 653 654 #define SHORT_FRACT_TYPE_SIZE 8 655 #define FRACT_TYPE_SIZE 16 656 #define LONG_FRACT_TYPE_SIZE 32 657 #define LONG_LONG_FRACT_TYPE_SIZE 64 658 659 #define SHORT_ACCUM_TYPE_SIZE 16 660 #define ACCUM_TYPE_SIZE 32 661 #define LONG_ACCUM_TYPE_SIZE 64 662 #define LONG_LONG_ACCUM_TYPE_SIZE 64 663 664 #define MAX_FIXED_MODE_SIZE 64 665 666 #ifndef SIZE_TYPE 667 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 668 #endif 669 670 #ifndef PTRDIFF_TYPE 671 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 672 #endif 673 674 /* AAPCS requires that structure alignment is affected by bitfields. */ 675 #ifndef PCC_BITFIELD_TYPE_MATTERS 676 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 677 #endif 678 679 /* The maximum size of the sync library functions supported. */ 680 #ifndef MAX_SYNC_LIBFUNC_SIZE 681 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 682 #endif 683 684 685 /* Standard register usage. */ 687 688 /* Register allocation in ARM Procedure Call Standard 689 (S - saved over call). 690 691 r0 * argument word/integer result 692 r1-r3 argument word 693 694 r4-r8 S register variable 695 r9 S (rfp) register variable (real frame pointer) 696 697 r10 F S (sl) stack limit (used by -mapcs-stack-check) 698 r11 F S (fp) argument pointer 699 r12 (ip) temp workspace 700 r13 F S (sp) lower end of current stack frame 701 r14 (lr) link address/workspace 702 r15 F (pc) program counter 703 704 cc This is NOT a real register, but is used internally 705 to represent things that use or set the condition 706 codes. 707 sfp This isn't either. It is used during rtl generation 708 since the offset between the frame pointer and the 709 auto's isn't known until after register allocation. 710 afp Nor this, we only need this because of non-local 711 goto. Without it fp appears to be used and the 712 elimination code won't get rid of sfp. It tracks 713 fp exactly at all times. 714 715 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 716 717 /* s0-s15 VFP scratch (aka d0-d7). 718 s16-s31 S VFP variable (aka d8-d15). 719 vfpcc Not a real register. Represents the VFP condition 720 code flags. */ 721 722 /* The stack backtrace structure is as follows: 723 fp points to here: | save code pointer | [fp] 724 | return link value | [fp, #-4] 725 | return sp value | [fp, #-8] 726 | return fp value | [fp, #-12] 727 [| saved r10 value |] 728 [| saved r9 value |] 729 [| saved r8 value |] 730 [| saved r7 value |] 731 [| saved r6 value |] 732 [| saved r5 value |] 733 [| saved r4 value |] 734 [| saved r3 value |] 735 [| saved r2 value |] 736 [| saved r1 value |] 737 [| saved r0 value |] 738 r0-r3 are not normally saved in a C function. */ 739 740 /* 1 for registers that have pervasive standard uses 741 and are not available for the register allocator. */ 742 #define FIXED_REGISTERS \ 743 { \ 744 /* Core regs. */ \ 745 0,0,0,0,0,0,0,0, \ 746 0,0,0,0,0,1,0,1, \ 747 /* VFP regs. */ \ 748 1,1,1,1,1,1,1,1, \ 749 1,1,1,1,1,1,1,1, \ 750 1,1,1,1,1,1,1,1, \ 751 1,1,1,1,1,1,1,1, \ 752 1,1,1,1,1,1,1,1, \ 753 1,1,1,1,1,1,1,1, \ 754 1,1,1,1,1,1,1,1, \ 755 1,1,1,1,1,1,1,1, \ 756 /* IWMMXT regs. */ \ 757 1,1,1,1,1,1,1,1, \ 758 1,1,1,1,1,1,1,1, \ 759 1,1,1,1, \ 760 /* Specials. */ \ 761 1,1,1,1 \ 762 } 763 764 /* 1 for registers not available across function calls. 765 These must include the FIXED_REGISTERS and also any 766 registers that can be used without being saved. 767 The latter must include the registers where values are returned 768 and the register where structure-value addresses are passed. 769 Aside from that, you can include as many other registers as you like. 770 The CC is not preserved over function calls on the ARM 6, so it is 771 easier to assume this for all. SFP is preserved, since FP is. */ 772 #define CALL_USED_REGISTERS \ 773 { \ 774 /* Core regs. */ \ 775 1,1,1,1,0,0,0,0, \ 776 0,0,0,0,1,1,1,1, \ 777 /* VFP Regs. */ \ 778 1,1,1,1,1,1,1,1, \ 779 1,1,1,1,1,1,1,1, \ 780 1,1,1,1,1,1,1,1, \ 781 1,1,1,1,1,1,1,1, \ 782 1,1,1,1,1,1,1,1, \ 783 1,1,1,1,1,1,1,1, \ 784 1,1,1,1,1,1,1,1, \ 785 1,1,1,1,1,1,1,1, \ 786 /* IWMMXT regs. */ \ 787 1,1,1,1,1,1,1,1, \ 788 1,1,1,1,1,1,1,1, \ 789 1,1,1,1, \ 790 /* Specials. */ \ 791 1,1,1,1 \ 792 } 793 794 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 795 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 796 #endif 797 798 /* These are a couple of extensions to the formats accepted 799 by asm_fprintf: 800 %@ prints out ASM_COMMENT_START 801 %r prints out REGISTER_PREFIX reg_names[arg] */ 802 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 803 case '@': \ 804 fputs (ASM_COMMENT_START, FILE); \ 805 break; \ 806 \ 807 case 'r': \ 808 fputs (REGISTER_PREFIX, FILE); \ 809 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 810 break; 811 812 /* Round X up to the nearest word. */ 813 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 814 815 /* Convert fron bytes to ints. */ 816 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 817 818 /* The number of (integer) registers required to hold a quantity of type MODE. 819 Also used for VFP registers. */ 820 #define ARM_NUM_REGS(MODE) \ 821 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 822 823 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 824 #define ARM_NUM_REGS2(MODE, TYPE) \ 825 ARM_NUM_INTS ((MODE) == BLKmode ? \ 826 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 827 828 /* The number of (integer) argument register available. */ 829 #define NUM_ARG_REGS 4 830 831 /* And similarly for the VFP. */ 832 #define NUM_VFP_ARG_REGS 16 833 834 /* Return the register number of the N'th (integer) argument. */ 835 #define ARG_REGISTER(N) (N - 1) 836 837 /* Specify the registers used for certain standard purposes. 838 The values of these macros are register numbers. */ 839 840 /* The number of the last argument register. */ 841 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 842 843 /* The numbers of the Thumb register ranges. */ 844 #define FIRST_LO_REGNUM 0 845 #define LAST_LO_REGNUM 7 846 #define FIRST_HI_REGNUM 8 847 #define LAST_HI_REGNUM 11 848 849 /* Overridden by config/arm/bpabi.h. */ 850 #ifndef ARM_UNWIND_INFO 851 #define ARM_UNWIND_INFO 0 852 #endif 853 854 /* Overriden by config/arm/netbsd-eabi.h. */ 855 #ifndef ARM_DWARF_UNWIND_TABLES 856 #define ARM_DWARF_UNWIND_TABLES 0 857 #endif 858 859 /* Use r0 and r1 to pass exception handling information. */ 860 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 861 862 /* The register that holds the return address in exception handlers. */ 863 #define ARM_EH_STACKADJ_REGNUM 2 864 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 865 866 #ifndef ARM_TARGET2_DWARF_FORMAT 867 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 868 #endif 869 870 #if ARM_DWARF_UNWIND_TABLES 871 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 872 for 32bit platforms. */ 873 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 874 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 875 : DW_EH_PE_absptr) 876 #else 877 /* ttype entries (the only interesting data references used) 878 use TARGET2 relocations. */ 879 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 880 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 881 : DW_EH_PE_absptr) 882 #endif 883 884 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 885 as an invisible last argument (possible since varargs don't exist in 886 Pascal), so the following is not true. */ 887 #define STATIC_CHAIN_REGNUM 12 888 889 /* Define this to be where the real frame pointer is if it is not possible to 890 work out the offset between the frame pointer and the automatic variables 891 until after register allocation has taken place. FRAME_POINTER_REGNUM 892 should point to a special register that we will make sure is eliminated. 893 894 For the Thumb we have another problem. The TPCS defines the frame pointer 895 as r11, and GCC believes that it is always possible to use the frame pointer 896 as base register for addressing purposes. (See comments in 897 find_reloads_address()). But - the Thumb does not allow high registers, 898 including r11, to be used as base address registers. Hence our problem. 899 900 The solution used here, and in the old thumb port is to use r7 instead of 901 r11 as the hard frame pointer and to have special code to generate 902 backtrace structures on the stack (if required to do so via a command line 903 option) using r11. This is the only 'user visible' use of r11 as a frame 904 pointer. */ 905 #define ARM_HARD_FRAME_POINTER_REGNUM 11 906 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 907 908 #define HARD_FRAME_POINTER_REGNUM \ 909 (TARGET_ARM \ 910 ? ARM_HARD_FRAME_POINTER_REGNUM \ 911 : THUMB_HARD_FRAME_POINTER_REGNUM) 912 913 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 914 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 915 916 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 917 918 /* Register to use for pushing function arguments. */ 919 #define STACK_POINTER_REGNUM SP_REGNUM 920 921 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 922 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 923 924 /* Need to sync with WCGR in iwmmxt.md. */ 925 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 926 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 927 928 #define IS_IWMMXT_REGNUM(REGNUM) \ 929 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 930 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 931 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 932 933 /* Base register for access to local variables of the function. */ 934 #define FRAME_POINTER_REGNUM 102 935 936 /* Base register for access to arguments of the function. */ 937 #define ARG_POINTER_REGNUM 103 938 939 #define FIRST_VFP_REGNUM 16 940 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 941 #define LAST_VFP_REGNUM \ 942 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 943 944 #define IS_VFP_REGNUM(REGNUM) \ 945 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 946 947 /* VFP registers are split into two types: those defined by VFP versions < 3 948 have D registers overlaid on consecutive pairs of S registers. VFP version 3 949 defines 16 new D registers (d16-d31) which, for simplicity and correctness 950 in various parts of the backend, we implement as "fake" single-precision 951 registers (which would be S32-S63, but cannot be used in that way). The 952 following macros define these ranges of registers. */ 953 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 954 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 955 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 956 957 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 958 ((REGNUM) <= LAST_LO_VFP_REGNUM) 959 960 /* DFmode values are only valid in even register pairs. */ 961 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 962 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 963 964 /* Neon Quad values must start at a multiple of four registers. */ 965 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 966 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 967 968 /* Neon structures of vectors must be in even register pairs and there 969 must be enough registers available. Because of various patterns 970 requiring quad registers, we require them to start at a multiple of 971 four. */ 972 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 973 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 974 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 975 976 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 977 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 978 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 979 #define FIRST_PSEUDO_REGISTER 104 980 981 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 982 983 /* Value should be nonzero if functions must have frame pointers. 984 Zero means the frame pointer need not be set up (and parms may be accessed 985 via the stack pointer) in functions that seem suitable. 986 If we have to have a frame pointer we might as well make use of it. 987 APCS says that the frame pointer does not need to be pushed in leaf 988 functions, or simple tail call functions. */ 989 990 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 991 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 992 #endif 993 994 /* Return number of consecutive hard regs needed starting at reg REGNO 995 to hold something of mode MODE. 996 This is ordinarily the length in words of a value of mode MODE 997 but can be less for certain modes in special long registers. 998 999 On the ARM core regs are UNITS_PER_WORD bits wide. */ 1000 #define HARD_REGNO_NREGS(REGNO, MODE) \ 1001 ((TARGET_32BIT \ 1002 && REGNO > PC_REGNUM \ 1003 && REGNO != FRAME_POINTER_REGNUM \ 1004 && REGNO != ARG_POINTER_REGNUM) \ 1005 && !IS_VFP_REGNUM (REGNO) \ 1006 ? 1 : ARM_NUM_REGS (MODE)) 1007 1008 /* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1009 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1010 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1011 1012 #define MODES_TIEABLE_P(MODE1, MODE2) arm_modes_tieable_p (MODE1, MODE2) 1013 1014 #define VALID_IWMMXT_REG_MODE(MODE) \ 1015 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1016 1017 /* Modes valid for Neon D registers. */ 1018 #define VALID_NEON_DREG_MODE(MODE) \ 1019 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1020 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1021 1022 /* Modes valid for Neon Q registers. */ 1023 #define VALID_NEON_QREG_MODE(MODE) \ 1024 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1025 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode) 1026 1027 /* Structure modes valid for Neon registers. */ 1028 #define VALID_NEON_STRUCT_MODE(MODE) \ 1029 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1030 || (MODE) == CImode || (MODE) == XImode) 1031 1032 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1033 extern int arm_regs_in_sequence[]; 1034 1035 /* The order in which register should be allocated. It is good to use ip 1036 since no saving is required (though calls clobber it) and it never contains 1037 function parameters. It is quite good to use lr since other calls may 1038 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1039 least likely to contain a function parameter; in addition results are 1040 returned in r0. 1041 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1042 then D8-D15. The reason for doing this is to attempt to reduce register 1043 pressure when both single- and double-precision registers are used in a 1044 function. */ 1045 1046 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1047 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1048 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1049 1050 #define REG_ALLOC_ORDER \ 1051 { \ 1052 /* General registers. */ \ 1053 3, 2, 1, 0, 12, 14, 4, 5, \ 1054 6, 7, 8, 9, 10, 11, \ 1055 /* High VFP registers. */ \ 1056 VREG(32), VREG(33), VREG(34), VREG(35), \ 1057 VREG(36), VREG(37), VREG(38), VREG(39), \ 1058 VREG(40), VREG(41), VREG(42), VREG(43), \ 1059 VREG(44), VREG(45), VREG(46), VREG(47), \ 1060 VREG(48), VREG(49), VREG(50), VREG(51), \ 1061 VREG(52), VREG(53), VREG(54), VREG(55), \ 1062 VREG(56), VREG(57), VREG(58), VREG(59), \ 1063 VREG(60), VREG(61), VREG(62), VREG(63), \ 1064 /* VFP argument registers. */ \ 1065 VREG(15), VREG(14), VREG(13), VREG(12), \ 1066 VREG(11), VREG(10), VREG(9), VREG(8), \ 1067 VREG(7), VREG(6), VREG(5), VREG(4), \ 1068 VREG(3), VREG(2), VREG(1), VREG(0), \ 1069 /* VFP call-saved registers. */ \ 1070 VREG(16), VREG(17), VREG(18), VREG(19), \ 1071 VREG(20), VREG(21), VREG(22), VREG(23), \ 1072 VREG(24), VREG(25), VREG(26), VREG(27), \ 1073 VREG(28), VREG(29), VREG(30), VREG(31), \ 1074 /* IWMMX registers. */ \ 1075 WREG(0), WREG(1), WREG(2), WREG(3), \ 1076 WREG(4), WREG(5), WREG(6), WREG(7), \ 1077 WREG(8), WREG(9), WREG(10), WREG(11), \ 1078 WREG(12), WREG(13), WREG(14), WREG(15), \ 1079 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1080 /* Registers not for general use. */ \ 1081 CC_REGNUM, VFPCC_REGNUM, \ 1082 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1083 SP_REGNUM, PC_REGNUM \ 1084 } 1085 1086 /* Use different register alloc ordering for Thumb. */ 1087 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1088 1089 /* Tell IRA to use the order we define rather than messing it up with its 1090 own cost calculations. */ 1091 #define HONOR_REG_ALLOC_ORDER 1 1092 1093 /* Interrupt functions can only use registers that have already been 1094 saved by the prologue, even if they would normally be 1095 call-clobbered. */ 1096 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1097 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1098 df_regs_ever_live_p (DST)) 1099 1100 /* Register and constant classes. */ 1102 1103 /* Register classes. */ 1104 enum reg_class 1105 { 1106 NO_REGS, 1107 LO_REGS, 1108 STACK_REG, 1109 BASE_REGS, 1110 HI_REGS, 1111 CALLER_SAVE_REGS, 1112 GENERAL_REGS, 1113 CORE_REGS, 1114 VFP_D0_D7_REGS, 1115 VFP_LO_REGS, 1116 VFP_HI_REGS, 1117 VFP_REGS, 1118 IWMMXT_REGS, 1119 IWMMXT_GR_REGS, 1120 CC_REG, 1121 VFPCC_REG, 1122 SFP_REG, 1123 AFP_REG, 1124 ALL_REGS, 1125 LIM_REG_CLASSES 1126 }; 1127 1128 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1129 1130 /* Give names of register classes as strings for dump file. */ 1131 #define REG_CLASS_NAMES \ 1132 { \ 1133 "NO_REGS", \ 1134 "LO_REGS", \ 1135 "STACK_REG", \ 1136 "BASE_REGS", \ 1137 "HI_REGS", \ 1138 "CALLER_SAVE_REGS", \ 1139 "GENERAL_REGS", \ 1140 "CORE_REGS", \ 1141 "VFP_D0_D7_REGS", \ 1142 "VFP_LO_REGS", \ 1143 "VFP_HI_REGS", \ 1144 "VFP_REGS", \ 1145 "IWMMXT_REGS", \ 1146 "IWMMXT_GR_REGS", \ 1147 "CC_REG", \ 1148 "VFPCC_REG", \ 1149 "SFP_REG", \ 1150 "AFP_REG", \ 1151 "ALL_REGS" \ 1152 } 1153 1154 /* Define which registers fit in which classes. 1155 This is an initializer for a vector of HARD_REG_SET 1156 of length N_REG_CLASSES. */ 1157 #define REG_CLASS_CONTENTS \ 1158 { \ 1159 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1160 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1161 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1162 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1163 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1164 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1165 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1166 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1167 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1168 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1169 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1170 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1171 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1172 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1173 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1174 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1175 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1176 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1177 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1178 } 1179 1180 /* Any of the VFP register classes. */ 1181 #define IS_VFP_CLASS(X) \ 1182 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1183 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1184 1185 /* The same information, inverted: 1186 Return the class number of the smallest class containing 1187 reg number REGNO. This could be a conditional expression 1188 or could index an array. */ 1189 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1190 1191 /* In VFPv1, VFP registers could only be accessed in the mode they 1192 were set, so subregs would be invalid there. However, we don't 1193 support VFPv1 at the moment, and the restriction was lifted in 1194 VFPv2. 1195 In big-endian mode, modes greater than word size (i.e. DFmode) are stored in 1196 VFP registers in little-endian order. We can't describe that accurately to 1197 GCC, so avoid taking subregs of such values. 1198 The only exception is going from a 128-bit to a 64-bit type. In that case 1199 the data layout happens to be consistent for big-endian, so we explicitly allow 1200 that case. */ 1201 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1202 (TARGET_BIG_END \ 1203 && !(GET_MODE_SIZE (FROM) == 16 && GET_MODE_SIZE (TO) == 8) \ 1204 && (GET_MODE_SIZE (FROM) > UNITS_PER_WORD \ 1205 || GET_MODE_SIZE (TO) > UNITS_PER_WORD) \ 1206 && reg_classes_intersect_p (VFP_REGS, (CLASS))) 1207 1208 /* The class value for index registers, and the one for base regs. */ 1209 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1210 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1211 1212 /* For the Thumb the high registers cannot be used as base registers 1213 when addressing quantities in QI or HI mode; if we don't know the 1214 mode, then we must be conservative. */ 1215 #define MODE_BASE_REG_CLASS(MODE) \ 1216 (TARGET_32BIT ? CORE_REGS \ 1217 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1218 : LO_REGS) 1219 1220 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1221 instead of BASE_REGS. */ 1222 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1223 1224 /* When this hook returns true for MODE, the compiler allows 1225 registers explicitly used in the rtl to be used as spill registers 1226 but prevents the compiler from extending the lifetime of these 1227 registers. */ 1228 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1229 arm_small_register_classes_for_mode_p 1230 1231 /* Must leave BASE_REGS reloads alone */ 1232 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1233 (lra_in_progress ? NO_REGS \ 1234 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1235 ? ((true_regnum (X) == -1 ? LO_REGS \ 1236 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1237 : NO_REGS)) \ 1238 : NO_REGS)) 1239 1240 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1241 (lra_in_progress ? NO_REGS \ 1242 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1243 ? ((true_regnum (X) == -1 ? LO_REGS \ 1244 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1245 : NO_REGS)) \ 1246 : NO_REGS) 1247 1248 /* Return the register class of a scratch register needed to copy IN into 1249 or out of a register in CLASS in MODE. If it can be done directly, 1250 NO_REGS is returned. */ 1251 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1252 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1253 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1254 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1255 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1256 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1257 : TARGET_32BIT \ 1258 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1259 ? GENERAL_REGS : NO_REGS) \ 1260 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1261 1262 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1263 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1264 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1265 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1266 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1267 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1268 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1269 (TARGET_32BIT ? \ 1270 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1271 && CONSTANT_P (X)) \ 1272 ? GENERAL_REGS : \ 1273 (((MODE) == HImode && ! arm_arch4 \ 1274 && (MEM_P (X) \ 1275 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1276 && true_regnum (X) == -1))) \ 1277 ? GENERAL_REGS : NO_REGS) \ 1278 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1279 1280 /* Return the maximum number of consecutive registers 1281 needed to represent mode MODE in a register of class CLASS. 1282 ARM regs are UNITS_PER_WORD bits. 1283 FIXME: Is this true for iWMMX? */ 1284 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1285 (ARM_NUM_REGS (MODE)) 1286 1287 /* If defined, gives a class of registers that cannot be used as the 1288 operand of a SUBREG that changes the mode of the object illegally. */ 1289 1290 /* Stack layout; function entry, exit and calling. */ 1292 1293 /* Define this if pushing a word on the stack 1294 makes the stack pointer a smaller address. */ 1295 #define STACK_GROWS_DOWNWARD 1 1296 1297 /* Define this to nonzero if the nominal address of the stack frame 1298 is at the high-address end of the local variables; 1299 that is, each additional local variable allocated 1300 goes at a more negative offset in the frame. */ 1301 #define FRAME_GROWS_DOWNWARD 1 1302 1303 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1304 When present, it is one word in size, and sits at the top of the frame, 1305 between the soft frame pointer and either r7 or r11. 1306 1307 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1308 and only then if some outgoing arguments are passed on the stack. It would 1309 be tempting to also check whether the stack arguments are passed by indirect 1310 calls, but there seems to be no reason in principle why a post-reload pass 1311 couldn't convert a direct call into an indirect one. */ 1312 #define CALLER_INTERWORKING_SLOT_SIZE \ 1313 (TARGET_CALLER_INTERWORKING \ 1314 && crtl->outgoing_args_size != 0 \ 1315 ? UNITS_PER_WORD : 0) 1316 1317 /* Offset within stack frame to start allocating local variables at. 1318 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1319 first local allocated. Otherwise, it is the offset to the BEGINNING 1320 of the first local allocated. */ 1321 #define STARTING_FRAME_OFFSET 0 1322 1323 /* If we generate an insn to push BYTES bytes, 1324 this says how many the stack pointer really advances by. */ 1325 /* The push insns do not do this rounding implicitly. 1326 So don't define this. */ 1327 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1328 1329 /* Define this if the maximum size of all the outgoing args is to be 1330 accumulated and pushed during the prologue. The amount can be 1331 found in the variable crtl->outgoing_args_size. */ 1332 #define ACCUMULATE_OUTGOING_ARGS 1 1333 1334 /* Offset of first parameter from the argument pointer register value. */ 1335 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1336 1337 /* Amount of memory needed for an untyped call to save all possible return 1338 registers. */ 1339 #define APPLY_RESULT_SIZE arm_apply_result_size() 1340 1341 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1342 values must be in memory. On the ARM, they need only do so if larger 1343 than a word, or if they contain elements offset from zero in the struct. */ 1344 #define DEFAULT_PCC_STRUCT_RETURN 0 1345 1346 /* These bits describe the different types of function supported 1347 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1348 normal function and an interworked function, for example. Knowing the 1349 type of a function is important for determining its prologue and 1350 epilogue sequences. 1351 Note value 7 is currently unassigned. Also note that the interrupt 1352 function types all have bit 2 set, so that they can be tested for easily. 1353 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1354 machine_function structure is initialized (to zero) func_type will 1355 default to unknown. This will force the first use of arm_current_func_type 1356 to call arm_compute_func_type. */ 1357 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1358 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1359 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1360 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1361 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1362 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1363 1364 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1365 1366 /* In addition functions can have several type modifiers, 1367 outlined by these bit masks: */ 1368 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1369 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1370 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1371 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1372 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1373 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1374 1375 /* Some macros to test these flags. */ 1376 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1377 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1378 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1379 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1380 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1381 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1382 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1383 1384 1385 /* Structure used to hold the function stack frame layout. Offsets are 1386 relative to the stack pointer on function entry. Positive offsets are 1387 in the direction of stack growth. 1388 Only soft_frame is used in thumb mode. */ 1389 1390 typedef struct GTY(()) arm_stack_offsets 1391 { 1392 int saved_args; /* ARG_POINTER_REGNUM. */ 1393 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1394 int saved_regs; 1395 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1396 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1397 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1398 unsigned int saved_regs_mask; 1399 } 1400 arm_stack_offsets; 1401 1402 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1403 /* A C structure for machine-specific, per-function data. 1404 This is added to the cfun structure. */ 1405 typedef struct GTY(()) machine_function 1406 { 1407 /* Additional stack adjustment in __builtin_eh_throw. */ 1408 rtx eh_epilogue_sp_ofs; 1409 /* Records if LR has to be saved for far jumps. */ 1410 int far_jump_used; 1411 /* Records if ARG_POINTER was ever live. */ 1412 int arg_pointer_live; 1413 /* Records if the save of LR has been eliminated. */ 1414 int lr_save_eliminated; 1415 /* The size of the stack frame. Only valid after reload. */ 1416 arm_stack_offsets stack_offsets; 1417 /* Records the type of the current function. */ 1418 unsigned long func_type; 1419 /* Record if the function has a variable argument list. */ 1420 int uses_anonymous_args; 1421 /* Records if sibcalls are blocked because an argument 1422 register is needed to preserve stack alignment. */ 1423 int sibcall_blocked; 1424 /* The PIC register for this function. This might be a pseudo. */ 1425 rtx pic_reg; 1426 /* Labels for per-function Thumb call-via stubs. One per potential calling 1427 register. We can never call via LR or PC. We can call via SP if a 1428 trampoline happens to be on the top of the stack. */ 1429 rtx call_via[14]; 1430 /* Set to 1 when a return insn is output, this means that the epilogue 1431 is not needed. */ 1432 int return_used_this_function; 1433 /* When outputting Thumb-1 code, record the last insn that provides 1434 information about condition codes, and the comparison operands. */ 1435 rtx thumb1_cc_insn; 1436 rtx thumb1_cc_op0; 1437 rtx thumb1_cc_op1; 1438 /* Also record the CC mode that is supported. */ 1439 machine_mode thumb1_cc_mode; 1440 /* Set to 1 after arm_reorg has started. */ 1441 int after_arm_reorg; 1442 /* The number of bytes used to store the static chain register on the 1443 stack, above the stack frame. */ 1444 int static_chain_stack_bytes; 1445 } 1446 machine_function; 1447 #endif 1448 1449 /* As in the machine_function, a global set of call-via labels, for code 1450 that is in text_section. */ 1451 extern GTY(()) rtx thumb_call_via_label[14]; 1452 1453 /* The number of potential ways of assigning to a co-processor. */ 1454 #define ARM_NUM_COPROC_SLOTS 1 1455 1456 /* Enumeration of procedure calling standard variants. We don't really 1457 support all of these yet. */ 1458 enum arm_pcs 1459 { 1460 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1461 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1462 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1463 /* This must be the last AAPCS variant. */ 1464 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1465 ARM_PCS_ATPCS, /* ATPCS. */ 1466 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1467 ARM_PCS_UNKNOWN 1468 }; 1469 1470 /* Default procedure calling standard of current compilation unit. */ 1471 extern enum arm_pcs arm_pcs_default; 1472 1473 #if !defined (USED_FOR_TARGET) 1474 /* A C type for declaring a variable that is used as the first argument of 1475 `FUNCTION_ARG' and other related values. */ 1476 typedef struct 1477 { 1478 /* This is the number of registers of arguments scanned so far. */ 1479 int nregs; 1480 /* This is the number of iWMMXt register arguments scanned so far. */ 1481 int iwmmxt_nregs; 1482 int named_count; 1483 int nargs; 1484 /* Which procedure call variant to use for this call. */ 1485 enum arm_pcs pcs_variant; 1486 1487 /* AAPCS related state tracking. */ 1488 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1489 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1490 this argument, or -1 if using core 1491 registers. */ 1492 int aapcs_ncrn; 1493 int aapcs_next_ncrn; 1494 rtx aapcs_reg; /* Register assigned to this argument. */ 1495 int aapcs_partial; /* How many bytes are passed in regs (if 1496 split between core regs and stack. 1497 Zero otherwise. */ 1498 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1499 int can_split; /* Argument can be split between core regs 1500 and the stack. */ 1501 /* Private data for tracking VFP register allocation */ 1502 unsigned aapcs_vfp_regs_free; 1503 unsigned aapcs_vfp_reg_alloc; 1504 int aapcs_vfp_rcount; 1505 MACHMODE aapcs_vfp_rmode; 1506 } CUMULATIVE_ARGS; 1507 #endif 1508 1509 #define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1510 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1511 1512 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1513 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1514 1515 /* For AAPCS, padding should never be below the argument. For other ABIs, 1516 * mimic the default. */ 1517 #define PAD_VARARGS_DOWN \ 1518 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1519 1520 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1521 for a call to a function whose data type is FNTYPE. 1522 For a library call, FNTYPE is 0. 1523 On the ARM, the offset starts at 0. */ 1524 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1525 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1526 1527 /* 1 if N is a possible register number for function argument passing. 1528 On the ARM, r0-r3 are used to pass args. */ 1529 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1530 (IN_RANGE ((REGNO), 0, 3) \ 1531 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1532 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1533 || (TARGET_IWMMXT_ABI \ 1534 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1535 1536 1537 /* If your target environment doesn't prefix user functions with an 1539 underscore, you may wish to re-define this to prevent any conflicts. */ 1540 #ifndef ARM_MCOUNT_NAME 1541 #define ARM_MCOUNT_NAME "*mcount" 1542 #endif 1543 1544 /* Call the function profiler with a given profile label. The Acorn 1545 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1546 On the ARM the full profile code will look like: 1547 .data 1548 LP1 1549 .word 0 1550 .text 1551 mov ip, lr 1552 bl mcount 1553 .word LP1 1554 1555 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1556 will output the .text section. 1557 1558 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1559 ``prof'' doesn't seem to mind about this! 1560 1561 Note - this version of the code is designed to work in both ARM and 1562 Thumb modes. */ 1563 #ifndef ARM_FUNCTION_PROFILER 1564 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1565 { \ 1566 char temp[20]; \ 1567 rtx sym; \ 1568 \ 1569 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1570 IP_REGNUM, LR_REGNUM); \ 1571 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1572 fputc ('\n', STREAM); \ 1573 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1574 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1575 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1576 } 1577 #endif 1578 1579 #ifdef THUMB_FUNCTION_PROFILER 1580 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1581 if (TARGET_ARM) \ 1582 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1583 else \ 1584 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1585 #else 1586 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1587 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1588 #endif 1589 1590 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1591 the stack pointer does not matter. The value is tested only in 1592 functions that have frame pointers. 1593 No definition is equivalent to always zero. 1594 1595 On the ARM, the function epilogue recovers the stack pointer from the 1596 frame. */ 1597 #define EXIT_IGNORE_STACK 1 1598 1599 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1600 1601 /* Determine if the epilogue should be output as RTL. 1602 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1603 #define USE_RETURN_INSN(ISCOND) \ 1604 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1605 1606 /* Definitions for register eliminations. 1607 1608 This is an array of structures. Each structure initializes one pair 1609 of eliminable registers. The "from" register number is given first, 1610 followed by "to". Eliminations of the same "from" register are listed 1611 in order of preference. 1612 1613 We have two registers that can be eliminated on the ARM. First, the 1614 arg pointer register can often be eliminated in favor of the stack 1615 pointer register. Secondly, the pseudo frame pointer register can always 1616 be eliminated; it is replaced with either the stack or the real frame 1617 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1618 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1619 1620 #define ELIMINABLE_REGS \ 1621 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1622 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1623 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1624 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1625 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1626 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1627 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1628 1629 /* Define the offset between two registers, one to be eliminated, and the 1630 other its replacement, at the start of a routine. */ 1631 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1632 if (TARGET_ARM) \ 1633 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1634 else \ 1635 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1636 1637 /* Special case handling of the location of arguments passed on the stack. */ 1638 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1639 1640 /* Initialize data used by insn expanders. This is called from insn_emit, 1641 once for every function before code is generated. */ 1642 #define INIT_EXPANDERS arm_init_expanders () 1643 1644 /* Length in units of the trampoline for entering a nested function. */ 1645 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1646 1647 /* Alignment required for a trampoline in bits. */ 1648 #define TRAMPOLINE_ALIGNMENT 32 1649 1650 /* Addressing modes, and classification of registers for them. */ 1652 #define HAVE_POST_INCREMENT 1 1653 #define HAVE_PRE_INCREMENT TARGET_32BIT 1654 #define HAVE_POST_DECREMENT TARGET_32BIT 1655 #define HAVE_PRE_DECREMENT TARGET_32BIT 1656 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1657 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1658 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1659 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1660 1661 enum arm_auto_incmodes 1662 { 1663 ARM_POST_INC, 1664 ARM_PRE_INC, 1665 ARM_POST_DEC, 1666 ARM_PRE_DEC 1667 }; 1668 1669 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1670 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1671 #define USE_LOAD_POST_INCREMENT(mode) \ 1672 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1673 #define USE_LOAD_PRE_INCREMENT(mode) \ 1674 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1675 #define USE_LOAD_POST_DECREMENT(mode) \ 1676 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1677 #define USE_LOAD_PRE_DECREMENT(mode) \ 1678 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1679 1680 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1681 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1682 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1683 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1684 1685 /* Macros to check register numbers against specific register classes. */ 1686 1687 /* These assume that REGNO is a hard or pseudo reg number. 1688 They give nonzero only if REGNO is a hard reg of the suitable class 1689 or a pseudo reg currently allocated to a suitable hard reg. */ 1690 #define TEST_REGNO(R, TEST, VALUE) \ 1691 ((R TEST VALUE) \ 1692 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1693 1694 /* Don't allow the pc to be used. */ 1695 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1696 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1697 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1698 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1699 1700 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1701 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1702 || (GET_MODE_SIZE (MODE) >= 4 \ 1703 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1704 1705 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1706 (TARGET_THUMB1 \ 1707 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1708 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1709 1710 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1711 For Thumb, we can not use SP + reg, so reject SP. */ 1712 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1713 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1714 1715 /* For ARM code, we don't care about the mode, but for Thumb, the index 1716 must be suitable for use in a QImode load. */ 1717 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1718 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1719 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1720 1721 /* Maximum number of registers that can appear in a valid memory address. 1722 Shifts in addresses can't be by a register. */ 1723 #define MAX_REGS_PER_ADDRESS 2 1724 1725 /* Recognize any constant value that is a valid address. */ 1726 /* XXX We can address any constant, eventually... */ 1727 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1728 #define CONSTANT_ADDRESS_P(X) \ 1729 (GET_CODE (X) == SYMBOL_REF \ 1730 && (CONSTANT_POOL_ADDRESS_P (X) \ 1731 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1732 1733 /* True if SYMBOL + OFFSET constants must refer to something within 1734 SYMBOL's section. */ 1735 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1736 1737 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1738 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1739 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1740 #endif 1741 1742 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1743 #define SUBTARGET_NAME_ENCODING_LENGTHS 1744 #endif 1745 1746 /* This is a C fragment for the inside of a switch statement. 1747 Each case label should return the number of characters to 1748 be stripped from the start of a function's name, if that 1749 name starts with the indicated character. */ 1750 #define ARM_NAME_ENCODING_LENGTHS \ 1751 case '*': return 1; \ 1752 SUBTARGET_NAME_ENCODING_LENGTHS 1753 1754 /* This is how to output a reference to a user-level label named NAME. 1755 `assemble_name' uses this. */ 1756 #undef ASM_OUTPUT_LABELREF 1757 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1758 arm_asm_output_labelref (FILE, NAME) 1759 1760 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1761 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1762 if (TARGET_THUMB2) \ 1763 thumb2_asm_output_opcode (STREAM); 1764 1765 /* The EABI specifies that constructors should go in .init_array. 1766 Other targets use .ctors for compatibility. */ 1767 #ifndef ARM_EABI_CTORS_SECTION_OP 1768 #define ARM_EABI_CTORS_SECTION_OP \ 1769 "\t.section\t.init_array,\"aw\",%init_array" 1770 #endif 1771 #ifndef ARM_EABI_DTORS_SECTION_OP 1772 #define ARM_EABI_DTORS_SECTION_OP \ 1773 "\t.section\t.fini_array,\"aw\",%fini_array" 1774 #endif 1775 #define ARM_CTORS_SECTION_OP \ 1776 "\t.section\t.ctors,\"aw\",%progbits" 1777 #define ARM_DTORS_SECTION_OP \ 1778 "\t.section\t.dtors,\"aw\",%progbits" 1779 1780 /* Define CTORS_SECTION_ASM_OP. */ 1781 #undef CTORS_SECTION_ASM_OP 1782 #undef DTORS_SECTION_ASM_OP 1783 #ifndef IN_LIBGCC2 1784 # define CTORS_SECTION_ASM_OP \ 1785 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1786 # define DTORS_SECTION_ASM_OP \ 1787 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1788 #else /* !defined (IN_LIBGCC2) */ 1789 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1790 so we cannot use the definition above. */ 1791 # ifdef __ARM_EABI__ 1792 /* The .ctors section is not part of the EABI, so we do not define 1793 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1794 from trying to use it. We do define it when doing normal 1795 compilation, as .init_array can be used instead of .ctors. */ 1796 /* There is no need to emit begin or end markers when using 1797 init_array; the dynamic linker will compute the size of the 1798 array itself based on special symbols created by the static 1799 linker. However, we do need to arrange to set up 1800 exception-handling here. */ 1801 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1802 # define CTOR_LIST_END /* empty */ 1803 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1804 # define DTOR_LIST_END /* empty */ 1805 # else /* !defined (__ARM_EABI__) */ 1806 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1807 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1808 # endif /* !defined (__ARM_EABI__) */ 1809 #endif /* !defined (IN_LIBCC2) */ 1810 1811 /* True if the operating system can merge entities with vague linkage 1812 (e.g., symbols in COMDAT group) during dynamic linking. */ 1813 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1814 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1815 #endif 1816 1817 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1818 1819 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1820 and check its validity for a certain class. 1821 We have two alternate definitions for each of them. 1822 The usual definition accepts all pseudo regs; the other rejects 1823 them unless they have been allocated suitable hard regs. 1824 The symbol REG_OK_STRICT causes the latter definition to be used. 1825 Thumb-2 has the same restrictions as arm. */ 1826 #ifndef REG_OK_STRICT 1827 1828 #define ARM_REG_OK_FOR_BASE_P(X) \ 1829 (REGNO (X) <= LAST_ARM_REGNUM \ 1830 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1831 || REGNO (X) == FRAME_POINTER_REGNUM \ 1832 || REGNO (X) == ARG_POINTER_REGNUM) 1833 1834 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1835 ((REGNO (X) <= LAST_ARM_REGNUM \ 1836 && REGNO (X) != STACK_POINTER_REGNUM) \ 1837 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1838 || REGNO (X) == FRAME_POINTER_REGNUM \ 1839 || REGNO (X) == ARG_POINTER_REGNUM) 1840 1841 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1842 (REGNO (X) <= LAST_LO_REGNUM \ 1843 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1844 || (GET_MODE_SIZE (MODE) >= 4 \ 1845 && (REGNO (X) == STACK_POINTER_REGNUM \ 1846 || (X) == hard_frame_pointer_rtx \ 1847 || (X) == arg_pointer_rtx))) 1848 1849 #define REG_STRICT_P 0 1850 1851 #else /* REG_OK_STRICT */ 1852 1853 #define ARM_REG_OK_FOR_BASE_P(X) \ 1854 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1855 1856 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1857 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1858 1859 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1860 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1861 1862 #define REG_STRICT_P 1 1863 1864 #endif /* REG_OK_STRICT */ 1865 1866 /* Now define some helpers in terms of the above. */ 1867 1868 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1869 (TARGET_THUMB1 \ 1870 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1871 : ARM_REG_OK_FOR_BASE_P (X)) 1872 1873 /* For 16-bit Thumb, a valid index register is anything that can be used in 1874 a byte load instruction. */ 1875 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1876 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1877 1878 /* Nonzero if X is a hard reg that can be used as an index 1879 or if it is a pseudo reg. On the Thumb, the stack pointer 1880 is not suitable. */ 1881 #define REG_OK_FOR_INDEX_P(X) \ 1882 (TARGET_THUMB1 \ 1883 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1884 : ARM_REG_OK_FOR_INDEX_P (X)) 1885 1886 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1887 For Thumb, we can not use SP + reg, so reject SP. */ 1888 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1889 REG_OK_FOR_INDEX_P (X) 1890 1891 #define ARM_BASE_REGISTER_RTX_P(X) \ 1893 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1894 1895 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1896 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1897 1898 /* Specify the machine mode that this machine uses 1900 for the index in the tablejump instruction. */ 1901 #define CASE_VECTOR_MODE Pmode 1902 1903 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 1904 || (TARGET_THUMB1 \ 1905 && (optimize_size || flag_pic))) 1906 1907 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1908 (TARGET_THUMB1 \ 1909 ? (min >= 0 && max < 512 \ 1910 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1911 : min >= -256 && max < 256 \ 1912 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1913 : min >= 0 && max < 8192 \ 1914 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1915 : min >= -4096 && max < 4096 \ 1916 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1917 : SImode) \ 1918 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1919 : (max >= 0x200) ? HImode \ 1920 : QImode)) 1921 1922 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1923 unsigned is probably best, but may break some code. */ 1924 #ifndef DEFAULT_SIGNED_CHAR 1925 #define DEFAULT_SIGNED_CHAR 0 1926 #endif 1927 1928 /* Max number of bytes we can move from memory to memory 1929 in one reasonably fast instruction. */ 1930 #define MOVE_MAX 4 1931 1932 #undef MOVE_RATIO 1933 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 1934 1935 /* Define if operations between registers always perform the operation 1936 on the full register even if a narrower mode is specified. */ 1937 #define WORD_REGISTER_OPERATIONS 1 1938 1939 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1940 will either zero-extend or sign-extend. The value of this macro should 1941 be the code that says which one of the two operations is implicitly 1942 done, UNKNOWN if none. */ 1943 #define LOAD_EXTEND_OP(MODE) \ 1944 (TARGET_THUMB ? ZERO_EXTEND : \ 1945 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 1946 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 1947 1948 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1949 #define SLOW_BYTE_ACCESS 0 1950 1951 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 1952 1953 /* Immediate shift counts are truncated by the output routines (or was it 1954 the assembler?). Shift counts in a register are truncated by ARM. Note 1955 that the native compiler puts too large (> 32) immediate shift counts 1956 into a register and shifts by the register, letting the ARM decide what 1957 to do instead of doing that itself. */ 1958 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1959 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1960 On the arm, Y in a register is used modulo 256 for the shift. Only for 1961 rotates is modulo 32 used. */ 1962 /* #define SHIFT_COUNT_TRUNCATED 1 */ 1963 1964 /* All integers have the same format so truncation is easy. */ 1965 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1966 1967 /* Calling from registers is a massive pain. */ 1968 #define NO_FUNCTION_CSE 1 1969 1970 /* The machine modes of pointers and functions */ 1971 #define Pmode SImode 1972 #define FUNCTION_MODE Pmode 1973 1974 #define ARM_FRAME_RTX(X) \ 1975 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1976 || (X) == arg_pointer_rtx) 1977 1978 /* Try to generate sequences that don't involve branches, we can then use 1979 conditional instructions. */ 1980 #define BRANCH_COST(speed_p, predictable_p) \ 1981 (current_tune->branch_cost (speed_p, predictable_p)) 1982 1983 /* False if short circuit operation is preferred. */ 1984 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 1985 ((optimize_size) \ 1986 ? (TARGET_THUMB ? false : true) \ 1987 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 1988 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 1989 1990 1991 /* Position Independent Code. */ 1993 /* We decide which register to use based on the compilation options and 1994 the assembler in use; this is more general than the APCS restriction of 1995 using sb (r9) all the time. */ 1996 extern unsigned arm_pic_register; 1997 1998 /* The register number of the register used to address a table of static 1999 data addresses in memory. */ 2000 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2001 2002 /* We can't directly access anything that contains a symbol, 2003 nor can we indirect via the constant pool. One exception is 2004 UNSPEC_TLS, which is always PIC. */ 2005 #define LEGITIMATE_PIC_OPERAND_P(X) \ 2006 (!(symbol_mentioned_p (X) \ 2007 || label_mentioned_p (X) \ 2008 || (GET_CODE (X) == SYMBOL_REF \ 2009 && CONSTANT_POOL_ADDRESS_P (X) \ 2010 && (symbol_mentioned_p (get_pool_constant (X)) \ 2011 || label_mentioned_p (get_pool_constant (X))))) \ 2012 || tls_mentioned_p (X)) 2013 2014 /* We need to know when we are making a constant pool; this determines 2015 whether data needs to be in the GOT or can be referenced via a GOT 2016 offset. */ 2017 extern int making_const_table; 2018 2019 /* Handle pragmas for compatibility with Intel's compilers. */ 2021 /* Also abuse this to register additional C specific EABI attributes. */ 2022 #define REGISTER_TARGET_PRAGMAS() do { \ 2023 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2024 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2025 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2026 arm_lang_object_attributes_init(); \ 2027 arm_register_target_pragmas(); \ 2028 } while (0) 2029 2030 /* Condition code information. */ 2031 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2032 return the mode to be used for the comparison. */ 2033 2034 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2035 2036 #define REVERSIBLE_CC_MODE(MODE) 1 2037 2038 #define REVERSE_CONDITION(CODE,MODE) \ 2039 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2040 ? reverse_condition_maybe_unordered (code) \ 2041 : reverse_condition (code)) 2042 2043 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2044 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2045 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2046 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2047 2048 #define CC_STATUS_INIT \ 2050 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2051 2052 #undef ASM_APP_ON 2053 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2054 "\t.syntax divided\n") 2055 2056 #undef ASM_APP_OFF 2057 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2058 "\t.thumb\n\t.syntax unified\n") 2059 2060 /* Output a push or a pop instruction (only used when profiling). 2061 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2062 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2063 that r7 isn't used by the function profiler, so we can use it as a 2064 scratch reg. WARNING: This isn't safe in the general case! It may be 2065 sensitive to future changes in final.c:profile_function. */ 2066 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2067 do \ 2068 { \ 2069 if (TARGET_THUMB1 \ 2070 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2071 { \ 2072 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2073 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2074 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2075 } \ 2076 else \ 2077 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2078 } while (0) 2079 2080 2081 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2082 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2083 do \ 2084 { \ 2085 if (TARGET_THUMB1 \ 2086 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2087 { \ 2088 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2089 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2090 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2091 } \ 2092 else \ 2093 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2094 } while (0) 2095 2096 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2097 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2098 2099 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2100 default alignment from elfos.h. */ 2101 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2102 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2103 2104 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2105 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2106 ? 1 : 0) 2107 2108 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2109 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2110 2111 /* For aliases of functions we use .thumb_set instead. */ 2112 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2113 do \ 2114 { \ 2115 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2116 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2117 \ 2118 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2119 { \ 2120 fprintf (FILE, "\t.thumb_set "); \ 2121 assemble_name (FILE, LABEL1); \ 2122 fprintf (FILE, ","); \ 2123 assemble_name (FILE, LABEL2); \ 2124 fprintf (FILE, "\n"); \ 2125 } \ 2126 else \ 2127 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2128 } \ 2129 while (0) 2130 2131 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2132 /* To support -falign-* switches we need to use .p2align so 2133 that alignment directives in code sections will be padded 2134 with no-op instructions, rather than zeroes. */ 2135 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2136 if ((LOG) != 0) \ 2137 { \ 2138 if ((MAX_SKIP) == 0) \ 2139 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2140 else \ 2141 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2142 (int) (LOG), (int) (MAX_SKIP)); \ 2143 } 2144 #endif 2145 2146 /* Add two bytes to the length of conditionally executed Thumb-2 2148 instructions for the IT instruction. */ 2149 #define ADJUST_INSN_LENGTH(insn, length) \ 2150 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2151 length += 2; 2152 2153 /* Only perform branch elimination (by making instructions conditional) if 2154 we're optimizing. For Thumb-2 check if any IT instructions need 2155 outputting. */ 2156 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2157 if (TARGET_ARM && optimize) \ 2158 arm_final_prescan_insn (INSN); \ 2159 else if (TARGET_THUMB2) \ 2160 thumb2_final_prescan_insn (INSN); \ 2161 else if (TARGET_THUMB1) \ 2162 thumb1_final_prescan_insn (INSN) 2163 2164 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2165 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2166 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2167 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2168 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2169 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2170 : 0)))) 2171 2172 /* A C expression whose value is RTL representing the value of the return 2173 address for the frame COUNT steps up from the current frame. */ 2174 2175 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2176 arm_return_addr (COUNT, FRAME) 2177 2178 /* Mask of the bits in the PC that contain the real return address 2179 when running in 26-bit mode. */ 2180 #define RETURN_ADDR_MASK26 (0x03fffffc) 2181 2182 /* Pick up the return address upon entry to a procedure. Used for 2183 dwarf2 unwind information. This also enables the table driven 2184 mechanism. */ 2185 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2186 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2187 2188 /* Used to mask out junk bits from the return address, such as 2189 processor state, interrupt status, condition codes and the like. */ 2190 #define MASK_RETURN_ADDR \ 2191 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2192 in 26 bit mode, the condition codes must be masked out of the \ 2193 return address. This does not apply to ARM6 and later processors \ 2194 when running in 32 bit mode. */ \ 2195 ((arm_arch4 || TARGET_THUMB) \ 2196 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2197 : arm_gen_return_addr_mask ()) 2198 2199 2200 /* Do not emit .note.GNU-stack by default. */ 2202 #ifndef NEED_INDICATE_EXEC_STACK 2203 #define NEED_INDICATE_EXEC_STACK 0 2204 #endif 2205 2206 #define TARGET_ARM_ARCH \ 2207 (arm_base_arch) \ 2208 2209 /* The highest Thumb instruction set version supported by the chip. */ 2210 #define TARGET_ARM_ARCH_ISA_THUMB \ 2211 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2212 2213 /* Expands to an upper-case char of the target's architectural 2214 profile. */ 2215 #define TARGET_ARM_ARCH_PROFILE \ 2216 (!arm_arch_notm \ 2217 ? 'M' \ 2218 : (arm_arch7 \ 2219 ? (strlen (arm_arch_name) >=3 \ 2220 ? (arm_arch_name[strlen (arm_arch_name) - 3]) \ 2221 : 0) \ 2222 : 0)) 2223 2224 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2225 Bit 0 for bytes, up to bit 3 for double-words. */ 2226 #define TARGET_ARM_FEATURE_LDREX \ 2227 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2228 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2229 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2230 2231 /* Set as a bit mask indicating the available widths of hardware floating 2232 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2233 32-bit support, bit 3 indicates 64-bit support. */ 2234 #define TARGET_ARM_FP \ 2235 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2236 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2237 : 0) 2238 2239 2240 /* Set as a bit mask indicating the available widths of floating point 2241 types for hardware NEON floating point. This is the same as 2242 TARGET_ARM_FP without the 64-bit bit set. */ 2243 #define TARGET_NEON_FP \ 2244 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2245 : 0) 2246 2247 /* The maximum number of parallel loads or stores we support in an ldm/stm 2248 instruction. */ 2249 #define MAX_LDM_STM_OPS 4 2250 2251 #define BIG_LITTLE_SPEC \ 2252 " %{mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})}" 2253 2254 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2255 #define BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2256 { "rewrite_mcpu", arm_rewrite_mcpu }, 2257 2258 #define ASM_CPU_SPEC \ 2259 " %{mcpu=generic-*:-march=%*;" \ 2260 " :%{march=*:-march=%*}}" \ 2261 BIG_LITTLE_SPEC 2262 2263 extern const char *arm_target_thumb_only (int argc, const char **argv); 2264 #define TARGET_MODE_SPEC_FUNCTIONS \ 2265 { "target_mode_check", arm_target_thumb_only }, 2266 2267 /* -mcpu=native handling only makes sense with compiler running on 2268 an ARM chip. */ 2269 #if defined(__arm__) && defined(__linux__) 2270 extern const char *host_detect_local_cpu (int argc, const char **argv); 2271 # define EXTRA_SPEC_FUNCTIONS \ 2272 { "local_cpu_detect", host_detect_local_cpu }, \ 2273 BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2274 TARGET_MODE_SPEC_FUNCTIONS 2275 2276 # define MCPU_MTUNE_NATIVE_SPECS \ 2277 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2278 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2279 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2280 #else 2281 # define MCPU_MTUNE_NATIVE_SPECS "" 2282 # define EXTRA_SPEC_FUNCTIONS \ 2283 BIG_LITTLE_CPU_SPEC_FUNCTIONS \ 2284 TARGET_MODE_SPEC_FUNCTIONS 2285 #endif 2286 2287 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2288 via the configuration option --with-mode or via the command line. The 2289 function target_mode_check is called to do the check with either: 2290 - an array of -march values if any is given; 2291 - an array of -mcpu values if any is given; 2292 - an empty array. */ 2293 #define TARGET_MODE_SPECS \ 2294 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:%*;mcpu=*:%*;:})}}" 2295 2296 #define DRIVER_SELF_SPECS MCPU_MTUNE_NATIVE_SPECS TARGET_MODE_SPECS 2297 #define TARGET_SUPPORTS_WIDE_INT 1 2298 2299 /* For switching between functions with different target attributes. */ 2300 #define SWITCHABLE_TARGET 1 2301 2302 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2303 representation for SHF_ARM_PURECODE in GCC. */ 2304 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2305 2306 #endif /* ! GCC_ARM_H */ 2307
Indexes created Wed Apr 15 00:22:22 UTC 2026