arm.h revision 1.1.1.8
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2018 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 #include "config/arm/arm-opts.h" 51 52 /* The processor for which instructions should be scheduled. */ 53 extern enum processor_type arm_tune; 54 55 typedef enum arm_cond_code 56 { 57 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 58 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 59 } 60 arm_cc; 61 62 extern arm_cc arm_current_cc; 63 64 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 65 66 /* The maximum number of instructions that is beneficial to 67 conditionally execute. */ 68 #undef MAX_CONDITIONAL_EXECUTE 69 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 70 71 extern int arm_target_label; 72 extern int arm_ccfsm_state; 73 extern GTY(()) rtx arm_target_insn; 74 /* Callback to output language specific object attributes. */ 75 extern void (*arm_lang_output_object_attributes_hook)(void); 76 77 /* This type is the user-visible __fp16. We need it in a few places in 78 the backend. Defined in arm-builtins.c. */ 79 extern tree arm_fp16_type_node; 80 81 82 #undef CPP_SPEC 84 #define CPP_SPEC "%(subtarget_cpp_spec) \ 85 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 86 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 87 %{mbig-endian:%{mlittle-endian: \ 88 %e-mbig-endian and -mlittle-endian may not be used together}}" 89 90 #ifndef CC1_SPEC 91 #define CC1_SPEC "" 92 #endif 93 94 /* This macro defines names of additional specifications to put in the specs 95 that can be used in various specifications like CC1_SPEC. Its definition 96 is an initializer with a subgrouping for each command option. 97 98 Each subgrouping contains a string constant, that defines the 99 specification name, and a string constant that used by the GCC driver 100 program. 101 102 Do not define this macro if it does not need to do anything. */ 103 #define EXTRA_SPECS \ 104 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 105 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 106 SUBTARGET_EXTRA_SPECS 107 108 #ifndef SUBTARGET_EXTRA_SPECS 109 #define SUBTARGET_EXTRA_SPECS 110 #endif 111 112 #ifndef SUBTARGET_CPP_SPEC 113 #define SUBTARGET_CPP_SPEC "" 114 #endif 115 116 /* Tree Target Specification. */ 118 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 119 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 120 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 121 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 122 123 /* Run-time Target Specification. */ 124 /* Use hardware floating point instructions. */ 125 #define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 126 && bitmap_bit_p (arm_active_target.isa, \ 127 isa_bit_vfpv2)) 128 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT) 129 /* User has permitted use of FP instructions, if they exist for this 130 target. */ 131 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 132 /* Use hardware floating point calling convention. */ 133 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 134 #define TARGET_IWMMXT (arm_arch_iwmmxt) 135 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 136 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 137 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT) 138 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 139 #define TARGET_ARM (! TARGET_THUMB) 140 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 141 #define TARGET_BACKTRACE (crtl->is_leaf \ 142 ? TARGET_TPCS_LEAF_FRAME \ 143 : TARGET_TPCS_FRAME) 144 #define TARGET_AAPCS_BASED \ 145 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 146 147 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 148 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 149 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 150 151 /* Only 16-bit thumb code. */ 152 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 153 /* Arm or Thumb-2 32-bit code. */ 154 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 155 /* 32-bit Thumb-2 code. */ 156 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 157 /* Thumb-1 only. */ 158 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 159 160 #define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN \ 161 && !TARGET_THUMB1) 162 163 #define TARGET_CRC32 (arm_arch_crc) 164 165 /* The following two macros concern the ability to execute coprocessor 166 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 167 only ever tested when we know we are generating for VFP hardware; we need 168 to be more careful with TARGET_NEON as noted below. */ 169 170 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 171 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 172 173 /* FPU supports VFPv3 instructions. */ 174 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 175 176 /* FPU supports FPv5 instructions. */ 177 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 178 179 /* FPU only supports VFP single-precision instructions. */ 180 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 181 182 /* FPU supports VFP double-precision instructions. */ 183 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 184 185 /* FPU supports half-precision floating-point with NEON element load/store. */ 186 #define TARGET_NEON_FP16 \ 187 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 188 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 189 190 /* FPU supports VFP half-precision floating-point conversions. */ 191 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 192 193 /* FPU supports converting between HFmode and DFmode in a single hardware 194 step. */ 195 #define TARGET_FP16_TO_DOUBLE \ 196 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 197 198 /* FPU supports fused-multiply-add operations. */ 199 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 200 201 /* FPU supports Crypto extensions. */ 202 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 203 204 /* FPU supports Neon instructions. The setting of this macro gets 205 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 206 and TARGET_HARD_FLOAT to ensure that NEON instructions are 207 available. */ 208 #define TARGET_NEON \ 209 (TARGET_32BIT && TARGET_HARD_FLOAT \ 210 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 211 212 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 213 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 214 215 /* Supports the Dot Product AdvSIMD extensions. */ 216 #define TARGET_DOTPROD (TARGET_NEON \ 217 && bitmap_bit_p (arm_active_target.isa, \ 218 isa_bit_dotprod) \ 219 && arm_arch8_2) 220 221 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 222 and later. */ 223 #define TARGET_VFP_FP16INST \ 224 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 225 226 /* Target supports the floating point FP16 instructions from ARMv8.2-A 227 and later. */ 228 #define TARGET_FP16FML (TARGET_NEON \ 229 && bitmap_bit_p (arm_active_target.isa, \ 230 isa_bit_fp16fml) \ 231 && arm_arch8_2) 232 233 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 234 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 235 236 /* Q-bit is present. */ 237 #define TARGET_ARM_QBIT \ 238 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7)) 239 /* Saturation operation, e.g. SSAT. */ 240 #define TARGET_ARM_SAT \ 241 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 242 /* "DSP" multiply instructions, eg. SMULxy. */ 243 #define TARGET_DSP_MULTIPLY \ 244 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 245 /* Integer SIMD instructions, and extend-accumulate instructions. */ 246 #define TARGET_INT_SIMD \ 247 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 248 249 /* Should MOVW/MOVT be used in preference to a constant pool. */ 250 #define TARGET_USE_MOVT \ 251 (TARGET_HAVE_MOVT \ 252 && (arm_disable_literal_pool \ 253 || (!optimize_size && !current_tune->prefer_constant_pool))) 254 255 /* Nonzero if this chip provides the DMB instruction. */ 256 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 257 258 /* Nonzero if this chip implements a memory barrier via CP15. */ 259 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 260 && ! TARGET_THUMB1) 261 262 /* Nonzero if this chip implements a memory barrier instruction. */ 263 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 264 265 /* Nonzero if this chip supports ldrex and strex */ 266 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 267 || arm_arch7 \ 268 || (arm_arch8 && !arm_arch_notm)) 269 270 /* Nonzero if this chip supports LPAE. */ 271 #define TARGET_HAVE_LPAE (arm_arch_lpae) 272 273 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 274 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 275 || arm_arch7 \ 276 || (arm_arch8 && !arm_arch_notm)) 277 278 /* Nonzero if this chip supports ldrexd and strexd. */ 279 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 280 || arm_arch7) && arm_arch_notm) 281 282 /* Nonzero if this chip supports load-acquire and store-release. */ 283 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 284 285 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 286 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 287 && TARGET_32BIT \ 288 && arm_arch_notm) 289 290 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 291 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 292 293 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 294 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 295 296 /* Nonzero if integer division instructions supported. */ 297 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 298 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 299 300 /* Nonzero if disallow volatile memory access in IT block. */ 301 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 302 303 /* Should NEON be used for 64-bits bitops. */ 304 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 305 306 /* Should constant I be slplit for OP. */ 307 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 308 ((optimize >= 2) \ 309 && can_create_pseudo_p () \ 310 && !const_ok_for_op (i, op)) 311 312 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 313 then TARGET_AAPCS_BASED must be true -- but the converse does not 314 hold. TARGET_BPABI implies the use of the BPABI runtime library, 315 etc., in addition to just the AAPCS calling conventions. */ 316 #ifndef TARGET_BPABI 317 #define TARGET_BPABI false 318 #endif 319 320 /* Transform lane numbers on big endian targets. This is used to allow for the 321 endianness difference between NEON architectural lane numbers and those 322 used in RTL */ 323 #define NEON_ENDIAN_LANE_N(mode, n) \ 324 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 325 326 /* Support for a compile-time default CPU, et cetera. The rules are: 327 --with-arch is ignored if -march or -mcpu are specified. 328 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 329 by --with-arch. 330 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 331 by -march). 332 --with-float is ignored if -mfloat-abi is specified. 333 --with-fpu is ignored if -mfpu is specified. 334 --with-abi is ignored if -mabi is specified. 335 --with-tls is ignored if -mtls-dialect is specified. */ 336 #define OPTION_DEFAULT_SPECS \ 337 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 338 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 339 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 340 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 341 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 342 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 343 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 344 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 345 346 extern const struct arm_fpu_desc 347 { 348 const char *name; 349 enum isa_feature isa_bits[isa_num_bits]; 350 } all_fpus[]; 351 352 /* Which floating point hardware to schedule for. */ 353 extern int arm_fpu_attr; 354 355 #ifndef TARGET_DEFAULT_FLOAT_ABI 356 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 357 #endif 358 359 #ifndef ARM_DEFAULT_ABI 360 #define ARM_DEFAULT_ABI ARM_ABI_APCS 361 #endif 362 363 /* AAPCS based ABIs use short enums by default. */ 364 #ifndef ARM_DEFAULT_SHORT_ENUMS 365 #define ARM_DEFAULT_SHORT_ENUMS \ 366 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 367 #endif 368 369 /* Map each of the micro-architecture variants to their corresponding 370 major architecture revision. */ 371 372 enum base_architecture 373 { 374 BASE_ARCH_0 = 0, 375 BASE_ARCH_2 = 2, 376 BASE_ARCH_3 = 3, 377 BASE_ARCH_3M = 3, 378 BASE_ARCH_4 = 4, 379 BASE_ARCH_4T = 4, 380 BASE_ARCH_5 = 5, 381 BASE_ARCH_5E = 5, 382 BASE_ARCH_5T = 5, 383 BASE_ARCH_5TE = 5, 384 BASE_ARCH_5TEJ = 5, 385 BASE_ARCH_6 = 6, 386 BASE_ARCH_6J = 6, 387 BASE_ARCH_6KZ = 6, 388 BASE_ARCH_6K = 6, 389 BASE_ARCH_6T2 = 6, 390 BASE_ARCH_6M = 6, 391 BASE_ARCH_6Z = 6, 392 BASE_ARCH_7 = 7, 393 BASE_ARCH_7A = 7, 394 BASE_ARCH_7R = 7, 395 BASE_ARCH_7M = 7, 396 BASE_ARCH_7EM = 7, 397 BASE_ARCH_8A = 8, 398 BASE_ARCH_8M_BASE = 8, 399 BASE_ARCH_8M_MAIN = 8, 400 BASE_ARCH_8R = 8 401 }; 402 403 /* The major revision number of the ARM Architecture implemented by the target. */ 404 extern enum base_architecture arm_base_arch; 405 406 /* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 407 extern int arm_arch3m; 408 409 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 410 extern int arm_arch4; 411 412 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 413 extern int arm_arch4t; 414 415 /* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 416 extern int arm_arch5; 417 418 /* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 419 extern int arm_arch5e; 420 421 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 422 extern int arm_arch6; 423 424 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 425 extern int arm_arch6k; 426 427 /* Nonzero if instructions present in ARMv6-M can be used. */ 428 extern int arm_arch6m; 429 430 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 431 extern int arm_arch7; 432 433 /* Nonzero if instructions not present in the 'M' profile can be used. */ 434 extern int arm_arch_notm; 435 436 /* Nonzero if instructions present in ARMv7E-M can be used. */ 437 extern int arm_arch7em; 438 439 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 440 extern int arm_arch8; 441 442 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 443 extern int arm_arch8_1; 444 445 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 446 extern int arm_arch8_2; 447 448 /* Nonzero if this chip supports the FP16 instructions extension of ARM 449 Architecture 8.2. */ 450 extern int arm_fp16_inst; 451 452 /* Nonzero if this chip can benefit from load scheduling. */ 453 extern int arm_ld_sched; 454 455 /* Nonzero if this chip is a StrongARM. */ 456 extern int arm_tune_strongarm; 457 458 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 459 extern int arm_arch_iwmmxt; 460 461 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 462 extern int arm_arch_iwmmxt2; 463 464 /* Nonzero if this chip is an XScale. */ 465 extern int arm_arch_xscale; 466 467 /* Nonzero if tuning for XScale. */ 468 extern int arm_tune_xscale; 469 470 /* Nonzero if tuning for stores via the write buffer. */ 471 extern int arm_tune_wbuf; 472 473 /* Nonzero if tuning for Cortex-A9. */ 474 extern int arm_tune_cortex_a9; 475 476 /* Nonzero if we should define __THUMB_INTERWORK__ in the 477 preprocessor. 478 XXX This is a bit of a hack, it's intended to help work around 479 problems in GLD which doesn't understand that armv5t code is 480 interworking clean. */ 481 extern int arm_cpp_interwork; 482 483 /* Nonzero if chip supports Thumb 1. */ 484 extern int arm_arch_thumb1; 485 486 /* Nonzero if chip supports Thumb 2. */ 487 extern int arm_arch_thumb2; 488 489 /* Nonzero if chip supports integer division instruction in ARM mode. */ 490 extern int arm_arch_arm_hwdiv; 491 492 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 493 extern int arm_arch_thumb_hwdiv; 494 495 /* Nonzero if chip disallows volatile memory access in IT block. */ 496 extern int arm_arch_no_volatile_ce; 497 498 /* Nonzero if we should use Neon to handle 64-bits operations rather 499 than core registers. */ 500 extern int prefer_neon_for_64bits; 501 502 /* Nonzero if we shouldn't use literal pools. */ 503 #ifndef USED_FOR_TARGET 504 extern bool arm_disable_literal_pool; 505 #endif 506 507 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 508 extern int arm_arch_crc; 509 510 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 511 extern int arm_arch_cmse; 512 513 #ifndef TARGET_DEFAULT 514 #define TARGET_DEFAULT (MASK_APCS_FRAME) 515 #endif 516 517 /* Nonzero if PIC code requires explicit qualifiers to generate 518 PLT and GOT relocs rather than the assembler doing so implicitly. 519 Subtargets can override these if required. */ 520 #ifndef NEED_GOT_RELOC 521 #define NEED_GOT_RELOC 0 522 #endif 523 #ifndef NEED_PLT_RELOC 524 #define NEED_PLT_RELOC 0 525 #endif 526 527 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 528 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 529 #endif 530 531 /* Nonzero if we need to refer to the GOT with a PC-relative 532 offset. In other words, generate 533 534 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 535 536 rather than 537 538 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 539 540 The default is true, which matches NetBSD. Subtargets can 541 override this if required. */ 542 #ifndef GOT_PCREL 543 #define GOT_PCREL 1 544 #endif 545 546 /* Target machine storage Layout. */ 548 549 550 /* Define this macro if it is advisable to hold scalars in registers 551 in a wider mode than that declared by the program. In such cases, 552 the value is constrained to be within the bounds of the declared 553 type, but kept valid in the wider mode. The signedness of the 554 extension may differ from that of the type. */ 555 556 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 557 if (GET_MODE_CLASS (MODE) == MODE_INT \ 558 && GET_MODE_SIZE (MODE) < 4) \ 559 { \ 560 (MODE) = SImode; \ 561 } 562 563 /* Define this if most significant bit is lowest numbered 564 in instructions that operate on numbered bit-fields. */ 565 #define BITS_BIG_ENDIAN 0 566 567 /* Define this if most significant byte of a word is the lowest numbered. 568 Most ARM processors are run in little endian mode, so that is the default. 569 If you want to have it run-time selectable, change the definition in a 570 cover file to be TARGET_BIG_ENDIAN. */ 571 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 572 573 /* Define this if most significant word of a multiword number is the lowest 574 numbered. */ 575 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 576 577 #define UNITS_PER_WORD 4 578 579 /* True if natural alignment is used for doubleword types. */ 580 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 581 582 #define DOUBLEWORD_ALIGNMENT 64 583 584 #define PARM_BOUNDARY 32 585 586 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 587 588 #define PREFERRED_STACK_BOUNDARY \ 589 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 590 591 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 592 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 593 594 /* The lowest bit is used to indicate Thumb-mode functions, so the 595 vbit must go into the delta field of pointers to member 596 functions. */ 597 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 598 599 #define EMPTY_FIELD_BOUNDARY 32 600 601 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 602 603 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 604 605 /* XXX Blah -- this macro is used directly by libobjc. Since it 606 supports no vector modes, cut out the complexity and fall back 607 on BIGGEST_FIELD_ALIGNMENT. */ 608 #ifdef IN_TARGET_LIBS 609 #define BIGGEST_FIELD_ALIGNMENT 64 610 #endif 611 612 /* Align definitions of arrays, unions and structures so that 613 initializations and copies can be made more efficient. This is not 614 ABI-changing, so it only affects places where we can see the 615 definition. Increasing the alignment tends to introduce padding, 616 so don't do this when optimizing for size/conserving stack space. */ 617 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 618 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 619 && (TREE_CODE (EXP) == ARRAY_TYPE \ 620 || TREE_CODE (EXP) == UNION_TYPE \ 621 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 622 623 /* Align global data. */ 624 #define DATA_ALIGNMENT(EXP, ALIGN) \ 625 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 626 627 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 628 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 629 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 630 631 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 632 value set in previous versions of this toolchain was 8, which produces more 633 compact structures. The command line option -mstructure_size_boundary=<n> 634 can be used to change this value. For compatibility with the ARM SDK 635 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 636 0020D) page 2-20 says "Structures are aligned on word boundaries". 637 The AAPCS specifies a value of 8. */ 638 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 639 640 /* This is the value used to initialize arm_structure_size_boundary. If a 641 particular arm target wants to change the default value it should change 642 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 643 for an example of this. */ 644 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 645 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 646 #endif 647 648 /* Nonzero if move instructions will actually fail to work 649 when given unaligned data. */ 650 #define STRICT_ALIGNMENT 1 651 652 /* wchar_t is unsigned under the AAPCS. */ 653 #ifndef WCHAR_TYPE 654 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 655 656 #define WCHAR_TYPE_SIZE BITS_PER_WORD 657 #endif 658 659 /* Sized for fixed-point types. */ 660 661 #define SHORT_FRACT_TYPE_SIZE 8 662 #define FRACT_TYPE_SIZE 16 663 #define LONG_FRACT_TYPE_SIZE 32 664 #define LONG_LONG_FRACT_TYPE_SIZE 64 665 666 #define SHORT_ACCUM_TYPE_SIZE 16 667 #define ACCUM_TYPE_SIZE 32 668 #define LONG_ACCUM_TYPE_SIZE 64 669 #define LONG_LONG_ACCUM_TYPE_SIZE 64 670 671 #define MAX_FIXED_MODE_SIZE 64 672 673 #ifndef SIZE_TYPE 674 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 675 #endif 676 677 #ifndef PTRDIFF_TYPE 678 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 679 #endif 680 681 /* AAPCS requires that structure alignment is affected by bitfields. */ 682 #ifndef PCC_BITFIELD_TYPE_MATTERS 683 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 684 #endif 685 686 /* The maximum size of the sync library functions supported. */ 687 #ifndef MAX_SYNC_LIBFUNC_SIZE 688 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 689 #endif 690 691 692 /* Standard register usage. */ 694 695 /* Register allocation in ARM Procedure Call Standard 696 (S - saved over call, F - Frame-related). 697 698 r0 * argument word/integer result 699 r1-r3 argument word 700 701 r4-r8 S register variable 702 r9 S (rfp) register variable (real frame pointer) 703 704 r10 F S (sl) stack limit (used by -mapcs-stack-check) 705 r11 F S (fp) argument pointer 706 r12 (ip) temp workspace 707 r13 F S (sp) lower end of current stack frame 708 r14 (lr) link address/workspace 709 r15 F (pc) program counter 710 711 cc This is NOT a real register, but is used internally 712 to represent things that use or set the condition 713 codes. 714 sfp This isn't either. It is used during rtl generation 715 since the offset between the frame pointer and the 716 auto's isn't known until after register allocation. 717 afp Nor this, we only need this because of non-local 718 goto. Without it fp appears to be used and the 719 elimination code won't get rid of sfp. It tracks 720 fp exactly at all times. 721 722 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 723 724 /* s0-s15 VFP scratch (aka d0-d7). 725 s16-s31 S VFP variable (aka d8-d15). 726 vfpcc Not a real register. Represents the VFP condition 727 code flags. */ 728 729 /* The stack backtrace structure is as follows: 730 fp points to here: | save code pointer | [fp] 731 | return link value | [fp, #-4] 732 | return sp value | [fp, #-8] 733 | return fp value | [fp, #-12] 734 [| saved r10 value |] 735 [| saved r9 value |] 736 [| saved r8 value |] 737 [| saved r7 value |] 738 [| saved r6 value |] 739 [| saved r5 value |] 740 [| saved r4 value |] 741 [| saved r3 value |] 742 [| saved r2 value |] 743 [| saved r1 value |] 744 [| saved r0 value |] 745 r0-r3 are not normally saved in a C function. */ 746 747 /* 1 for registers that have pervasive standard uses 748 and are not available for the register allocator. */ 749 #define FIXED_REGISTERS \ 750 { \ 751 /* Core regs. */ \ 752 0,0,0,0,0,0,0,0, \ 753 0,0,0,0,0,1,0,1, \ 754 /* VFP regs. */ \ 755 1,1,1,1,1,1,1,1, \ 756 1,1,1,1,1,1,1,1, \ 757 1,1,1,1,1,1,1,1, \ 758 1,1,1,1,1,1,1,1, \ 759 1,1,1,1,1,1,1,1, \ 760 1,1,1,1,1,1,1,1, \ 761 1,1,1,1,1,1,1,1, \ 762 1,1,1,1,1,1,1,1, \ 763 /* IWMMXT regs. */ \ 764 1,1,1,1,1,1,1,1, \ 765 1,1,1,1,1,1,1,1, \ 766 1,1,1,1, \ 767 /* Specials. */ \ 768 1,1,1,1 \ 769 } 770 771 /* 1 for registers not available across function calls. 772 These must include the FIXED_REGISTERS and also any 773 registers that can be used without being saved. 774 The latter must include the registers where values are returned 775 and the register where structure-value addresses are passed. 776 Aside from that, you can include as many other registers as you like. 777 The CC is not preserved over function calls on the ARM 6, so it is 778 easier to assume this for all. SFP is preserved, since FP is. */ 779 #define CALL_USED_REGISTERS \ 780 { \ 781 /* Core regs. */ \ 782 1,1,1,1,0,0,0,0, \ 783 0,0,0,0,1,1,1,1, \ 784 /* VFP Regs. */ \ 785 1,1,1,1,1,1,1,1, \ 786 1,1,1,1,1,1,1,1, \ 787 1,1,1,1,1,1,1,1, \ 788 1,1,1,1,1,1,1,1, \ 789 1,1,1,1,1,1,1,1, \ 790 1,1,1,1,1,1,1,1, \ 791 1,1,1,1,1,1,1,1, \ 792 1,1,1,1,1,1,1,1, \ 793 /* IWMMXT regs. */ \ 794 1,1,1,1,1,1,1,1, \ 795 1,1,1,1,1,1,1,1, \ 796 1,1,1,1, \ 797 /* Specials. */ \ 798 1,1,1,1 \ 799 } 800 801 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 802 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 803 #endif 804 805 /* These are a couple of extensions to the formats accepted 806 by asm_fprintf: 807 %@ prints out ASM_COMMENT_START 808 %r prints out REGISTER_PREFIX reg_names[arg] */ 809 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 810 case '@': \ 811 fputs (ASM_COMMENT_START, FILE); \ 812 break; \ 813 \ 814 case 'r': \ 815 fputs (REGISTER_PREFIX, FILE); \ 816 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 817 break; 818 819 /* Round X up to the nearest word. */ 820 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 821 822 /* Convert fron bytes to ints. */ 823 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 824 825 /* The number of (integer) registers required to hold a quantity of type MODE. 826 Also used for VFP registers. */ 827 #define ARM_NUM_REGS(MODE) \ 828 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 829 830 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 831 #define ARM_NUM_REGS2(MODE, TYPE) \ 832 ARM_NUM_INTS ((MODE) == BLKmode ? \ 833 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 834 835 /* The number of (integer) argument register available. */ 836 #define NUM_ARG_REGS 4 837 838 /* And similarly for the VFP. */ 839 #define NUM_VFP_ARG_REGS 16 840 841 /* Return the register number of the N'th (integer) argument. */ 842 #define ARG_REGISTER(N) (N - 1) 843 844 /* Specify the registers used for certain standard purposes. 845 The values of these macros are register numbers. */ 846 847 /* The number of the last argument register. */ 848 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 849 850 /* The numbers of the Thumb register ranges. */ 851 #define FIRST_LO_REGNUM 0 852 #define LAST_LO_REGNUM 7 853 #define FIRST_HI_REGNUM 8 854 #define LAST_HI_REGNUM 11 855 856 /* Overridden by config/arm/bpabi.h. */ 857 #ifndef ARM_UNWIND_INFO 858 #define ARM_UNWIND_INFO 0 859 #endif 860 861 /* Overriden by config/arm/netbsd-eabi.h. */ 862 #ifndef ARM_DWARF_UNWIND_TABLES 863 #define ARM_DWARF_UNWIND_TABLES 0 864 #endif 865 866 /* Use r0 and r1 to pass exception handling information. */ 867 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 868 869 /* The register that holds the return address in exception handlers. */ 870 #define ARM_EH_STACKADJ_REGNUM 2 871 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 872 873 #ifndef ARM_TARGET2_DWARF_FORMAT 874 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 875 #endif 876 877 #if ARM_DWARF_UNWIND_TABLES 878 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 879 for 32bit platforms. */ 880 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 881 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 882 : DW_EH_PE_absptr) 883 #else 884 /* ttype entries (the only interesting data references used) 885 use TARGET2 relocations. */ 886 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 887 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 888 : DW_EH_PE_absptr) 889 #endif 890 891 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 892 as an invisible last argument (possible since varargs don't exist in 893 Pascal), so the following is not true. */ 894 #define STATIC_CHAIN_REGNUM 12 895 896 /* Define this to be where the real frame pointer is if it is not possible to 897 work out the offset between the frame pointer and the automatic variables 898 until after register allocation has taken place. FRAME_POINTER_REGNUM 899 should point to a special register that we will make sure is eliminated. 900 901 For the Thumb we have another problem. The TPCS defines the frame pointer 902 as r11, and GCC believes that it is always possible to use the frame pointer 903 as base register for addressing purposes. (See comments in 904 find_reloads_address()). But - the Thumb does not allow high registers, 905 including r11, to be used as base address registers. Hence our problem. 906 907 The solution used here, and in the old thumb port is to use r7 instead of 908 r11 as the hard frame pointer and to have special code to generate 909 backtrace structures on the stack (if required to do so via a command line 910 option) using r11. This is the only 'user visible' use of r11 as a frame 911 pointer. */ 912 #define ARM_HARD_FRAME_POINTER_REGNUM 11 913 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 914 915 #define HARD_FRAME_POINTER_REGNUM \ 916 (TARGET_ARM \ 917 ? ARM_HARD_FRAME_POINTER_REGNUM \ 918 : THUMB_HARD_FRAME_POINTER_REGNUM) 919 920 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 921 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 922 923 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 924 925 /* Register to use for pushing function arguments. */ 926 #define STACK_POINTER_REGNUM SP_REGNUM 927 928 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 929 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 930 931 /* Need to sync with WCGR in iwmmxt.md. */ 932 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 933 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 934 935 #define IS_IWMMXT_REGNUM(REGNUM) \ 936 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 937 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 938 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 939 940 /* Base register for access to local variables of the function. */ 941 #define FRAME_POINTER_REGNUM 102 942 943 /* Base register for access to arguments of the function. */ 944 #define ARG_POINTER_REGNUM 103 945 946 #define FIRST_VFP_REGNUM 16 947 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 948 #define LAST_VFP_REGNUM \ 949 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 950 951 #define IS_VFP_REGNUM(REGNUM) \ 952 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 953 954 /* VFP registers are split into two types: those defined by VFP versions < 3 955 have D registers overlaid on consecutive pairs of S registers. VFP version 3 956 defines 16 new D registers (d16-d31) which, for simplicity and correctness 957 in various parts of the backend, we implement as "fake" single-precision 958 registers (which would be S32-S63, but cannot be used in that way). The 959 following macros define these ranges of registers. */ 960 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 961 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 962 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 963 964 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 965 ((REGNUM) <= LAST_LO_VFP_REGNUM) 966 967 /* DFmode values are only valid in even register pairs. */ 968 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 969 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 970 971 /* Neon Quad values must start at a multiple of four registers. */ 972 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 973 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 974 975 /* Neon structures of vectors must be in even register pairs and there 976 must be enough registers available. Because of various patterns 977 requiring quad registers, we require them to start at a multiple of 978 four. */ 979 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 980 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 981 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 982 983 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 984 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 985 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 986 #define FIRST_PSEUDO_REGISTER 104 987 988 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 989 990 /* Value should be nonzero if functions must have frame pointers. 991 Zero means the frame pointer need not be set up (and parms may be accessed 992 via the stack pointer) in functions that seem suitable. 993 If we have to have a frame pointer we might as well make use of it. 994 APCS says that the frame pointer does not need to be pushed in leaf 995 functions, or simple tail call functions. */ 996 997 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 998 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 999 #endif 1000 1001 #define VALID_IWMMXT_REG_MODE(MODE) \ 1002 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1003 1004 /* Modes valid for Neon D registers. */ 1005 #define VALID_NEON_DREG_MODE(MODE) \ 1006 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1007 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1008 1009 /* Modes valid for Neon Q registers. */ 1010 #define VALID_NEON_QREG_MODE(MODE) \ 1011 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1012 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode) 1013 1014 /* Structure modes valid for Neon registers. */ 1015 #define VALID_NEON_STRUCT_MODE(MODE) \ 1016 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1017 || (MODE) == CImode || (MODE) == XImode) 1018 1019 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1020 extern int arm_regs_in_sequence[]; 1021 1022 /* The order in which register should be allocated. It is good to use ip 1023 since no saving is required (though calls clobber it) and it never contains 1024 function parameters. It is quite good to use lr since other calls may 1025 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1026 least likely to contain a function parameter; in addition results are 1027 returned in r0. 1028 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1029 then D8-D15. The reason for doing this is to attempt to reduce register 1030 pressure when both single- and double-precision registers are used in a 1031 function. */ 1032 1033 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1034 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1035 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1036 1037 #define REG_ALLOC_ORDER \ 1038 { \ 1039 /* General registers. */ \ 1040 3, 2, 1, 0, 12, 14, 4, 5, \ 1041 6, 7, 8, 9, 10, 11, \ 1042 /* High VFP registers. */ \ 1043 VREG(32), VREG(33), VREG(34), VREG(35), \ 1044 VREG(36), VREG(37), VREG(38), VREG(39), \ 1045 VREG(40), VREG(41), VREG(42), VREG(43), \ 1046 VREG(44), VREG(45), VREG(46), VREG(47), \ 1047 VREG(48), VREG(49), VREG(50), VREG(51), \ 1048 VREG(52), VREG(53), VREG(54), VREG(55), \ 1049 VREG(56), VREG(57), VREG(58), VREG(59), \ 1050 VREG(60), VREG(61), VREG(62), VREG(63), \ 1051 /* VFP argument registers. */ \ 1052 VREG(15), VREG(14), VREG(13), VREG(12), \ 1053 VREG(11), VREG(10), VREG(9), VREG(8), \ 1054 VREG(7), VREG(6), VREG(5), VREG(4), \ 1055 VREG(3), VREG(2), VREG(1), VREG(0), \ 1056 /* VFP call-saved registers. */ \ 1057 VREG(16), VREG(17), VREG(18), VREG(19), \ 1058 VREG(20), VREG(21), VREG(22), VREG(23), \ 1059 VREG(24), VREG(25), VREG(26), VREG(27), \ 1060 VREG(28), VREG(29), VREG(30), VREG(31), \ 1061 /* IWMMX registers. */ \ 1062 WREG(0), WREG(1), WREG(2), WREG(3), \ 1063 WREG(4), WREG(5), WREG(6), WREG(7), \ 1064 WREG(8), WREG(9), WREG(10), WREG(11), \ 1065 WREG(12), WREG(13), WREG(14), WREG(15), \ 1066 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1067 /* Registers not for general use. */ \ 1068 CC_REGNUM, VFPCC_REGNUM, \ 1069 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1070 SP_REGNUM, PC_REGNUM \ 1071 } 1072 1073 /* Use different register alloc ordering for Thumb. */ 1074 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1075 1076 /* Tell IRA to use the order we define rather than messing it up with its 1077 own cost calculations. */ 1078 #define HONOR_REG_ALLOC_ORDER 1 1079 1080 /* Interrupt functions can only use registers that have already been 1081 saved by the prologue, even if they would normally be 1082 call-clobbered. */ 1083 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1084 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1085 df_regs_ever_live_p (DST)) 1086 1087 /* Register and constant classes. */ 1089 1090 /* Register classes. */ 1091 enum reg_class 1092 { 1093 NO_REGS, 1094 LO_REGS, 1095 STACK_REG, 1096 BASE_REGS, 1097 HI_REGS, 1098 CALLER_SAVE_REGS, 1099 GENERAL_REGS, 1100 CORE_REGS, 1101 VFP_D0_D7_REGS, 1102 VFP_LO_REGS, 1103 VFP_HI_REGS, 1104 VFP_REGS, 1105 IWMMXT_REGS, 1106 IWMMXT_GR_REGS, 1107 CC_REG, 1108 VFPCC_REG, 1109 SFP_REG, 1110 AFP_REG, 1111 ALL_REGS, 1112 LIM_REG_CLASSES 1113 }; 1114 1115 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1116 1117 /* Give names of register classes as strings for dump file. */ 1118 #define REG_CLASS_NAMES \ 1119 { \ 1120 "NO_REGS", \ 1121 "LO_REGS", \ 1122 "STACK_REG", \ 1123 "BASE_REGS", \ 1124 "HI_REGS", \ 1125 "CALLER_SAVE_REGS", \ 1126 "GENERAL_REGS", \ 1127 "CORE_REGS", \ 1128 "VFP_D0_D7_REGS", \ 1129 "VFP_LO_REGS", \ 1130 "VFP_HI_REGS", \ 1131 "VFP_REGS", \ 1132 "IWMMXT_REGS", \ 1133 "IWMMXT_GR_REGS", \ 1134 "CC_REG", \ 1135 "VFPCC_REG", \ 1136 "SFP_REG", \ 1137 "AFP_REG", \ 1138 "ALL_REGS" \ 1139 } 1140 1141 /* Define which registers fit in which classes. 1142 This is an initializer for a vector of HARD_REG_SET 1143 of length N_REG_CLASSES. */ 1144 #define REG_CLASS_CONTENTS \ 1145 { \ 1146 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1147 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1148 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1149 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1150 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1151 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1152 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1153 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1154 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1155 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1156 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1157 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1158 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1159 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1160 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1161 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1162 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1163 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1164 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1165 } 1166 1167 /* Any of the VFP register classes. */ 1168 #define IS_VFP_CLASS(X) \ 1169 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1170 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1171 1172 /* The same information, inverted: 1173 Return the class number of the smallest class containing 1174 reg number REGNO. This could be a conditional expression 1175 or could index an array. */ 1176 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1177 1178 /* The class value for index registers, and the one for base regs. */ 1179 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1180 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1181 1182 /* For the Thumb the high registers cannot be used as base registers 1183 when addressing quantities in QI or HI mode; if we don't know the 1184 mode, then we must be conservative. */ 1185 #define MODE_BASE_REG_CLASS(MODE) \ 1186 (TARGET_32BIT ? CORE_REGS \ 1187 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1188 : LO_REGS) 1189 1190 /* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1191 instead of BASE_REGS. */ 1192 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1193 1194 /* When this hook returns true for MODE, the compiler allows 1195 registers explicitly used in the rtl to be used as spill registers 1196 but prevents the compiler from extending the lifetime of these 1197 registers. */ 1198 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1199 arm_small_register_classes_for_mode_p 1200 1201 /* Must leave BASE_REGS reloads alone */ 1202 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1203 (lra_in_progress ? NO_REGS \ 1204 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1205 ? ((true_regnum (X) == -1 ? LO_REGS \ 1206 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1207 : NO_REGS)) \ 1208 : NO_REGS)) 1209 1210 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1211 (lra_in_progress ? NO_REGS \ 1212 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1213 ? ((true_regnum (X) == -1 ? LO_REGS \ 1214 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1215 : NO_REGS)) \ 1216 : NO_REGS) 1217 1218 /* Return the register class of a scratch register needed to copy IN into 1219 or out of a register in CLASS in MODE. If it can be done directly, 1220 NO_REGS is returned. */ 1221 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1222 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1223 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1224 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1225 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1226 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1227 : TARGET_32BIT \ 1228 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1229 ? GENERAL_REGS : NO_REGS) \ 1230 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1231 1232 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1233 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1234 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1235 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1236 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1237 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1238 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1239 (TARGET_32BIT ? \ 1240 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1241 && CONSTANT_P (X)) \ 1242 ? GENERAL_REGS : \ 1243 (((MODE) == HImode && ! arm_arch4 \ 1244 && (MEM_P (X) \ 1245 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1246 && true_regnum (X) == -1))) \ 1247 ? GENERAL_REGS : NO_REGS) \ 1248 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1249 1250 /* Return the maximum number of consecutive registers 1251 needed to represent mode MODE in a register of class CLASS. 1252 ARM regs are UNITS_PER_WORD bits. 1253 FIXME: Is this true for iWMMX? */ 1254 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1255 (ARM_NUM_REGS (MODE)) 1256 1257 /* If defined, gives a class of registers that cannot be used as the 1258 operand of a SUBREG that changes the mode of the object illegally. */ 1259 1260 /* Stack layout; function entry, exit and calling. */ 1262 1263 /* Define this if pushing a word on the stack 1264 makes the stack pointer a smaller address. */ 1265 #define STACK_GROWS_DOWNWARD 1 1266 1267 /* Define this to nonzero if the nominal address of the stack frame 1268 is at the high-address end of the local variables; 1269 that is, each additional local variable allocated 1270 goes at a more negative offset in the frame. */ 1271 #define FRAME_GROWS_DOWNWARD 1 1272 1273 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1274 When present, it is one word in size, and sits at the top of the frame, 1275 between the soft frame pointer and either r7 or r11. 1276 1277 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1278 and only then if some outgoing arguments are passed on the stack. It would 1279 be tempting to also check whether the stack arguments are passed by indirect 1280 calls, but there seems to be no reason in principle why a post-reload pass 1281 couldn't convert a direct call into an indirect one. */ 1282 #define CALLER_INTERWORKING_SLOT_SIZE \ 1283 (TARGET_CALLER_INTERWORKING \ 1284 && maybe_ne (crtl->outgoing_args_size, 0) \ 1285 ? UNITS_PER_WORD : 0) 1286 1287 /* If we generate an insn to push BYTES bytes, 1288 this says how many the stack pointer really advances by. */ 1289 /* The push insns do not do this rounding implicitly. 1290 So don't define this. */ 1291 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1292 1293 /* Define this if the maximum size of all the outgoing args is to be 1294 accumulated and pushed during the prologue. The amount can be 1295 found in the variable crtl->outgoing_args_size. */ 1296 #define ACCUMULATE_OUTGOING_ARGS 1 1297 1298 /* Offset of first parameter from the argument pointer register value. */ 1299 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1300 1301 /* Amount of memory needed for an untyped call to save all possible return 1302 registers. */ 1303 #define APPLY_RESULT_SIZE arm_apply_result_size() 1304 1305 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1306 values must be in memory. On the ARM, they need only do so if larger 1307 than a word, or if they contain elements offset from zero in the struct. */ 1308 #define DEFAULT_PCC_STRUCT_RETURN 0 1309 1310 /* These bits describe the different types of function supported 1311 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1312 normal function and an interworked function, for example. Knowing the 1313 type of a function is important for determining its prologue and 1314 epilogue sequences. 1315 Note value 7 is currently unassigned. Also note that the interrupt 1316 function types all have bit 2 set, so that they can be tested for easily. 1317 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1318 machine_function structure is initialized (to zero) func_type will 1319 default to unknown. This will force the first use of arm_current_func_type 1320 to call arm_compute_func_type. */ 1321 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1322 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1323 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1324 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1325 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1326 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1327 1328 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1329 1330 /* In addition functions can have several type modifiers, 1331 outlined by these bit masks: */ 1332 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1333 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1334 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1335 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1336 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1337 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1338 1339 /* Some macros to test these flags. */ 1340 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1341 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1342 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1343 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1344 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1345 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1346 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1347 1348 1349 /* Structure used to hold the function stack frame layout. Offsets are 1350 relative to the stack pointer on function entry. Positive offsets are 1351 in the direction of stack growth. 1352 Only soft_frame is used in thumb mode. */ 1353 1354 typedef struct GTY(()) arm_stack_offsets 1355 { 1356 int saved_args; /* ARG_POINTER_REGNUM. */ 1357 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1358 int saved_regs; 1359 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1360 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1361 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1362 unsigned int saved_regs_mask; 1363 } 1364 arm_stack_offsets; 1365 1366 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1367 /* A C structure for machine-specific, per-function data. 1368 This is added to the cfun structure. */ 1369 typedef struct GTY(()) machine_function 1370 { 1371 /* Additional stack adjustment in __builtin_eh_throw. */ 1372 rtx eh_epilogue_sp_ofs; 1373 /* Records if LR has to be saved for far jumps. */ 1374 int far_jump_used; 1375 /* Records if ARG_POINTER was ever live. */ 1376 int arg_pointer_live; 1377 /* Records if the save of LR has been eliminated. */ 1378 int lr_save_eliminated; 1379 /* The size of the stack frame. Only valid after reload. */ 1380 arm_stack_offsets stack_offsets; 1381 /* Records the type of the current function. */ 1382 unsigned long func_type; 1383 /* Record if the function has a variable argument list. */ 1384 int uses_anonymous_args; 1385 /* Records if sibcalls are blocked because an argument 1386 register is needed to preserve stack alignment. */ 1387 int sibcall_blocked; 1388 /* The PIC register for this function. This might be a pseudo. */ 1389 rtx pic_reg; 1390 /* Labels for per-function Thumb call-via stubs. One per potential calling 1391 register. We can never call via LR or PC. We can call via SP if a 1392 trampoline happens to be on the top of the stack. */ 1393 rtx call_via[14]; 1394 /* Set to 1 when a return insn is output, this means that the epilogue 1395 is not needed. */ 1396 int return_used_this_function; 1397 /* When outputting Thumb-1 code, record the last insn that provides 1398 information about condition codes, and the comparison operands. */ 1399 rtx thumb1_cc_insn; 1400 rtx thumb1_cc_op0; 1401 rtx thumb1_cc_op1; 1402 /* Also record the CC mode that is supported. */ 1403 machine_mode thumb1_cc_mode; 1404 /* Set to 1 after arm_reorg has started. */ 1405 int after_arm_reorg; 1406 /* The number of bytes used to store the static chain register on the 1407 stack, above the stack frame. */ 1408 int static_chain_stack_bytes; 1409 } 1410 machine_function; 1411 #endif 1412 1413 /* As in the machine_function, a global set of call-via labels, for code 1414 that is in text_section. */ 1415 extern GTY(()) rtx thumb_call_via_label[14]; 1416 1417 /* The number of potential ways of assigning to a co-processor. */ 1418 #define ARM_NUM_COPROC_SLOTS 1 1419 1420 /* Enumeration of procedure calling standard variants. We don't really 1421 support all of these yet. */ 1422 enum arm_pcs 1423 { 1424 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1425 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1426 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1427 /* This must be the last AAPCS variant. */ 1428 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1429 ARM_PCS_ATPCS, /* ATPCS. */ 1430 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1431 ARM_PCS_UNKNOWN 1432 }; 1433 1434 /* Default procedure calling standard of current compilation unit. */ 1435 extern enum arm_pcs arm_pcs_default; 1436 1437 #if !defined (USED_FOR_TARGET) 1438 /* A C type for declaring a variable that is used as the first argument of 1439 `FUNCTION_ARG' and other related values. */ 1440 typedef struct 1441 { 1442 /* This is the number of registers of arguments scanned so far. */ 1443 int nregs; 1444 /* This is the number of iWMMXt register arguments scanned so far. */ 1445 int iwmmxt_nregs; 1446 int named_count; 1447 int nargs; 1448 /* Which procedure call variant to use for this call. */ 1449 enum arm_pcs pcs_variant; 1450 1451 /* AAPCS related state tracking. */ 1452 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1453 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1454 this argument, or -1 if using core 1455 registers. */ 1456 int aapcs_ncrn; 1457 int aapcs_next_ncrn; 1458 rtx aapcs_reg; /* Register assigned to this argument. */ 1459 int aapcs_partial; /* How many bytes are passed in regs (if 1460 split between core regs and stack. 1461 Zero otherwise. */ 1462 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1463 int can_split; /* Argument can be split between core regs 1464 and the stack. */ 1465 /* Private data for tracking VFP register allocation */ 1466 unsigned aapcs_vfp_regs_free; 1467 unsigned aapcs_vfp_reg_alloc; 1468 int aapcs_vfp_rcount; 1469 MACHMODE aapcs_vfp_rmode; 1470 } CUMULATIVE_ARGS; 1471 #endif 1472 1473 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1474 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1475 1476 /* For AAPCS, padding should never be below the argument. For other ABIs, 1477 * mimic the default. */ 1478 #define PAD_VARARGS_DOWN \ 1479 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1480 1481 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1482 for a call to a function whose data type is FNTYPE. 1483 For a library call, FNTYPE is 0. 1484 On the ARM, the offset starts at 0. */ 1485 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1486 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1487 1488 /* 1 if N is a possible register number for function argument passing. 1489 On the ARM, r0-r3 are used to pass args. */ 1490 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1491 (IN_RANGE ((REGNO), 0, 3) \ 1492 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1493 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1494 || (TARGET_IWMMXT_ABI \ 1495 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1496 1497 1498 /* If your target environment doesn't prefix user functions with an 1500 underscore, you may wish to re-define this to prevent any conflicts. */ 1501 #ifndef ARM_MCOUNT_NAME 1502 #define ARM_MCOUNT_NAME "*mcount" 1503 #endif 1504 1505 /* Call the function profiler with a given profile label. The Acorn 1506 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1507 On the ARM the full profile code will look like: 1508 .data 1509 LP1 1510 .word 0 1511 .text 1512 mov ip, lr 1513 bl mcount 1514 .word LP1 1515 1516 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1517 will output the .text section. 1518 1519 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1520 ``prof'' doesn't seem to mind about this! 1521 1522 Note - this version of the code is designed to work in both ARM and 1523 Thumb modes. */ 1524 #ifndef ARM_FUNCTION_PROFILER 1525 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1526 { \ 1527 char temp[20]; \ 1528 rtx sym; \ 1529 \ 1530 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1531 IP_REGNUM, LR_REGNUM); \ 1532 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1533 fputc ('\n', STREAM); \ 1534 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1535 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1536 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1537 } 1538 #endif 1539 1540 #ifdef THUMB_FUNCTION_PROFILER 1541 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1542 if (TARGET_ARM) \ 1543 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1544 else \ 1545 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1546 #else 1547 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1548 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1549 #endif 1550 1551 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1552 the stack pointer does not matter. The value is tested only in 1553 functions that have frame pointers. 1554 No definition is equivalent to always zero. 1555 1556 On the ARM, the function epilogue recovers the stack pointer from the 1557 frame. */ 1558 #define EXIT_IGNORE_STACK 1 1559 1560 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1561 1562 /* Determine if the epilogue should be output as RTL. 1563 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1564 #define USE_RETURN_INSN(ISCOND) \ 1565 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1566 1567 /* Definitions for register eliminations. 1568 1569 This is an array of structures. Each structure initializes one pair 1570 of eliminable registers. The "from" register number is given first, 1571 followed by "to". Eliminations of the same "from" register are listed 1572 in order of preference. 1573 1574 We have two registers that can be eliminated on the ARM. First, the 1575 arg pointer register can often be eliminated in favor of the stack 1576 pointer register. Secondly, the pseudo frame pointer register can always 1577 be eliminated; it is replaced with either the stack or the real frame 1578 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1579 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1580 1581 #define ELIMINABLE_REGS \ 1582 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1583 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1584 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1585 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1586 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1587 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1588 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1589 1590 /* Define the offset between two registers, one to be eliminated, and the 1591 other its replacement, at the start of a routine. */ 1592 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1593 if (TARGET_ARM) \ 1594 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1595 else \ 1596 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1597 1598 /* Special case handling of the location of arguments passed on the stack. */ 1599 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1600 1601 /* Initialize data used by insn expanders. This is called from insn_emit, 1602 once for every function before code is generated. */ 1603 #define INIT_EXPANDERS arm_init_expanders () 1604 1605 /* Length in units of the trampoline for entering a nested function. */ 1606 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1607 1608 /* Alignment required for a trampoline in bits. */ 1609 #define TRAMPOLINE_ALIGNMENT 32 1610 1611 /* Addressing modes, and classification of registers for them. */ 1613 #define HAVE_POST_INCREMENT 1 1614 #define HAVE_PRE_INCREMENT TARGET_32BIT 1615 #define HAVE_POST_DECREMENT TARGET_32BIT 1616 #define HAVE_PRE_DECREMENT TARGET_32BIT 1617 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1618 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1619 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1620 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1621 1622 enum arm_auto_incmodes 1623 { 1624 ARM_POST_INC, 1625 ARM_PRE_INC, 1626 ARM_POST_DEC, 1627 ARM_PRE_DEC 1628 }; 1629 1630 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1631 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1632 #define USE_LOAD_POST_INCREMENT(mode) \ 1633 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1634 #define USE_LOAD_PRE_INCREMENT(mode) \ 1635 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1636 #define USE_LOAD_POST_DECREMENT(mode) \ 1637 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1638 #define USE_LOAD_PRE_DECREMENT(mode) \ 1639 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1640 1641 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1642 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1643 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1644 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1645 1646 /* Macros to check register numbers against specific register classes. */ 1647 1648 /* These assume that REGNO is a hard or pseudo reg number. 1649 They give nonzero only if REGNO is a hard reg of the suitable class 1650 or a pseudo reg currently allocated to a suitable hard reg. */ 1651 #define TEST_REGNO(R, TEST, VALUE) \ 1652 ((R TEST VALUE) \ 1653 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1654 1655 /* Don't allow the pc to be used. */ 1656 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1657 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1658 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1659 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1660 1661 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1662 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1663 || (GET_MODE_SIZE (MODE) >= 4 \ 1664 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1665 1666 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1667 (TARGET_THUMB1 \ 1668 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1669 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1670 1671 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1672 For Thumb, we can not use SP + reg, so reject SP. */ 1673 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1674 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1675 1676 /* For ARM code, we don't care about the mode, but for Thumb, the index 1677 must be suitable for use in a QImode load. */ 1678 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1679 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1680 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1681 1682 /* Maximum number of registers that can appear in a valid memory address. 1683 Shifts in addresses can't be by a register. */ 1684 #define MAX_REGS_PER_ADDRESS 2 1685 1686 /* Recognize any constant value that is a valid address. */ 1687 /* XXX We can address any constant, eventually... */ 1688 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1689 #define CONSTANT_ADDRESS_P(X) \ 1690 (GET_CODE (X) == SYMBOL_REF \ 1691 && (CONSTANT_POOL_ADDRESS_P (X) \ 1692 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1693 1694 /* True if SYMBOL + OFFSET constants must refer to something within 1695 SYMBOL's section. */ 1696 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1697 1698 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1699 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1700 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1701 #endif 1702 1703 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1704 #define SUBTARGET_NAME_ENCODING_LENGTHS 1705 #endif 1706 1707 /* This is a C fragment for the inside of a switch statement. 1708 Each case label should return the number of characters to 1709 be stripped from the start of a function's name, if that 1710 name starts with the indicated character. */ 1711 #define ARM_NAME_ENCODING_LENGTHS \ 1712 case '*': return 1; \ 1713 SUBTARGET_NAME_ENCODING_LENGTHS 1714 1715 /* This is how to output a reference to a user-level label named NAME. 1716 `assemble_name' uses this. */ 1717 #undef ASM_OUTPUT_LABELREF 1718 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1719 arm_asm_output_labelref (FILE, NAME) 1720 1721 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1722 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1723 if (TARGET_THUMB2) \ 1724 thumb2_asm_output_opcode (STREAM); 1725 1726 /* The EABI specifies that constructors should go in .init_array. 1727 Other targets use .ctors for compatibility. */ 1728 #ifndef ARM_EABI_CTORS_SECTION_OP 1729 #define ARM_EABI_CTORS_SECTION_OP \ 1730 "\t.section\t.init_array,\"aw\",%init_array" 1731 #endif 1732 #ifndef ARM_EABI_DTORS_SECTION_OP 1733 #define ARM_EABI_DTORS_SECTION_OP \ 1734 "\t.section\t.fini_array,\"aw\",%fini_array" 1735 #endif 1736 #define ARM_CTORS_SECTION_OP \ 1737 "\t.section\t.ctors,\"aw\",%progbits" 1738 #define ARM_DTORS_SECTION_OP \ 1739 "\t.section\t.dtors,\"aw\",%progbits" 1740 1741 /* Define CTORS_SECTION_ASM_OP. */ 1742 #undef CTORS_SECTION_ASM_OP 1743 #undef DTORS_SECTION_ASM_OP 1744 #ifndef IN_LIBGCC2 1745 # define CTORS_SECTION_ASM_OP \ 1746 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1747 # define DTORS_SECTION_ASM_OP \ 1748 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1749 #else /* !defined (IN_LIBGCC2) */ 1750 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1751 so we cannot use the definition above. */ 1752 # ifdef __ARM_EABI__ 1753 /* The .ctors section is not part of the EABI, so we do not define 1754 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1755 from trying to use it. We do define it when doing normal 1756 compilation, as .init_array can be used instead of .ctors. */ 1757 /* There is no need to emit begin or end markers when using 1758 init_array; the dynamic linker will compute the size of the 1759 array itself based on special symbols created by the static 1760 linker. However, we do need to arrange to set up 1761 exception-handling here. */ 1762 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1763 # define CTOR_LIST_END /* empty */ 1764 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1765 # define DTOR_LIST_END /* empty */ 1766 # else /* !defined (__ARM_EABI__) */ 1767 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1768 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1769 # endif /* !defined (__ARM_EABI__) */ 1770 #endif /* !defined (IN_LIBCC2) */ 1771 1772 /* True if the operating system can merge entities with vague linkage 1773 (e.g., symbols in COMDAT group) during dynamic linking. */ 1774 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1775 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1776 #endif 1777 1778 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1779 1780 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1781 and check its validity for a certain class. 1782 We have two alternate definitions for each of them. 1783 The usual definition accepts all pseudo regs; the other rejects 1784 them unless they have been allocated suitable hard regs. 1785 The symbol REG_OK_STRICT causes the latter definition to be used. 1786 Thumb-2 has the same restrictions as arm. */ 1787 #ifndef REG_OK_STRICT 1788 1789 #define ARM_REG_OK_FOR_BASE_P(X) \ 1790 (REGNO (X) <= LAST_ARM_REGNUM \ 1791 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1792 || REGNO (X) == FRAME_POINTER_REGNUM \ 1793 || REGNO (X) == ARG_POINTER_REGNUM) 1794 1795 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1796 ((REGNO (X) <= LAST_ARM_REGNUM \ 1797 && REGNO (X) != STACK_POINTER_REGNUM) \ 1798 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1799 || REGNO (X) == FRAME_POINTER_REGNUM \ 1800 || REGNO (X) == ARG_POINTER_REGNUM) 1801 1802 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1803 (REGNO (X) <= LAST_LO_REGNUM \ 1804 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1805 || (GET_MODE_SIZE (MODE) >= 4 \ 1806 && (REGNO (X) == STACK_POINTER_REGNUM \ 1807 || (X) == hard_frame_pointer_rtx \ 1808 || (X) == arg_pointer_rtx))) 1809 1810 #define REG_STRICT_P 0 1811 1812 #else /* REG_OK_STRICT */ 1813 1814 #define ARM_REG_OK_FOR_BASE_P(X) \ 1815 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1816 1817 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1818 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1819 1820 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1821 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1822 1823 #define REG_STRICT_P 1 1824 1825 #endif /* REG_OK_STRICT */ 1826 1827 /* Now define some helpers in terms of the above. */ 1828 1829 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1830 (TARGET_THUMB1 \ 1831 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1832 : ARM_REG_OK_FOR_BASE_P (X)) 1833 1834 /* For 16-bit Thumb, a valid index register is anything that can be used in 1835 a byte load instruction. */ 1836 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1837 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1838 1839 /* Nonzero if X is a hard reg that can be used as an index 1840 or if it is a pseudo reg. On the Thumb, the stack pointer 1841 is not suitable. */ 1842 #define REG_OK_FOR_INDEX_P(X) \ 1843 (TARGET_THUMB1 \ 1844 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1845 : ARM_REG_OK_FOR_INDEX_P (X)) 1846 1847 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1848 For Thumb, we can not use SP + reg, so reject SP. */ 1849 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1850 REG_OK_FOR_INDEX_P (X) 1851 1852 #define ARM_BASE_REGISTER_RTX_P(X) \ 1854 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1855 1856 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1857 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1858 1859 /* Specify the machine mode that this machine uses 1861 for the index in the tablejump instruction. */ 1862 #define CASE_VECTOR_MODE Pmode 1863 1864 #define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 1865 || (TARGET_THUMB1 \ 1866 && (optimize_size || flag_pic))) 1867 1868 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1869 (TARGET_THUMB1 \ 1870 ? (min >= 0 && max < 512 \ 1871 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1872 : min >= -256 && max < 256 \ 1873 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1874 : min >= 0 && max < 8192 \ 1875 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1876 : min >= -4096 && max < 4096 \ 1877 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1878 : SImode) \ 1879 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1880 : (max >= 0x200) ? HImode \ 1881 : QImode)) 1882 1883 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1884 unsigned is probably best, but may break some code. */ 1885 #ifndef DEFAULT_SIGNED_CHAR 1886 #define DEFAULT_SIGNED_CHAR 0 1887 #endif 1888 1889 /* Max number of bytes we can move from memory to memory 1890 in one reasonably fast instruction. */ 1891 #define MOVE_MAX 4 1892 1893 #undef MOVE_RATIO 1894 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 1895 1896 /* Define if operations between registers always perform the operation 1897 on the full register even if a narrower mode is specified. */ 1898 #define WORD_REGISTER_OPERATIONS 1 1899 1900 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1901 will either zero-extend or sign-extend. The value of this macro should 1902 be the code that says which one of the two operations is implicitly 1903 done, UNKNOWN if none. */ 1904 #define LOAD_EXTEND_OP(MODE) \ 1905 (TARGET_THUMB ? ZERO_EXTEND : \ 1906 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 1907 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 1908 1909 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1910 #define SLOW_BYTE_ACCESS 0 1911 1912 /* Immediate shift counts are truncated by the output routines (or was it 1913 the assembler?). Shift counts in a register are truncated by ARM. Note 1914 that the native compiler puts too large (> 32) immediate shift counts 1915 into a register and shifts by the register, letting the ARM decide what 1916 to do instead of doing that itself. */ 1917 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1918 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1919 On the arm, Y in a register is used modulo 256 for the shift. Only for 1920 rotates is modulo 32 used. */ 1921 /* #define SHIFT_COUNT_TRUNCATED 1 */ 1922 1923 /* Calling from registers is a massive pain. */ 1924 #define NO_FUNCTION_CSE 1 1925 1926 /* The machine modes of pointers and functions */ 1927 #define Pmode SImode 1928 #define FUNCTION_MODE Pmode 1929 1930 #define ARM_FRAME_RTX(X) \ 1931 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1932 || (X) == arg_pointer_rtx) 1933 1934 /* Try to generate sequences that don't involve branches, we can then use 1935 conditional instructions. */ 1936 #define BRANCH_COST(speed_p, predictable_p) \ 1937 ((arm_branch_cost != -1) ? arm_branch_cost : \ 1938 (current_tune->branch_cost (speed_p, predictable_p))) 1939 1940 /* False if short circuit operation is preferred. */ 1941 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 1942 ((optimize_size) \ 1943 ? (TARGET_THUMB ? false : true) \ 1944 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 1945 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 1946 1947 1948 /* Position Independent Code. */ 1950 /* We decide which register to use based on the compilation options and 1951 the assembler in use; this is more general than the APCS restriction of 1952 using sb (r9) all the time. */ 1953 extern unsigned arm_pic_register; 1954 1955 /* The register number of the register used to address a table of static 1956 data addresses in memory. */ 1957 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 1958 1959 /* We can't directly access anything that contains a symbol, 1960 nor can we indirect via the constant pool. One exception is 1961 UNSPEC_TLS, which is always PIC. */ 1962 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1963 (!(symbol_mentioned_p (X) \ 1964 || label_mentioned_p (X) \ 1965 || (GET_CODE (X) == SYMBOL_REF \ 1966 && CONSTANT_POOL_ADDRESS_P (X) \ 1967 && (symbol_mentioned_p (get_pool_constant (X)) \ 1968 || label_mentioned_p (get_pool_constant (X))))) \ 1969 || tls_mentioned_p (X)) 1970 1971 /* We need to know when we are making a constant pool; this determines 1972 whether data needs to be in the GOT or can be referenced via a GOT 1973 offset. */ 1974 extern int making_const_table; 1975 1976 /* Handle pragmas for compatibility with Intel's compilers. */ 1978 /* Also abuse this to register additional C specific EABI attributes. */ 1979 #define REGISTER_TARGET_PRAGMAS() do { \ 1980 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 1981 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 1982 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 1983 arm_lang_object_attributes_init(); \ 1984 arm_register_target_pragmas(); \ 1985 } while (0) 1986 1987 /* Condition code information. */ 1988 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1989 return the mode to be used for the comparison. */ 1990 1991 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 1992 1993 #define REVERSIBLE_CC_MODE(MODE) 1 1994 1995 #define REVERSE_CONDITION(CODE,MODE) \ 1996 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 1997 ? reverse_condition_maybe_unordered (code) \ 1998 : reverse_condition (code)) 1999 2000 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2001 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2002 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2003 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2004 2005 #define CC_STATUS_INIT \ 2007 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2008 2009 #undef ASM_APP_ON 2010 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2011 "\t.syntax divided\n") 2012 2013 #undef ASM_APP_OFF 2014 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2015 "\t.thumb\n\t.syntax unified\n") 2016 2017 /* Output a push or a pop instruction (only used when profiling). 2018 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2019 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2020 that r7 isn't used by the function profiler, so we can use it as a 2021 scratch reg. WARNING: This isn't safe in the general case! It may be 2022 sensitive to future changes in final.c:profile_function. */ 2023 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2024 do \ 2025 { \ 2026 if (TARGET_THUMB1 \ 2027 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2028 { \ 2029 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2030 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2031 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2032 } \ 2033 else \ 2034 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2035 } while (0) 2036 2037 2038 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2039 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2040 do \ 2041 { \ 2042 if (TARGET_THUMB1 \ 2043 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2044 { \ 2045 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2046 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2047 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2048 } \ 2049 else \ 2050 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2051 } while (0) 2052 2053 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2054 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2055 2056 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2057 default alignment from elfos.h. */ 2058 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2059 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2060 2061 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2062 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2063 ? 1 : 0) 2064 2065 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2066 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2067 2068 /* For aliases of functions we use .thumb_set instead. */ 2069 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2070 do \ 2071 { \ 2072 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2073 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2074 \ 2075 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2076 { \ 2077 fprintf (FILE, "\t.thumb_set "); \ 2078 assemble_name (FILE, LABEL1); \ 2079 fprintf (FILE, ","); \ 2080 assemble_name (FILE, LABEL2); \ 2081 fprintf (FILE, "\n"); \ 2082 } \ 2083 else \ 2084 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2085 } \ 2086 while (0) 2087 2088 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2089 /* To support -falign-* switches we need to use .p2align so 2090 that alignment directives in code sections will be padded 2091 with no-op instructions, rather than zeroes. */ 2092 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2093 if ((LOG) != 0) \ 2094 { \ 2095 if ((MAX_SKIP) == 0) \ 2096 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2097 else \ 2098 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2099 (int) (LOG), (int) (MAX_SKIP)); \ 2100 } 2101 #endif 2102 2103 /* Add two bytes to the length of conditionally executed Thumb-2 2105 instructions for the IT instruction. */ 2106 #define ADJUST_INSN_LENGTH(insn, length) \ 2107 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2108 length += 2; 2109 2110 /* Only perform branch elimination (by making instructions conditional) if 2111 we're optimizing. For Thumb-2 check if any IT instructions need 2112 outputting. */ 2113 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2114 if (TARGET_ARM && optimize) \ 2115 arm_final_prescan_insn (INSN); \ 2116 else if (TARGET_THUMB2) \ 2117 thumb2_final_prescan_insn (INSN); \ 2118 else if (TARGET_THUMB1) \ 2119 thumb1_final_prescan_insn (INSN) 2120 2121 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2122 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2123 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2124 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2125 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2126 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2127 : 0)))) 2128 2129 /* A C expression whose value is RTL representing the value of the return 2130 address for the frame COUNT steps up from the current frame. */ 2131 2132 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2133 arm_return_addr (COUNT, FRAME) 2134 2135 /* Mask of the bits in the PC that contain the real return address 2136 when running in 26-bit mode. */ 2137 #define RETURN_ADDR_MASK26 (0x03fffffc) 2138 2139 /* Pick up the return address upon entry to a procedure. Used for 2140 dwarf2 unwind information. This also enables the table driven 2141 mechanism. */ 2142 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2143 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2144 2145 /* Used to mask out junk bits from the return address, such as 2146 processor state, interrupt status, condition codes and the like. */ 2147 #define MASK_RETURN_ADDR \ 2148 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2149 in 26 bit mode, the condition codes must be masked out of the \ 2150 return address. This does not apply to ARM6 and later processors \ 2151 when running in 32 bit mode. */ \ 2152 ((arm_arch4 || TARGET_THUMB) \ 2153 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2154 : arm_gen_return_addr_mask ()) 2155 2156 2157 /* Do not emit .note.GNU-stack by default. */ 2159 #ifndef NEED_INDICATE_EXEC_STACK 2160 #define NEED_INDICATE_EXEC_STACK 0 2161 #endif 2162 2163 #define TARGET_ARM_ARCH \ 2164 (arm_base_arch) \ 2165 2166 /* The highest Thumb instruction set version supported by the chip. */ 2167 #define TARGET_ARM_ARCH_ISA_THUMB \ 2168 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2169 2170 /* Expands to an upper-case char of the target's architectural 2171 profile. */ 2172 #define TARGET_ARM_ARCH_PROFILE \ 2173 (arm_active_target.profile) 2174 2175 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2176 Bit 0 for bytes, up to bit 3 for double-words. */ 2177 #define TARGET_ARM_FEATURE_LDREX \ 2178 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2179 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2180 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2181 2182 /* Set as a bit mask indicating the available widths of hardware floating 2183 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2184 32-bit support, bit 3 indicates 64-bit support. */ 2185 #define TARGET_ARM_FP \ 2186 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2187 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2188 : 0) 2189 2190 2191 /* Set as a bit mask indicating the available widths of floating point 2192 types for hardware NEON floating point. This is the same as 2193 TARGET_ARM_FP without the 64-bit bit set. */ 2194 #define TARGET_NEON_FP \ 2195 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2196 : 0) 2197 2198 /* Name of the automatic fpu-selection option. */ 2199 #define FPUTYPE_AUTO "auto" 2200 2201 /* The maximum number of parallel loads or stores we support in an ldm/stm 2202 instruction. */ 2203 #define MAX_LDM_STM_OPS 4 2204 2205 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2206 extern const char *arm_rewrite_march (int argc, const char **argv); 2207 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2208 #define ASM_CPU_SPEC_FUNCTIONS \ 2209 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2210 { "rewrite_march", arm_rewrite_march }, \ 2211 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2212 2213 #define ASM_CPU_SPEC \ 2214 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2215 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2216 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2217 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2218 " }" 2219 2220 extern const char *arm_target_thumb_only (int argc, const char **argv); 2221 #define TARGET_MODE_SPEC_FUNCTIONS \ 2222 { "target_mode_check", arm_target_thumb_only }, 2223 2224 /* -mcpu=native handling only makes sense with compiler running on 2225 an ARM chip. */ 2226 #if defined(__arm__) && defined(__linux__) 2227 extern const char *host_detect_local_cpu (int argc, const char **argv); 2228 #define HAVE_LOCAL_CPU_DETECT 2229 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2230 { "local_cpu_detect", host_detect_local_cpu }, 2231 # define MCPU_MTUNE_NATIVE_SPECS \ 2232 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2233 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2234 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2235 #else 2236 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2237 # define MCPU_MTUNE_NATIVE_SPECS "" 2238 #endif 2239 2240 const char *arm_canon_arch_option (int argc, const char **argv); 2241 2242 #define CANON_ARCH_SPEC_FUNCTION \ 2243 { "canon_arch", arm_canon_arch_option }, 2244 2245 const char *arm_be8_option (int argc, const char **argv); 2246 #define BE8_SPEC_FUNCTION \ 2247 { "be8_linkopt", arm_be8_option }, 2248 2249 # define EXTRA_SPEC_FUNCTIONS \ 2250 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2251 ASM_CPU_SPEC_FUNCTIONS \ 2252 CANON_ARCH_SPEC_FUNCTION \ 2253 TARGET_MODE_SPEC_FUNCTIONS \ 2254 BE8_SPEC_FUNCTION 2255 2256 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2257 via the configuration option --with-mode or via the command line. The 2258 function target_mode_check is called to do the check with either: 2259 - an array of -march values if any is given; 2260 - an array of -mcpu values if any is given; 2261 - an empty array. */ 2262 #define TARGET_MODE_SPECS \ 2263 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2264 2265 /* Generate a canonical string to represent the architecture selected. */ 2266 #define ARCH_CANONICAL_SPECS \ 2267 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2268 " %{march=*: arch %*} " \ 2269 " %{mfpu=*: fpu %*} " \ 2270 " %{mfloat-abi=*: abi %*}" \ 2271 " %<march=*) " 2272 2273 /* Complete set of specs for the driver. Commas separate the 2274 individual rules so that any option suppression (%<opt...)is 2275 completed before starting subsequent rules. */ 2276 #define DRIVER_SELF_SPECS \ 2277 MCPU_MTUNE_NATIVE_SPECS, \ 2278 TARGET_MODE_SPECS, \ 2279 ARCH_CANONICAL_SPECS 2280 2281 #define TARGET_SUPPORTS_WIDE_INT 1 2282 2283 /* For switching between functions with different target attributes. */ 2284 #define SWITCHABLE_TARGET 1 2285 2286 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2287 representation for SHF_ARM_PURECODE in GCC. */ 2288 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2289 2290 #endif /* ! GCC_ARM_H */ 2291
Indexes created Wed Apr 15 00:22:22 UTC 2026