arm.h revision 1.1.1.9
1 /* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991-2019 Free Software Foundation, Inc. 3 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter (at) win.tue.nl) 4 and Martin Simmons (@harleqn.co.uk). 5 More major hacks by Richard Earnshaw (rearnsha (at) arm.com) 6 Minor hacks by Nick Clifton (nickc (at) cygnus.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 #ifndef GCC_ARM_H 30 #define GCC_ARM_H 31 32 /* We can't use machine_mode inside a generator file because it 33 hasn't been created yet; we shouldn't be using any code that 34 needs the real definition though, so this ought to be safe. */ 35 #ifdef GENERATOR_FILE 36 #define MACHMODE int 37 #else 38 #include "insn-modes.h" 39 #define MACHMODE machine_mode 40 #endif 41 42 #include "config/vxworks-dummy.h" 43 44 /* The architecture define. */ 45 extern char arm_arch_name[]; 46 47 /* Target CPU builtins. */ 48 #define TARGET_CPU_CPP_BUILTINS() arm_cpu_cpp_builtins (pfile) 49 50 /* Target CPU versions for D. */ 51 #define TARGET_D_CPU_VERSIONS arm_d_target_versions 52 53 #include "config/arm/arm-opts.h" 54 55 /* The processor for which instructions should be scheduled. */ 56 extern enum processor_type arm_tune; 57 58 typedef enum arm_cond_code 59 { 60 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 61 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 62 } 63 arm_cc; 64 65 extern arm_cc arm_current_cc; 66 67 #define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 68 69 /* The maximum number of instructions that is beneficial to 70 conditionally execute. */ 71 #undef MAX_CONDITIONAL_EXECUTE 72 #define MAX_CONDITIONAL_EXECUTE arm_max_conditional_execute () 73 74 extern int arm_target_label; 75 extern int arm_ccfsm_state; 76 extern GTY(()) rtx arm_target_insn; 77 /* Callback to output language specific object attributes. */ 78 extern void (*arm_lang_output_object_attributes_hook)(void); 79 80 /* This type is the user-visible __fp16. We need it in a few places in 81 the backend. Defined in arm-builtins.c. */ 82 extern tree arm_fp16_type_node; 83 84 85 #undef CPP_SPEC 87 #define CPP_SPEC "%(subtarget_cpp_spec) \ 88 %{mfloat-abi=soft:%{mfloat-abi=hard: \ 89 %e-mfloat-abi=soft and -mfloat-abi=hard may not be used together}} \ 90 %{mbig-endian:%{mlittle-endian: \ 91 %e-mbig-endian and -mlittle-endian may not be used together}}" 92 93 #ifndef CC1_SPEC 94 #define CC1_SPEC "" 95 #endif 96 97 /* This macro defines names of additional specifications to put in the specs 98 that can be used in various specifications like CC1_SPEC. Its definition 99 is an initializer with a subgrouping for each command option. 100 101 Each subgrouping contains a string constant, that defines the 102 specification name, and a string constant that used by the GCC driver 103 program. 104 105 Do not define this macro if it does not need to do anything. */ 106 #define EXTRA_SPECS \ 107 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 108 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 109 SUBTARGET_EXTRA_SPECS 110 111 #ifndef SUBTARGET_EXTRA_SPECS 112 #define SUBTARGET_EXTRA_SPECS 113 #endif 114 115 #ifndef SUBTARGET_CPP_SPEC 116 #define SUBTARGET_CPP_SPEC "" 117 #endif 118 119 /* Tree Target Specification. */ 121 #define TARGET_ARM_P(flags) (!TARGET_THUMB_P (flags)) 122 #define TARGET_THUMB1_P(flags) (TARGET_THUMB_P (flags) && !arm_arch_thumb2) 123 #define TARGET_THUMB2_P(flags) (TARGET_THUMB_P (flags) && arm_arch_thumb2) 124 #define TARGET_32BIT_P(flags) (TARGET_ARM_P (flags) || TARGET_THUMB2_P (flags)) 125 126 /* Run-time Target Specification. */ 127 /* Use hardware floating point instructions. -mgeneral-regs-only prevents 128 the use of floating point instructions and registers but does not prevent 129 emission of floating point pcs attributes. */ 130 #define TARGET_HARD_FLOAT_SUB (arm_float_abi != ARM_FLOAT_ABI_SOFT \ 131 && bitmap_bit_p (arm_active_target.isa, \ 132 isa_bit_vfpv2) \ 133 && TARGET_32BIT) 134 135 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \ 136 && !TARGET_GENERAL_REGS_ONLY) 137 138 #define TARGET_SOFT_FLOAT (!TARGET_HARD_FLOAT_SUB) 139 /* User has permitted use of FP instructions, if they exist for this 140 target. */ 141 #define TARGET_MAYBE_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 142 /* Use hardware floating point calling convention. */ 143 #define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 144 #define TARGET_IWMMXT (arm_arch_iwmmxt) 145 #define TARGET_IWMMXT2 (arm_arch_iwmmxt2) 146 #define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT \ 147 && !TARGET_GENERAL_REGS_ONLY) 148 #define TARGET_REALLY_IWMMXT2 (TARGET_IWMMXT2 && TARGET_32BIT \ 149 && !TARGET_GENERAL_REGS_ONLY) 150 #define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 151 #define TARGET_ARM (! TARGET_THUMB) 152 #define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 153 #define TARGET_BACKTRACE (crtl->is_leaf \ 154 ? TARGET_TPCS_LEAF_FRAME \ 155 : TARGET_TPCS_FRAME) 156 #define TARGET_AAPCS_BASED \ 157 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 158 159 #define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 160 #define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 161 #define TARGET_GNU2_TLS (target_tls_dialect == TLS_GNU2) 162 163 /* Only 16-bit thumb code. */ 164 #define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 165 /* Arm or Thumb-2 32-bit code. */ 166 #define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 167 /* 32-bit Thumb-2 code. */ 168 #define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 169 /* Thumb-1 only. */ 170 #define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 171 172 #define TARGET_LDRD (arm_arch5te && ARM_DOUBLEWORD_ALIGN \ 173 && !TARGET_THUMB1) 174 175 #define TARGET_CRC32 (arm_arch_crc) 176 177 /* The following two macros concern the ability to execute coprocessor 178 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 179 only ever tested when we know we are generating for VFP hardware; we need 180 to be more careful with TARGET_NEON as noted below. */ 181 182 /* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 183 #define TARGET_VFPD32 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_d32)) 184 185 /* FPU supports VFPv3 instructions. */ 186 #define TARGET_VFP3 (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv3)) 187 188 /* FPU supports FPv5 instructions. */ 189 #define TARGET_VFP5 (bitmap_bit_p (arm_active_target.isa, isa_bit_fpv5)) 190 191 /* FPU only supports VFP single-precision instructions. */ 192 #define TARGET_VFP_SINGLE (!TARGET_VFP_DOUBLE) 193 194 /* FPU supports VFP double-precision instructions. */ 195 #define TARGET_VFP_DOUBLE (bitmap_bit_p (arm_active_target.isa, isa_bit_fp_dbl)) 196 197 /* FPU supports half-precision floating-point with NEON element load/store. */ 198 #define TARGET_NEON_FP16 \ 199 (bitmap_bit_p (arm_active_target.isa, isa_bit_neon) \ 200 && bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 201 202 /* FPU supports VFP half-precision floating-point conversions. */ 203 #define TARGET_FP16 (bitmap_bit_p (arm_active_target.isa, isa_bit_fp16conv)) 204 205 /* FPU supports converting between HFmode and DFmode in a single hardware 206 step. */ 207 #define TARGET_FP16_TO_DOUBLE \ 208 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE) 209 210 /* FPU supports fused-multiply-add operations. */ 211 #define TARGET_FMA (bitmap_bit_p (arm_active_target.isa, isa_bit_vfpv4)) 212 213 /* FPU supports Crypto extensions. */ 214 #define TARGET_CRYPTO (bitmap_bit_p (arm_active_target.isa, isa_bit_crypto)) 215 216 /* FPU supports Neon instructions. The setting of this macro gets 217 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 218 and TARGET_HARD_FLOAT to ensure that NEON instructions are 219 available. */ 220 #define TARGET_NEON \ 221 (TARGET_32BIT && TARGET_HARD_FLOAT \ 222 && bitmap_bit_p (arm_active_target.isa, isa_bit_neon)) 223 224 /* FPU supports ARMv8.1 Adv.SIMD extensions. */ 225 #define TARGET_NEON_RDMA (TARGET_NEON && arm_arch8_1) 226 227 /* Supports the Dot Product AdvSIMD extensions. */ 228 #define TARGET_DOTPROD (TARGET_NEON && TARGET_VFP5 \ 229 && bitmap_bit_p (arm_active_target.isa, \ 230 isa_bit_dotprod) \ 231 && arm_arch8_2) 232 233 /* Supports the Armv8.3-a Complex number AdvSIMD extensions. */ 234 #define TARGET_COMPLEX (TARGET_NEON && arm_arch8_3) 235 236 /* FPU supports the floating point FP16 instructions for ARMv8.2-A 237 and later. */ 238 #define TARGET_VFP_FP16INST \ 239 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst) 240 241 /* Target supports the floating point FP16 instructions from ARMv8.2-A 242 and later. */ 243 #define TARGET_FP16FML (TARGET_NEON \ 244 && bitmap_bit_p (arm_active_target.isa, \ 245 isa_bit_fp16fml) \ 246 && arm_arch8_2) 247 248 /* FPU supports the AdvSIMD FP16 instructions for ARMv8.2 and later. */ 249 #define TARGET_NEON_FP16INST (TARGET_VFP_FP16INST && TARGET_NEON_RDMA) 250 251 /* Q-bit is present. */ 252 #define TARGET_ARM_QBIT \ 253 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7)) 254 /* Saturation operation, e.g. SSAT. */ 255 #define TARGET_ARM_SAT \ 256 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7)) 257 /* "DSP" multiply instructions, eg. SMULxy. */ 258 #define TARGET_DSP_MULTIPLY \ 259 (TARGET_32BIT && arm_arch5te && (arm_arch_notm || arm_arch7em)) 260 /* Integer SIMD instructions, and extend-accumulate instructions. */ 261 #define TARGET_INT_SIMD \ 262 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 263 264 /* Should MOVW/MOVT be used in preference to a constant pool. */ 265 #define TARGET_USE_MOVT \ 266 (TARGET_HAVE_MOVT \ 267 && (arm_disable_literal_pool \ 268 || (!optimize_size && !current_tune->prefer_constant_pool))) 269 270 /* Nonzero if this chip provides the DMB instruction. */ 271 #define TARGET_HAVE_DMB (arm_arch6m || arm_arch7) 272 273 /* Nonzero if this chip implements a memory barrier via CP15. */ 274 #define TARGET_HAVE_DMB_MCR (arm_arch6 && ! TARGET_HAVE_DMB \ 275 && ! TARGET_THUMB1) 276 277 /* Nonzero if this chip implements a memory barrier instruction. */ 278 #define TARGET_HAVE_MEMORY_BARRIER (TARGET_HAVE_DMB || TARGET_HAVE_DMB_MCR) 279 280 /* Nonzero if this chip supports ldrex and strex */ 281 #define TARGET_HAVE_LDREX ((arm_arch6 && TARGET_ARM) \ 282 || arm_arch7 \ 283 || (arm_arch8 && !arm_arch_notm)) 284 285 /* Nonzero if this chip supports LPAE. */ 286 #define TARGET_HAVE_LPAE (arm_arch_lpae) 287 288 /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ 289 #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \ 290 || arm_arch7 \ 291 || (arm_arch8 && !arm_arch_notm)) 292 293 /* Nonzero if this chip supports ldrexd and strexd. */ 294 #define TARGET_HAVE_LDREXD (((arm_arch6k && TARGET_ARM) \ 295 || arm_arch7) && arm_arch_notm) 296 297 /* Nonzero if this chip supports load-acquire and store-release. */ 298 #define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8) 299 300 /* Nonzero if this chip supports LDAEXD and STLEXD. */ 301 #define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \ 302 && TARGET_32BIT \ 303 && arm_arch_notm) 304 305 /* Nonzero if this chip provides the MOVW and MOVT instructions. */ 306 #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) 307 308 /* Nonzero if this chip provides the CBZ and CBNZ instructions. */ 309 #define TARGET_HAVE_CBZ (arm_arch_thumb2 || arm_arch8) 310 311 /* Nonzero if integer division instructions supported. */ 312 #define TARGET_IDIV ((TARGET_ARM && arm_arch_arm_hwdiv) \ 313 || (TARGET_THUMB && arm_arch_thumb_hwdiv)) 314 315 /* Nonzero if disallow volatile memory access in IT block. */ 316 #define TARGET_NO_VOLATILE_CE (arm_arch_no_volatile_ce) 317 318 /* Should NEON be used for 64-bits bitops. */ 319 #define TARGET_PREFER_NEON_64BITS (prefer_neon_for_64bits) 320 321 /* Should constant I be slplit for OP. */ 322 #define DONT_EARLY_SPLIT_CONSTANT(i, op) \ 323 ((optimize >= 2) \ 324 && can_create_pseudo_p () \ 325 && !const_ok_for_op (i, op)) 326 327 /* True iff the full BPABI is being used. If TARGET_BPABI is true, 328 then TARGET_AAPCS_BASED must be true -- but the converse does not 329 hold. TARGET_BPABI implies the use of the BPABI runtime library, 330 etc., in addition to just the AAPCS calling conventions. */ 331 #ifndef TARGET_BPABI 332 #define TARGET_BPABI false 333 #endif 334 335 /* Transform lane numbers on big endian targets. This is used to allow for the 336 endianness difference between NEON architectural lane numbers and those 337 used in RTL */ 338 #define NEON_ENDIAN_LANE_N(mode, n) \ 339 (BYTES_BIG_ENDIAN ? GET_MODE_NUNITS (mode) - 1 - n : n) 340 341 /* Support for a compile-time default CPU, et cetera. The rules are: 342 --with-arch is ignored if -march or -mcpu are specified. 343 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 344 by --with-arch. 345 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 346 by -march). 347 --with-float is ignored if -mfloat-abi is specified. 348 --with-fpu is ignored if -mfpu is specified. 349 --with-abi is ignored if -mabi is specified. 350 --with-tls is ignored if -mtls-dialect is specified. */ 351 #define OPTION_DEFAULT_SPECS \ 352 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 353 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 354 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 355 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" }, \ 356 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 357 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 358 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, \ 359 {"tls", "%{!mtls-dialect=*:-mtls-dialect=%(VALUE)}"}, 360 361 extern const struct arm_fpu_desc 362 { 363 const char *name; 364 enum isa_feature isa_bits[isa_num_bits]; 365 } all_fpus[]; 366 367 /* Which floating point hardware to schedule for. */ 368 extern int arm_fpu_attr; 369 370 #ifndef TARGET_DEFAULT_FLOAT_ABI 371 #define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 372 #endif 373 374 #ifndef ARM_DEFAULT_ABI 375 #define ARM_DEFAULT_ABI ARM_ABI_APCS 376 #endif 377 378 /* AAPCS based ABIs use short enums by default. */ 379 #ifndef ARM_DEFAULT_SHORT_ENUMS 380 #define ARM_DEFAULT_SHORT_ENUMS \ 381 (TARGET_AAPCS_BASED && arm_abi != ARM_ABI_AAPCS_LINUX) 382 #endif 383 384 /* Map each of the micro-architecture variants to their corresponding 385 major architecture revision. */ 386 387 enum base_architecture 388 { 389 BASE_ARCH_0 = 0, 390 BASE_ARCH_2 = 2, 391 BASE_ARCH_3 = 3, 392 BASE_ARCH_3M = 3, 393 BASE_ARCH_4 = 4, 394 BASE_ARCH_4T = 4, 395 BASE_ARCH_5T = 5, 396 BASE_ARCH_5TE = 5, 397 BASE_ARCH_5TEJ = 5, 398 BASE_ARCH_6 = 6, 399 BASE_ARCH_6J = 6, 400 BASE_ARCH_6KZ = 6, 401 BASE_ARCH_6K = 6, 402 BASE_ARCH_6T2 = 6, 403 BASE_ARCH_6M = 6, 404 BASE_ARCH_6Z = 6, 405 BASE_ARCH_7 = 7, 406 BASE_ARCH_7A = 7, 407 BASE_ARCH_7R = 7, 408 BASE_ARCH_7M = 7, 409 BASE_ARCH_7EM = 7, 410 BASE_ARCH_8A = 8, 411 BASE_ARCH_8M_BASE = 8, 412 BASE_ARCH_8M_MAIN = 8, 413 BASE_ARCH_8R = 8 414 }; 415 416 /* The major revision number of the ARM Architecture implemented by the target. */ 417 extern enum base_architecture arm_base_arch; 418 419 /* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 420 extern int arm_arch4; 421 422 /* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 423 extern int arm_arch4t; 424 425 /* Nonzero if this chip supports the ARM Architecture 5T extensions. */ 426 extern int arm_arch5t; 427 428 /* Nonzero if this chip supports the ARM Architecture 5TE extensions. */ 429 extern int arm_arch5te; 430 431 /* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 432 extern int arm_arch6; 433 434 /* Nonzero if this chip supports the ARM Architecture 6k extensions. */ 435 extern int arm_arch6k; 436 437 /* Nonzero if instructions present in ARMv6-M can be used. */ 438 extern int arm_arch6m; 439 440 /* Nonzero if this chip supports the ARM Architecture 7 extensions. */ 441 extern int arm_arch7; 442 443 /* Nonzero if instructions not present in the 'M' profile can be used. */ 444 extern int arm_arch_notm; 445 446 /* Nonzero if instructions present in ARMv7E-M can be used. */ 447 extern int arm_arch7em; 448 449 /* Nonzero if this chip supports the ARM Architecture 8 extensions. */ 450 extern int arm_arch8; 451 452 /* Nonzero if this chip supports the ARM Architecture 8.1 extensions. */ 453 extern int arm_arch8_1; 454 455 /* Nonzero if this chip supports the ARM Architecture 8.2 extensions. */ 456 extern int arm_arch8_2; 457 458 /* Nonzero if this chip supports the ARM Architecture 8.3 extensions. */ 459 extern int arm_arch8_3; 460 461 /* Nonzero if this chip supports the ARM Architecture 8.4 extensions. */ 462 extern int arm_arch8_4; 463 464 /* Nonzero if this chip supports the FP16 instructions extension of ARM 465 Architecture 8.2. */ 466 extern int arm_fp16_inst; 467 468 /* Nonzero if this chip can benefit from load scheduling. */ 469 extern int arm_ld_sched; 470 471 /* Nonzero if this chip is a StrongARM. */ 472 extern int arm_tune_strongarm; 473 474 /* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 475 extern int arm_arch_iwmmxt; 476 477 /* Nonzero if this chip supports Intel Wireless MMX2 technology. */ 478 extern int arm_arch_iwmmxt2; 479 480 /* Nonzero if this chip is an XScale. */ 481 extern int arm_arch_xscale; 482 483 /* Nonzero if tuning for XScale. */ 484 extern int arm_tune_xscale; 485 486 /* Nonzero if tuning for stores via the write buffer. */ 487 extern int arm_tune_wbuf; 488 489 /* Nonzero if tuning for Cortex-A9. */ 490 extern int arm_tune_cortex_a9; 491 492 /* Nonzero if we should define __THUMB_INTERWORK__ in the 493 preprocessor. 494 XXX This is a bit of a hack, it's intended to help work around 495 problems in GLD which doesn't understand that armv5t code is 496 interworking clean. */ 497 extern int arm_cpp_interwork; 498 499 /* Nonzero if chip supports Thumb 1. */ 500 extern int arm_arch_thumb1; 501 502 /* Nonzero if chip supports Thumb 2. */ 503 extern int arm_arch_thumb2; 504 505 /* Nonzero if chip supports integer division instruction in ARM mode. */ 506 extern int arm_arch_arm_hwdiv; 507 508 /* Nonzero if chip supports integer division instruction in Thumb mode. */ 509 extern int arm_arch_thumb_hwdiv; 510 511 /* Nonzero if chip disallows volatile memory access in IT block. */ 512 extern int arm_arch_no_volatile_ce; 513 514 /* Nonzero if we should use Neon to handle 64-bits operations rather 515 than core registers. */ 516 extern int prefer_neon_for_64bits; 517 518 /* Nonzero if we shouldn't use literal pools. */ 519 #ifndef USED_FOR_TARGET 520 extern bool arm_disable_literal_pool; 521 #endif 522 523 /* Nonzero if chip supports the ARMv8 CRC instructions. */ 524 extern int arm_arch_crc; 525 526 /* Nonzero if chip supports the ARMv8-M Security Extensions. */ 527 extern int arm_arch_cmse; 528 529 #ifndef TARGET_DEFAULT 530 #define TARGET_DEFAULT (MASK_APCS_FRAME) 531 #endif 532 533 /* Nonzero if PIC code requires explicit qualifiers to generate 534 PLT and GOT relocs rather than the assembler doing so implicitly. 535 Subtargets can override these if required. */ 536 #ifndef NEED_GOT_RELOC 537 #define NEED_GOT_RELOC 0 538 #endif 539 #ifndef NEED_PLT_RELOC 540 #define NEED_PLT_RELOC 0 541 #endif 542 543 #ifndef TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 544 #define TARGET_DEFAULT_PIC_DATA_IS_TEXT_RELATIVE 1 545 #endif 546 547 /* Nonzero if we need to refer to the GOT with a PC-relative 548 offset. In other words, generate 549 550 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 551 552 rather than 553 554 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 555 556 The default is true, which matches NetBSD. Subtargets can 557 override this if required. */ 558 #ifndef GOT_PCREL 559 #define GOT_PCREL 1 560 #endif 561 562 /* Target machine storage Layout. */ 564 565 566 /* Define this macro if it is advisable to hold scalars in registers 567 in a wider mode than that declared by the program. In such cases, 568 the value is constrained to be within the bounds of the declared 569 type, but kept valid in the wider mode. The signedness of the 570 extension may differ from that of the type. */ 571 572 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 573 if (GET_MODE_CLASS (MODE) == MODE_INT \ 574 && GET_MODE_SIZE (MODE) < 4) \ 575 { \ 576 (MODE) = SImode; \ 577 } 578 579 /* Define this if most significant bit is lowest numbered 580 in instructions that operate on numbered bit-fields. */ 581 #define BITS_BIG_ENDIAN 0 582 583 /* Define this if most significant byte of a word is the lowest numbered. 584 Most ARM processors are run in little endian mode, so that is the default. 585 If you want to have it run-time selectable, change the definition in a 586 cover file to be TARGET_BIG_ENDIAN. */ 587 #define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 588 589 /* Define this if most significant word of a multiword number is the lowest 590 numbered. */ 591 #define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN) 592 593 #define UNITS_PER_WORD 4 594 595 /* True if natural alignment is used for doubleword types. */ 596 #define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 597 598 #define DOUBLEWORD_ALIGNMENT 64 599 600 #define PARM_BOUNDARY 32 601 602 #define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 603 604 #define PREFERRED_STACK_BOUNDARY \ 605 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 606 607 #define FUNCTION_BOUNDARY_P(flags) (TARGET_THUMB_P (flags) ? 16 : 32) 608 #define FUNCTION_BOUNDARY (FUNCTION_BOUNDARY_P (target_flags)) 609 610 /* The lowest bit is used to indicate Thumb-mode functions, so the 611 vbit must go into the delta field of pointers to member 612 functions. */ 613 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 614 615 #define EMPTY_FIELD_BOUNDARY 32 616 617 #define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 618 619 #define MALLOC_ABI_ALIGNMENT BIGGEST_ALIGNMENT 620 621 /* XXX Blah -- this macro is used directly by libobjc. Since it 622 supports no vector modes, cut out the complexity and fall back 623 on BIGGEST_FIELD_ALIGNMENT. */ 624 #ifdef IN_TARGET_LIBS 625 #define BIGGEST_FIELD_ALIGNMENT 64 626 #endif 627 628 /* Align definitions of arrays, unions and structures so that 629 initializations and copies can be made more efficient. This is not 630 ABI-changing, so it only affects places where we can see the 631 definition. Increasing the alignment tends to introduce padding, 632 so don't do this when optimizing for size/conserving stack space. */ 633 #define ARM_EXPAND_ALIGNMENT(COND, EXP, ALIGN) \ 634 (((COND) && ((ALIGN) < BITS_PER_WORD) \ 635 && (TREE_CODE (EXP) == ARRAY_TYPE \ 636 || TREE_CODE (EXP) == UNION_TYPE \ 637 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 638 639 /* Align global data. */ 640 #define DATA_ALIGNMENT(EXP, ALIGN) \ 641 ARM_EXPAND_ALIGNMENT(!optimize_size, EXP, ALIGN) 642 643 /* Similarly, make sure that objects on the stack are sensibly aligned. */ 644 #define LOCAL_ALIGNMENT(EXP, ALIGN) \ 645 ARM_EXPAND_ALIGNMENT(!flag_conserve_stack, EXP, ALIGN) 646 647 /* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 648 value set in previous versions of this toolchain was 8, which produces more 649 compact structures. The command line option -mstructure_size_boundary=<n> 650 can be used to change this value. For compatibility with the ARM SDK 651 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 652 0020D) page 2-20 says "Structures are aligned on word boundaries". 653 The AAPCS specifies a value of 8. */ 654 #define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 655 656 /* This is the value used to initialize arm_structure_size_boundary. If a 657 particular arm target wants to change the default value it should change 658 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 659 for an example of this. */ 660 #ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 661 #define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 662 #endif 663 664 /* Nonzero if move instructions will actually fail to work 665 when given unaligned data. */ 666 #define STRICT_ALIGNMENT 1 667 668 /* wchar_t is unsigned under the AAPCS. */ 669 #ifndef WCHAR_TYPE 670 #define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 671 672 #define WCHAR_TYPE_SIZE BITS_PER_WORD 673 #endif 674 675 /* Sized for fixed-point types. */ 676 677 #define SHORT_FRACT_TYPE_SIZE 8 678 #define FRACT_TYPE_SIZE 16 679 #define LONG_FRACT_TYPE_SIZE 32 680 #define LONG_LONG_FRACT_TYPE_SIZE 64 681 682 #define SHORT_ACCUM_TYPE_SIZE 16 683 #define ACCUM_TYPE_SIZE 32 684 #define LONG_ACCUM_TYPE_SIZE 64 685 #define LONG_LONG_ACCUM_TYPE_SIZE 64 686 687 #define MAX_FIXED_MODE_SIZE 64 688 689 #ifndef SIZE_TYPE 690 #define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 691 #endif 692 693 #ifndef PTRDIFF_TYPE 694 #define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 695 #endif 696 697 /* AAPCS requires that structure alignment is affected by bitfields. */ 698 #ifndef PCC_BITFIELD_TYPE_MATTERS 699 #define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 700 #endif 701 702 /* The maximum size of the sync library functions supported. */ 703 #ifndef MAX_SYNC_LIBFUNC_SIZE 704 #define MAX_SYNC_LIBFUNC_SIZE (2 * UNITS_PER_WORD) 705 #endif 706 707 708 /* Standard register usage. */ 710 711 /* Register allocation in ARM Procedure Call Standard 712 (S - saved over call, F - Frame-related). 713 714 r0 * argument word/integer result 715 r1-r3 argument word 716 717 r4-r8 S register variable 718 r9 S (rfp) register variable (real frame pointer) 719 720 r10 F S (sl) stack limit (used by -mapcs-stack-check) 721 r11 F S (fp) argument pointer 722 r12 (ip) temp workspace 723 r13 F S (sp) lower end of current stack frame 724 r14 (lr) link address/workspace 725 r15 F (pc) program counter 726 727 cc This is NOT a real register, but is used internally 728 to represent things that use or set the condition 729 codes. 730 sfp This isn't either. It is used during rtl generation 731 since the offset between the frame pointer and the 732 auto's isn't known until after register allocation. 733 afp Nor this, we only need this because of non-local 734 goto. Without it fp appears to be used and the 735 elimination code won't get rid of sfp. It tracks 736 fp exactly at all times. 737 738 *: See TARGET_CONDITIONAL_REGISTER_USAGE */ 739 740 /* s0-s15 VFP scratch (aka d0-d7). 741 s16-s31 S VFP variable (aka d8-d15). 742 vfpcc Not a real register. Represents the VFP condition 743 code flags. */ 744 745 /* The stack backtrace structure is as follows: 746 fp points to here: | save code pointer | [fp] 747 | return link value | [fp, #-4] 748 | return sp value | [fp, #-8] 749 | return fp value | [fp, #-12] 750 [| saved r10 value |] 751 [| saved r9 value |] 752 [| saved r8 value |] 753 [| saved r7 value |] 754 [| saved r6 value |] 755 [| saved r5 value |] 756 [| saved r4 value |] 757 [| saved r3 value |] 758 [| saved r2 value |] 759 [| saved r1 value |] 760 [| saved r0 value |] 761 r0-r3 are not normally saved in a C function. */ 762 763 /* 1 for registers that have pervasive standard uses 764 and are not available for the register allocator. */ 765 #define FIXED_REGISTERS \ 766 { \ 767 /* Core regs. */ \ 768 0,0,0,0,0,0,0,0, \ 769 0,0,0,0,0,1,0,1, \ 770 /* VFP regs. */ \ 771 1,1,1,1,1,1,1,1, \ 772 1,1,1,1,1,1,1,1, \ 773 1,1,1,1,1,1,1,1, \ 774 1,1,1,1,1,1,1,1, \ 775 1,1,1,1,1,1,1,1, \ 776 1,1,1,1,1,1,1,1, \ 777 1,1,1,1,1,1,1,1, \ 778 1,1,1,1,1,1,1,1, \ 779 /* IWMMXT regs. */ \ 780 1,1,1,1,1,1,1,1, \ 781 1,1,1,1,1,1,1,1, \ 782 1,1,1,1, \ 783 /* Specials. */ \ 784 1,1,1,1 \ 785 } 786 787 /* 1 for registers not available across function calls. 788 These must include the FIXED_REGISTERS and also any 789 registers that can be used without being saved. 790 The latter must include the registers where values are returned 791 and the register where structure-value addresses are passed. 792 Aside from that, you can include as many other registers as you like. 793 The CC is not preserved over function calls on the ARM 6, so it is 794 easier to assume this for all. SFP is preserved, since FP is. */ 795 #define CALL_USED_REGISTERS \ 796 { \ 797 /* Core regs. */ \ 798 1,1,1,1,0,0,0,0, \ 799 0,0,0,0,1,1,1,1, \ 800 /* VFP Regs. */ \ 801 1,1,1,1,1,1,1,1, \ 802 1,1,1,1,1,1,1,1, \ 803 1,1,1,1,1,1,1,1, \ 804 1,1,1,1,1,1,1,1, \ 805 1,1,1,1,1,1,1,1, \ 806 1,1,1,1,1,1,1,1, \ 807 1,1,1,1,1,1,1,1, \ 808 1,1,1,1,1,1,1,1, \ 809 /* IWMMXT regs. */ \ 810 1,1,1,1,1,1,1,1, \ 811 1,1,1,1,1,1,1,1, \ 812 1,1,1,1, \ 813 /* Specials. */ \ 814 1,1,1,1 \ 815 } 816 817 #ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 818 #define SUBTARGET_CONDITIONAL_REGISTER_USAGE 819 #endif 820 821 /* These are a couple of extensions to the formats accepted 822 by asm_fprintf: 823 %@ prints out ASM_COMMENT_START 824 %r prints out REGISTER_PREFIX reg_names[arg] */ 825 #define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 826 case '@': \ 827 fputs (ASM_COMMENT_START, FILE); \ 828 break; \ 829 \ 830 case 'r': \ 831 fputs (REGISTER_PREFIX, FILE); \ 832 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 833 break; 834 835 /* Round X up to the nearest word. */ 836 #define ROUND_UP_WORD(X) (((X) + 3) & ~3) 837 838 /* Convert fron bytes to ints. */ 839 #define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 840 841 /* The number of (integer) registers required to hold a quantity of type MODE. 842 Also used for VFP registers. */ 843 #define ARM_NUM_REGS(MODE) \ 844 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 845 846 /* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 847 #define ARM_NUM_REGS2(MODE, TYPE) \ 848 ARM_NUM_INTS ((MODE) == BLKmode ? \ 849 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 850 851 /* The number of (integer) argument register available. */ 852 #define NUM_ARG_REGS 4 853 854 /* And similarly for the VFP. */ 855 #define NUM_VFP_ARG_REGS 16 856 857 /* Return the register number of the N'th (integer) argument. */ 858 #define ARG_REGISTER(N) (N - 1) 859 860 /* Specify the registers used for certain standard purposes. 861 The values of these macros are register numbers. */ 862 863 /* The number of the last argument register. */ 864 #define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 865 866 /* The numbers of the Thumb register ranges. */ 867 #define FIRST_LO_REGNUM 0 868 #define LAST_LO_REGNUM 7 869 #define FIRST_HI_REGNUM 8 870 #define LAST_HI_REGNUM 11 871 872 /* Overridden by config/arm/bpabi.h. */ 873 #ifndef ARM_UNWIND_INFO 874 #define ARM_UNWIND_INFO 0 875 #endif 876 877 /* Overriden by config/arm/netbsd-eabi.h. */ 878 #ifndef ARM_DWARF_UNWIND_TABLES 879 #define ARM_DWARF_UNWIND_TABLES 0 880 #endif 881 882 /* Use r0 and r1 to pass exception handling information. */ 883 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 884 885 /* The register that holds the return address in exception handlers. */ 886 #define ARM_EH_STACKADJ_REGNUM 2 887 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 888 889 #ifndef ARM_TARGET2_DWARF_FORMAT 890 #define ARM_TARGET2_DWARF_FORMAT DW_EH_PE_pcrel 891 #endif 892 893 #if ARM_DWARF_UNWIND_TABLES 894 /* DWARF unwinding uses the normal indirect/pcrel vs absptr format 895 for 32bit platforms. */ 896 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 897 (flag_pic ? (((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4) \ 898 : DW_EH_PE_absptr) 899 #else 900 /* ttype entries (the only interesting data references used) 901 use TARGET2 relocations. */ 902 #define ASM_PREFERRED_EH_DATA_FORMAT(code, data) \ 903 (((code) == 0 && (data) == 1 && ARM_UNWIND_INFO) ? ARM_TARGET2_DWARF_FORMAT \ 904 : DW_EH_PE_absptr) 905 #endif 906 907 /* The native (Norcroft) Pascal compiler for the ARM passes the static chain 908 as an invisible last argument (possible since varargs don't exist in 909 Pascal), so the following is not true. */ 910 #define STATIC_CHAIN_REGNUM 12 911 912 /* Define this to be where the real frame pointer is if it is not possible to 913 work out the offset between the frame pointer and the automatic variables 914 until after register allocation has taken place. FRAME_POINTER_REGNUM 915 should point to a special register that we will make sure is eliminated. 916 917 For the Thumb we have another problem. The TPCS defines the frame pointer 918 as r11, and GCC believes that it is always possible to use the frame pointer 919 as base register for addressing purposes. (See comments in 920 find_reloads_address()). But - the Thumb does not allow high registers, 921 including r11, to be used as base address registers. Hence our problem. 922 923 The solution used here, and in the old thumb port is to use r7 instead of 924 r11 as the hard frame pointer and to have special code to generate 925 backtrace structures on the stack (if required to do so via a command line 926 option) using r11. This is the only 'user visible' use of r11 as a frame 927 pointer. */ 928 #define ARM_HARD_FRAME_POINTER_REGNUM 11 929 #define THUMB_HARD_FRAME_POINTER_REGNUM 7 930 931 #define HARD_FRAME_POINTER_REGNUM \ 932 (TARGET_ARM \ 933 ? ARM_HARD_FRAME_POINTER_REGNUM \ 934 : THUMB_HARD_FRAME_POINTER_REGNUM) 935 936 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 937 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 938 939 #define FP_REGNUM HARD_FRAME_POINTER_REGNUM 940 941 /* Register to use for pushing function arguments. */ 942 #define STACK_POINTER_REGNUM SP_REGNUM 943 944 #define FIRST_IWMMXT_REGNUM (LAST_HI_VFP_REGNUM + 1) 945 #define LAST_IWMMXT_REGNUM (FIRST_IWMMXT_REGNUM + 15) 946 947 /* Need to sync with WCGR in iwmmxt.md. */ 948 #define FIRST_IWMMXT_GR_REGNUM (LAST_IWMMXT_REGNUM + 1) 949 #define LAST_IWMMXT_GR_REGNUM (FIRST_IWMMXT_GR_REGNUM + 3) 950 951 #define IS_IWMMXT_REGNUM(REGNUM) \ 952 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 953 #define IS_IWMMXT_GR_REGNUM(REGNUM) \ 954 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 955 956 /* Base register for access to local variables of the function. */ 957 #define FRAME_POINTER_REGNUM 102 958 959 /* Base register for access to arguments of the function. */ 960 #define ARG_POINTER_REGNUM 103 961 962 #define FIRST_VFP_REGNUM 16 963 #define D7_VFP_REGNUM (FIRST_VFP_REGNUM + 15) 964 #define LAST_VFP_REGNUM \ 965 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 966 967 #define IS_VFP_REGNUM(REGNUM) \ 968 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 969 970 /* VFP registers are split into two types: those defined by VFP versions < 3 971 have D registers overlaid on consecutive pairs of S registers. VFP version 3 972 defines 16 new D registers (d16-d31) which, for simplicity and correctness 973 in various parts of the backend, we implement as "fake" single-precision 974 registers (which would be S32-S63, but cannot be used in that way). The 975 following macros define these ranges of registers. */ 976 #define LAST_LO_VFP_REGNUM (FIRST_VFP_REGNUM + 31) 977 #define FIRST_HI_VFP_REGNUM (LAST_LO_VFP_REGNUM + 1) 978 #define LAST_HI_VFP_REGNUM (FIRST_HI_VFP_REGNUM + 31) 979 980 #define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 981 ((REGNUM) <= LAST_LO_VFP_REGNUM) 982 983 /* DFmode values are only valid in even register pairs. */ 984 #define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 985 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 986 987 /* Neon Quad values must start at a multiple of four registers. */ 988 #define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 989 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 990 991 /* Neon structures of vectors must be in even register pairs and there 992 must be enough registers available. Because of various patterns 993 requiring quad registers, we require them to start at a multiple of 994 four. */ 995 #define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 996 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 997 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 998 999 /* The number of hard registers is 16 ARM + 1 CC + 1 SFP + 1 AFP. */ 1000 /* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1001 /* VFP (VFP3) adds 32 (64) + 1 VFPCC. */ 1002 #define FIRST_PSEUDO_REGISTER 104 1003 1004 #define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1005 1006 /* Value should be nonzero if functions must have frame pointers. 1007 Zero means the frame pointer need not be set up (and parms may be accessed 1008 via the stack pointer) in functions that seem suitable. 1009 If we have to have a frame pointer we might as well make use of it. 1010 APCS says that the frame pointer does not need to be pushed in leaf 1011 functions, or simple tail call functions. */ 1012 1013 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1014 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1015 #endif 1016 1017 #define VALID_IWMMXT_REG_MODE(MODE) \ 1018 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1019 1020 /* Modes valid for Neon D registers. */ 1021 #define VALID_NEON_DREG_MODE(MODE) \ 1022 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1023 || (MODE) == V4HFmode || (MODE) == V2SFmode || (MODE) == DImode) 1024 1025 /* Modes valid for Neon Q registers. */ 1026 #define VALID_NEON_QREG_MODE(MODE) \ 1027 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1028 || (MODE) == V8HFmode || (MODE) == V4SFmode || (MODE) == V2DImode) 1029 1030 /* Structure modes valid for Neon registers. */ 1031 #define VALID_NEON_STRUCT_MODE(MODE) \ 1032 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1033 || (MODE) == CImode || (MODE) == XImode) 1034 1035 /* The register numbers in sequence, for passing to arm_gen_load_multiple. */ 1036 extern int arm_regs_in_sequence[]; 1037 1038 /* The order in which register should be allocated. It is good to use ip 1039 since no saving is required (though calls clobber it) and it never contains 1040 function parameters. It is quite good to use lr since other calls may 1041 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1042 least likely to contain a function parameter; in addition results are 1043 returned in r0. 1044 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1045 then D8-D15. The reason for doing this is to attempt to reduce register 1046 pressure when both single- and double-precision registers are used in a 1047 function. */ 1048 1049 #define VREG(X) (FIRST_VFP_REGNUM + (X)) 1050 #define WREG(X) (FIRST_IWMMXT_REGNUM + (X)) 1051 #define WGREG(X) (FIRST_IWMMXT_GR_REGNUM + (X)) 1052 1053 #define REG_ALLOC_ORDER \ 1054 { \ 1055 /* General registers. */ \ 1056 3, 2, 1, 0, 12, 14, 4, 5, \ 1057 6, 7, 8, 9, 10, 11, \ 1058 /* High VFP registers. */ \ 1059 VREG(32), VREG(33), VREG(34), VREG(35), \ 1060 VREG(36), VREG(37), VREG(38), VREG(39), \ 1061 VREG(40), VREG(41), VREG(42), VREG(43), \ 1062 VREG(44), VREG(45), VREG(46), VREG(47), \ 1063 VREG(48), VREG(49), VREG(50), VREG(51), \ 1064 VREG(52), VREG(53), VREG(54), VREG(55), \ 1065 VREG(56), VREG(57), VREG(58), VREG(59), \ 1066 VREG(60), VREG(61), VREG(62), VREG(63), \ 1067 /* VFP argument registers. */ \ 1068 VREG(15), VREG(14), VREG(13), VREG(12), \ 1069 VREG(11), VREG(10), VREG(9), VREG(8), \ 1070 VREG(7), VREG(6), VREG(5), VREG(4), \ 1071 VREG(3), VREG(2), VREG(1), VREG(0), \ 1072 /* VFP call-saved registers. */ \ 1073 VREG(16), VREG(17), VREG(18), VREG(19), \ 1074 VREG(20), VREG(21), VREG(22), VREG(23), \ 1075 VREG(24), VREG(25), VREG(26), VREG(27), \ 1076 VREG(28), VREG(29), VREG(30), VREG(31), \ 1077 /* IWMMX registers. */ \ 1078 WREG(0), WREG(1), WREG(2), WREG(3), \ 1079 WREG(4), WREG(5), WREG(6), WREG(7), \ 1080 WREG(8), WREG(9), WREG(10), WREG(11), \ 1081 WREG(12), WREG(13), WREG(14), WREG(15), \ 1082 WGREG(0), WGREG(1), WGREG(2), WGREG(3), \ 1083 /* Registers not for general use. */ \ 1084 CC_REGNUM, VFPCC_REGNUM, \ 1085 FRAME_POINTER_REGNUM, ARG_POINTER_REGNUM, \ 1086 SP_REGNUM, PC_REGNUM \ 1087 } 1088 1089 /* Use different register alloc ordering for Thumb. */ 1090 #define ADJUST_REG_ALLOC_ORDER arm_order_regs_for_local_alloc () 1091 1092 /* Tell IRA to use the order we define rather than messing it up with its 1093 own cost calculations. */ 1094 #define HONOR_REG_ALLOC_ORDER 1 1095 1096 /* Interrupt functions can only use registers that have already been 1097 saved by the prologue, even if they would normally be 1098 call-clobbered. */ 1099 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1100 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1101 df_regs_ever_live_p (DST)) 1102 1103 /* Register and constant classes. */ 1105 1106 /* Register classes. */ 1107 enum reg_class 1108 { 1109 NO_REGS, 1110 LO_REGS, 1111 STACK_REG, 1112 BASE_REGS, 1113 HI_REGS, 1114 CALLER_SAVE_REGS, 1115 GENERAL_REGS, 1116 CORE_REGS, 1117 VFP_D0_D7_REGS, 1118 VFP_LO_REGS, 1119 VFP_HI_REGS, 1120 VFP_REGS, 1121 IWMMXT_REGS, 1122 IWMMXT_GR_REGS, 1123 CC_REG, 1124 VFPCC_REG, 1125 SFP_REG, 1126 AFP_REG, 1127 ALL_REGS, 1128 LIM_REG_CLASSES 1129 }; 1130 1131 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1132 1133 /* Give names of register classes as strings for dump file. */ 1134 #define REG_CLASS_NAMES \ 1135 { \ 1136 "NO_REGS", \ 1137 "LO_REGS", \ 1138 "STACK_REG", \ 1139 "BASE_REGS", \ 1140 "HI_REGS", \ 1141 "CALLER_SAVE_REGS", \ 1142 "GENERAL_REGS", \ 1143 "CORE_REGS", \ 1144 "VFP_D0_D7_REGS", \ 1145 "VFP_LO_REGS", \ 1146 "VFP_HI_REGS", \ 1147 "VFP_REGS", \ 1148 "IWMMXT_REGS", \ 1149 "IWMMXT_GR_REGS", \ 1150 "CC_REG", \ 1151 "VFPCC_REG", \ 1152 "SFP_REG", \ 1153 "AFP_REG", \ 1154 "ALL_REGS" \ 1155 } 1156 1157 /* Define which registers fit in which classes. 1158 This is an initializer for a vector of HARD_REG_SET 1159 of length N_REG_CLASSES. */ 1160 #define REG_CLASS_CONTENTS \ 1161 { \ 1162 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1163 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1164 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1165 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1166 { 0x00005F00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1167 { 0x0000100F, 0x00000000, 0x00000000, 0x00000000 }, /* CALLER_SAVE_REGS */ \ 1168 { 0x00005FFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1169 { 0x00007FFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1170 { 0xFFFF0000, 0x00000000, 0x00000000, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1171 { 0xFFFF0000, 0x0000FFFF, 0x00000000, 0x00000000 }, /* VFP_LO_REGS */ \ 1172 { 0x00000000, 0xFFFF0000, 0x0000FFFF, 0x00000000 }, /* VFP_HI_REGS */ \ 1173 { 0xFFFF0000, 0xFFFFFFFF, 0x0000FFFF, 0x00000000 }, /* VFP_REGS */ \ 1174 { 0x00000000, 0x00000000, 0xFFFF0000, 0x00000000 }, /* IWMMXT_REGS */ \ 1175 { 0x00000000, 0x00000000, 0x00000000, 0x0000000F }, /* IWMMXT_GR_REGS */ \ 1176 { 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, /* CC_REG */ \ 1177 { 0x00000000, 0x00000000, 0x00000000, 0x00000020 }, /* VFPCC_REG */ \ 1178 { 0x00000000, 0x00000000, 0x00000000, 0x00000040 }, /* SFP_REG */ \ 1179 { 0x00000000, 0x00000000, 0x00000000, 0x00000080 }, /* AFP_REG */ \ 1180 { 0xFFFF7FFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x0000000F } /* ALL_REGS */ \ 1181 } 1182 1183 /* Any of the VFP register classes. */ 1184 #define IS_VFP_CLASS(X) \ 1185 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1186 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1187 1188 /* The same information, inverted: 1189 Return the class number of the smallest class containing 1190 reg number REGNO. This could be a conditional expression 1191 or could index an array. */ 1192 #define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1193 1194 /* The class value for index registers, and the one for base regs. */ 1195 #define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1196 #define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1197 1198 /* For the Thumb the high registers cannot be used as base registers 1199 when addressing quantities in QI or HI mode; if we don't know the 1200 mode, then we must be conservative. */ 1201 #define MODE_BASE_REG_CLASS(MODE) \ 1202 (TARGET_32BIT ? CORE_REGS \ 1203 : GET_MODE_SIZE (MODE) >= 4 ? BASE_REGS \ 1204 : LO_REGS) 1205 1206 /* For Thumb we cannot support SP+reg addressing, so we return LO_REGS 1207 instead of BASE_REGS. */ 1208 #define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1209 1210 /* When this hook returns true for MODE, the compiler allows 1211 registers explicitly used in the rtl to be used as spill registers 1212 but prevents the compiler from extending the lifetime of these 1213 registers. */ 1214 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P \ 1215 arm_small_register_classes_for_mode_p 1216 1217 /* Must leave BASE_REGS reloads alone */ 1218 #define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1219 (lra_in_progress ? NO_REGS \ 1220 : ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1221 ? ((true_regnum (X) == -1 ? LO_REGS \ 1222 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1223 : NO_REGS)) \ 1224 : NO_REGS)) 1225 1226 #define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1227 (lra_in_progress ? NO_REGS \ 1228 : (CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1229 ? ((true_regnum (X) == -1 ? LO_REGS \ 1230 : (true_regnum (X) + hard_regno_nregs (0, MODE) > 8) ? LO_REGS \ 1231 : NO_REGS)) \ 1232 : NO_REGS) 1233 1234 /* Return the register class of a scratch register needed to copy IN into 1235 or out of a register in CLASS in MODE. If it can be done directly, 1236 NO_REGS is returned. */ 1237 #define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1238 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1239 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1240 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1241 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1242 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1243 : TARGET_32BIT \ 1244 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1245 ? GENERAL_REGS : NO_REGS) \ 1246 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1247 1248 /* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1249 #define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1250 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1251 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \ 1252 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1253 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1254 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1255 (TARGET_32BIT ? \ 1256 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1257 && CONSTANT_P (X)) \ 1258 ? GENERAL_REGS : \ 1259 (((MODE) == HImode && ! arm_arch4 \ 1260 && (MEM_P (X) \ 1261 || ((REG_P (X) || GET_CODE (X) == SUBREG) \ 1262 && true_regnum (X) == -1))) \ 1263 ? GENERAL_REGS : NO_REGS) \ 1264 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1265 1266 /* Return the maximum number of consecutive registers 1267 needed to represent mode MODE in a register of class CLASS. 1268 ARM regs are UNITS_PER_WORD bits. 1269 FIXME: Is this true for iWMMX? */ 1270 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1271 (ARM_NUM_REGS (MODE)) 1272 1273 /* If defined, gives a class of registers that cannot be used as the 1274 operand of a SUBREG that changes the mode of the object illegally. */ 1275 1276 /* Stack layout; function entry, exit and calling. */ 1278 1279 /* Define this if pushing a word on the stack 1280 makes the stack pointer a smaller address. */ 1281 #define STACK_GROWS_DOWNWARD 1 1282 1283 /* Define this to nonzero if the nominal address of the stack frame 1284 is at the high-address end of the local variables; 1285 that is, each additional local variable allocated 1286 goes at a more negative offset in the frame. */ 1287 #define FRAME_GROWS_DOWNWARD 1 1288 1289 /* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1290 When present, it is one word in size, and sits at the top of the frame, 1291 between the soft frame pointer and either r7 or r11. 1292 1293 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1294 and only then if some outgoing arguments are passed on the stack. It would 1295 be tempting to also check whether the stack arguments are passed by indirect 1296 calls, but there seems to be no reason in principle why a post-reload pass 1297 couldn't convert a direct call into an indirect one. */ 1298 #define CALLER_INTERWORKING_SLOT_SIZE \ 1299 (TARGET_CALLER_INTERWORKING \ 1300 && maybe_ne (crtl->outgoing_args_size, 0) \ 1301 ? UNITS_PER_WORD : 0) 1302 1303 /* If we generate an insn to push BYTES bytes, 1304 this says how many the stack pointer really advances by. */ 1305 /* The push insns do not do this rounding implicitly. 1306 So don't define this. */ 1307 /* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1308 1309 /* Define this if the maximum size of all the outgoing args is to be 1310 accumulated and pushed during the prologue. The amount can be 1311 found in the variable crtl->outgoing_args_size. */ 1312 #define ACCUMULATE_OUTGOING_ARGS 1 1313 1314 /* Offset of first parameter from the argument pointer register value. */ 1315 #define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1316 1317 /* Amount of memory needed for an untyped call to save all possible return 1318 registers. */ 1319 #define APPLY_RESULT_SIZE arm_apply_result_size() 1320 1321 /* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1322 values must be in memory. On the ARM, they need only do so if larger 1323 than a word, or if they contain elements offset from zero in the struct. */ 1324 #define DEFAULT_PCC_STRUCT_RETURN 0 1325 1326 /* These bits describe the different types of function supported 1327 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1328 normal function and an interworked function, for example. Knowing the 1329 type of a function is important for determining its prologue and 1330 epilogue sequences. 1331 Note value 7 is currently unassigned. Also note that the interrupt 1332 function types all have bit 2 set, so that they can be tested for easily. 1333 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1334 machine_function structure is initialized (to zero) func_type will 1335 default to unknown. This will force the first use of arm_current_func_type 1336 to call arm_compute_func_type. */ 1337 #define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1338 #define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1339 #define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1340 #define ARM_FT_ISR 4 /* An interrupt service routine. */ 1341 #define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1342 #define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1343 1344 #define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1345 1346 /* In addition functions can have several type modifiers, 1347 outlined by these bit masks: */ 1348 #define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1349 #define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1350 #define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1351 #define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1352 #define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1353 #define ARM_FT_CMSE_ENTRY (1 << 7) /* ARMv8-M non-secure entry function. */ 1354 1355 /* Some macros to test these flags. */ 1356 #define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1357 #define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1358 #define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1359 #define IS_NAKED(t) (t & ARM_FT_NAKED) 1360 #define IS_NESTED(t) (t & ARM_FT_NESTED) 1361 #define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1362 #define IS_CMSE_ENTRY(t) (t & ARM_FT_CMSE_ENTRY) 1363 1364 1365 /* Structure used to hold the function stack frame layout. Offsets are 1366 relative to the stack pointer on function entry. Positive offsets are 1367 in the direction of stack growth. 1368 Only soft_frame is used in thumb mode. */ 1369 1370 typedef struct GTY(()) arm_stack_offsets 1371 { 1372 int saved_args; /* ARG_POINTER_REGNUM. */ 1373 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1374 int saved_regs; 1375 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1376 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1377 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1378 unsigned int saved_regs_mask; 1379 } 1380 arm_stack_offsets; 1381 1382 #if !defined(GENERATOR_FILE) && !defined (USED_FOR_TARGET) 1383 /* A C structure for machine-specific, per-function data. 1384 This is added to the cfun structure. */ 1385 typedef struct GTY(()) machine_function 1386 { 1387 /* Additional stack adjustment in __builtin_eh_throw. */ 1388 rtx eh_epilogue_sp_ofs; 1389 /* Records if LR has to be saved for far jumps. */ 1390 int far_jump_used; 1391 /* Records if ARG_POINTER was ever live. */ 1392 int arg_pointer_live; 1393 /* Records if the save of LR has been eliminated. */ 1394 int lr_save_eliminated; 1395 /* The size of the stack frame. Only valid after reload. */ 1396 arm_stack_offsets stack_offsets; 1397 /* Records the type of the current function. */ 1398 unsigned long func_type; 1399 /* Record if the function has a variable argument list. */ 1400 int uses_anonymous_args; 1401 /* Records if sibcalls are blocked because an argument 1402 register is needed to preserve stack alignment. */ 1403 int sibcall_blocked; 1404 /* The PIC register for this function. This might be a pseudo. */ 1405 rtx pic_reg; 1406 /* Labels for per-function Thumb call-via stubs. One per potential calling 1407 register. We can never call via LR or PC. We can call via SP if a 1408 trampoline happens to be on the top of the stack. */ 1409 rtx call_via[14]; 1410 /* Set to 1 when a return insn is output, this means that the epilogue 1411 is not needed. */ 1412 int return_used_this_function; 1413 /* When outputting Thumb-1 code, record the last insn that provides 1414 information about condition codes, and the comparison operands. */ 1415 rtx thumb1_cc_insn; 1416 rtx thumb1_cc_op0; 1417 rtx thumb1_cc_op1; 1418 /* Also record the CC mode that is supported. */ 1419 machine_mode thumb1_cc_mode; 1420 /* Set to 1 after arm_reorg has started. */ 1421 int after_arm_reorg; 1422 /* The number of bytes used to store the static chain register on the 1423 stack, above the stack frame. */ 1424 int static_chain_stack_bytes; 1425 } 1426 machine_function; 1427 #endif 1428 1429 /* As in the machine_function, a global set of call-via labels, for code 1430 that is in text_section. */ 1431 extern GTY(()) rtx thumb_call_via_label[14]; 1432 1433 /* The number of potential ways of assigning to a co-processor. */ 1434 #define ARM_NUM_COPROC_SLOTS 1 1435 1436 /* Enumeration of procedure calling standard variants. We don't really 1437 support all of these yet. */ 1438 enum arm_pcs 1439 { 1440 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1441 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1442 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1443 /* This must be the last AAPCS variant. */ 1444 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1445 ARM_PCS_ATPCS, /* ATPCS. */ 1446 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1447 ARM_PCS_UNKNOWN 1448 }; 1449 1450 /* Default procedure calling standard of current compilation unit. */ 1451 extern enum arm_pcs arm_pcs_default; 1452 1453 #if !defined (USED_FOR_TARGET) 1454 /* A C type for declaring a variable that is used as the first argument of 1455 `FUNCTION_ARG' and other related values. */ 1456 typedef struct 1457 { 1458 /* This is the number of registers of arguments scanned so far. */ 1459 int nregs; 1460 /* This is the number of iWMMXt register arguments scanned so far. */ 1461 int iwmmxt_nregs; 1462 int named_count; 1463 int nargs; 1464 /* Which procedure call variant to use for this call. */ 1465 enum arm_pcs pcs_variant; 1466 1467 /* AAPCS related state tracking. */ 1468 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1469 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1470 this argument, or -1 if using core 1471 registers. */ 1472 int aapcs_ncrn; 1473 int aapcs_next_ncrn; 1474 rtx aapcs_reg; /* Register assigned to this argument. */ 1475 int aapcs_partial; /* How many bytes are passed in regs (if 1476 split between core regs and stack. 1477 Zero otherwise. */ 1478 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1479 int can_split; /* Argument can be split between core regs 1480 and the stack. */ 1481 /* Private data for tracking VFP register allocation */ 1482 unsigned aapcs_vfp_regs_free; 1483 unsigned aapcs_vfp_reg_alloc; 1484 int aapcs_vfp_rcount; 1485 MACHMODE aapcs_vfp_rmode; 1486 } CUMULATIVE_ARGS; 1487 #endif 1488 1489 #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1490 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? PAD_UPWARD : PAD_DOWNWARD) 1491 1492 /* For AAPCS, padding should never be below the argument. For other ABIs, 1493 * mimic the default. */ 1494 #define PAD_VARARGS_DOWN \ 1495 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1496 1497 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1498 for a call to a function whose data type is FNTYPE. 1499 For a library call, FNTYPE is 0. 1500 On the ARM, the offset starts at 0. */ 1501 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1502 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1503 1504 /* 1 if N is a possible register number for function argument passing. 1505 On the ARM, r0-r3 are used to pass args. */ 1506 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1507 (IN_RANGE ((REGNO), 0, 3) \ 1508 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \ 1509 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1510 || (TARGET_IWMMXT_ABI \ 1511 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1512 1513 1514 /* If your target environment doesn't prefix user functions with an 1516 underscore, you may wish to re-define this to prevent any conflicts. */ 1517 #ifndef ARM_MCOUNT_NAME 1518 #define ARM_MCOUNT_NAME "*mcount" 1519 #endif 1520 1521 /* Call the function profiler with a given profile label. The Acorn 1522 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1523 On the ARM the full profile code will look like: 1524 .data 1525 LP1 1526 .word 0 1527 .text 1528 mov ip, lr 1529 bl mcount 1530 .word LP1 1531 1532 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1533 will output the .text section. 1534 1535 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1536 ``prof'' doesn't seem to mind about this! 1537 1538 Note - this version of the code is designed to work in both ARM and 1539 Thumb modes. */ 1540 #ifndef ARM_FUNCTION_PROFILER 1541 #define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1542 { \ 1543 char temp[20]; \ 1544 rtx sym; \ 1545 \ 1546 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1547 IP_REGNUM, LR_REGNUM); \ 1548 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1549 fputc ('\n', STREAM); \ 1550 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1551 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1552 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1553 } 1554 #endif 1555 1556 #ifdef THUMB_FUNCTION_PROFILER 1557 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1558 if (TARGET_ARM) \ 1559 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1560 else \ 1561 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1562 #else 1563 #define FUNCTION_PROFILER(STREAM, LABELNO) \ 1564 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1565 #endif 1566 1567 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1568 the stack pointer does not matter. The value is tested only in 1569 functions that have frame pointers. 1570 No definition is equivalent to always zero. 1571 1572 On the ARM, the function epilogue recovers the stack pointer from the 1573 frame. */ 1574 #define EXIT_IGNORE_STACK 1 1575 1576 #define EPILOGUE_USES(REGNO) (epilogue_completed && (REGNO) == LR_REGNUM) 1577 1578 /* Determine if the epilogue should be output as RTL. 1579 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1580 #define USE_RETURN_INSN(ISCOND) \ 1581 (TARGET_32BIT ? use_return_insn (ISCOND, NULL) : 0) 1582 1583 /* Definitions for register eliminations. 1584 1585 This is an array of structures. Each structure initializes one pair 1586 of eliminable registers. The "from" register number is given first, 1587 followed by "to". Eliminations of the same "from" register are listed 1588 in order of preference. 1589 1590 We have two registers that can be eliminated on the ARM. First, the 1591 arg pointer register can often be eliminated in favor of the stack 1592 pointer register. Secondly, the pseudo frame pointer register can always 1593 be eliminated; it is replaced with either the stack or the real frame 1594 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1595 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1596 1597 #define ELIMINABLE_REGS \ 1598 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1599 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1600 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1601 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1602 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1603 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1604 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1605 1606 /* Define the offset between two registers, one to be eliminated, and the 1607 other its replacement, at the start of a routine. */ 1608 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1609 if (TARGET_ARM) \ 1610 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1611 else \ 1612 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1613 1614 /* Special case handling of the location of arguments passed on the stack. */ 1615 #define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1616 1617 /* Initialize data used by insn expanders. This is called from insn_emit, 1618 once for every function before code is generated. */ 1619 #define INIT_EXPANDERS arm_init_expanders () 1620 1621 /* Length in units of the trampoline for entering a nested function. */ 1622 #define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1623 1624 /* Alignment required for a trampoline in bits. */ 1625 #define TRAMPOLINE_ALIGNMENT 32 1626 1627 /* Addressing modes, and classification of registers for them. */ 1629 #define HAVE_POST_INCREMENT 1 1630 #define HAVE_PRE_INCREMENT TARGET_32BIT 1631 #define HAVE_POST_DECREMENT TARGET_32BIT 1632 #define HAVE_PRE_DECREMENT TARGET_32BIT 1633 #define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1634 #define HAVE_POST_MODIFY_DISP TARGET_32BIT 1635 #define HAVE_PRE_MODIFY_REG TARGET_32BIT 1636 #define HAVE_POST_MODIFY_REG TARGET_32BIT 1637 1638 enum arm_auto_incmodes 1639 { 1640 ARM_POST_INC, 1641 ARM_PRE_INC, 1642 ARM_POST_DEC, 1643 ARM_PRE_DEC 1644 }; 1645 1646 #define ARM_AUTOINC_VALID_FOR_MODE_P(mode, code) \ 1647 (TARGET_32BIT && arm_autoinc_modes_ok_p (mode, code)) 1648 #define USE_LOAD_POST_INCREMENT(mode) \ 1649 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_INC) 1650 #define USE_LOAD_PRE_INCREMENT(mode) \ 1651 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_INC) 1652 #define USE_LOAD_POST_DECREMENT(mode) \ 1653 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_POST_DEC) 1654 #define USE_LOAD_PRE_DECREMENT(mode) \ 1655 ARM_AUTOINC_VALID_FOR_MODE_P(mode, ARM_PRE_DEC) 1656 1657 #define USE_STORE_PRE_DECREMENT(mode) USE_LOAD_PRE_DECREMENT(mode) 1658 #define USE_STORE_PRE_INCREMENT(mode) USE_LOAD_PRE_INCREMENT(mode) 1659 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1660 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1661 1662 /* Macros to check register numbers against specific register classes. */ 1663 1664 /* These assume that REGNO is a hard or pseudo reg number. 1665 They give nonzero only if REGNO is a hard reg of the suitable class 1666 or a pseudo reg currently allocated to a suitable hard reg. */ 1667 #define TEST_REGNO(R, TEST, VALUE) \ 1668 ((R TEST VALUE) \ 1669 || (reg_renumber && ((unsigned) reg_renumber[R] TEST VALUE))) 1670 1671 /* Don't allow the pc to be used. */ 1672 #define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1673 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1674 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1675 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1676 1677 #define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1678 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1679 || (GET_MODE_SIZE (MODE) >= 4 \ 1680 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1681 1682 #define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1683 (TARGET_THUMB1 \ 1684 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1685 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1686 1687 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1688 For Thumb, we cannot use SP + reg, so reject SP. */ 1689 #define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1690 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1691 1692 /* For ARM code, we don't care about the mode, but for Thumb, the index 1693 must be suitable for use in a QImode load. */ 1694 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1695 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1696 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1697 1698 /* Maximum number of registers that can appear in a valid memory address. 1699 Shifts in addresses can't be by a register. */ 1700 #define MAX_REGS_PER_ADDRESS 2 1701 1702 /* Recognize any constant value that is a valid address. */ 1703 /* XXX We can address any constant, eventually... */ 1704 /* ??? Should the TARGET_ARM here also apply to thumb2? */ 1705 #define CONSTANT_ADDRESS_P(X) \ 1706 (GET_CODE (X) == SYMBOL_REF \ 1707 && (CONSTANT_POOL_ADDRESS_P (X) \ 1708 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1709 1710 /* True if SYMBOL + OFFSET constants must refer to something within 1711 SYMBOL's section. */ 1712 #define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1713 1714 /* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1715 #ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1716 #define TARGET_DEFAULT_WORD_RELOCATIONS 0 1717 #endif 1718 1719 #ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1720 #define SUBTARGET_NAME_ENCODING_LENGTHS 1721 #endif 1722 1723 /* This is a C fragment for the inside of a switch statement. 1724 Each case label should return the number of characters to 1725 be stripped from the start of a function's name, if that 1726 name starts with the indicated character. */ 1727 #define ARM_NAME_ENCODING_LENGTHS \ 1728 case '*': return 1; \ 1729 SUBTARGET_NAME_ENCODING_LENGTHS 1730 1731 /* This is how to output a reference to a user-level label named NAME. 1732 `assemble_name' uses this. */ 1733 #undef ASM_OUTPUT_LABELREF 1734 #define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1735 arm_asm_output_labelref (FILE, NAME) 1736 1737 /* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1738 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1739 if (TARGET_THUMB2) \ 1740 thumb2_asm_output_opcode (STREAM); 1741 1742 /* The EABI specifies that constructors should go in .init_array. 1743 Other targets use .ctors for compatibility. */ 1744 #ifndef ARM_EABI_CTORS_SECTION_OP 1745 #define ARM_EABI_CTORS_SECTION_OP \ 1746 "\t.section\t.init_array,\"aw\",%init_array" 1747 #endif 1748 #ifndef ARM_EABI_DTORS_SECTION_OP 1749 #define ARM_EABI_DTORS_SECTION_OP \ 1750 "\t.section\t.fini_array,\"aw\",%fini_array" 1751 #endif 1752 #define ARM_CTORS_SECTION_OP \ 1753 "\t.section\t.ctors,\"aw\",%progbits" 1754 #define ARM_DTORS_SECTION_OP \ 1755 "\t.section\t.dtors,\"aw\",%progbits" 1756 1757 /* Define CTORS_SECTION_ASM_OP. */ 1758 #undef CTORS_SECTION_ASM_OP 1759 #undef DTORS_SECTION_ASM_OP 1760 #ifndef IN_LIBGCC2 1761 # define CTORS_SECTION_ASM_OP \ 1762 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1763 # define DTORS_SECTION_ASM_OP \ 1764 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1765 #else /* !defined (IN_LIBGCC2) */ 1766 /* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1767 so we cannot use the definition above. */ 1768 # ifdef __ARM_EABI__ 1769 /* The .ctors section is not part of the EABI, so we do not define 1770 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 1771 from trying to use it. We do define it when doing normal 1772 compilation, as .init_array can be used instead of .ctors. */ 1773 /* There is no need to emit begin or end markers when using 1774 init_array; the dynamic linker will compute the size of the 1775 array itself based on special symbols created by the static 1776 linker. However, we do need to arrange to set up 1777 exception-handling here. */ 1778 # define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 1779 # define CTOR_LIST_END /* empty */ 1780 # define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 1781 # define DTOR_LIST_END /* empty */ 1782 # else /* !defined (__ARM_EABI__) */ 1783 # define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 1784 # define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 1785 # endif /* !defined (__ARM_EABI__) */ 1786 #endif /* !defined (IN_LIBCC2) */ 1787 1788 /* True if the operating system can merge entities with vague linkage 1789 (e.g., symbols in COMDAT group) during dynamic linking. */ 1790 #ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 1791 #define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 1792 #endif 1793 1794 #define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 1795 1796 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1797 and check its validity for a certain class. 1798 We have two alternate definitions for each of them. 1799 The usual definition accepts all pseudo regs; the other rejects 1800 them unless they have been allocated suitable hard regs. 1801 The symbol REG_OK_STRICT causes the latter definition to be used. 1802 Thumb-2 has the same restrictions as arm. */ 1803 #ifndef REG_OK_STRICT 1804 1805 #define ARM_REG_OK_FOR_BASE_P(X) \ 1806 (REGNO (X) <= LAST_ARM_REGNUM \ 1807 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1808 || REGNO (X) == FRAME_POINTER_REGNUM \ 1809 || REGNO (X) == ARG_POINTER_REGNUM) 1810 1811 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1812 ((REGNO (X) <= LAST_ARM_REGNUM \ 1813 && REGNO (X) != STACK_POINTER_REGNUM) \ 1814 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1815 || REGNO (X) == FRAME_POINTER_REGNUM \ 1816 || REGNO (X) == ARG_POINTER_REGNUM) 1817 1818 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1819 (REGNO (X) <= LAST_LO_REGNUM \ 1820 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 1821 || (GET_MODE_SIZE (MODE) >= 4 \ 1822 && (REGNO (X) == STACK_POINTER_REGNUM \ 1823 || (X) == hard_frame_pointer_rtx \ 1824 || (X) == arg_pointer_rtx))) 1825 1826 #define REG_STRICT_P 0 1827 1828 #else /* REG_OK_STRICT */ 1829 1830 #define ARM_REG_OK_FOR_BASE_P(X) \ 1831 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 1832 1833 #define ARM_REG_OK_FOR_INDEX_P(X) \ 1834 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 1835 1836 #define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1837 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 1838 1839 #define REG_STRICT_P 1 1840 1841 #endif /* REG_OK_STRICT */ 1842 1843 /* Now define some helpers in terms of the above. */ 1844 1845 #define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 1846 (TARGET_THUMB1 \ 1847 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 1848 : ARM_REG_OK_FOR_BASE_P (X)) 1849 1850 /* For 16-bit Thumb, a valid index register is anything that can be used in 1851 a byte load instruction. */ 1852 #define THUMB1_REG_OK_FOR_INDEX_P(X) \ 1853 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 1854 1855 /* Nonzero if X is a hard reg that can be used as an index 1856 or if it is a pseudo reg. On the Thumb, the stack pointer 1857 is not suitable. */ 1858 #define REG_OK_FOR_INDEX_P(X) \ 1859 (TARGET_THUMB1 \ 1860 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 1861 : ARM_REG_OK_FOR_INDEX_P (X)) 1862 1863 /* Nonzero if X can be the base register in a reg+reg addressing mode. 1864 For Thumb, we cannot use SP + reg, so reject SP. */ 1865 #define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1866 REG_OK_FOR_INDEX_P (X) 1867 1868 #define ARM_BASE_REGISTER_RTX_P(X) \ 1870 (REG_P (X) && ARM_REG_OK_FOR_BASE_P (X)) 1871 1872 #define ARM_INDEX_REGISTER_RTX_P(X) \ 1873 (REG_P (X) && ARM_REG_OK_FOR_INDEX_P (X)) 1874 1875 /* Specify the machine mode that this machine uses 1877 for the index in the tablejump instruction. */ 1878 #define CASE_VECTOR_MODE Pmode 1879 1880 #define CASE_VECTOR_PC_RELATIVE ((TARGET_THUMB2 \ 1881 || (TARGET_THUMB1 \ 1882 && (optimize_size || flag_pic))) \ 1883 && (!target_pure_code)) 1884 1885 1886 #define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 1887 (TARGET_THUMB1 \ 1888 ? (min >= 0 && max < 512 \ 1889 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 1890 : min >= -256 && max < 256 \ 1891 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 1892 : min >= 0 && max < 8192 \ 1893 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 1894 : min >= -4096 && max < 4096 \ 1895 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 1896 : SImode) \ 1897 : ((min < 0 || max >= 0x20000 || !TARGET_THUMB2) ? SImode \ 1898 : (max >= 0x200) ? HImode \ 1899 : QImode)) 1900 1901 /* signed 'char' is most compatible, but RISC OS wants it unsigned. 1902 unsigned is probably best, but may break some code. */ 1903 #ifndef DEFAULT_SIGNED_CHAR 1904 #define DEFAULT_SIGNED_CHAR 0 1905 #endif 1906 1907 /* Max number of bytes we can move from memory to memory 1908 in one reasonably fast instruction. */ 1909 #define MOVE_MAX 4 1910 1911 #undef MOVE_RATIO 1912 #define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 1913 1914 /* Define if operations between registers always perform the operation 1915 on the full register even if a narrower mode is specified. */ 1916 #define WORD_REGISTER_OPERATIONS 1 1917 1918 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1919 will either zero-extend or sign-extend. The value of this macro should 1920 be the code that says which one of the two operations is implicitly 1921 done, UNKNOWN if none. */ 1922 #define LOAD_EXTEND_OP(MODE) \ 1923 (TARGET_THUMB ? ZERO_EXTEND : \ 1924 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 1925 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 1926 1927 /* Nonzero if access to memory by bytes is slow and undesirable. */ 1928 #define SLOW_BYTE_ACCESS 0 1929 1930 /* Immediate shift counts are truncated by the output routines (or was it 1931 the assembler?). Shift counts in a register are truncated by ARM. Note 1932 that the native compiler puts too large (> 32) immediate shift counts 1933 into a register and shifts by the register, letting the ARM decide what 1934 to do instead of doing that itself. */ 1935 /* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 1936 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 1937 On the arm, Y in a register is used modulo 256 for the shift. Only for 1938 rotates is modulo 32 used. */ 1939 /* #define SHIFT_COUNT_TRUNCATED 1 */ 1940 1941 /* Calling from registers is a massive pain. */ 1942 #define NO_FUNCTION_CSE 1 1943 1944 /* The machine modes of pointers and functions */ 1945 #define Pmode SImode 1946 #define FUNCTION_MODE Pmode 1947 1948 #define ARM_FRAME_RTX(X) \ 1949 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 1950 || (X) == arg_pointer_rtx) 1951 1952 /* Try to generate sequences that don't involve branches, we can then use 1953 conditional instructions. */ 1954 #define BRANCH_COST(speed_p, predictable_p) \ 1955 ((arm_branch_cost != -1) ? arm_branch_cost : \ 1956 (current_tune->branch_cost (speed_p, predictable_p))) 1957 1958 /* False if short circuit operation is preferred. */ 1959 #define LOGICAL_OP_NON_SHORT_CIRCUIT \ 1960 ((optimize_size) \ 1961 ? (TARGET_THUMB ? false : true) \ 1962 : TARGET_THUMB ? static_cast<bool> (current_tune->logical_op_non_short_circuit_thumb) \ 1963 : static_cast<bool> (current_tune->logical_op_non_short_circuit_arm)) 1964 1965 1966 /* Position Independent Code. */ 1968 /* We decide which register to use based on the compilation options and 1969 the assembler in use; this is more general than the APCS restriction of 1970 using sb (r9) all the time. */ 1971 extern unsigned arm_pic_register; 1972 1973 /* The register number of the register used to address a table of static 1974 data addresses in memory. */ 1975 #define PIC_OFFSET_TABLE_REGNUM arm_pic_register 1976 1977 /* We can't directly access anything that contains a symbol, 1978 nor can we indirect via the constant pool. One exception is 1979 UNSPEC_TLS, which is always PIC. */ 1980 #define LEGITIMATE_PIC_OPERAND_P(X) \ 1981 (!(symbol_mentioned_p (X) \ 1982 || label_mentioned_p (X) \ 1983 || (GET_CODE (X) == SYMBOL_REF \ 1984 && CONSTANT_POOL_ADDRESS_P (X) \ 1985 && (symbol_mentioned_p (get_pool_constant (X)) \ 1986 || label_mentioned_p (get_pool_constant (X))))) \ 1987 || tls_mentioned_p (X)) 1988 1989 /* We need to know when we are making a constant pool; this determines 1990 whether data needs to be in the GOT or can be referenced via a GOT 1991 offset. */ 1992 extern int making_const_table; 1993 1994 /* Handle pragmas for compatibility with Intel's compilers. */ 1996 /* Also abuse this to register additional C specific EABI attributes. */ 1997 #define REGISTER_TARGET_PRAGMAS() do { \ 1998 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 1999 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2000 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2001 arm_lang_object_attributes_init(); \ 2002 arm_register_target_pragmas(); \ 2003 } while (0) 2004 2005 /* Condition code information. */ 2006 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2007 return the mode to be used for the comparison. */ 2008 2009 #define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2010 2011 #define REVERSIBLE_CC_MODE(MODE) 1 2012 2013 #define REVERSE_CONDITION(CODE,MODE) \ 2014 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2015 ? reverse_condition_maybe_unordered (code) \ 2016 : reverse_condition (code)) 2017 2018 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2019 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2020 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2021 ((VALUE) = GET_MODE_UNIT_BITSIZE (MODE), 2) 2022 2023 #define CC_STATUS_INIT \ 2025 do { cfun->machine->thumb1_cc_insn = NULL_RTX; } while (0) 2026 2027 #undef ASM_APP_ON 2028 #define ASM_APP_ON (inline_asm_unified ? "\t.syntax unified\n" : \ 2029 "\t.syntax divided\n") 2030 2031 #undef ASM_APP_OFF 2032 #define ASM_APP_OFF (TARGET_ARM ? "\t.arm\n\t.syntax unified\n" : \ 2033 "\t.thumb\n\t.syntax unified\n") 2034 2035 /* Output a push or a pop instruction (only used when profiling). 2036 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2037 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2038 that r7 isn't used by the function profiler, so we can use it as a 2039 scratch reg. WARNING: This isn't safe in the general case! It may be 2040 sensitive to future changes in final.c:profile_function. */ 2041 #define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2042 do \ 2043 { \ 2044 if (TARGET_THUMB1 \ 2045 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2046 { \ 2047 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2048 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2049 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2050 } \ 2051 else \ 2052 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2053 } while (0) 2054 2055 2056 /* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2057 #define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2058 do \ 2059 { \ 2060 if (TARGET_THUMB1 \ 2061 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2062 { \ 2063 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2064 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2065 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2066 } \ 2067 else \ 2068 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2069 } while (0) 2070 2071 #define ADDR_VEC_ALIGN(JUMPTABLE) \ 2072 ((TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) ? 2 : 0) 2073 2074 /* Alignment for case labels comes from ADDR_VEC_ALIGN; avoid the 2075 default alignment from elfos.h. */ 2076 #undef ASM_OUTPUT_BEFORE_CASE_LABEL 2077 #define ASM_OUTPUT_BEFORE_CASE_LABEL(FILE, PREFIX, NUM, TABLE) /* Empty. */ 2078 2079 #define LABEL_ALIGN_AFTER_BARRIER(LABEL) \ 2080 (GET_CODE (PATTERN (prev_active_insn (LABEL))) == ADDR_DIFF_VEC \ 2081 ? 1 : 0) 2082 2083 #define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2084 arm_declare_function_name ((STREAM), (NAME), (DECL)); 2085 2086 /* For aliases of functions we use .thumb_set instead. */ 2087 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2088 do \ 2089 { \ 2090 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2091 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2092 \ 2093 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2094 { \ 2095 fprintf (FILE, "\t.thumb_set "); \ 2096 assemble_name (FILE, LABEL1); \ 2097 fprintf (FILE, ","); \ 2098 assemble_name (FILE, LABEL2); \ 2099 fprintf (FILE, "\n"); \ 2100 } \ 2101 else \ 2102 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2103 } \ 2104 while (0) 2105 2106 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2107 /* To support -falign-* switches we need to use .p2align so 2108 that alignment directives in code sections will be padded 2109 with no-op instructions, rather than zeroes. */ 2110 #define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2111 if ((LOG) != 0) \ 2112 { \ 2113 if ((MAX_SKIP) == 0) \ 2114 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2115 else \ 2116 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2117 (int) (LOG), (int) (MAX_SKIP)); \ 2118 } 2119 #endif 2120 2121 /* Add two bytes to the length of conditionally executed Thumb-2 2123 instructions for the IT instruction. */ 2124 #define ADJUST_INSN_LENGTH(insn, length) \ 2125 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2126 length += 2; 2127 2128 /* Only perform branch elimination (by making instructions conditional) if 2129 we're optimizing. For Thumb-2 check if any IT instructions need 2130 outputting. */ 2131 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2132 if (TARGET_ARM && optimize) \ 2133 arm_final_prescan_insn (INSN); \ 2134 else if (TARGET_THUMB2) \ 2135 thumb2_final_prescan_insn (INSN); \ 2136 else if (TARGET_THUMB1) \ 2137 thumb1_final_prescan_insn (INSN) 2138 2139 #define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2140 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2141 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2142 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2143 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2144 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2145 : 0)))) 2146 2147 /* A C expression whose value is RTL representing the value of the return 2148 address for the frame COUNT steps up from the current frame. */ 2149 2150 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2151 arm_return_addr (COUNT, FRAME) 2152 2153 /* Mask of the bits in the PC that contain the real return address 2154 when running in 26-bit mode. */ 2155 #define RETURN_ADDR_MASK26 (0x03fffffc) 2156 2157 /* Pick up the return address upon entry to a procedure. Used for 2158 dwarf2 unwind information. This also enables the table driven 2159 mechanism. */ 2160 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2161 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2162 2163 /* Used to mask out junk bits from the return address, such as 2164 processor state, interrupt status, condition codes and the like. */ 2165 #define MASK_RETURN_ADDR \ 2166 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2167 in 26 bit mode, the condition codes must be masked out of the \ 2168 return address. This does not apply to ARM6 and later processors \ 2169 when running in 32 bit mode. */ \ 2170 ((arm_arch4 || TARGET_THUMB) \ 2171 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2172 : arm_gen_return_addr_mask ()) 2173 2174 2175 /* Do not emit .note.GNU-stack by default. */ 2177 #ifndef NEED_INDICATE_EXEC_STACK 2178 #define NEED_INDICATE_EXEC_STACK 0 2179 #endif 2180 2181 #define TARGET_ARM_ARCH \ 2182 (arm_base_arch) \ 2183 2184 /* The highest Thumb instruction set version supported by the chip. */ 2185 #define TARGET_ARM_ARCH_ISA_THUMB \ 2186 (arm_arch_thumb2 ? 2 : (arm_arch_thumb1 ? 1 : 0)) 2187 2188 /* Expands to an upper-case char of the target's architectural 2189 profile. */ 2190 #define TARGET_ARM_ARCH_PROFILE \ 2191 (arm_active_target.profile) 2192 2193 /* Bit-field indicating what size LDREX/STREX loads/stores are available. 2194 Bit 0 for bytes, up to bit 3 for double-words. */ 2195 #define TARGET_ARM_FEATURE_LDREX \ 2196 ((TARGET_HAVE_LDREX ? 4 : 0) \ 2197 | (TARGET_HAVE_LDREXBH ? 3 : 0) \ 2198 | (TARGET_HAVE_LDREXD ? 8 : 0)) 2199 2200 /* Set as a bit mask indicating the available widths of hardware floating 2201 point types. Where bit 1 indicates 16-bit support, bit 2 indicates 2202 32-bit support, bit 3 indicates 64-bit support. */ 2203 #define TARGET_ARM_FP \ 2204 (!TARGET_SOFT_FLOAT ? (TARGET_VFP_SINGLE ? 4 \ 2205 : (TARGET_VFP_DOUBLE ? (TARGET_FP16 ? 14 : 12) : 0)) \ 2206 : 0) 2207 2208 2209 /* Set as a bit mask indicating the available widths of floating point 2210 types for hardware NEON floating point. This is the same as 2211 TARGET_ARM_FP without the 64-bit bit set. */ 2212 #define TARGET_NEON_FP \ 2213 (TARGET_NEON ? (TARGET_ARM_FP & (0xff ^ 0x08)) \ 2214 : 0) 2215 2216 /* Name of the automatic fpu-selection option. */ 2217 #define FPUTYPE_AUTO "auto" 2218 2219 /* The maximum number of parallel loads or stores we support in an ldm/stm 2220 instruction. */ 2221 #define MAX_LDM_STM_OPS 4 2222 2223 extern const char *arm_rewrite_mcpu (int argc, const char **argv); 2224 extern const char *arm_rewrite_march (int argc, const char **argv); 2225 extern const char *arm_asm_auto_mfpu (int argc, const char **argv); 2226 #define ASM_CPU_SPEC_FUNCTIONS \ 2227 { "rewrite_mcpu", arm_rewrite_mcpu }, \ 2228 { "rewrite_march", arm_rewrite_march }, \ 2229 { "asm_auto_mfpu", arm_asm_auto_mfpu }, 2230 2231 #define ASM_CPU_SPEC \ 2232 " %{mfpu=auto:%<mfpu=auto %:asm_auto_mfpu(%{march=*: arch %*})}" \ 2233 " %{mcpu=generic-*:-march=%:rewrite_march(%{mcpu=generic-*:%*});" \ 2234 " march=*:-march=%:rewrite_march(%{march=*:%*});" \ 2235 " mcpu=*:-mcpu=%:rewrite_mcpu(%{mcpu=*:%*})" \ 2236 " }" 2237 2238 extern const char *arm_target_thumb_only (int argc, const char **argv); 2239 #define TARGET_MODE_SPEC_FUNCTIONS \ 2240 { "target_mode_check", arm_target_thumb_only }, 2241 2242 /* -mcpu=native handling only makes sense with compiler running on 2243 an ARM chip. */ 2244 #if defined(__arm__) && defined(__linux__) 2245 extern const char *host_detect_local_cpu (int argc, const char **argv); 2246 #define HAVE_LOCAL_CPU_DETECT 2247 # define MCPU_MTUNE_NATIVE_FUNCTIONS \ 2248 { "local_cpu_detect", host_detect_local_cpu }, 2249 # define MCPU_MTUNE_NATIVE_SPECS \ 2250 " %{march=native:%<march=native %:local_cpu_detect(arch)}" \ 2251 " %{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)}" \ 2252 " %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 2253 #else 2254 # define MCPU_MTUNE_NATIVE_FUNCTIONS 2255 # define MCPU_MTUNE_NATIVE_SPECS "" 2256 #endif 2257 2258 const char *arm_canon_arch_option (int argc, const char **argv); 2259 2260 #define CANON_ARCH_SPEC_FUNCTION \ 2261 { "canon_arch", arm_canon_arch_option }, 2262 2263 const char *arm_be8_option (int argc, const char **argv); 2264 #define BE8_SPEC_FUNCTION \ 2265 { "be8_linkopt", arm_be8_option }, 2266 2267 # define EXTRA_SPEC_FUNCTIONS \ 2268 MCPU_MTUNE_NATIVE_FUNCTIONS \ 2269 ASM_CPU_SPEC_FUNCTIONS \ 2270 CANON_ARCH_SPEC_FUNCTION \ 2271 TARGET_MODE_SPEC_FUNCTIONS \ 2272 BE8_SPEC_FUNCTION 2273 2274 /* Automatically add -mthumb for Thumb-only targets if mode isn't specified 2275 via the configuration option --with-mode or via the command line. The 2276 function target_mode_check is called to do the check with either: 2277 - an array of -march values if any is given; 2278 - an array of -mcpu values if any is given; 2279 - an empty array. */ 2280 #define TARGET_MODE_SPECS \ 2281 " %{!marm:%{!mthumb:%:target_mode_check(%{march=*:arch %*;mcpu=*:cpu %*;:})}}" 2282 2283 /* Generate a canonical string to represent the architecture selected. */ 2284 #define ARCH_CANONICAL_SPECS \ 2285 " -march=%:canon_arch(%{mcpu=*: cpu %*} " \ 2286 " %{march=*: arch %*} " \ 2287 " %{mfpu=*: fpu %*} " \ 2288 " %{mfloat-abi=*: abi %*}" \ 2289 " %<march=*) " 2290 2291 /* Complete set of specs for the driver. Commas separate the 2292 individual rules so that any option suppression (%<opt...)is 2293 completed before starting subsequent rules. */ 2294 #define DRIVER_SELF_SPECS \ 2295 MCPU_MTUNE_NATIVE_SPECS, \ 2296 TARGET_MODE_SPECS, \ 2297 ARCH_CANONICAL_SPECS 2298 2299 #define TARGET_SUPPORTS_WIDE_INT 1 2300 2301 /* For switching between functions with different target attributes. */ 2302 #define SWITCHABLE_TARGET 1 2303 2304 /* Define SECTION_ARM_PURECODE as the ARM specific section attribute 2305 representation for SHF_ARM_PURECODE in GCC. */ 2306 #define SECTION_ARM_PURECODE SECTION_MACH_DEP 2307 2308 #endif /* ! GCC_ARM_H */ 2309
Indexes created Wed Apr 15 00:22:22 UTC 2026