bfin.h revision 1.1.1.1.8.2
1 /* Definitions for the Blackfin port. 2 Copyright (C) 2005, 2007, 2008, 2009 Free Software Foundation, Inc. 3 Contributed by Analog Devices. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _BFIN_CONFIG 22 #define _BFIN_CONFIG 23 24 #define OBJECT_FORMAT_ELF 25 26 #define BRT 1 27 #define BRF 0 28 29 /* CPU type. */ 30 typedef enum bfin_cpu_type 31 { 32 BFIN_CPU_UNKNOWN, 33 BFIN_CPU_BF512, 34 BFIN_CPU_BF514, 35 BFIN_CPU_BF516, 36 BFIN_CPU_BF518, 37 BFIN_CPU_BF522, 38 BFIN_CPU_BF523, 39 BFIN_CPU_BF524, 40 BFIN_CPU_BF525, 41 BFIN_CPU_BF526, 42 BFIN_CPU_BF527, 43 BFIN_CPU_BF531, 44 BFIN_CPU_BF532, 45 BFIN_CPU_BF533, 46 BFIN_CPU_BF534, 47 BFIN_CPU_BF536, 48 BFIN_CPU_BF537, 49 BFIN_CPU_BF538, 50 BFIN_CPU_BF539, 51 BFIN_CPU_BF542, 52 BFIN_CPU_BF542M, 53 BFIN_CPU_BF544, 54 BFIN_CPU_BF544M, 55 BFIN_CPU_BF547, 56 BFIN_CPU_BF547M, 57 BFIN_CPU_BF548, 58 BFIN_CPU_BF548M, 59 BFIN_CPU_BF549, 60 BFIN_CPU_BF549M, 61 BFIN_CPU_BF561 62 } bfin_cpu_t; 63 64 /* Value of -mcpu= */ 65 extern bfin_cpu_t bfin_cpu_type; 66 67 /* Value of -msi-revision= */ 68 extern int bfin_si_revision; 69 70 extern unsigned int bfin_workarounds; 71 72 /* Print subsidiary information on the compiler version in use. */ 73 #define TARGET_VERSION fprintf (stderr, " (BlackFin bfin)") 74 75 /* Run-time compilation parameters selecting different hardware subsets. */ 76 77 extern int target_flags; 78 79 /* Predefinition in the preprocessor for this target machine */ 80 #ifndef TARGET_CPU_CPP_BUILTINS 81 #define TARGET_CPU_CPP_BUILTINS() \ 82 do \ 83 { \ 84 builtin_define_std ("bfin"); \ 85 builtin_define_std ("BFIN"); \ 86 builtin_define ("__ADSPBLACKFIN__"); \ 87 builtin_define ("__ADSPLPBLACKFIN__"); \ 88 \ 89 switch (bfin_cpu_type) \ 90 { \ 91 case BFIN_CPU_BF512: \ 92 builtin_define ("__ADSPBF512__"); \ 93 builtin_define ("__ADSPBF51x__"); \ 94 break; \ 95 case BFIN_CPU_BF514: \ 96 builtin_define ("__ADSPBF514__"); \ 97 builtin_define ("__ADSPBF51x__"); \ 98 break; \ 99 case BFIN_CPU_BF516: \ 100 builtin_define ("__ADSPBF516__"); \ 101 builtin_define ("__ADSPBF51x__"); \ 102 break; \ 103 case BFIN_CPU_BF518: \ 104 builtin_define ("__ADSPBF518__"); \ 105 builtin_define ("__ADSPBF51x__"); \ 106 break; \ 107 case BFIN_CPU_BF522: \ 108 builtin_define ("__ADSPBF522__"); \ 109 builtin_define ("__ADSPBF52x__"); \ 110 break; \ 111 case BFIN_CPU_BF523: \ 112 builtin_define ("__ADSPBF523__"); \ 113 builtin_define ("__ADSPBF52x__"); \ 114 break; \ 115 case BFIN_CPU_BF524: \ 116 builtin_define ("__ADSPBF524__"); \ 117 builtin_define ("__ADSPBF52x__"); \ 118 break; \ 119 case BFIN_CPU_BF525: \ 120 builtin_define ("__ADSPBF525__"); \ 121 builtin_define ("__ADSPBF52x__"); \ 122 break; \ 123 case BFIN_CPU_BF526: \ 124 builtin_define ("__ADSPBF526__"); \ 125 builtin_define ("__ADSPBF52x__"); \ 126 break; \ 127 case BFIN_CPU_BF527: \ 128 builtin_define ("__ADSPBF527__"); \ 129 builtin_define ("__ADSPBF52x__"); \ 130 break; \ 131 case BFIN_CPU_BF531: \ 132 builtin_define ("__ADSPBF531__"); \ 133 break; \ 134 case BFIN_CPU_BF532: \ 135 builtin_define ("__ADSPBF532__"); \ 136 break; \ 137 case BFIN_CPU_BF533: \ 138 builtin_define ("__ADSPBF533__"); \ 139 break; \ 140 case BFIN_CPU_BF534: \ 141 builtin_define ("__ADSPBF534__"); \ 142 break; \ 143 case BFIN_CPU_BF536: \ 144 builtin_define ("__ADSPBF536__"); \ 145 break; \ 146 case BFIN_CPU_BF537: \ 147 builtin_define ("__ADSPBF537__"); \ 148 break; \ 149 case BFIN_CPU_BF538: \ 150 builtin_define ("__ADSPBF538__"); \ 151 break; \ 152 case BFIN_CPU_BF539: \ 153 builtin_define ("__ADSPBF539__"); \ 154 break; \ 155 case BFIN_CPU_BF542M: \ 156 builtin_define ("__ADSPBF542M__"); \ 157 case BFIN_CPU_BF542: \ 158 builtin_define ("__ADSPBF542__"); \ 159 builtin_define ("__ADSPBF54x__"); \ 160 break; \ 161 case BFIN_CPU_BF544M: \ 162 builtin_define ("__ADSPBF544M__"); \ 163 case BFIN_CPU_BF544: \ 164 builtin_define ("__ADSPBF544__"); \ 165 builtin_define ("__ADSPBF54x__"); \ 166 break; \ 167 case BFIN_CPU_BF547M: \ 168 builtin_define ("__ADSPBF547M__"); \ 169 case BFIN_CPU_BF547: \ 170 builtin_define ("__ADSPBF547__"); \ 171 builtin_define ("__ADSPBF54x__"); \ 172 break; \ 173 case BFIN_CPU_BF548M: \ 174 builtin_define ("__ADSPBF548M__"); \ 175 case BFIN_CPU_BF548: \ 176 builtin_define ("__ADSPBF548__"); \ 177 builtin_define ("__ADSPBF54x__"); \ 178 break; \ 179 case BFIN_CPU_BF549M: \ 180 builtin_define ("__ADSPBF549M__"); \ 181 case BFIN_CPU_BF549: \ 182 builtin_define ("__ADSPBF549__"); \ 183 builtin_define ("__ADSPBF54x__"); \ 184 break; \ 185 case BFIN_CPU_BF561: \ 186 builtin_define ("__ADSPBF561__"); \ 187 break; \ 188 } \ 189 \ 190 if (bfin_si_revision != -1) \ 191 { \ 192 /* space of 0xnnnn and a NUL */ \ 193 char *buf = XALLOCAVEC (char, 7); \ 194 \ 195 sprintf (buf, "0x%04x", bfin_si_revision); \ 196 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ 197 } \ 198 \ 199 if (bfin_workarounds) \ 200 builtin_define ("__WORKAROUNDS_ENABLED"); \ 201 if (ENABLE_WA_SPECULATIVE_LOADS) \ 202 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ 203 if (ENABLE_WA_SPECULATIVE_SYNCS) \ 204 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ 205 if (ENABLE_WA_INDIRECT_CALLS) \ 206 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \ 207 if (ENABLE_WA_RETS) \ 208 builtin_define ("__WORKAROUND_RETS"); \ 209 \ 210 if (TARGET_FDPIC) \ 211 { \ 212 builtin_define ("__BFIN_FDPIC__"); \ 213 builtin_define ("__FDPIC__"); \ 214 } \ 215 if (TARGET_ID_SHARED_LIBRARY \ 216 && !TARGET_SEP_DATA) \ 217 builtin_define ("__ID_SHARED_LIB__"); \ 218 if (flag_no_builtin) \ 219 builtin_define ("__NO_BUILTIN"); \ 220 if (TARGET_MULTICORE) \ 221 builtin_define ("__BFIN_MULTICORE"); \ 222 if (TARGET_COREA) \ 223 builtin_define ("__BFIN_COREA"); \ 224 if (TARGET_COREB) \ 225 builtin_define ("__BFIN_COREB"); \ 226 if (TARGET_SDRAM) \ 227 builtin_define ("__BFIN_SDRAM"); \ 228 } \ 229 while (0) 230 #endif 231 232 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 233 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ 234 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 235 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 236 " 237 #ifndef SUBTARGET_DRIVER_SELF_SPECS 238 # define SUBTARGET_DRIVER_SELF_SPECS 239 #endif 240 241 #define LINK_GCC_C_SEQUENCE_SPEC "\ 242 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \ 243 " 244 245 /* A C string constant that tells the GCC driver program options to pass to 246 the assembler. It can also specify how to translate options you give to GNU 247 CC into options for GCC to pass to the assembler. See the file `sun3.h' 248 for an example of this. 249 250 Do not define this macro if it does not need to do anything. 251 252 Defined in svr4.h. */ 253 #undef ASM_SPEC 254 #define ASM_SPEC "\ 255 %{G*} %{v} %{n} %{T} %{Ym,*} %{Yd,*} %{Wa,*:%*} \ 256 %{mno-fdpic:-mnopic} %{mfdpic}" 257 258 #define LINK_SPEC "\ 259 %{h*} %{v:-V} \ 260 %{b} \ 261 %{mfdpic:-melf32bfinfd -z text} \ 262 %{static:-dn -Bstatic} \ 263 %{shared:-G -Bdynamic} \ 264 %{symbolic:-Bsymbolic} \ 265 %{G*} \ 266 %{YP,*} \ 267 %{Qy:} %{!Qn:-Qy} \ 268 -init __init -fini __fini " 269 270 /* Generate DSP instructions, like DSP halfword loads */ 271 #define TARGET_DSP (1) 272 273 #define TARGET_DEFAULT 0 274 275 /* Maximum number of library ids we permit */ 276 #define MAX_LIBRARY_ID 255 277 278 extern const char *bfin_library_id_string; 279 280 /* Sometimes certain combinations of command options do not make 281 sense on a particular target machine. You can define a macro 282 `OVERRIDE_OPTIONS' to take account of this. This macro, if 283 defined, is executed once just after all the command options have 284 been parsed. 285 286 Don't use this macro to turn on various extra optimizations for 287 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 288 289 #define OVERRIDE_OPTIONS override_options () 290 291 #define FUNCTION_MODE SImode 292 #define Pmode SImode 293 294 /* store-condition-codes instructions store 0 for false 295 This is the value stored for true. */ 296 #define STORE_FLAG_VALUE 1 297 298 /* Define this if pushing a word on the stack 299 makes the stack pointer a smaller address. */ 300 #define STACK_GROWS_DOWNWARD 301 302 #define STACK_PUSH_CODE PRE_DEC 303 304 /* Define this to nonzero if the nominal address of the stack frame 305 is at the high-address end of the local variables; 306 that is, each additional local variable allocated 307 goes at a more negative offset in the frame. */ 308 #define FRAME_GROWS_DOWNWARD 1 309 310 /* We define a dummy ARGP register; the parameters start at offset 0 from 311 it. */ 312 #define FIRST_PARM_OFFSET(DECL) 0 313 314 /* Offset within stack frame to start allocating local variables at. 315 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 316 first local allocated. Otherwise, it is the offset to the BEGINNING 317 of the first local allocated. */ 318 #define STARTING_FRAME_OFFSET 0 319 320 /* Register to use for pushing function arguments. */ 321 #define STACK_POINTER_REGNUM REG_P6 322 323 /* Base register for access to local variables of the function. */ 324 #define FRAME_POINTER_REGNUM REG_P7 325 326 /* A dummy register that will be eliminated to either FP or SP. */ 327 #define ARG_POINTER_REGNUM REG_ARGP 328 329 /* `PIC_OFFSET_TABLE_REGNUM' 330 The register number of the register used to address a table of 331 static data addresses in memory. In some cases this register is 332 defined by a processor's "application binary interface" (ABI). 333 When this macro is defined, RTL is generated for this register 334 once, as with the stack pointer and frame pointer registers. If 335 this macro is not defined, it is up to the machine-dependent files 336 to allocate such a register (if necessary). */ 337 #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 338 339 #define FDPIC_FPTR_REGNO REG_P1 340 #define FDPIC_REGNO REG_P3 341 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 342 343 /* A static chain register for nested functions. We need to use a 344 call-clobbered register for this. */ 345 #define STATIC_CHAIN_REGNUM REG_P2 346 347 /* Define this if functions should assume that stack space has been 348 allocated for arguments even when their values are passed in 349 registers. 350 351 The value of this macro is the size, in bytes, of the area reserved for 352 arguments passed in registers. 353 354 This space can either be allocated by the caller or be a part of the 355 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 356 says which. */ 357 #define FIXED_STACK_AREA 12 358 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 359 360 /* Define this if the above stack space is to be considered part of the 361 * space allocated by the caller. */ 362 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 363 364 /* Define this if the maximum size of all the outgoing args is to be 365 accumulated and pushed during the prologue. The amount can be 366 found in the variable crtl->outgoing_args_size. */ 367 #define ACCUMULATE_OUTGOING_ARGS 1 368 369 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 370 371 /* If defined, a C expression to compute the alignment for a local 372 variable. TYPE is the data type, and ALIGN is the alignment that 373 the object would ordinarily have. The value of this macro is used 374 instead of that alignment to align the object. 375 376 If this macro is not defined, then ALIGN is used. 377 378 One use of this macro is to increase alignment of medium-size 379 data to make it all fit in fewer cache lines. */ 380 381 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) 382 383 /* Make strings word-aligned so strcpy from constants will be faster. */ 384 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 385 (TREE_CODE (EXP) == STRING_CST \ 386 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 387 388 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 389 390 /* Definitions for register eliminations. 392 393 This is an array of structures. Each structure initializes one pair 394 of eliminable registers. The "from" register number is given first, 395 followed by "to". Eliminations of the same "from" register are listed 396 in order of preference. 397 398 There are two registers that can always be eliminated on the i386. 399 The frame pointer and the arg pointer can be replaced by either the 400 hard frame pointer or to the stack pointer, depending upon the 401 circumstances. The hard frame pointer is not used before reload and 402 so it is not eligible for elimination. */ 403 404 #define ELIMINABLE_REGS \ 405 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 406 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 407 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 408 409 /* Define the offset between two registers, one to be eliminated, and the other 410 its replacement, at the start of a routine. */ 411 412 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 413 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 414 415 /* This processor has 417 8 data register for doing arithmetic 418 8 pointer register for doing addressing, including 419 1 stack pointer P6 420 1 frame pointer P7 421 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 422 1 condition code flag register CC 423 5 return address registers RETS/I/X/N/E 424 1 arithmetic status register (ASTAT). */ 425 426 #define FIRST_PSEUDO_REGISTER 50 427 428 #define D_REGNO_P(X) ((X) <= REG_R7) 429 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 430 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 431 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 432 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 433 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 434 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 435 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 436 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 437 438 #define REGISTER_NAMES { \ 439 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 440 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 441 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 442 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 443 "A0", "A1", \ 444 "CC", \ 445 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 446 "ARGP", \ 447 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 448 } 449 450 #define SHORT_REGISTER_NAMES { \ 451 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 452 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 453 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 454 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 455 456 #define HIGH_REGISTER_NAMES { \ 457 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 458 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 459 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 460 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 461 462 #define DREGS_PAIR_NAMES { \ 463 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 464 465 #define BYTE_REGISTER_NAMES { \ 466 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 467 468 469 /* 1 for registers that have pervasive standard uses 470 and are not available for the register allocator. */ 471 472 #define FIXED_REGISTERS \ 473 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 474 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 475 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 476 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 477 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 478 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 479 /*lb0/1 */ \ 480 1, 1 \ 481 } 482 483 /* 1 for registers not available across function calls. 484 These must include the FIXED_REGISTERS and also any 485 registers that can be used without being saved. 486 The latter must include the registers where values are returned 487 and the register where structure-value addresses are passed. 488 Aside from that, you can include as many other registers as you like. */ 489 490 #define CALL_USED_REGISTERS \ 491 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 492 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 493 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 494 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 495 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 496 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 497 /*lb0/1 */ \ 498 1, 1 \ 499 } 500 501 /* Order in which to allocate registers. Each register must be 502 listed once, even those in FIXED_REGISTERS. List frame pointer 503 late and fixed registers last. Note that, in general, we prefer 504 registers listed in CALL_USED_REGISTERS, keeping the others 505 available for storage of persistent values. */ 506 507 #define REG_ALLOC_ORDER \ 508 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 509 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 510 REG_A0, REG_A1, \ 511 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 512 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 513 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 514 REG_ASTAT, REG_SEQSTAT, REG_USP, \ 515 REG_CC, REG_ARGP, \ 516 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 517 } 518 519 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 520 #define CONDITIONAL_REGISTER_USAGE \ 521 { \ 522 conditional_register_usage(); \ 523 if (TARGET_FDPIC) \ 524 call_used_regs[FDPIC_REGNO] = 1; \ 525 if (!TARGET_FDPIC && flag_pic) \ 526 { \ 527 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 528 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 529 } \ 530 } 531 532 /* Define the classes of registers for register constraints in the 533 machine description. Also define ranges of constants. 534 535 One of the classes must always be named ALL_REGS and include all hard regs. 536 If there is more than one class, another class must be named NO_REGS 537 and contain no registers. 538 539 The name GENERAL_REGS must be the name of a class (or an alias for 540 another name such as ALL_REGS). This is the class of registers 541 that is allowed by "g" or "r" in a register constraint. 542 Also, registers outside this class are allocated only when 543 instructions express preferences for them. 544 545 The classes must be numbered in nondecreasing order; that is, 546 a larger-numbered class must never be contained completely 547 in a smaller-numbered class. 548 549 For any two classes, it is very desirable that there be another 550 class that represents their union. */ 551 552 553 enum reg_class 554 { 555 NO_REGS, 556 IREGS, 557 BREGS, 558 LREGS, 559 MREGS, 560 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 561 DAGREGS, 562 EVEN_AREGS, 563 ODD_AREGS, 564 AREGS, 565 CCREGS, 566 EVEN_DREGS, 567 ODD_DREGS, 568 D0REGS, 569 D1REGS, 570 D2REGS, 571 D3REGS, 572 D4REGS, 573 D5REGS, 574 D6REGS, 575 D7REGS, 576 DREGS, 577 P0REGS, 578 FDPIC_REGS, 579 FDPIC_FPTR_REGS, 580 PREGS_CLOBBERED, 581 PREGS, 582 IPREGS, 583 DPREGS, 584 MOST_REGS, 585 LT_REGS, 586 LC_REGS, 587 LB_REGS, 588 PROLOGUE_REGS, 589 NON_A_CC_REGS, 590 ALL_REGS, LIM_REG_CLASSES 591 }; 592 593 #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 594 595 #define GENERAL_REGS DPREGS 596 597 /* Give names of register classes as strings for dump file. */ 598 599 #define REG_CLASS_NAMES \ 600 { "NO_REGS", \ 601 "IREGS", \ 602 "BREGS", \ 603 "LREGS", \ 604 "MREGS", \ 605 "CIRCREGS", \ 606 "DAGREGS", \ 607 "EVEN_AREGS", \ 608 "ODD_AREGS", \ 609 "AREGS", \ 610 "CCREGS", \ 611 "EVEN_DREGS", \ 612 "ODD_DREGS", \ 613 "D0REGS", \ 614 "D1REGS", \ 615 "D2REGS", \ 616 "D3REGS", \ 617 "D4REGS", \ 618 "D5REGS", \ 619 "D6REGS", \ 620 "D7REGS", \ 621 "DREGS", \ 622 "P0REGS", \ 623 "FDPIC_REGS", \ 624 "FDPIC_FPTR_REGS", \ 625 "PREGS_CLOBBERED", \ 626 "PREGS", \ 627 "IPREGS", \ 628 "DPREGS", \ 629 "MOST_REGS", \ 630 "LT_REGS", \ 631 "LC_REGS", \ 632 "LB_REGS", \ 633 "PROLOGUE_REGS", \ 634 "NON_A_CC_REGS", \ 635 "ALL_REGS" } 636 637 /* An initializer containing the contents of the register classes, as integers 638 which are bit masks. The Nth integer specifies the contents of class N. 639 The way the integer MASK is interpreted is that register R is in the class 640 if `MASK & (1 << R)' is 1. 641 642 When the machine has more than 32 registers, an integer does not suffice. 643 Then the integers are replaced by sub-initializers, braced groupings 644 containing several integers. Each sub-initializer must be suitable as an 645 initializer for the type `HARD_REG_SET' which is defined in 646 `hard-reg-set.h'. */ 647 648 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 649 MOST_REGS as the union of DPREGS and DAGREGS. */ 650 651 #define REG_CLASS_CONTENTS \ 652 /* 31 - 0 63-32 */ \ 653 { { 0x00000000, 0 }, /* NO_REGS */ \ 654 { 0x000f0000, 0 }, /* IREGS */ \ 655 { 0x00f00000, 0 }, /* BREGS */ \ 656 { 0x0f000000, 0 }, /* LREGS */ \ 657 { 0xf0000000, 0 }, /* MREGS */ \ 658 { 0x0fff0000, 0 }, /* CIRCREGS */ \ 659 { 0xffff0000, 0 }, /* DAGREGS */ \ 660 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 661 { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 662 { 0x00000000, 0x3 }, /* AREGS */ \ 663 { 0x00000000, 0x4 }, /* CCREGS */ \ 664 { 0x00000055, 0 }, /* EVEN_DREGS */ \ 665 { 0x000000aa, 0 }, /* ODD_DREGS */ \ 666 { 0x00000001, 0 }, /* D0REGS */ \ 667 { 0x00000002, 0 }, /* D1REGS */ \ 668 { 0x00000004, 0 }, /* D2REGS */ \ 669 { 0x00000008, 0 }, /* D3REGS */ \ 670 { 0x00000010, 0 }, /* D4REGS */ \ 671 { 0x00000020, 0 }, /* D5REGS */ \ 672 { 0x00000040, 0 }, /* D6REGS */ \ 673 { 0x00000080, 0 }, /* D7REGS */ \ 674 { 0x000000ff, 0 }, /* DREGS */ \ 675 { 0x00000100, 0x000 }, /* P0REGS */ \ 676 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 677 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 678 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 679 { 0x0000ff00, 0x800 }, /* PREGS */ \ 680 { 0x000fff00, 0x800 }, /* IPREGS */ \ 681 { 0x0000ffff, 0x800 }, /* DPREGS */ \ 682 { 0xffffffff, 0x800 }, /* MOST_REGS */\ 683 { 0x00000000, 0x3000 }, /* LT_REGS */\ 684 { 0x00000000, 0xc000 }, /* LC_REGS */\ 685 { 0x00000000, 0x30000 }, /* LB_REGS */\ 686 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 687 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 688 { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 689 690 #define IREG_POSSIBLE_P(OUTER) \ 691 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 692 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 693 || (OUTER) == MEM || (OUTER) == ADDRESS) 694 695 #define MODE_CODE_BASE_REG_CLASS(MODE, OUTER, INDEX) \ 696 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 697 698 #define INDEX_REG_CLASS PREGS 699 700 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 701 (P_REGNO_P (X) || (X) == REG_ARGP \ 702 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 703 && I_REGNO_P (X))) 704 705 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 706 ((X) >= FIRST_PSEUDO_REGISTER \ 707 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 708 709 #ifdef REG_OK_STRICT 710 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 711 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 712 #else 713 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, OUTER, INDEX) \ 714 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 715 #endif 716 717 #define REGNO_OK_FOR_INDEX_P(X) 0 718 719 /* The same information, inverted: 720 Return the class number of the smallest class containing 721 reg number REGNO. This could be a conditional expression 722 or could index an array. */ 723 724 #define REGNO_REG_CLASS(REGNO) \ 725 ((REGNO) == REG_R0 ? D0REGS \ 726 : (REGNO) == REG_R1 ? D1REGS \ 727 : (REGNO) == REG_R2 ? D2REGS \ 728 : (REGNO) == REG_R3 ? D3REGS \ 729 : (REGNO) == REG_R4 ? D4REGS \ 730 : (REGNO) == REG_R5 ? D5REGS \ 731 : (REGNO) == REG_R6 ? D6REGS \ 732 : (REGNO) == REG_R7 ? D7REGS \ 733 : (REGNO) == REG_P0 ? P0REGS \ 734 : (REGNO) < REG_I0 ? PREGS \ 735 : (REGNO) == REG_ARGP ? PREGS \ 736 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 737 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 738 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 739 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 740 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 741 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 742 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 743 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 744 : (REGNO) == REG_CC ? CCREGS \ 745 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 746 : NO_REGS) 747 748 /* The following macro defines cover classes for Integrated Register 749 Allocator. Cover classes is a set of non-intersected register 750 classes covering all hard registers used for register allocation 751 purpose. Any move between two registers of a cover class should be 752 cheaper than load or store of the registers. The macro value is 753 array of register classes with LIM_REG_CLASSES used as the end 754 marker. */ 755 756 #define IRA_COVER_CLASSES \ 757 { \ 758 MOST_REGS, AREGS, CCREGS, LIM_REG_CLASSES \ 759 } 760 761 /* When defined, the compiler allows registers explicitly used in the 762 rtl to be used as spill registers but prevents the compiler from 763 extending the lifetime of these registers. */ 764 #define SMALL_REGISTER_CLASSES 1 765 766 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 767 ((CLASS) == PREGS_CLOBBERED \ 768 || (CLASS) == PROLOGUE_REGS \ 769 || (CLASS) == P0REGS \ 770 || (CLASS) == D0REGS \ 771 || (CLASS) == D1REGS \ 772 || (CLASS) == D2REGS \ 773 || (CLASS) == CCREGS) 774 775 /* Do not allow to store a value in REG_CC for any mode */ 776 /* Do not allow to store value in pregs if mode is not SI*/ 777 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 778 779 /* Return the maximum number of consecutive registers 780 needed to represent mode MODE in a register of class CLASS. */ 781 #define CLASS_MAX_NREGS(CLASS, MODE) \ 782 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 783 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 784 785 #define HARD_REGNO_NREGS(REGNO, MODE) \ 786 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ 787 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ 788 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) 789 790 /* A C expression that is nonzero if hard register TO can be 791 considered for use as a rename register for FROM register */ 792 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 793 794 /* A C expression that is nonzero if it is desirable to choose 795 register allocation so as to avoid move instructions between a 796 value of mode MODE1 and a value of mode MODE2. 797 798 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 799 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 800 MODE2)' must be zero. */ 801 #define MODES_TIEABLE_P(MODE1, MODE2) \ 802 ((MODE1) == (MODE2) \ 803 || ((GET_MODE_CLASS (MODE1) == MODE_INT \ 804 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \ 805 && (GET_MODE_CLASS (MODE2) == MODE_INT \ 806 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \ 807 && (MODE1) != BImode && (MODE2) != BImode \ 808 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 809 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)) 810 811 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 812 A C expression that places additional restrictions on the register 813 class to use when it is necessary to copy value X into a register 814 in class CLASS. The value is a register class; perhaps CLASS, or 815 perhaps another, smaller class. */ 816 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 817 (GET_CODE (X) == POST_INC \ 818 || GET_CODE (X) == POST_DEC \ 819 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) 820 821 /* Function Calling Conventions. */ 822 823 /* The type of the current function; normal functions are of type 824 SUBROUTINE. */ 825 typedef enum { 826 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 827 } e_funkind; 828 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN } 829 830 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 831 832 /* Flags for the call/call_value rtl operations set up by function_arg */ 833 #define CALL_NORMAL 0x00000000 /* no special processing */ 834 #define CALL_LONG 0x00000001 /* always call indirect */ 835 #define CALL_SHORT 0x00000002 /* always call by symbol */ 836 837 typedef struct { 838 int words; /* # words passed so far */ 839 int nregs; /* # registers available for passing */ 840 int *arg_regs; /* array of register -1 terminated */ 841 int call_cookie; /* Do special things for this call */ 842 } CUMULATIVE_ARGS; 843 844 /* Define where to put the arguments to a function. 845 Value is zero to push the argument on the stack, 846 or a hard register in which to store the argument. 847 848 MODE is the argument's machine mode. 849 TYPE is the data type of the argument (as a tree). 850 This is null for libcalls where that information may 851 not be available. 852 CUM is a variable of type CUMULATIVE_ARGS which gives info about 853 the preceding args and about the function being called. 854 NAMED is nonzero if this argument is a named parameter 855 (otherwise it is an extra parameter matching an ellipsis). */ 856 857 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 858 (function_arg (&CUM, MODE, TYPE, NAMED)) 859 860 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 861 862 863 /* Initialize a variable CUM of type CUMULATIVE_ARGS 864 for a call to a function whose data type is FNTYPE. 865 For a library call, FNTYPE is 0. */ 866 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 867 (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 868 869 /* Update the data in CUM to advance over an argument 870 of mode MODE and data type TYPE. 871 (TYPE is null for libcalls where that information may not be available.) */ 872 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 873 (function_arg_advance (&CUM, MODE, TYPE, NAMED)) 874 875 #define RETURN_POPS_ARGS(FDECL, FUNTYPE, STKSIZE) 0 876 877 /* Define how to find the value returned by a function. 878 VALTYPE is the data type of the value (as a tree). 879 If the precise function being called is known, FUNC is its FUNCTION_DECL; 880 otherwise, FUNC is 0. 881 */ 882 883 #define VALUE_REGNO(MODE) (REG_R0) 884 885 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 886 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 887 VALUE_REGNO(TYPE_MODE(VALTYPE))) 888 889 /* Define how to find the value returned by a library function 890 assuming the value has mode MODE. */ 891 892 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 893 894 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 895 896 #define DEFAULT_PCC_STRUCT_RETURN 0 897 898 /* Before the prologue, the return address is in the RETS register. */ 899 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 900 901 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 902 903 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 904 905 /* Call instructions don't modify the stack pointer on the Blackfin. */ 906 #define INCOMING_FRAME_SP_OFFSET 0 907 908 /* Describe how we implement __builtin_eh_return. */ 909 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 910 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 911 #define EH_RETURN_HANDLER_RTX \ 912 gen_frame_mem (Pmode, plus_constant (frame_pointer_rtx, UNITS_PER_WORD)) 913 914 /* Addressing Modes */ 915 916 /* Nonzero if the constant value X is a legitimate general operand. 917 symbol_ref are not legitimate and will be put into constant pool. 918 See force_const_mem(). 919 If -mno-pool, all constants are legitimate. 920 */ 921 #define LEGITIMATE_CONSTANT_P(X) bfin_legitimate_constant_p (X) 922 923 /* A number, the maximum number of registers that can appear in a 924 valid memory address. Note that it is up to you to specify a 925 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' 926 would ever accept. */ 927 #define MAX_REGS_PER_ADDRESS 1 928 929 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 930 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 931 932 #define HAVE_POST_INCREMENT 1 933 #define HAVE_POST_DECREMENT 1 934 #define HAVE_PRE_DECREMENT 1 935 936 /* `LEGITIMATE_PIC_OPERAND_P (X)' 937 A C expression that is nonzero if X is a legitimate immediate 938 operand on the target machine when generating position independent 939 code. You can assume that X satisfies `CONSTANT_P', so you need 940 not check this. You can also assume FLAG_PIC is true, so you need 941 not check it either. You need not define this macro if all 942 constants (including `SYMBOL_REF') can be immediate operands when 943 generating position independent code. */ 944 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 945 946 #define SYMBOLIC_CONST(X) \ 947 (GET_CODE (X) == SYMBOL_REF \ 948 || GET_CODE (X) == LABEL_REF \ 949 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 950 951 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 952 953 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 954 is done just by pretending it is already truncated. */ 955 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 956 957 /* Max number of bytes we can move from memory to memory 958 in one reasonably fast instruction. */ 959 #define MOVE_MAX UNITS_PER_WORD 960 961 /* If a memory-to-memory move would take MOVE_RATIO or more simple 962 move-instruction pairs, we will do a movmem or libcall instead. */ 963 964 #define MOVE_RATIO(speed) 5 965 966 /* STORAGE LAYOUT: target machine storage layout 967 Define this macro as a C expression which is nonzero if accessing 968 less than a word of memory (i.e. a `char' or a `short') is no 969 faster than accessing a word of memory, i.e., if such access 970 require more than one instruction or if there is no difference in 971 cost between byte and (aligned) word loads. 972 973 When this macro is not defined, the compiler will access a field by 974 finding the smallest containing object; when it is defined, a 975 fullword load will be used if alignment permits. Unless bytes 976 accesses are faster than word accesses, using word accesses is 977 preferable since it may eliminate subsequent memory access if 978 subsequent accesses occur to other fields in the same word of the 979 structure, but to different bytes. */ 980 #define SLOW_BYTE_ACCESS 0 981 #define SLOW_SHORT_ACCESS 0 982 983 /* Define this if most significant bit is lowest numbered 984 in instructions that operate on numbered bit-fields. */ 985 #define BITS_BIG_ENDIAN 0 986 987 /* Define this if most significant byte of a word is the lowest numbered. 988 We can't access bytes but if we could we would in the Big Endian order. */ 989 #define BYTES_BIG_ENDIAN 0 990 991 /* Define this if most significant word of a multiword number is numbered. */ 992 #define WORDS_BIG_ENDIAN 0 993 994 /* number of bits in an addressable storage unit */ 995 #define BITS_PER_UNIT 8 996 997 /* Width in bits of a "word", which is the contents of a machine register. 998 Note that this is not necessarily the width of data type `int'; 999 if using 16-bit ints on a 68000, this would still be 32. 1000 But on a machine with 16-bit registers, this would be 16. */ 1001 #define BITS_PER_WORD 32 1002 1003 /* Width of a word, in units (bytes). */ 1004 #define UNITS_PER_WORD 4 1005 1006 /* Width in bits of a pointer. 1007 See also the macro `Pmode1' defined below. */ 1008 #define POINTER_SIZE 32 1009 1010 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 1011 #define POINTER_BOUNDARY 32 1012 1013 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 1014 #define PARM_BOUNDARY 32 1015 1016 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 1017 #define STACK_BOUNDARY 32 1018 1019 /* Allocation boundary (in *bits*) for the code of a function. */ 1020 #define FUNCTION_BOUNDARY 32 1021 1022 /* Alignment of field after `int : 0' in a structure. */ 1023 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 1024 1025 /* No data type wants to be aligned rounder than this. */ 1026 #define BIGGEST_ALIGNMENT 32 1027 1028 /* Define this if move instructions will actually fail to work 1029 when given unaligned data. */ 1030 #define STRICT_ALIGNMENT 1 1031 1032 /* (shell-command "rm c-decl.o stor-layout.o") 1033 * never define PCC_BITFIELD_TYPE_MATTERS 1034 * really cause some alignment problem 1035 */ 1036 1037 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 1038 BITS_PER_UNIT) 1039 1040 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 1041 BITS_PER_UNIT) 1042 1043 1044 /* what is the 'type' of size_t */ 1045 #define SIZE_TYPE "long unsigned int" 1046 1047 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1048 #define DEFAULT_SIGNED_CHAR 1 1049 #define FLOAT_TYPE_SIZE BITS_PER_WORD 1050 #define SHORT_TYPE_SIZE 16 1051 #define CHAR_TYPE_SIZE 8 1052 #define INT_TYPE_SIZE 32 1053 #define LONG_TYPE_SIZE 32 1054 #define LONG_LONG_TYPE_SIZE 64 1055 1056 /* Note: Fix this to depend on target switch. -- lev */ 1057 1058 /* Note: Try to implement double and force long double. -- tonyko 1059 * #define __DOUBLES_ARE_FLOATS__ 1060 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 1061 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 1062 * #define DOUBLES_ARE_FLOATS 1 1063 */ 1064 1065 #define DOUBLE_TYPE_SIZE 64 1066 #define LONG_DOUBLE_TYPE_SIZE 64 1067 1068 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 1069 A macro to update M and UNSIGNEDP when an object whose type is 1070 TYPE and which has the specified mode and signedness is to be 1071 stored in a register. This macro is only called when TYPE is a 1072 scalar type. 1073 1074 On most RISC machines, which only have operations that operate on 1075 a full register, define this macro to set M to `word_mode' if M is 1076 an integer mode narrower than `BITS_PER_WORD'. In most cases, 1077 only integer modes should be widened because wider-precision 1078 floating-point operations are usually more expensive than their 1079 narrower counterparts. 1080 1081 For most machines, the macro definition does not change UNSIGNEDP. 1082 However, some machines, have instructions that preferentially 1083 handle either signed or unsigned quantities of certain modes. For 1084 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 1085 instructions sign-extend the result to 64 bits. On such machines, 1086 set UNSIGNEDP according to which kind of extension is more 1087 efficient. 1088 1089 Do not define this macro if it would never modify M.*/ 1090 1091 #define BFIN_PROMOTE_MODE_P(MODE) \ 1092 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 1093 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 1094 1095 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1096 if (BFIN_PROMOTE_MODE_P(MODE)) \ 1097 { \ 1098 if (MODE == QImode) \ 1099 UNSIGNEDP = 1; \ 1100 else if (MODE == HImode) \ 1101 UNSIGNEDP = 0; \ 1102 (MODE) = SImode; \ 1103 } 1104 1105 /* Describing Relative Costs of Operations */ 1106 1107 /* Do not put function addr into constant pool */ 1108 #define NO_FUNCTION_CSE 1 1109 1110 /* A C expression for the cost of moving data from a register in class FROM to 1111 one in class TO. The classes are expressed using the enumeration values 1112 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1113 interpreted relative to that. 1114 1115 It is not required that the cost always equal 2 when FROM is the same as TO; 1116 on some machines it is expensive to move between registers if they are not 1117 general registers. */ 1118 1119 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1120 bfin_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1121 1122 /* A C expression for the cost of moving data of mode M between a 1123 register and memory. A value of 2 is the default; this cost is 1124 relative to those in `REGISTER_MOVE_COST'. 1125 1126 If moving between registers and memory is more expensive than 1127 between two registers, you should define this macro to express the 1128 relative cost. */ 1129 1130 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1131 bfin_memory_move_cost ((MODE), (CLASS), (IN)) 1132 1133 /* Specify the machine mode that this machine uses 1134 for the index in the tablejump instruction. */ 1135 #define CASE_VECTOR_MODE SImode 1136 1137 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 1138 1139 /* Define if operations between registers always perform the operation 1140 on the full register even if a narrower mode is specified. 1141 #define WORD_REGISTER_OPERATIONS 1142 */ 1143 1144 /* Evaluates to true if A and B are mac flags that can be used 1145 together in a single multiply insn. That is the case if they are 1146 both the same flag not involving M, or if one is a combination of 1147 the other with M. */ 1148 #define MACFLAGS_MATCH_P(A, B) \ 1149 ((A) == (B) \ 1150 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ 1151 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ 1152 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ 1153 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) 1154 1155 /* Switch into a generic section. */ 1156 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 1157 1158 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 1159 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 1160 1161 typedef enum sections { 1162 CODE_DIR, 1163 DATA_DIR, 1164 LAST_SECT_NM 1165 } SECT_ENUM_T; 1166 1167 typedef enum directives { 1168 LONG_CONST_DIR, 1169 SHORT_CONST_DIR, 1170 BYTE_CONST_DIR, 1171 SPACE_DIR, 1172 INIT_DIR, 1173 LAST_DIR_NM 1174 } DIR_ENUM_T; 1175 1176 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ 1177 ((C) == ';' \ 1178 || ((C) == '|' && (STR)[1] == '|')) 1179 1180 #define TEXT_SECTION_ASM_OP ".text;" 1181 #define DATA_SECTION_ASM_OP ".data;" 1182 1183 #define ASM_APP_ON "" 1184 #define ASM_APP_OFF "" 1185 1186 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 1187 do { fputs (".global ", FILE); \ 1188 assemble_name (FILE, NAME); \ 1189 fputc (';',FILE); \ 1190 fputc ('\n',FILE); \ 1191 } while (0) 1192 1193 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1194 do { \ 1195 fputs (".type ", FILE); \ 1196 assemble_name (FILE, NAME); \ 1197 fputs (", STT_FUNC", FILE); \ 1198 fputc (';',FILE); \ 1199 fputc ('\n',FILE); \ 1200 ASM_OUTPUT_LABEL(FILE, NAME); \ 1201 } while (0) 1202 1203 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1204 do { assemble_name (FILE, NAME); \ 1205 fputs (":\n",FILE); \ 1206 } while (0) 1207 1208 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1209 do { fprintf (FILE, "_%s", NAME); \ 1210 } while (0) 1211 1212 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1213 do { char __buf[256]; \ 1214 fprintf (FILE, "\t.dd\t"); \ 1215 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1216 assemble_name (FILE, __buf); \ 1217 fputc (';', FILE); \ 1218 fputc ('\n', FILE); \ 1219 } while (0) 1220 1221 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1222 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1223 1224 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1225 do { \ 1226 char __buf[256]; \ 1227 fprintf (FILE, "\t.dd\t"); \ 1228 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1229 assemble_name (FILE, __buf); \ 1230 fputs (" - ", FILE); \ 1231 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1232 assemble_name (FILE, __buf); \ 1233 fputc (';', FILE); \ 1234 fputc ('\n', FILE); \ 1235 } while (0) 1236 1237 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1238 do { \ 1239 if ((LOG) != 0) \ 1240 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1241 } while (0) 1242 1243 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1244 do { \ 1245 asm_output_skip (FILE, SIZE); \ 1246 } while (0) 1247 1248 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1249 do { \ 1250 switch_to_section (data_section); \ 1251 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1252 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1253 ASM_OUTPUT_LABEL (FILE, NAME); \ 1254 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1255 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1256 } while (0) 1257 1258 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1259 do { \ 1260 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1261 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1262 1263 #define ASM_COMMENT_START "//" 1264 1265 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1266 do { \ 1267 fprintf (FILE, "\tCALL __mcount;\n"); \ 1268 } while(0) 1269 1270 #undef NO_PROFILE_COUNTERS 1271 #define NO_PROFILE_COUNTERS 1 1272 1273 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "[SP--] = %s;\n", reg_names[REGNO]) 1274 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "%s = [SP++];\n", reg_names[REGNO]) 1275 1276 extern struct rtx_def *bfin_cc_rtx, *bfin_rets_rtx; 1277 1278 /* This works for GAS and some other assemblers. */ 1279 #define SET_ASM_OP ".set " 1280 1281 /* DBX register number for a given compiler register number */ 1282 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1283 1284 #define SIZE_ASM_OP "\t.size\t" 1285 1286 extern int splitting_for_sched, splitting_loops; 1287 1288 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') 1289 1290 #ifndef TARGET_SUPPORTS_SYNC_CALLS 1291 #define TARGET_SUPPORTS_SYNC_CALLS 0 1292 #endif 1293 1294 #endif /* _BFIN_CONFIG */ 1295
Indexes created Sun Apr 19 00:22:55 UTC 2026