bfin.h revision 1.10
1 /* Definitions for the Blackfin port. 2 Copyright (C) 2005-2019 Free Software Foundation, Inc. 3 Contributed by Analog Devices. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _BFIN_CONFIG 22 #define _BFIN_CONFIG 23 24 #ifndef BFIN_OPTS_H 25 #include "config/bfin/bfin-opts.h" 26 #endif 27 28 #define OBJECT_FORMAT_ELF 29 30 #define BRT 1 31 #define BRF 0 32 33 /* Predefinition in the preprocessor for this target machine */ 34 #ifndef TARGET_CPU_CPP_BUILTINS 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do \ 37 { \ 38 builtin_define_std ("bfin"); \ 39 builtin_define_std ("BFIN"); \ 40 builtin_define ("__ADSPBLACKFIN__"); \ 41 builtin_define ("__ADSPLPBLACKFIN__"); \ 42 \ 43 switch (bfin_cpu_type) \ 44 { \ 45 case BFIN_CPU_UNKNOWN: \ 46 break; \ 47 case BFIN_CPU_BF512: \ 48 builtin_define ("__ADSPBF512__"); \ 49 builtin_define ("__ADSPBF51x__"); \ 50 break; \ 51 case BFIN_CPU_BF514: \ 52 builtin_define ("__ADSPBF514__"); \ 53 builtin_define ("__ADSPBF51x__"); \ 54 break; \ 55 case BFIN_CPU_BF516: \ 56 builtin_define ("__ADSPBF516__"); \ 57 builtin_define ("__ADSPBF51x__"); \ 58 break; \ 59 case BFIN_CPU_BF518: \ 60 builtin_define ("__ADSPBF518__"); \ 61 builtin_define ("__ADSPBF51x__"); \ 62 break; \ 63 case BFIN_CPU_BF522: \ 64 builtin_define ("__ADSPBF522__"); \ 65 builtin_define ("__ADSPBF52x__"); \ 66 break; \ 67 case BFIN_CPU_BF523: \ 68 builtin_define ("__ADSPBF523__"); \ 69 builtin_define ("__ADSPBF52x__"); \ 70 break; \ 71 case BFIN_CPU_BF524: \ 72 builtin_define ("__ADSPBF524__"); \ 73 builtin_define ("__ADSPBF52x__"); \ 74 break; \ 75 case BFIN_CPU_BF525: \ 76 builtin_define ("__ADSPBF525__"); \ 77 builtin_define ("__ADSPBF52x__"); \ 78 break; \ 79 case BFIN_CPU_BF526: \ 80 builtin_define ("__ADSPBF526__"); \ 81 builtin_define ("__ADSPBF52x__"); \ 82 break; \ 83 case BFIN_CPU_BF527: \ 84 builtin_define ("__ADSPBF527__"); \ 85 builtin_define ("__ADSPBF52x__"); \ 86 break; \ 87 case BFIN_CPU_BF531: \ 88 builtin_define ("__ADSPBF531__"); \ 89 break; \ 90 case BFIN_CPU_BF532: \ 91 builtin_define ("__ADSPBF532__"); \ 92 break; \ 93 case BFIN_CPU_BF533: \ 94 builtin_define ("__ADSPBF533__"); \ 95 break; \ 96 case BFIN_CPU_BF534: \ 97 builtin_define ("__ADSPBF534__"); \ 98 break; \ 99 case BFIN_CPU_BF536: \ 100 builtin_define ("__ADSPBF536__"); \ 101 break; \ 102 case BFIN_CPU_BF537: \ 103 builtin_define ("__ADSPBF537__"); \ 104 break; \ 105 case BFIN_CPU_BF538: \ 106 builtin_define ("__ADSPBF538__"); \ 107 break; \ 108 case BFIN_CPU_BF539: \ 109 builtin_define ("__ADSPBF539__"); \ 110 break; \ 111 case BFIN_CPU_BF542M: \ 112 builtin_define ("__ADSPBF542M__"); \ 113 /* FALLTHRU */ \ 114 case BFIN_CPU_BF542: \ 115 builtin_define ("__ADSPBF542__"); \ 116 builtin_define ("__ADSPBF54x__"); \ 117 break; \ 118 case BFIN_CPU_BF544M: \ 119 builtin_define ("__ADSPBF544M__"); \ 120 /* FALLTHRU */ \ 121 case BFIN_CPU_BF544: \ 122 builtin_define ("__ADSPBF544__"); \ 123 builtin_define ("__ADSPBF54x__"); \ 124 break; \ 125 case BFIN_CPU_BF547M: \ 126 builtin_define ("__ADSPBF547M__"); \ 127 /* FALLTHRU */ \ 128 case BFIN_CPU_BF547: \ 129 builtin_define ("__ADSPBF547__"); \ 130 builtin_define ("__ADSPBF54x__"); \ 131 break; \ 132 case BFIN_CPU_BF548M: \ 133 builtin_define ("__ADSPBF548M__"); \ 134 /* FALLTHRU */ \ 135 case BFIN_CPU_BF548: \ 136 builtin_define ("__ADSPBF548__"); \ 137 builtin_define ("__ADSPBF54x__"); \ 138 break; \ 139 case BFIN_CPU_BF549M: \ 140 builtin_define ("__ADSPBF549M__"); \ 141 /* FALLTHRU */ \ 142 case BFIN_CPU_BF549: \ 143 builtin_define ("__ADSPBF549__"); \ 144 builtin_define ("__ADSPBF54x__"); \ 145 break; \ 146 case BFIN_CPU_BF561: \ 147 builtin_define ("__ADSPBF561__"); \ 148 break; \ 149 case BFIN_CPU_BF592: \ 150 builtin_define ("__ADSPBF592__"); \ 151 builtin_define ("__ADSPBF59x__"); \ 152 break; \ 153 } \ 154 \ 155 if (bfin_si_revision != -1) \ 156 { \ 157 /* space of 0xnnnn and a NUL */ \ 158 char *buf = XALLOCAVEC (char, 7); \ 159 \ 160 sprintf (buf, "0x%04x", bfin_si_revision); \ 161 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ 162 } \ 163 \ 164 if (bfin_workarounds) \ 165 builtin_define ("__WORKAROUNDS_ENABLED"); \ 166 if (ENABLE_WA_SPECULATIVE_LOADS) \ 167 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ 168 if (ENABLE_WA_SPECULATIVE_SYNCS) \ 169 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ 170 if (ENABLE_WA_INDIRECT_CALLS) \ 171 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \ 172 if (ENABLE_WA_RETS) \ 173 builtin_define ("__WORKAROUND_RETS"); \ 174 \ 175 if (TARGET_FDPIC) \ 176 { \ 177 builtin_define ("__BFIN_FDPIC__"); \ 178 builtin_define ("__FDPIC__"); \ 179 } \ 180 if (TARGET_ID_SHARED_LIBRARY \ 181 && !TARGET_SEP_DATA) \ 182 builtin_define ("__ID_SHARED_LIB__"); \ 183 if (flag_no_builtin) \ 184 builtin_define ("__NO_BUILTIN"); \ 185 if (TARGET_MULTICORE) \ 186 builtin_define ("__BFIN_MULTICORE"); \ 187 if (TARGET_COREA) \ 188 builtin_define ("__BFIN_COREA"); \ 189 if (TARGET_COREB) \ 190 builtin_define ("__BFIN_COREB"); \ 191 if (TARGET_SDRAM) \ 192 builtin_define ("__BFIN_SDRAM"); \ 193 } \ 194 while (0) 195 #endif 196 197 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 198 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ 199 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 200 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 201 " 202 #ifndef SUBTARGET_DRIVER_SELF_SPECS 203 # define SUBTARGET_DRIVER_SELF_SPECS 204 #endif 205 206 #define LINK_GCC_C_SEQUENCE_SPEC "\ 207 %{mfast-fp:-lbffastfp} %G %{!nolibc:%L} %{mfast-fp:-lbffastfp} %G \ 208 " 209 210 #undef ASM_SPEC 211 #define ASM_SPEC "\ 212 %{mno-fdpic:-mnopic} %{mfdpic}" 213 214 #define LINK_SPEC "\ 215 %{h*} %{v:-V} \ 216 %{mfdpic:-melf32bfinfd -z text} \ 217 %{static:-dn -Bstatic} \ 218 %{shared:-G -Bdynamic} \ 219 %{symbolic:-Bsymbolic} \ 220 -init __init -fini __fini " 221 222 /* Generate DSP instructions, like DSP halfword loads */ 223 #define TARGET_DSP (1) 224 225 #define TARGET_DEFAULT 0 226 227 /* Maximum number of library ids we permit */ 228 #define MAX_LIBRARY_ID 255 229 230 extern const char *bfin_library_id_string; 231 232 #define FUNCTION_MODE SImode 233 #define Pmode SImode 234 235 /* store-condition-codes instructions store 0 for false 236 This is the value stored for true. */ 237 #define STORE_FLAG_VALUE 1 238 239 /* Define this if pushing a word on the stack 240 makes the stack pointer a smaller address. */ 241 #define STACK_GROWS_DOWNWARD 1 242 243 #define STACK_PUSH_CODE PRE_DEC 244 245 /* Define this to nonzero if the nominal address of the stack frame 246 is at the high-address end of the local variables; 247 that is, each additional local variable allocated 248 goes at a more negative offset in the frame. */ 249 #define FRAME_GROWS_DOWNWARD 1 250 251 /* We define a dummy ARGP register; the parameters start at offset 0 from 252 it. */ 253 #define FIRST_PARM_OFFSET(DECL) 0 254 255 /* Register to use for pushing function arguments. */ 256 #define STACK_POINTER_REGNUM REG_P6 257 258 /* Base register for access to local variables of the function. */ 259 #define FRAME_POINTER_REGNUM REG_P7 260 261 /* A dummy register that will be eliminated to either FP or SP. */ 262 #define ARG_POINTER_REGNUM REG_ARGP 263 264 /* `PIC_OFFSET_TABLE_REGNUM' 265 The register number of the register used to address a table of 266 static data addresses in memory. In some cases this register is 267 defined by a processor's "application binary interface" (ABI). 268 When this macro is defined, RTL is generated for this register 269 once, as with the stack pointer and frame pointer registers. If 270 this macro is not defined, it is up to the machine-dependent files 271 to allocate such a register (if necessary). */ 272 #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 273 274 #define FDPIC_FPTR_REGNO REG_P1 275 #define FDPIC_REGNO REG_P3 276 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 277 278 /* A static chain register for nested functions. We need to use a 279 call-clobbered register for this. */ 280 #define STATIC_CHAIN_REGNUM REG_P2 281 282 /* Define this if functions should assume that stack space has been 283 allocated for arguments even when their values are passed in 284 registers. 285 286 The value of this macro is the size, in bytes, of the area reserved for 287 arguments passed in registers. 288 289 This space can either be allocated by the caller or be a part of the 290 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 291 says which. */ 292 #define FIXED_STACK_AREA 12 293 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 294 295 /* Define this if the above stack space is to be considered part of the 296 * space allocated by the caller. */ 297 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 298 299 /* Define this if the maximum size of all the outgoing args is to be 300 accumulated and pushed during the prologue. The amount can be 301 found in the variable crtl->outgoing_args_size. */ 302 #define ACCUMULATE_OUTGOING_ARGS 1 303 304 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 305 306 /* If defined, a C expression to compute the alignment for a local 307 variable. TYPE is the data type, and ALIGN is the alignment that 308 the object would ordinarily have. The value of this macro is used 309 instead of that alignment to align the object. 310 311 If this macro is not defined, then ALIGN is used. 312 313 One use of this macro is to increase alignment of medium-size 314 data to make it all fit in fewer cache lines. */ 315 316 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) 317 318 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 319 320 /* Definitions for register eliminations. 322 323 This is an array of structures. Each structure initializes one pair 324 of eliminable registers. The "from" register number is given first, 325 followed by "to". Eliminations of the same "from" register are listed 326 in order of preference. 327 328 There are two registers that can always be eliminated on the i386. 329 The frame pointer and the arg pointer can be replaced by either the 330 hard frame pointer or to the stack pointer, depending upon the 331 circumstances. The hard frame pointer is not used before reload and 332 so it is not eligible for elimination. */ 333 334 #define ELIMINABLE_REGS \ 335 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 336 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 337 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 338 339 /* Define the offset between two registers, one to be eliminated, and the other 340 its replacement, at the start of a routine. */ 341 342 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 343 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 344 345 /* This processor has 347 8 data register for doing arithmetic 348 8 pointer register for doing addressing, including 349 1 stack pointer P6 350 1 frame pointer P7 351 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 352 1 condition code flag register CC 353 5 return address registers RETS/I/X/N/E 354 1 arithmetic status register (ASTAT). */ 355 356 #define FIRST_PSEUDO_REGISTER 50 357 358 #define D_REGNO_P(X) ((X) <= REG_R7) 359 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 360 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 361 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 362 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 363 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 364 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 365 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 366 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 367 368 #define REGISTER_NAMES { \ 369 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 370 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 371 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 372 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 373 "A0", "A1", \ 374 "CC", \ 375 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 376 "ARGP", \ 377 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 378 } 379 380 #define SHORT_REGISTER_NAMES { \ 381 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 382 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 383 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 384 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 385 386 #define HIGH_REGISTER_NAMES { \ 387 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 388 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 389 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 390 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 391 392 #define DREGS_PAIR_NAMES { \ 393 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 394 395 #define BYTE_REGISTER_NAMES { \ 396 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 397 398 399 /* 1 for registers that have pervasive standard uses 400 and are not available for the register allocator. */ 401 402 #define FIXED_REGISTERS \ 403 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 404 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 405 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 406 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 407 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 408 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 409 /*lb0/1 */ \ 410 1, 1 \ 411 } 412 413 /* 1 for registers not available across function calls. 414 These must include the FIXED_REGISTERS and also any 415 registers that can be used without being saved. 416 The latter must include the registers where values are returned 417 and the register where structure-value addresses are passed. 418 Aside from that, you can include as many other registers as you like. */ 419 420 #define CALL_USED_REGISTERS \ 421 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 422 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 423 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 424 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 425 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 426 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 427 /*lb0/1 */ \ 428 1, 1 \ 429 } 430 431 /* Order in which to allocate registers. Each register must be 432 listed once, even those in FIXED_REGISTERS. List frame pointer 433 late and fixed registers last. Note that, in general, we prefer 434 registers listed in CALL_USED_REGISTERS, keeping the others 435 available for storage of persistent values. */ 436 437 #define REG_ALLOC_ORDER \ 438 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 439 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 440 REG_A0, REG_A1, \ 441 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 442 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 443 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 444 REG_ASTAT, REG_SEQSTAT, REG_USP, \ 445 REG_CC, REG_ARGP, \ 446 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 447 } 448 449 /* Define the classes of registers for register constraints in the 450 machine description. Also define ranges of constants. 451 452 One of the classes must always be named ALL_REGS and include all hard regs. 453 If there is more than one class, another class must be named NO_REGS 454 and contain no registers. 455 456 The name GENERAL_REGS must be the name of a class (or an alias for 457 another name such as ALL_REGS). This is the class of registers 458 that is allowed by "g" or "r" in a register constraint. 459 Also, registers outside this class are allocated only when 460 instructions express preferences for them. 461 462 The classes must be numbered in nondecreasing order; that is, 463 a larger-numbered class must never be contained completely 464 in a smaller-numbered class. 465 466 For any two classes, it is very desirable that there be another 467 class that represents their union. */ 468 469 470 enum reg_class 471 { 472 NO_REGS, 473 IREGS, 474 BREGS, 475 LREGS, 476 MREGS, 477 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 478 DAGREGS, 479 EVEN_AREGS, 480 ODD_AREGS, 481 AREGS, 482 CCREGS, 483 EVEN_DREGS, 484 ODD_DREGS, 485 D0REGS, 486 D1REGS, 487 D2REGS, 488 D3REGS, 489 D4REGS, 490 D5REGS, 491 D6REGS, 492 D7REGS, 493 DREGS, 494 P0REGS, 495 FDPIC_REGS, 496 FDPIC_FPTR_REGS, 497 PREGS_CLOBBERED, 498 PREGS, 499 IPREGS, 500 DPREGS, 501 MOST_REGS, 502 LT_REGS, 503 LC_REGS, 504 LB_REGS, 505 PROLOGUE_REGS, 506 NON_A_CC_REGS, 507 ALL_REGS, LIM_REG_CLASSES 508 }; 509 510 #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 511 512 #define GENERAL_REGS DPREGS 513 514 /* Give names of register classes as strings for dump file. */ 515 516 #define REG_CLASS_NAMES \ 517 { "NO_REGS", \ 518 "IREGS", \ 519 "BREGS", \ 520 "LREGS", \ 521 "MREGS", \ 522 "CIRCREGS", \ 523 "DAGREGS", \ 524 "EVEN_AREGS", \ 525 "ODD_AREGS", \ 526 "AREGS", \ 527 "CCREGS", \ 528 "EVEN_DREGS", \ 529 "ODD_DREGS", \ 530 "D0REGS", \ 531 "D1REGS", \ 532 "D2REGS", \ 533 "D3REGS", \ 534 "D4REGS", \ 535 "D5REGS", \ 536 "D6REGS", \ 537 "D7REGS", \ 538 "DREGS", \ 539 "P0REGS", \ 540 "FDPIC_REGS", \ 541 "FDPIC_FPTR_REGS", \ 542 "PREGS_CLOBBERED", \ 543 "PREGS", \ 544 "IPREGS", \ 545 "DPREGS", \ 546 "MOST_REGS", \ 547 "LT_REGS", \ 548 "LC_REGS", \ 549 "LB_REGS", \ 550 "PROLOGUE_REGS", \ 551 "NON_A_CC_REGS", \ 552 "ALL_REGS" } 553 554 /* An initializer containing the contents of the register classes, as integers 555 which are bit masks. The Nth integer specifies the contents of class N. 556 The way the integer MASK is interpreted is that register R is in the class 557 if `MASK & (1 << R)' is 1. 558 559 When the machine has more than 32 registers, an integer does not suffice. 560 Then the integers are replaced by sub-initializers, braced groupings 561 containing several integers. Each sub-initializer must be suitable as an 562 initializer for the type `HARD_REG_SET' which is defined in 563 `hard-reg-set.h'. */ 564 565 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 566 MOST_REGS as the union of DPREGS and DAGREGS. */ 567 568 #define REG_CLASS_CONTENTS \ 569 /* 31 - 0 63-32 */ \ 570 { { 0x00000000, 0 }, /* NO_REGS */ \ 571 { 0x000f0000, 0 }, /* IREGS */ \ 572 { 0x00f00000, 0 }, /* BREGS */ \ 573 { 0x0f000000, 0 }, /* LREGS */ \ 574 { 0xf0000000, 0 }, /* MREGS */ \ 575 { 0x0fff0000, 0 }, /* CIRCREGS */ \ 576 { 0xffff0000, 0 }, /* DAGREGS */ \ 577 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 578 { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 579 { 0x00000000, 0x3 }, /* AREGS */ \ 580 { 0x00000000, 0x4 }, /* CCREGS */ \ 581 { 0x00000055, 0 }, /* EVEN_DREGS */ \ 582 { 0x000000aa, 0 }, /* ODD_DREGS */ \ 583 { 0x00000001, 0 }, /* D0REGS */ \ 584 { 0x00000002, 0 }, /* D1REGS */ \ 585 { 0x00000004, 0 }, /* D2REGS */ \ 586 { 0x00000008, 0 }, /* D3REGS */ \ 587 { 0x00000010, 0 }, /* D4REGS */ \ 588 { 0x00000020, 0 }, /* D5REGS */ \ 589 { 0x00000040, 0 }, /* D6REGS */ \ 590 { 0x00000080, 0 }, /* D7REGS */ \ 591 { 0x000000ff, 0 }, /* DREGS */ \ 592 { 0x00000100, 0x000 }, /* P0REGS */ \ 593 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 594 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 595 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 596 { 0x0000ff00, 0x800 }, /* PREGS */ \ 597 { 0x000fff00, 0x800 }, /* IPREGS */ \ 598 { 0x0000ffff, 0x800 }, /* DPREGS */ \ 599 { 0xffffffff, 0x800 }, /* MOST_REGS */\ 600 { 0x00000000, 0x3000 }, /* LT_REGS */\ 601 { 0x00000000, 0xc000 }, /* LC_REGS */\ 602 { 0x00000000, 0x30000 }, /* LB_REGS */\ 603 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 604 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 605 { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 606 607 #define IREG_POSSIBLE_P(OUTER) \ 608 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 609 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 610 || (OUTER) == MEM || (OUTER) == ADDRESS) 611 612 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ 613 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 614 615 #define INDEX_REG_CLASS PREGS 616 617 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 618 (P_REGNO_P (X) || (X) == REG_ARGP \ 619 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 620 && I_REGNO_P (X))) 621 622 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 623 ((X) >= FIRST_PSEUDO_REGISTER \ 624 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 625 626 #ifdef REG_OK_STRICT 627 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 628 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 629 #else 630 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 631 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 632 #endif 633 634 #define REGNO_OK_FOR_INDEX_P(X) 0 635 636 /* The same information, inverted: 637 Return the class number of the smallest class containing 638 reg number REGNO. This could be a conditional expression 639 or could index an array. */ 640 641 #define REGNO_REG_CLASS(REGNO) \ 642 ((REGNO) == REG_R0 ? D0REGS \ 643 : (REGNO) == REG_R1 ? D1REGS \ 644 : (REGNO) == REG_R2 ? D2REGS \ 645 : (REGNO) == REG_R3 ? D3REGS \ 646 : (REGNO) == REG_R4 ? D4REGS \ 647 : (REGNO) == REG_R5 ? D5REGS \ 648 : (REGNO) == REG_R6 ? D6REGS \ 649 : (REGNO) == REG_R7 ? D7REGS \ 650 : (REGNO) == REG_P0 ? P0REGS \ 651 : (REGNO) < REG_I0 ? PREGS \ 652 : (REGNO) == REG_ARGP ? PREGS \ 653 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 654 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 655 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 656 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 657 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 658 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 659 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 660 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 661 : (REGNO) == REG_CC ? CCREGS \ 662 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 663 : NO_REGS) 664 665 /* When this hook returns true for MODE, the compiler allows 666 registers explicitly used in the rtl to be used as spill registers 667 but prevents the compiler from extending the lifetime of these 668 registers. */ 669 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 670 671 /* Return the maximum number of consecutive registers 672 needed to represent mode MODE in a register of class CLASS. */ 673 #define CLASS_MAX_NREGS(CLASS, MODE) \ 674 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 675 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 676 677 /* A C expression that is nonzero if hard register TO can be 678 considered for use as a rename register for FROM register */ 679 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 680 681 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 682 A C expression that places additional restrictions on the register 683 class to use when it is necessary to copy value X into a register 684 in class CLASS. The value is a register class; perhaps CLASS, or 685 perhaps another, smaller class. */ 686 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 687 (GET_CODE (X) == POST_INC \ 688 || GET_CODE (X) == POST_DEC \ 689 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) 690 691 /* Function Calling Conventions. */ 692 693 /* The type of the current function; normal functions are of type 694 SUBROUTINE. */ 695 typedef enum { 696 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 697 } e_funkind; 698 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN } 699 700 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 701 702 /* Flags for the call/call_value rtl operations set up by function_arg */ 703 #define CALL_NORMAL 0x00000000 /* no special processing */ 704 #define CALL_LONG 0x00000001 /* always call indirect */ 705 #define CALL_SHORT 0x00000002 /* always call by symbol */ 706 707 typedef struct { 708 int words; /* # words passed so far */ 709 int nregs; /* # registers available for passing */ 710 int *arg_regs; /* array of register -1 terminated */ 711 int call_cookie; /* Do special things for this call */ 712 } CUMULATIVE_ARGS; 713 714 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 715 716 717 /* Initialize a variable CUM of type CUMULATIVE_ARGS 718 for a call to a function whose data type is FNTYPE. 719 For a library call, FNTYPE is 0. */ 720 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 721 (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 722 723 /* Define how to find the value returned by a function. 724 VALTYPE is the data type of the value (as a tree). 725 If the precise function being called is known, FUNC is its FUNCTION_DECL; 726 otherwise, FUNC is 0. 727 */ 728 729 #define VALUE_REGNO(MODE) (REG_R0) 730 731 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 732 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 733 VALUE_REGNO(TYPE_MODE(VALTYPE))) 734 735 /* Define how to find the value returned by a library function 736 assuming the value has mode MODE. */ 737 738 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 739 740 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 741 742 #define DEFAULT_PCC_STRUCT_RETURN 0 743 744 /* Before the prologue, the return address is in the RETS register. */ 745 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 746 747 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 748 749 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 750 751 /* Call instructions don't modify the stack pointer on the Blackfin. */ 752 #define INCOMING_FRAME_SP_OFFSET 0 753 754 /* Describe how we implement __builtin_eh_return. */ 755 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 756 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 757 #define EH_RETURN_HANDLER_RTX \ 758 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \ 759 UNITS_PER_WORD)) 760 761 /* Addressing Modes */ 762 763 /* A number, the maximum number of registers that can appear in a 764 valid memory address. Note that it is up to you to specify a 765 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' 766 would ever accept. */ 767 #define MAX_REGS_PER_ADDRESS 1 768 769 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 770 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 771 772 #define HAVE_POST_INCREMENT 1 773 #define HAVE_POST_DECREMENT 1 774 #define HAVE_PRE_DECREMENT 1 775 776 /* `LEGITIMATE_PIC_OPERAND_P (X)' 777 A C expression that is nonzero if X is a legitimate immediate 778 operand on the target machine when generating position independent 779 code. You can assume that X satisfies `CONSTANT_P', so you need 780 not check this. You can also assume FLAG_PIC is true, so you need 781 not check it either. You need not define this macro if all 782 constants (including `SYMBOL_REF') can be immediate operands when 783 generating position independent code. */ 784 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 785 786 #define SYMBOLIC_CONST(X) \ 787 (GET_CODE (X) == SYMBOL_REF \ 788 || GET_CODE (X) == LABEL_REF \ 789 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 790 791 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 792 793 /* Max number of bytes we can move from memory to memory 794 in one reasonably fast instruction. */ 795 #define MOVE_MAX UNITS_PER_WORD 796 797 /* If a memory-to-memory move would take MOVE_RATIO or more simple 798 move-instruction pairs, we will do a movmem or libcall instead. */ 799 800 #define MOVE_RATIO(speed) 5 801 802 /* STORAGE LAYOUT: target machine storage layout 803 Define this macro as a C expression which is nonzero if accessing 804 less than a word of memory (i.e. a `char' or a `short') is no 805 faster than accessing a word of memory, i.e., if such access 806 require more than one instruction or if there is no difference in 807 cost between byte and (aligned) word loads. 808 809 When this macro is not defined, the compiler will access a field by 810 finding the smallest containing object; when it is defined, a 811 fullword load will be used if alignment permits. Unless bytes 812 accesses are faster than word accesses, using word accesses is 813 preferable since it may eliminate subsequent memory access if 814 subsequent accesses occur to other fields in the same word of the 815 structure, but to different bytes. */ 816 #define SLOW_BYTE_ACCESS 0 817 #define SLOW_SHORT_ACCESS 0 818 819 /* Define this if most significant bit is lowest numbered 820 in instructions that operate on numbered bit-fields. */ 821 #define BITS_BIG_ENDIAN 0 822 823 /* Define this if most significant byte of a word is the lowest numbered. 824 We can't access bytes but if we could we would in the Big Endian order. */ 825 #define BYTES_BIG_ENDIAN 0 826 827 /* Define this if most significant word of a multiword number is numbered. */ 828 #define WORDS_BIG_ENDIAN 0 829 830 /* Width in bits of a "word", which is the contents of a machine register. 831 Note that this is not necessarily the width of data type `int'; 832 if using 16-bit ints on a 68000, this would still be 32. 833 But on a machine with 16-bit registers, this would be 16. */ 834 #define BITS_PER_WORD 32 835 836 /* Width of a word, in units (bytes). */ 837 #define UNITS_PER_WORD 4 838 839 /* Width in bits of a pointer. 840 See also the macro `Pmode1' defined below. */ 841 #define POINTER_SIZE 32 842 843 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 844 #define POINTER_BOUNDARY 32 845 846 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 847 #define PARM_BOUNDARY 32 848 849 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 850 #define STACK_BOUNDARY 32 851 852 /* Allocation boundary (in *bits*) for the code of a function. */ 853 #define FUNCTION_BOUNDARY 32 854 855 /* Alignment of field after `int : 0' in a structure. */ 856 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 857 858 /* No data type wants to be aligned rounder than this. */ 859 #define BIGGEST_ALIGNMENT 32 860 861 /* Define this if move instructions will actually fail to work 862 when given unaligned data. */ 863 #define STRICT_ALIGNMENT 1 864 865 /* (shell-command "rm c-decl.o stor-layout.o") 866 * never define PCC_BITFIELD_TYPE_MATTERS 867 * really cause some alignment problem 868 */ 869 870 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 871 BITS_PER_UNIT) 872 873 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 874 BITS_PER_UNIT) 875 876 877 /* what is the 'type' of size_t */ 878 #define SIZE_TYPE "long unsigned int" 879 880 /* Define this as 1 if `char' should by default be signed; else as 0. */ 881 #define DEFAULT_SIGNED_CHAR 1 882 #define FLOAT_TYPE_SIZE BITS_PER_WORD 883 #define SHORT_TYPE_SIZE 16 884 #define CHAR_TYPE_SIZE 8 885 #define INT_TYPE_SIZE 32 886 #define LONG_TYPE_SIZE 32 887 #define LONG_LONG_TYPE_SIZE 64 888 889 /* Note: Fix this to depend on target switch. -- lev */ 890 891 /* Note: Try to implement double and force long double. -- tonyko 892 * #define __DOUBLES_ARE_FLOATS__ 893 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 894 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 895 * #define DOUBLES_ARE_FLOATS 1 896 */ 897 898 #define DOUBLE_TYPE_SIZE 64 899 #define LONG_DOUBLE_TYPE_SIZE 64 900 901 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 902 A macro to update M and UNSIGNEDP when an object whose type is 903 TYPE and which has the specified mode and signedness is to be 904 stored in a register. This macro is only called when TYPE is a 905 scalar type. 906 907 On most RISC machines, which only have operations that operate on 908 a full register, define this macro to set M to `word_mode' if M is 909 an integer mode narrower than `BITS_PER_WORD'. In most cases, 910 only integer modes should be widened because wider-precision 911 floating-point operations are usually more expensive than their 912 narrower counterparts. 913 914 For most machines, the macro definition does not change UNSIGNEDP. 915 However, some machines, have instructions that preferentially 916 handle either signed or unsigned quantities of certain modes. For 917 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 918 instructions sign-extend the result to 64 bits. On such machines, 919 set UNSIGNEDP according to which kind of extension is more 920 efficient. 921 922 Do not define this macro if it would never modify M.*/ 923 924 #define BFIN_PROMOTE_MODE_P(MODE) \ 925 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 926 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 927 928 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 929 if (BFIN_PROMOTE_MODE_P(MODE)) \ 930 { \ 931 if (MODE == QImode) \ 932 UNSIGNEDP = 1; \ 933 else if (MODE == HImode) \ 934 UNSIGNEDP = 0; \ 935 (MODE) = SImode; \ 936 } 937 938 /* Describing Relative Costs of Operations */ 939 940 /* Do not put function addr into constant pool */ 941 #define NO_FUNCTION_CSE 1 942 943 /* Specify the machine mode that this machine uses 944 for the index in the tablejump instruction. */ 945 #define CASE_VECTOR_MODE SImode 946 947 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 948 949 /* Define if operations between registers always perform the operation 950 on the full register even if a narrower mode is specified. 951 #define WORD_REGISTER_OPERATIONS 1 952 */ 953 954 /* Evaluates to true if A and B are mac flags that can be used 955 together in a single multiply insn. That is the case if they are 956 both the same flag not involving M, or if one is a combination of 957 the other with M. */ 958 #define MACFLAGS_MATCH_P(A, B) \ 959 ((A) == (B) \ 960 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ 961 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ 962 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ 963 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) 964 965 /* Switch into a generic section. */ 966 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 967 968 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 969 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 970 971 typedef enum sections { 972 CODE_DIR, 973 DATA_DIR, 974 LAST_SECT_NM 975 } SECT_ENUM_T; 976 977 typedef enum directives { 978 LONG_CONST_DIR, 979 SHORT_CONST_DIR, 980 BYTE_CONST_DIR, 981 SPACE_DIR, 982 INIT_DIR, 983 LAST_DIR_NM 984 } DIR_ENUM_T; 985 986 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ 987 ((C) == ';' \ 988 || ((C) == '|' && (STR)[1] == '|')) 989 990 #define TEXT_SECTION_ASM_OP ".text;" 991 #define DATA_SECTION_ASM_OP ".data;" 992 993 #define ASM_APP_ON "" 994 #define ASM_APP_OFF "" 995 996 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 997 do { fputs (".global ", FILE); \ 998 assemble_name (FILE, NAME); \ 999 fputc (';',FILE); \ 1000 fputc ('\n',FILE); \ 1001 } while (0) 1002 1003 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1004 do { \ 1005 fputs (".type ", FILE); \ 1006 assemble_name (FILE, NAME); \ 1007 fputs (", STT_FUNC", FILE); \ 1008 fputc (';',FILE); \ 1009 fputc ('\n',FILE); \ 1010 ASM_OUTPUT_LABEL(FILE, NAME); \ 1011 } while (0) 1012 1013 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1014 do { assemble_name (FILE, NAME); \ 1015 fputs (":\n",FILE); \ 1016 } while (0) 1017 1018 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1019 do { fprintf (FILE, "_%s", NAME); \ 1020 } while (0) 1021 1022 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1023 do { char __buf[256]; \ 1024 fprintf (FILE, "\t.dd\t"); \ 1025 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1026 assemble_name (FILE, __buf); \ 1027 fputc (';', FILE); \ 1028 fputc ('\n', FILE); \ 1029 } while (0) 1030 1031 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1032 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1033 1034 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1035 do { \ 1036 char __buf[256]; \ 1037 fprintf (FILE, "\t.dd\t"); \ 1038 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1039 assemble_name (FILE, __buf); \ 1040 fputs (" - ", FILE); \ 1041 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1042 assemble_name (FILE, __buf); \ 1043 fputc (';', FILE); \ 1044 fputc ('\n', FILE); \ 1045 } while (0) 1046 1047 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1048 do { \ 1049 if ((LOG) != 0) \ 1050 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1051 } while (0) 1052 1053 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1054 do { \ 1055 asm_output_skip (FILE, SIZE); \ 1056 } while (0) 1057 1058 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1059 do { \ 1060 switch_to_section (data_section); \ 1061 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1062 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1063 ASM_OUTPUT_LABEL (FILE, NAME); \ 1064 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1065 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1066 } while (0) 1067 1068 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1069 do { \ 1070 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1071 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1072 1073 #define ASM_COMMENT_START "//" 1074 1075 #define PROFILE_BEFORE_PROLOGUE 1076 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1077 do { \ 1078 fprintf (FILE, "\t[--SP] = RETS;\n"); \ 1079 if (TARGET_LONG_CALLS) \ 1080 { \ 1081 fprintf (FILE, "\tP2.h = __mcount;\n"); \ 1082 fprintf (FILE, "\tP2.l = __mcount;\n"); \ 1083 fprintf (FILE, "\tCALL (P2);\n"); \ 1084 } \ 1085 else \ 1086 fprintf (FILE, "\tCALL __mcount;\n"); \ 1087 fprintf (FILE, "\tRETS = [SP++];\n"); \ 1088 } while(0) 1089 1090 #undef NO_PROFILE_COUNTERS 1091 #define NO_PROFILE_COUNTERS 1 1092 1093 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO]) 1094 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO]) 1095 1096 extern rtx bfin_cc_rtx, bfin_rets_rtx; 1097 1098 /* This works for GAS and some other assemblers. */ 1099 #define SET_ASM_OP ".set " 1100 1101 /* DBX register number for a given compiler register number */ 1102 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1103 1104 #define SIZE_ASM_OP "\t.size\t" 1105 1106 extern int splitting_for_sched, splitting_loops; 1107 1108 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') 1109 1110 #ifndef TARGET_SUPPORTS_SYNC_CALLS 1111 #define TARGET_SUPPORTS_SYNC_CALLS 0 1112 #endif 1113 1114 struct bfin_cpu 1115 { 1116 const char *name; 1117 bfin_cpu_t type; 1118 int si_revision; 1119 unsigned int workarounds; 1120 }; 1121 1122 extern const struct bfin_cpu bfin_cpus[]; 1123 1124 #endif /* _BFIN_CONFIG */ 1125
Indexes created Sun Apr 19 00:22:55 UTC 2026