bfin.h revision 1.5
1 /* Definitions for the Blackfin port. 2 Copyright (C) 2005-2015 Free Software Foundation, Inc. 3 Contributed by Analog Devices. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _BFIN_CONFIG 22 #define _BFIN_CONFIG 23 24 #ifndef BFIN_OPTS_H 25 #include "config/bfin/bfin-opts.h" 26 #endif 27 28 #define OBJECT_FORMAT_ELF 29 30 #define BRT 1 31 #define BRF 0 32 33 /* Predefinition in the preprocessor for this target machine */ 34 #ifndef TARGET_CPU_CPP_BUILTINS 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do \ 37 { \ 38 builtin_define_std ("bfin"); \ 39 builtin_define_std ("BFIN"); \ 40 builtin_define ("__ADSPBLACKFIN__"); \ 41 builtin_define ("__ADSPLPBLACKFIN__"); \ 42 \ 43 switch (bfin_cpu_type) \ 44 { \ 45 case BFIN_CPU_BF512: \ 46 builtin_define ("__ADSPBF512__"); \ 47 builtin_define ("__ADSPBF51x__"); \ 48 break; \ 49 case BFIN_CPU_BF514: \ 50 builtin_define ("__ADSPBF514__"); \ 51 builtin_define ("__ADSPBF51x__"); \ 52 break; \ 53 case BFIN_CPU_BF516: \ 54 builtin_define ("__ADSPBF516__"); \ 55 builtin_define ("__ADSPBF51x__"); \ 56 break; \ 57 case BFIN_CPU_BF518: \ 58 builtin_define ("__ADSPBF518__"); \ 59 builtin_define ("__ADSPBF51x__"); \ 60 break; \ 61 case BFIN_CPU_BF522: \ 62 builtin_define ("__ADSPBF522__"); \ 63 builtin_define ("__ADSPBF52x__"); \ 64 break; \ 65 case BFIN_CPU_BF523: \ 66 builtin_define ("__ADSPBF523__"); \ 67 builtin_define ("__ADSPBF52x__"); \ 68 break; \ 69 case BFIN_CPU_BF524: \ 70 builtin_define ("__ADSPBF524__"); \ 71 builtin_define ("__ADSPBF52x__"); \ 72 break; \ 73 case BFIN_CPU_BF525: \ 74 builtin_define ("__ADSPBF525__"); \ 75 builtin_define ("__ADSPBF52x__"); \ 76 break; \ 77 case BFIN_CPU_BF526: \ 78 builtin_define ("__ADSPBF526__"); \ 79 builtin_define ("__ADSPBF52x__"); \ 80 break; \ 81 case BFIN_CPU_BF527: \ 82 builtin_define ("__ADSPBF527__"); \ 83 builtin_define ("__ADSPBF52x__"); \ 84 break; \ 85 case BFIN_CPU_BF531: \ 86 builtin_define ("__ADSPBF531__"); \ 87 break; \ 88 case BFIN_CPU_BF532: \ 89 builtin_define ("__ADSPBF532__"); \ 90 break; \ 91 case BFIN_CPU_BF533: \ 92 builtin_define ("__ADSPBF533__"); \ 93 break; \ 94 case BFIN_CPU_BF534: \ 95 builtin_define ("__ADSPBF534__"); \ 96 break; \ 97 case BFIN_CPU_BF536: \ 98 builtin_define ("__ADSPBF536__"); \ 99 break; \ 100 case BFIN_CPU_BF537: \ 101 builtin_define ("__ADSPBF537__"); \ 102 break; \ 103 case BFIN_CPU_BF538: \ 104 builtin_define ("__ADSPBF538__"); \ 105 break; \ 106 case BFIN_CPU_BF539: \ 107 builtin_define ("__ADSPBF539__"); \ 108 break; \ 109 case BFIN_CPU_BF542M: \ 110 builtin_define ("__ADSPBF542M__"); \ 111 case BFIN_CPU_BF542: \ 112 builtin_define ("__ADSPBF542__"); \ 113 builtin_define ("__ADSPBF54x__"); \ 114 break; \ 115 case BFIN_CPU_BF544M: \ 116 builtin_define ("__ADSPBF544M__"); \ 117 case BFIN_CPU_BF544: \ 118 builtin_define ("__ADSPBF544__"); \ 119 builtin_define ("__ADSPBF54x__"); \ 120 break; \ 121 case BFIN_CPU_BF547M: \ 122 builtin_define ("__ADSPBF547M__"); \ 123 case BFIN_CPU_BF547: \ 124 builtin_define ("__ADSPBF547__"); \ 125 builtin_define ("__ADSPBF54x__"); \ 126 break; \ 127 case BFIN_CPU_BF548M: \ 128 builtin_define ("__ADSPBF548M__"); \ 129 case BFIN_CPU_BF548: \ 130 builtin_define ("__ADSPBF548__"); \ 131 builtin_define ("__ADSPBF54x__"); \ 132 break; \ 133 case BFIN_CPU_BF549M: \ 134 builtin_define ("__ADSPBF549M__"); \ 135 case BFIN_CPU_BF549: \ 136 builtin_define ("__ADSPBF549__"); \ 137 builtin_define ("__ADSPBF54x__"); \ 138 break; \ 139 case BFIN_CPU_BF561: \ 140 builtin_define ("__ADSPBF561__"); \ 141 break; \ 142 case BFIN_CPU_BF592: \ 143 builtin_define ("__ADSPBF592__"); \ 144 builtin_define ("__ADSPBF59x__"); \ 145 break; \ 146 } \ 147 \ 148 if (bfin_si_revision != -1) \ 149 { \ 150 /* space of 0xnnnn and a NUL */ \ 151 char *buf = XALLOCAVEC (char, 7); \ 152 \ 153 sprintf (buf, "0x%04x", bfin_si_revision); \ 154 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ 155 } \ 156 \ 157 if (bfin_workarounds) \ 158 builtin_define ("__WORKAROUNDS_ENABLED"); \ 159 if (ENABLE_WA_SPECULATIVE_LOADS) \ 160 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ 161 if (ENABLE_WA_SPECULATIVE_SYNCS) \ 162 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ 163 if (ENABLE_WA_INDIRECT_CALLS) \ 164 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \ 165 if (ENABLE_WA_RETS) \ 166 builtin_define ("__WORKAROUND_RETS"); \ 167 \ 168 if (TARGET_FDPIC) \ 169 { \ 170 builtin_define ("__BFIN_FDPIC__"); \ 171 builtin_define ("__FDPIC__"); \ 172 } \ 173 if (TARGET_ID_SHARED_LIBRARY \ 174 && !TARGET_SEP_DATA) \ 175 builtin_define ("__ID_SHARED_LIB__"); \ 176 if (flag_no_builtin) \ 177 builtin_define ("__NO_BUILTIN"); \ 178 if (TARGET_MULTICORE) \ 179 builtin_define ("__BFIN_MULTICORE"); \ 180 if (TARGET_COREA) \ 181 builtin_define ("__BFIN_COREA"); \ 182 if (TARGET_COREB) \ 183 builtin_define ("__BFIN_COREB"); \ 184 if (TARGET_SDRAM) \ 185 builtin_define ("__BFIN_SDRAM"); \ 186 } \ 187 while (0) 188 #endif 189 190 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 191 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ 192 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 193 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 194 " 195 #ifndef SUBTARGET_DRIVER_SELF_SPECS 196 # define SUBTARGET_DRIVER_SELF_SPECS 197 #endif 198 199 #define LINK_GCC_C_SEQUENCE_SPEC "\ 200 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \ 201 " 202 203 #undef ASM_SPEC 204 #define ASM_SPEC "\ 205 %{mno-fdpic:-mnopic} %{mfdpic}" 206 207 #define LINK_SPEC "\ 208 %{h*} %{v:-V} \ 209 %{mfdpic:-melf32bfinfd -z text} \ 210 %{static:-dn -Bstatic} \ 211 %{shared:-G -Bdynamic} \ 212 %{symbolic:-Bsymbolic} \ 213 -init __init -fini __fini " 214 215 /* Generate DSP instructions, like DSP halfword loads */ 216 #define TARGET_DSP (1) 217 218 #define TARGET_DEFAULT 0 219 220 /* Maximum number of library ids we permit */ 221 #define MAX_LIBRARY_ID 255 222 223 extern const char *bfin_library_id_string; 224 225 #define FUNCTION_MODE SImode 226 #define Pmode SImode 227 228 /* store-condition-codes instructions store 0 for false 229 This is the value stored for true. */ 230 #define STORE_FLAG_VALUE 1 231 232 /* Define this if pushing a word on the stack 233 makes the stack pointer a smaller address. */ 234 #define STACK_GROWS_DOWNWARD 235 236 #define STACK_PUSH_CODE PRE_DEC 237 238 /* Define this to nonzero if the nominal address of the stack frame 239 is at the high-address end of the local variables; 240 that is, each additional local variable allocated 241 goes at a more negative offset in the frame. */ 242 #define FRAME_GROWS_DOWNWARD 1 243 244 /* We define a dummy ARGP register; the parameters start at offset 0 from 245 it. */ 246 #define FIRST_PARM_OFFSET(DECL) 0 247 248 /* Offset within stack frame to start allocating local variables at. 249 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 250 first local allocated. Otherwise, it is the offset to the BEGINNING 251 of the first local allocated. */ 252 #define STARTING_FRAME_OFFSET 0 253 254 /* Register to use for pushing function arguments. */ 255 #define STACK_POINTER_REGNUM REG_P6 256 257 /* Base register for access to local variables of the function. */ 258 #define FRAME_POINTER_REGNUM REG_P7 259 260 /* A dummy register that will be eliminated to either FP or SP. */ 261 #define ARG_POINTER_REGNUM REG_ARGP 262 263 /* `PIC_OFFSET_TABLE_REGNUM' 264 The register number of the register used to address a table of 265 static data addresses in memory. In some cases this register is 266 defined by a processor's "application binary interface" (ABI). 267 When this macro is defined, RTL is generated for this register 268 once, as with the stack pointer and frame pointer registers. If 269 this macro is not defined, it is up to the machine-dependent files 270 to allocate such a register (if necessary). */ 271 #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 272 273 #define FDPIC_FPTR_REGNO REG_P1 274 #define FDPIC_REGNO REG_P3 275 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 276 277 /* A static chain register for nested functions. We need to use a 278 call-clobbered register for this. */ 279 #define STATIC_CHAIN_REGNUM REG_P2 280 281 /* Define this if functions should assume that stack space has been 282 allocated for arguments even when their values are passed in 283 registers. 284 285 The value of this macro is the size, in bytes, of the area reserved for 286 arguments passed in registers. 287 288 This space can either be allocated by the caller or be a part of the 289 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 290 says which. */ 291 #define FIXED_STACK_AREA 12 292 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 293 294 /* Define this if the above stack space is to be considered part of the 295 * space allocated by the caller. */ 296 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 297 298 /* Define this if the maximum size of all the outgoing args is to be 299 accumulated and pushed during the prologue. The amount can be 300 found in the variable crtl->outgoing_args_size. */ 301 #define ACCUMULATE_OUTGOING_ARGS 1 302 303 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 304 305 /* If defined, a C expression to compute the alignment for a local 306 variable. TYPE is the data type, and ALIGN is the alignment that 307 the object would ordinarily have. The value of this macro is used 308 instead of that alignment to align the object. 309 310 If this macro is not defined, then ALIGN is used. 311 312 One use of this macro is to increase alignment of medium-size 313 data to make it all fit in fewer cache lines. */ 314 315 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) 316 317 /* Make strings word-aligned so strcpy from constants will be faster. */ 318 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 319 (TREE_CODE (EXP) == STRING_CST \ 320 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 321 322 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 323 324 /* Definitions for register eliminations. 326 327 This is an array of structures. Each structure initializes one pair 328 of eliminable registers. The "from" register number is given first, 329 followed by "to". Eliminations of the same "from" register are listed 330 in order of preference. 331 332 There are two registers that can always be eliminated on the i386. 333 The frame pointer and the arg pointer can be replaced by either the 334 hard frame pointer or to the stack pointer, depending upon the 335 circumstances. The hard frame pointer is not used before reload and 336 so it is not eligible for elimination. */ 337 338 #define ELIMINABLE_REGS \ 339 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 340 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 341 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 342 343 /* Define the offset between two registers, one to be eliminated, and the other 344 its replacement, at the start of a routine. */ 345 346 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 347 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 348 349 /* This processor has 351 8 data register for doing arithmetic 352 8 pointer register for doing addressing, including 353 1 stack pointer P6 354 1 frame pointer P7 355 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 356 1 condition code flag register CC 357 5 return address registers RETS/I/X/N/E 358 1 arithmetic status register (ASTAT). */ 359 360 #define FIRST_PSEUDO_REGISTER 50 361 362 #define D_REGNO_P(X) ((X) <= REG_R7) 363 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 364 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 365 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 366 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 367 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 368 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 369 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 370 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 371 372 #define REGISTER_NAMES { \ 373 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 374 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 375 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 376 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 377 "A0", "A1", \ 378 "CC", \ 379 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 380 "ARGP", \ 381 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 382 } 383 384 #define SHORT_REGISTER_NAMES { \ 385 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 386 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 387 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 388 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 389 390 #define HIGH_REGISTER_NAMES { \ 391 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 392 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 393 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 394 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 395 396 #define DREGS_PAIR_NAMES { \ 397 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 398 399 #define BYTE_REGISTER_NAMES { \ 400 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 401 402 403 /* 1 for registers that have pervasive standard uses 404 and are not available for the register allocator. */ 405 406 #define FIXED_REGISTERS \ 407 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 408 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 409 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 410 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 411 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 412 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 413 /*lb0/1 */ \ 414 1, 1 \ 415 } 416 417 /* 1 for registers not available across function calls. 418 These must include the FIXED_REGISTERS and also any 419 registers that can be used without being saved. 420 The latter must include the registers where values are returned 421 and the register where structure-value addresses are passed. 422 Aside from that, you can include as many other registers as you like. */ 423 424 #define CALL_USED_REGISTERS \ 425 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 426 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 427 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 428 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 429 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 431 /*lb0/1 */ \ 432 1, 1 \ 433 } 434 435 /* Order in which to allocate registers. Each register must be 436 listed once, even those in FIXED_REGISTERS. List frame pointer 437 late and fixed registers last. Note that, in general, we prefer 438 registers listed in CALL_USED_REGISTERS, keeping the others 439 available for storage of persistent values. */ 440 441 #define REG_ALLOC_ORDER \ 442 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 443 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 444 REG_A0, REG_A1, \ 445 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 446 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 447 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 448 REG_ASTAT, REG_SEQSTAT, REG_USP, \ 449 REG_CC, REG_ARGP, \ 450 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 451 } 452 453 /* Define the classes of registers for register constraints in the 454 machine description. Also define ranges of constants. 455 456 One of the classes must always be named ALL_REGS and include all hard regs. 457 If there is more than one class, another class must be named NO_REGS 458 and contain no registers. 459 460 The name GENERAL_REGS must be the name of a class (or an alias for 461 another name such as ALL_REGS). This is the class of registers 462 that is allowed by "g" or "r" in a register constraint. 463 Also, registers outside this class are allocated only when 464 instructions express preferences for them. 465 466 The classes must be numbered in nondecreasing order; that is, 467 a larger-numbered class must never be contained completely 468 in a smaller-numbered class. 469 470 For any two classes, it is very desirable that there be another 471 class that represents their union. */ 472 473 474 enum reg_class 475 { 476 NO_REGS, 477 IREGS, 478 BREGS, 479 LREGS, 480 MREGS, 481 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 482 DAGREGS, 483 EVEN_AREGS, 484 ODD_AREGS, 485 AREGS, 486 CCREGS, 487 EVEN_DREGS, 488 ODD_DREGS, 489 D0REGS, 490 D1REGS, 491 D2REGS, 492 D3REGS, 493 D4REGS, 494 D5REGS, 495 D6REGS, 496 D7REGS, 497 DREGS, 498 P0REGS, 499 FDPIC_REGS, 500 FDPIC_FPTR_REGS, 501 PREGS_CLOBBERED, 502 PREGS, 503 IPREGS, 504 DPREGS, 505 MOST_REGS, 506 LT_REGS, 507 LC_REGS, 508 LB_REGS, 509 PROLOGUE_REGS, 510 NON_A_CC_REGS, 511 ALL_REGS, LIM_REG_CLASSES 512 }; 513 514 #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 515 516 #define GENERAL_REGS DPREGS 517 518 /* Give names of register classes as strings for dump file. */ 519 520 #define REG_CLASS_NAMES \ 521 { "NO_REGS", \ 522 "IREGS", \ 523 "BREGS", \ 524 "LREGS", \ 525 "MREGS", \ 526 "CIRCREGS", \ 527 "DAGREGS", \ 528 "EVEN_AREGS", \ 529 "ODD_AREGS", \ 530 "AREGS", \ 531 "CCREGS", \ 532 "EVEN_DREGS", \ 533 "ODD_DREGS", \ 534 "D0REGS", \ 535 "D1REGS", \ 536 "D2REGS", \ 537 "D3REGS", \ 538 "D4REGS", \ 539 "D5REGS", \ 540 "D6REGS", \ 541 "D7REGS", \ 542 "DREGS", \ 543 "P0REGS", \ 544 "FDPIC_REGS", \ 545 "FDPIC_FPTR_REGS", \ 546 "PREGS_CLOBBERED", \ 547 "PREGS", \ 548 "IPREGS", \ 549 "DPREGS", \ 550 "MOST_REGS", \ 551 "LT_REGS", \ 552 "LC_REGS", \ 553 "LB_REGS", \ 554 "PROLOGUE_REGS", \ 555 "NON_A_CC_REGS", \ 556 "ALL_REGS" } 557 558 /* An initializer containing the contents of the register classes, as integers 559 which are bit masks. The Nth integer specifies the contents of class N. 560 The way the integer MASK is interpreted is that register R is in the class 561 if `MASK & (1 << R)' is 1. 562 563 When the machine has more than 32 registers, an integer does not suffice. 564 Then the integers are replaced by sub-initializers, braced groupings 565 containing several integers. Each sub-initializer must be suitable as an 566 initializer for the type `HARD_REG_SET' which is defined in 567 `hard-reg-set.h'. */ 568 569 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 570 MOST_REGS as the union of DPREGS and DAGREGS. */ 571 572 #define REG_CLASS_CONTENTS \ 573 /* 31 - 0 63-32 */ \ 574 { { 0x00000000, 0 }, /* NO_REGS */ \ 575 { 0x000f0000, 0 }, /* IREGS */ \ 576 { 0x00f00000, 0 }, /* BREGS */ \ 577 { 0x0f000000, 0 }, /* LREGS */ \ 578 { 0xf0000000, 0 }, /* MREGS */ \ 579 { 0x0fff0000, 0 }, /* CIRCREGS */ \ 580 { 0xffff0000, 0 }, /* DAGREGS */ \ 581 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 582 { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 583 { 0x00000000, 0x3 }, /* AREGS */ \ 584 { 0x00000000, 0x4 }, /* CCREGS */ \ 585 { 0x00000055, 0 }, /* EVEN_DREGS */ \ 586 { 0x000000aa, 0 }, /* ODD_DREGS */ \ 587 { 0x00000001, 0 }, /* D0REGS */ \ 588 { 0x00000002, 0 }, /* D1REGS */ \ 589 { 0x00000004, 0 }, /* D2REGS */ \ 590 { 0x00000008, 0 }, /* D3REGS */ \ 591 { 0x00000010, 0 }, /* D4REGS */ \ 592 { 0x00000020, 0 }, /* D5REGS */ \ 593 { 0x00000040, 0 }, /* D6REGS */ \ 594 { 0x00000080, 0 }, /* D7REGS */ \ 595 { 0x000000ff, 0 }, /* DREGS */ \ 596 { 0x00000100, 0x000 }, /* P0REGS */ \ 597 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 598 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 599 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 600 { 0x0000ff00, 0x800 }, /* PREGS */ \ 601 { 0x000fff00, 0x800 }, /* IPREGS */ \ 602 { 0x0000ffff, 0x800 }, /* DPREGS */ \ 603 { 0xffffffff, 0x800 }, /* MOST_REGS */\ 604 { 0x00000000, 0x3000 }, /* LT_REGS */\ 605 { 0x00000000, 0xc000 }, /* LC_REGS */\ 606 { 0x00000000, 0x30000 }, /* LB_REGS */\ 607 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 608 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 609 { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 610 611 #define IREG_POSSIBLE_P(OUTER) \ 612 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 613 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 614 || (OUTER) == MEM || (OUTER) == ADDRESS) 615 616 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ 617 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 618 619 #define INDEX_REG_CLASS PREGS 620 621 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 622 (P_REGNO_P (X) || (X) == REG_ARGP \ 623 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 624 && I_REGNO_P (X))) 625 626 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 627 ((X) >= FIRST_PSEUDO_REGISTER \ 628 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 629 630 #ifdef REG_OK_STRICT 631 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 632 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 633 #else 634 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 635 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 636 #endif 637 638 #define REGNO_OK_FOR_INDEX_P(X) 0 639 640 /* The same information, inverted: 641 Return the class number of the smallest class containing 642 reg number REGNO. This could be a conditional expression 643 or could index an array. */ 644 645 #define REGNO_REG_CLASS(REGNO) \ 646 ((REGNO) == REG_R0 ? D0REGS \ 647 : (REGNO) == REG_R1 ? D1REGS \ 648 : (REGNO) == REG_R2 ? D2REGS \ 649 : (REGNO) == REG_R3 ? D3REGS \ 650 : (REGNO) == REG_R4 ? D4REGS \ 651 : (REGNO) == REG_R5 ? D5REGS \ 652 : (REGNO) == REG_R6 ? D6REGS \ 653 : (REGNO) == REG_R7 ? D7REGS \ 654 : (REGNO) == REG_P0 ? P0REGS \ 655 : (REGNO) < REG_I0 ? PREGS \ 656 : (REGNO) == REG_ARGP ? PREGS \ 657 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 658 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 659 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 660 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 661 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 662 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 663 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 664 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 665 : (REGNO) == REG_CC ? CCREGS \ 666 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 667 : NO_REGS) 668 669 /* When this hook returns true for MODE, the compiler allows 670 registers explicitly used in the rtl to be used as spill registers 671 but prevents the compiler from extending the lifetime of these 672 registers. */ 673 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 674 675 /* Do not allow to store a value in REG_CC for any mode */ 676 /* Do not allow to store value in pregs if mode is not SI*/ 677 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 678 679 /* Return the maximum number of consecutive registers 680 needed to represent mode MODE in a register of class CLASS. */ 681 #define CLASS_MAX_NREGS(CLASS, MODE) \ 682 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 683 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 684 685 #define HARD_REGNO_NREGS(REGNO, MODE) \ 686 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ 687 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ 688 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) 689 690 /* A C expression that is nonzero if hard register TO can be 691 considered for use as a rename register for FROM register */ 692 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 693 694 /* A C expression that is nonzero if it is desirable to choose 695 register allocation so as to avoid move instructions between a 696 value of mode MODE1 and a value of mode MODE2. 697 698 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 699 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 700 MODE2)' must be zero. */ 701 #define MODES_TIEABLE_P(MODE1, MODE2) \ 702 ((MODE1) == (MODE2) \ 703 || ((GET_MODE_CLASS (MODE1) == MODE_INT \ 704 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \ 705 && (GET_MODE_CLASS (MODE2) == MODE_INT \ 706 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \ 707 && (MODE1) != BImode && (MODE2) != BImode \ 708 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 709 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)) 710 711 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 712 A C expression that places additional restrictions on the register 713 class to use when it is necessary to copy value X into a register 714 in class CLASS. The value is a register class; perhaps CLASS, or 715 perhaps another, smaller class. */ 716 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 717 (GET_CODE (X) == POST_INC \ 718 || GET_CODE (X) == POST_DEC \ 719 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) 720 721 /* Function Calling Conventions. */ 722 723 /* The type of the current function; normal functions are of type 724 SUBROUTINE. */ 725 typedef enum { 726 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 727 } e_funkind; 728 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN } 729 730 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 731 732 /* Flags for the call/call_value rtl operations set up by function_arg */ 733 #define CALL_NORMAL 0x00000000 /* no special processing */ 734 #define CALL_LONG 0x00000001 /* always call indirect */ 735 #define CALL_SHORT 0x00000002 /* always call by symbol */ 736 737 typedef struct { 738 int words; /* # words passed so far */ 739 int nregs; /* # registers available for passing */ 740 int *arg_regs; /* array of register -1 terminated */ 741 int call_cookie; /* Do special things for this call */ 742 } CUMULATIVE_ARGS; 743 744 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 745 746 747 /* Initialize a variable CUM of type CUMULATIVE_ARGS 748 for a call to a function whose data type is FNTYPE. 749 For a library call, FNTYPE is 0. */ 750 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 751 (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 752 753 /* Define how to find the value returned by a function. 754 VALTYPE is the data type of the value (as a tree). 755 If the precise function being called is known, FUNC is its FUNCTION_DECL; 756 otherwise, FUNC is 0. 757 */ 758 759 #define VALUE_REGNO(MODE) (REG_R0) 760 761 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 762 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 763 VALUE_REGNO(TYPE_MODE(VALTYPE))) 764 765 /* Define how to find the value returned by a library function 766 assuming the value has mode MODE. */ 767 768 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 769 770 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 771 772 #define DEFAULT_PCC_STRUCT_RETURN 0 773 774 /* Before the prologue, the return address is in the RETS register. */ 775 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 776 777 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 778 779 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 780 781 /* Call instructions don't modify the stack pointer on the Blackfin. */ 782 #define INCOMING_FRAME_SP_OFFSET 0 783 784 /* Describe how we implement __builtin_eh_return. */ 785 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 786 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 787 #define EH_RETURN_HANDLER_RTX \ 788 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \ 789 UNITS_PER_WORD)) 790 791 /* Addressing Modes */ 792 793 /* A number, the maximum number of registers that can appear in a 794 valid memory address. Note that it is up to you to specify a 795 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' 796 would ever accept. */ 797 #define MAX_REGS_PER_ADDRESS 1 798 799 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 800 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 801 802 #define HAVE_POST_INCREMENT 1 803 #define HAVE_POST_DECREMENT 1 804 #define HAVE_PRE_DECREMENT 1 805 806 /* `LEGITIMATE_PIC_OPERAND_P (X)' 807 A C expression that is nonzero if X is a legitimate immediate 808 operand on the target machine when generating position independent 809 code. You can assume that X satisfies `CONSTANT_P', so you need 810 not check this. You can also assume FLAG_PIC is true, so you need 811 not check it either. You need not define this macro if all 812 constants (including `SYMBOL_REF') can be immediate operands when 813 generating position independent code. */ 814 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 815 816 #define SYMBOLIC_CONST(X) \ 817 (GET_CODE (X) == SYMBOL_REF \ 818 || GET_CODE (X) == LABEL_REF \ 819 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 820 821 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 822 823 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 824 is done just by pretending it is already truncated. */ 825 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 826 827 /* Max number of bytes we can move from memory to memory 828 in one reasonably fast instruction. */ 829 #define MOVE_MAX UNITS_PER_WORD 830 831 /* If a memory-to-memory move would take MOVE_RATIO or more simple 832 move-instruction pairs, we will do a movmem or libcall instead. */ 833 834 #define MOVE_RATIO(speed) 5 835 836 /* STORAGE LAYOUT: target machine storage layout 837 Define this macro as a C expression which is nonzero if accessing 838 less than a word of memory (i.e. a `char' or a `short') is no 839 faster than accessing a word of memory, i.e., if such access 840 require more than one instruction or if there is no difference in 841 cost between byte and (aligned) word loads. 842 843 When this macro is not defined, the compiler will access a field by 844 finding the smallest containing object; when it is defined, a 845 fullword load will be used if alignment permits. Unless bytes 846 accesses are faster than word accesses, using word accesses is 847 preferable since it may eliminate subsequent memory access if 848 subsequent accesses occur to other fields in the same word of the 849 structure, but to different bytes. */ 850 #define SLOW_BYTE_ACCESS 0 851 #define SLOW_SHORT_ACCESS 0 852 853 /* Define this if most significant bit is lowest numbered 854 in instructions that operate on numbered bit-fields. */ 855 #define BITS_BIG_ENDIAN 0 856 857 /* Define this if most significant byte of a word is the lowest numbered. 858 We can't access bytes but if we could we would in the Big Endian order. */ 859 #define BYTES_BIG_ENDIAN 0 860 861 /* Define this if most significant word of a multiword number is numbered. */ 862 #define WORDS_BIG_ENDIAN 0 863 864 /* Width in bits of a "word", which is the contents of a machine register. 865 Note that this is not necessarily the width of data type `int'; 866 if using 16-bit ints on a 68000, this would still be 32. 867 But on a machine with 16-bit registers, this would be 16. */ 868 #define BITS_PER_WORD 32 869 870 /* Width of a word, in units (bytes). */ 871 #define UNITS_PER_WORD 4 872 873 /* Width in bits of a pointer. 874 See also the macro `Pmode1' defined below. */ 875 #define POINTER_SIZE 32 876 877 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 878 #define POINTER_BOUNDARY 32 879 880 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 881 #define PARM_BOUNDARY 32 882 883 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 884 #define STACK_BOUNDARY 32 885 886 /* Allocation boundary (in *bits*) for the code of a function. */ 887 #define FUNCTION_BOUNDARY 32 888 889 /* Alignment of field after `int : 0' in a structure. */ 890 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 891 892 /* No data type wants to be aligned rounder than this. */ 893 #define BIGGEST_ALIGNMENT 32 894 895 /* Define this if move instructions will actually fail to work 896 when given unaligned data. */ 897 #define STRICT_ALIGNMENT 1 898 899 /* (shell-command "rm c-decl.o stor-layout.o") 900 * never define PCC_BITFIELD_TYPE_MATTERS 901 * really cause some alignment problem 902 */ 903 904 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 905 BITS_PER_UNIT) 906 907 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 908 BITS_PER_UNIT) 909 910 911 /* what is the 'type' of size_t */ 912 #define SIZE_TYPE "long unsigned int" 913 914 /* Define this as 1 if `char' should by default be signed; else as 0. */ 915 #define DEFAULT_SIGNED_CHAR 1 916 #define FLOAT_TYPE_SIZE BITS_PER_WORD 917 #define SHORT_TYPE_SIZE 16 918 #define CHAR_TYPE_SIZE 8 919 #define INT_TYPE_SIZE 32 920 #define LONG_TYPE_SIZE 32 921 #define LONG_LONG_TYPE_SIZE 64 922 923 /* Note: Fix this to depend on target switch. -- lev */ 924 925 /* Note: Try to implement double and force long double. -- tonyko 926 * #define __DOUBLES_ARE_FLOATS__ 927 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 928 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 929 * #define DOUBLES_ARE_FLOATS 1 930 */ 931 932 #define DOUBLE_TYPE_SIZE 64 933 #define LONG_DOUBLE_TYPE_SIZE 64 934 935 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 936 A macro to update M and UNSIGNEDP when an object whose type is 937 TYPE and which has the specified mode and signedness is to be 938 stored in a register. This macro is only called when TYPE is a 939 scalar type. 940 941 On most RISC machines, which only have operations that operate on 942 a full register, define this macro to set M to `word_mode' if M is 943 an integer mode narrower than `BITS_PER_WORD'. In most cases, 944 only integer modes should be widened because wider-precision 945 floating-point operations are usually more expensive than their 946 narrower counterparts. 947 948 For most machines, the macro definition does not change UNSIGNEDP. 949 However, some machines, have instructions that preferentially 950 handle either signed or unsigned quantities of certain modes. For 951 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 952 instructions sign-extend the result to 64 bits. On such machines, 953 set UNSIGNEDP according to which kind of extension is more 954 efficient. 955 956 Do not define this macro if it would never modify M.*/ 957 958 #define BFIN_PROMOTE_MODE_P(MODE) \ 959 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 960 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 961 962 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 963 if (BFIN_PROMOTE_MODE_P(MODE)) \ 964 { \ 965 if (MODE == QImode) \ 966 UNSIGNEDP = 1; \ 967 else if (MODE == HImode) \ 968 UNSIGNEDP = 0; \ 969 (MODE) = SImode; \ 970 } 971 972 /* Describing Relative Costs of Operations */ 973 974 /* Do not put function addr into constant pool */ 975 #define NO_FUNCTION_CSE 1 976 977 /* Specify the machine mode that this machine uses 978 for the index in the tablejump instruction. */ 979 #define CASE_VECTOR_MODE SImode 980 981 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 982 983 /* Define if operations between registers always perform the operation 984 on the full register even if a narrower mode is specified. 985 #define WORD_REGISTER_OPERATIONS 986 */ 987 988 /* Evaluates to true if A and B are mac flags that can be used 989 together in a single multiply insn. That is the case if they are 990 both the same flag not involving M, or if one is a combination of 991 the other with M. */ 992 #define MACFLAGS_MATCH_P(A, B) \ 993 ((A) == (B) \ 994 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ 995 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ 996 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ 997 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) 998 999 /* Switch into a generic section. */ 1000 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 1001 1002 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 1003 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 1004 1005 typedef enum sections { 1006 CODE_DIR, 1007 DATA_DIR, 1008 LAST_SECT_NM 1009 } SECT_ENUM_T; 1010 1011 typedef enum directives { 1012 LONG_CONST_DIR, 1013 SHORT_CONST_DIR, 1014 BYTE_CONST_DIR, 1015 SPACE_DIR, 1016 INIT_DIR, 1017 LAST_DIR_NM 1018 } DIR_ENUM_T; 1019 1020 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ 1021 ((C) == ';' \ 1022 || ((C) == '|' && (STR)[1] == '|')) 1023 1024 #define TEXT_SECTION_ASM_OP ".text;" 1025 #define DATA_SECTION_ASM_OP ".data;" 1026 1027 #define ASM_APP_ON "" 1028 #define ASM_APP_OFF "" 1029 1030 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 1031 do { fputs (".global ", FILE); \ 1032 assemble_name (FILE, NAME); \ 1033 fputc (';',FILE); \ 1034 fputc ('\n',FILE); \ 1035 } while (0) 1036 1037 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1038 do { \ 1039 fputs (".type ", FILE); \ 1040 assemble_name (FILE, NAME); \ 1041 fputs (", STT_FUNC", FILE); \ 1042 fputc (';',FILE); \ 1043 fputc ('\n',FILE); \ 1044 ASM_OUTPUT_LABEL(FILE, NAME); \ 1045 } while (0) 1046 1047 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1048 do { assemble_name (FILE, NAME); \ 1049 fputs (":\n",FILE); \ 1050 } while (0) 1051 1052 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1053 do { fprintf (FILE, "_%s", NAME); \ 1054 } while (0) 1055 1056 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1057 do { char __buf[256]; \ 1058 fprintf (FILE, "\t.dd\t"); \ 1059 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1060 assemble_name (FILE, __buf); \ 1061 fputc (';', FILE); \ 1062 fputc ('\n', FILE); \ 1063 } while (0) 1064 1065 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1066 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1067 1068 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1069 do { \ 1070 char __buf[256]; \ 1071 fprintf (FILE, "\t.dd\t"); \ 1072 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1073 assemble_name (FILE, __buf); \ 1074 fputs (" - ", FILE); \ 1075 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1076 assemble_name (FILE, __buf); \ 1077 fputc (';', FILE); \ 1078 fputc ('\n', FILE); \ 1079 } while (0) 1080 1081 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1082 do { \ 1083 if ((LOG) != 0) \ 1084 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1085 } while (0) 1086 1087 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1088 do { \ 1089 asm_output_skip (FILE, SIZE); \ 1090 } while (0) 1091 1092 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1093 do { \ 1094 switch_to_section (data_section); \ 1095 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1096 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1097 ASM_OUTPUT_LABEL (FILE, NAME); \ 1098 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1099 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1100 } while (0) 1101 1102 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1103 do { \ 1104 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1105 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1106 1107 #define ASM_COMMENT_START "//" 1108 1109 #define PROFILE_BEFORE_PROLOGUE 1110 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1111 do { \ 1112 fprintf (FILE, "\t[--SP] = RETS;\n"); \ 1113 if (TARGET_LONG_CALLS) \ 1114 { \ 1115 fprintf (FILE, "\tP2.h = __mcount;\n"); \ 1116 fprintf (FILE, "\tP2.l = __mcount;\n"); \ 1117 fprintf (FILE, "\tCALL (P2);\n"); \ 1118 } \ 1119 else \ 1120 fprintf (FILE, "\tCALL __mcount;\n"); \ 1121 fprintf (FILE, "\tRETS = [SP++];\n"); \ 1122 } while(0) 1123 1124 #undef NO_PROFILE_COUNTERS 1125 #define NO_PROFILE_COUNTERS 1 1126 1127 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO]) 1128 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO]) 1129 1130 extern rtx bfin_cc_rtx, bfin_rets_rtx; 1131 1132 /* This works for GAS and some other assemblers. */ 1133 #define SET_ASM_OP ".set " 1134 1135 /* DBX register number for a given compiler register number */ 1136 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1137 1138 #define SIZE_ASM_OP "\t.size\t" 1139 1140 extern int splitting_for_sched, splitting_loops; 1141 1142 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') 1143 1144 #ifndef TARGET_SUPPORTS_SYNC_CALLS 1145 #define TARGET_SUPPORTS_SYNC_CALLS 0 1146 #endif 1147 1148 struct bfin_cpu 1149 { 1150 const char *name; 1151 bfin_cpu_t type; 1152 int si_revision; 1153 unsigned int workarounds; 1154 }; 1155 1156 extern const struct bfin_cpu bfin_cpus[]; 1157 1158 #endif /* _BFIN_CONFIG */ 1159
Indexes created Sun Apr 19 00:22:55 UTC 2026