bfin.h revision 1.6
1 /* Definitions for the Blackfin port. 2 Copyright (C) 2005-2016 Free Software Foundation, Inc. 3 Contributed by Analog Devices. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _BFIN_CONFIG 22 #define _BFIN_CONFIG 23 24 #ifndef BFIN_OPTS_H 25 #include "config/bfin/bfin-opts.h" 26 #endif 27 28 #define OBJECT_FORMAT_ELF 29 30 #define BRT 1 31 #define BRF 0 32 33 /* Predefinition in the preprocessor for this target machine */ 34 #ifndef TARGET_CPU_CPP_BUILTINS 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do \ 37 { \ 38 builtin_define_std ("bfin"); \ 39 builtin_define_std ("BFIN"); \ 40 builtin_define ("__ADSPBLACKFIN__"); \ 41 builtin_define ("__ADSPLPBLACKFIN__"); \ 42 \ 43 switch (bfin_cpu_type) \ 44 { \ 45 case BFIN_CPU_UNKNOWN: \ 46 break; \ 47 case BFIN_CPU_BF512: \ 48 builtin_define ("__ADSPBF512__"); \ 49 builtin_define ("__ADSPBF51x__"); \ 50 break; \ 51 case BFIN_CPU_BF514: \ 52 builtin_define ("__ADSPBF514__"); \ 53 builtin_define ("__ADSPBF51x__"); \ 54 break; \ 55 case BFIN_CPU_BF516: \ 56 builtin_define ("__ADSPBF516__"); \ 57 builtin_define ("__ADSPBF51x__"); \ 58 break; \ 59 case BFIN_CPU_BF518: \ 60 builtin_define ("__ADSPBF518__"); \ 61 builtin_define ("__ADSPBF51x__"); \ 62 break; \ 63 case BFIN_CPU_BF522: \ 64 builtin_define ("__ADSPBF522__"); \ 65 builtin_define ("__ADSPBF52x__"); \ 66 break; \ 67 case BFIN_CPU_BF523: \ 68 builtin_define ("__ADSPBF523__"); \ 69 builtin_define ("__ADSPBF52x__"); \ 70 break; \ 71 case BFIN_CPU_BF524: \ 72 builtin_define ("__ADSPBF524__"); \ 73 builtin_define ("__ADSPBF52x__"); \ 74 break; \ 75 case BFIN_CPU_BF525: \ 76 builtin_define ("__ADSPBF525__"); \ 77 builtin_define ("__ADSPBF52x__"); \ 78 break; \ 79 case BFIN_CPU_BF526: \ 80 builtin_define ("__ADSPBF526__"); \ 81 builtin_define ("__ADSPBF52x__"); \ 82 break; \ 83 case BFIN_CPU_BF527: \ 84 builtin_define ("__ADSPBF527__"); \ 85 builtin_define ("__ADSPBF52x__"); \ 86 break; \ 87 case BFIN_CPU_BF531: \ 88 builtin_define ("__ADSPBF531__"); \ 89 break; \ 90 case BFIN_CPU_BF532: \ 91 builtin_define ("__ADSPBF532__"); \ 92 break; \ 93 case BFIN_CPU_BF533: \ 94 builtin_define ("__ADSPBF533__"); \ 95 break; \ 96 case BFIN_CPU_BF534: \ 97 builtin_define ("__ADSPBF534__"); \ 98 break; \ 99 case BFIN_CPU_BF536: \ 100 builtin_define ("__ADSPBF536__"); \ 101 break; \ 102 case BFIN_CPU_BF537: \ 103 builtin_define ("__ADSPBF537__"); \ 104 break; \ 105 case BFIN_CPU_BF538: \ 106 builtin_define ("__ADSPBF538__"); \ 107 break; \ 108 case BFIN_CPU_BF539: \ 109 builtin_define ("__ADSPBF539__"); \ 110 break; \ 111 case BFIN_CPU_BF542M: \ 112 builtin_define ("__ADSPBF542M__"); \ 113 case BFIN_CPU_BF542: \ 114 builtin_define ("__ADSPBF542__"); \ 115 builtin_define ("__ADSPBF54x__"); \ 116 break; \ 117 case BFIN_CPU_BF544M: \ 118 builtin_define ("__ADSPBF544M__"); \ 119 case BFIN_CPU_BF544: \ 120 builtin_define ("__ADSPBF544__"); \ 121 builtin_define ("__ADSPBF54x__"); \ 122 break; \ 123 case BFIN_CPU_BF547M: \ 124 builtin_define ("__ADSPBF547M__"); \ 125 case BFIN_CPU_BF547: \ 126 builtin_define ("__ADSPBF547__"); \ 127 builtin_define ("__ADSPBF54x__"); \ 128 break; \ 129 case BFIN_CPU_BF548M: \ 130 builtin_define ("__ADSPBF548M__"); \ 131 case BFIN_CPU_BF548: \ 132 builtin_define ("__ADSPBF548__"); \ 133 builtin_define ("__ADSPBF54x__"); \ 134 break; \ 135 case BFIN_CPU_BF549M: \ 136 builtin_define ("__ADSPBF549M__"); \ 137 case BFIN_CPU_BF549: \ 138 builtin_define ("__ADSPBF549__"); \ 139 builtin_define ("__ADSPBF54x__"); \ 140 break; \ 141 case BFIN_CPU_BF561: \ 142 builtin_define ("__ADSPBF561__"); \ 143 break; \ 144 case BFIN_CPU_BF592: \ 145 builtin_define ("__ADSPBF592__"); \ 146 builtin_define ("__ADSPBF59x__"); \ 147 break; \ 148 } \ 149 \ 150 if (bfin_si_revision != -1) \ 151 { \ 152 /* space of 0xnnnn and a NUL */ \ 153 char *buf = XALLOCAVEC (char, 7); \ 154 \ 155 sprintf (buf, "0x%04x", bfin_si_revision); \ 156 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ 157 } \ 158 \ 159 if (bfin_workarounds) \ 160 builtin_define ("__WORKAROUNDS_ENABLED"); \ 161 if (ENABLE_WA_SPECULATIVE_LOADS) \ 162 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ 163 if (ENABLE_WA_SPECULATIVE_SYNCS) \ 164 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ 165 if (ENABLE_WA_INDIRECT_CALLS) \ 166 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \ 167 if (ENABLE_WA_RETS) \ 168 builtin_define ("__WORKAROUND_RETS"); \ 169 \ 170 if (TARGET_FDPIC) \ 171 { \ 172 builtin_define ("__BFIN_FDPIC__"); \ 173 builtin_define ("__FDPIC__"); \ 174 } \ 175 if (TARGET_ID_SHARED_LIBRARY \ 176 && !TARGET_SEP_DATA) \ 177 builtin_define ("__ID_SHARED_LIB__"); \ 178 if (flag_no_builtin) \ 179 builtin_define ("__NO_BUILTIN"); \ 180 if (TARGET_MULTICORE) \ 181 builtin_define ("__BFIN_MULTICORE"); \ 182 if (TARGET_COREA) \ 183 builtin_define ("__BFIN_COREA"); \ 184 if (TARGET_COREB) \ 185 builtin_define ("__BFIN_COREB"); \ 186 if (TARGET_SDRAM) \ 187 builtin_define ("__BFIN_SDRAM"); \ 188 } \ 189 while (0) 190 #endif 191 192 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 193 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ 194 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 195 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 196 " 197 #ifndef SUBTARGET_DRIVER_SELF_SPECS 198 # define SUBTARGET_DRIVER_SELF_SPECS 199 #endif 200 201 #define LINK_GCC_C_SEQUENCE_SPEC "\ 202 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \ 203 " 204 205 #undef ASM_SPEC 206 #define ASM_SPEC "\ 207 %{mno-fdpic:-mnopic} %{mfdpic}" 208 209 #define LINK_SPEC "\ 210 %{h*} %{v:-V} \ 211 %{mfdpic:-melf32bfinfd -z text} \ 212 %{static:-dn -Bstatic} \ 213 %{shared:-G -Bdynamic} \ 214 %{symbolic:-Bsymbolic} \ 215 -init __init -fini __fini " 216 217 /* Generate DSP instructions, like DSP halfword loads */ 218 #define TARGET_DSP (1) 219 220 #define TARGET_DEFAULT 0 221 222 /* Maximum number of library ids we permit */ 223 #define MAX_LIBRARY_ID 255 224 225 extern const char *bfin_library_id_string; 226 227 #define FUNCTION_MODE SImode 228 #define Pmode SImode 229 230 /* store-condition-codes instructions store 0 for false 231 This is the value stored for true. */ 232 #define STORE_FLAG_VALUE 1 233 234 /* Define this if pushing a word on the stack 235 makes the stack pointer a smaller address. */ 236 #define STACK_GROWS_DOWNWARD 1 237 238 #define STACK_PUSH_CODE PRE_DEC 239 240 /* Define this to nonzero if the nominal address of the stack frame 241 is at the high-address end of the local variables; 242 that is, each additional local variable allocated 243 goes at a more negative offset in the frame. */ 244 #define FRAME_GROWS_DOWNWARD 1 245 246 /* We define a dummy ARGP register; the parameters start at offset 0 from 247 it. */ 248 #define FIRST_PARM_OFFSET(DECL) 0 249 250 /* Offset within stack frame to start allocating local variables at. 251 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 252 first local allocated. Otherwise, it is the offset to the BEGINNING 253 of the first local allocated. */ 254 #define STARTING_FRAME_OFFSET 0 255 256 /* Register to use for pushing function arguments. */ 257 #define STACK_POINTER_REGNUM REG_P6 258 259 /* Base register for access to local variables of the function. */ 260 #define FRAME_POINTER_REGNUM REG_P7 261 262 /* A dummy register that will be eliminated to either FP or SP. */ 263 #define ARG_POINTER_REGNUM REG_ARGP 264 265 /* `PIC_OFFSET_TABLE_REGNUM' 266 The register number of the register used to address a table of 267 static data addresses in memory. In some cases this register is 268 defined by a processor's "application binary interface" (ABI). 269 When this macro is defined, RTL is generated for this register 270 once, as with the stack pointer and frame pointer registers. If 271 this macro is not defined, it is up to the machine-dependent files 272 to allocate such a register (if necessary). */ 273 #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 274 275 #define FDPIC_FPTR_REGNO REG_P1 276 #define FDPIC_REGNO REG_P3 277 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 278 279 /* A static chain register for nested functions. We need to use a 280 call-clobbered register for this. */ 281 #define STATIC_CHAIN_REGNUM REG_P2 282 283 /* Define this if functions should assume that stack space has been 284 allocated for arguments even when their values are passed in 285 registers. 286 287 The value of this macro is the size, in bytes, of the area reserved for 288 arguments passed in registers. 289 290 This space can either be allocated by the caller or be a part of the 291 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 292 says which. */ 293 #define FIXED_STACK_AREA 12 294 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 295 296 /* Define this if the above stack space is to be considered part of the 297 * space allocated by the caller. */ 298 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 299 300 /* Define this if the maximum size of all the outgoing args is to be 301 accumulated and pushed during the prologue. The amount can be 302 found in the variable crtl->outgoing_args_size. */ 303 #define ACCUMULATE_OUTGOING_ARGS 1 304 305 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 306 307 /* If defined, a C expression to compute the alignment for a local 308 variable. TYPE is the data type, and ALIGN is the alignment that 309 the object would ordinarily have. The value of this macro is used 310 instead of that alignment to align the object. 311 312 If this macro is not defined, then ALIGN is used. 313 314 One use of this macro is to increase alignment of medium-size 315 data to make it all fit in fewer cache lines. */ 316 317 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) 318 319 /* Make strings word-aligned so strcpy from constants will be faster. */ 320 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 321 (TREE_CODE (EXP) == STRING_CST \ 322 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 323 324 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 325 326 /* Definitions for register eliminations. 328 329 This is an array of structures. Each structure initializes one pair 330 of eliminable registers. The "from" register number is given first, 331 followed by "to". Eliminations of the same "from" register are listed 332 in order of preference. 333 334 There are two registers that can always be eliminated on the i386. 335 The frame pointer and the arg pointer can be replaced by either the 336 hard frame pointer or to the stack pointer, depending upon the 337 circumstances. The hard frame pointer is not used before reload and 338 so it is not eligible for elimination. */ 339 340 #define ELIMINABLE_REGS \ 341 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 342 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 343 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 344 345 /* Define the offset between two registers, one to be eliminated, and the other 346 its replacement, at the start of a routine. */ 347 348 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 349 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 350 351 /* This processor has 353 8 data register for doing arithmetic 354 8 pointer register for doing addressing, including 355 1 stack pointer P6 356 1 frame pointer P7 357 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 358 1 condition code flag register CC 359 5 return address registers RETS/I/X/N/E 360 1 arithmetic status register (ASTAT). */ 361 362 #define FIRST_PSEUDO_REGISTER 50 363 364 #define D_REGNO_P(X) ((X) <= REG_R7) 365 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 366 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 367 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 368 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 369 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 370 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 371 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 372 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 373 374 #define REGISTER_NAMES { \ 375 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 376 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 377 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 378 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 379 "A0", "A1", \ 380 "CC", \ 381 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 382 "ARGP", \ 383 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 384 } 385 386 #define SHORT_REGISTER_NAMES { \ 387 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 388 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 389 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 390 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 391 392 #define HIGH_REGISTER_NAMES { \ 393 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 394 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 395 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 396 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 397 398 #define DREGS_PAIR_NAMES { \ 399 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 400 401 #define BYTE_REGISTER_NAMES { \ 402 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 403 404 405 /* 1 for registers that have pervasive standard uses 406 and are not available for the register allocator. */ 407 408 #define FIXED_REGISTERS \ 409 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 410 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 411 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 412 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 413 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 414 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 415 /*lb0/1 */ \ 416 1, 1 \ 417 } 418 419 /* 1 for registers not available across function calls. 420 These must include the FIXED_REGISTERS and also any 421 registers that can be used without being saved. 422 The latter must include the registers where values are returned 423 and the register where structure-value addresses are passed. 424 Aside from that, you can include as many other registers as you like. */ 425 426 #define CALL_USED_REGISTERS \ 427 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 428 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 429 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 430 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 431 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 432 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 433 /*lb0/1 */ \ 434 1, 1 \ 435 } 436 437 /* Order in which to allocate registers. Each register must be 438 listed once, even those in FIXED_REGISTERS. List frame pointer 439 late and fixed registers last. Note that, in general, we prefer 440 registers listed in CALL_USED_REGISTERS, keeping the others 441 available for storage of persistent values. */ 442 443 #define REG_ALLOC_ORDER \ 444 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 445 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 446 REG_A0, REG_A1, \ 447 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 448 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 449 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 450 REG_ASTAT, REG_SEQSTAT, REG_USP, \ 451 REG_CC, REG_ARGP, \ 452 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 453 } 454 455 /* Define the classes of registers for register constraints in the 456 machine description. Also define ranges of constants. 457 458 One of the classes must always be named ALL_REGS and include all hard regs. 459 If there is more than one class, another class must be named NO_REGS 460 and contain no registers. 461 462 The name GENERAL_REGS must be the name of a class (or an alias for 463 another name such as ALL_REGS). This is the class of registers 464 that is allowed by "g" or "r" in a register constraint. 465 Also, registers outside this class are allocated only when 466 instructions express preferences for them. 467 468 The classes must be numbered in nondecreasing order; that is, 469 a larger-numbered class must never be contained completely 470 in a smaller-numbered class. 471 472 For any two classes, it is very desirable that there be another 473 class that represents their union. */ 474 475 476 enum reg_class 477 { 478 NO_REGS, 479 IREGS, 480 BREGS, 481 LREGS, 482 MREGS, 483 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 484 DAGREGS, 485 EVEN_AREGS, 486 ODD_AREGS, 487 AREGS, 488 CCREGS, 489 EVEN_DREGS, 490 ODD_DREGS, 491 D0REGS, 492 D1REGS, 493 D2REGS, 494 D3REGS, 495 D4REGS, 496 D5REGS, 497 D6REGS, 498 D7REGS, 499 DREGS, 500 P0REGS, 501 FDPIC_REGS, 502 FDPIC_FPTR_REGS, 503 PREGS_CLOBBERED, 504 PREGS, 505 IPREGS, 506 DPREGS, 507 MOST_REGS, 508 LT_REGS, 509 LC_REGS, 510 LB_REGS, 511 PROLOGUE_REGS, 512 NON_A_CC_REGS, 513 ALL_REGS, LIM_REG_CLASSES 514 }; 515 516 #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 517 518 #define GENERAL_REGS DPREGS 519 520 /* Give names of register classes as strings for dump file. */ 521 522 #define REG_CLASS_NAMES \ 523 { "NO_REGS", \ 524 "IREGS", \ 525 "BREGS", \ 526 "LREGS", \ 527 "MREGS", \ 528 "CIRCREGS", \ 529 "DAGREGS", \ 530 "EVEN_AREGS", \ 531 "ODD_AREGS", \ 532 "AREGS", \ 533 "CCREGS", \ 534 "EVEN_DREGS", \ 535 "ODD_DREGS", \ 536 "D0REGS", \ 537 "D1REGS", \ 538 "D2REGS", \ 539 "D3REGS", \ 540 "D4REGS", \ 541 "D5REGS", \ 542 "D6REGS", \ 543 "D7REGS", \ 544 "DREGS", \ 545 "P0REGS", \ 546 "FDPIC_REGS", \ 547 "FDPIC_FPTR_REGS", \ 548 "PREGS_CLOBBERED", \ 549 "PREGS", \ 550 "IPREGS", \ 551 "DPREGS", \ 552 "MOST_REGS", \ 553 "LT_REGS", \ 554 "LC_REGS", \ 555 "LB_REGS", \ 556 "PROLOGUE_REGS", \ 557 "NON_A_CC_REGS", \ 558 "ALL_REGS" } 559 560 /* An initializer containing the contents of the register classes, as integers 561 which are bit masks. The Nth integer specifies the contents of class N. 562 The way the integer MASK is interpreted is that register R is in the class 563 if `MASK & (1 << R)' is 1. 564 565 When the machine has more than 32 registers, an integer does not suffice. 566 Then the integers are replaced by sub-initializers, braced groupings 567 containing several integers. Each sub-initializer must be suitable as an 568 initializer for the type `HARD_REG_SET' which is defined in 569 `hard-reg-set.h'. */ 570 571 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 572 MOST_REGS as the union of DPREGS and DAGREGS. */ 573 574 #define REG_CLASS_CONTENTS \ 575 /* 31 - 0 63-32 */ \ 576 { { 0x00000000, 0 }, /* NO_REGS */ \ 577 { 0x000f0000, 0 }, /* IREGS */ \ 578 { 0x00f00000, 0 }, /* BREGS */ \ 579 { 0x0f000000, 0 }, /* LREGS */ \ 580 { 0xf0000000, 0 }, /* MREGS */ \ 581 { 0x0fff0000, 0 }, /* CIRCREGS */ \ 582 { 0xffff0000, 0 }, /* DAGREGS */ \ 583 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 584 { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 585 { 0x00000000, 0x3 }, /* AREGS */ \ 586 { 0x00000000, 0x4 }, /* CCREGS */ \ 587 { 0x00000055, 0 }, /* EVEN_DREGS */ \ 588 { 0x000000aa, 0 }, /* ODD_DREGS */ \ 589 { 0x00000001, 0 }, /* D0REGS */ \ 590 { 0x00000002, 0 }, /* D1REGS */ \ 591 { 0x00000004, 0 }, /* D2REGS */ \ 592 { 0x00000008, 0 }, /* D3REGS */ \ 593 { 0x00000010, 0 }, /* D4REGS */ \ 594 { 0x00000020, 0 }, /* D5REGS */ \ 595 { 0x00000040, 0 }, /* D6REGS */ \ 596 { 0x00000080, 0 }, /* D7REGS */ \ 597 { 0x000000ff, 0 }, /* DREGS */ \ 598 { 0x00000100, 0x000 }, /* P0REGS */ \ 599 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 600 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 601 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 602 { 0x0000ff00, 0x800 }, /* PREGS */ \ 603 { 0x000fff00, 0x800 }, /* IPREGS */ \ 604 { 0x0000ffff, 0x800 }, /* DPREGS */ \ 605 { 0xffffffff, 0x800 }, /* MOST_REGS */\ 606 { 0x00000000, 0x3000 }, /* LT_REGS */\ 607 { 0x00000000, 0xc000 }, /* LC_REGS */\ 608 { 0x00000000, 0x30000 }, /* LB_REGS */\ 609 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 610 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 611 { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 612 613 #define IREG_POSSIBLE_P(OUTER) \ 614 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 615 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 616 || (OUTER) == MEM || (OUTER) == ADDRESS) 617 618 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ 619 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 620 621 #define INDEX_REG_CLASS PREGS 622 623 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 624 (P_REGNO_P (X) || (X) == REG_ARGP \ 625 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 626 && I_REGNO_P (X))) 627 628 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 629 ((X) >= FIRST_PSEUDO_REGISTER \ 630 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 631 632 #ifdef REG_OK_STRICT 633 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 634 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 635 #else 636 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 637 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 638 #endif 639 640 #define REGNO_OK_FOR_INDEX_P(X) 0 641 642 /* The same information, inverted: 643 Return the class number of the smallest class containing 644 reg number REGNO. This could be a conditional expression 645 or could index an array. */ 646 647 #define REGNO_REG_CLASS(REGNO) \ 648 ((REGNO) == REG_R0 ? D0REGS \ 649 : (REGNO) == REG_R1 ? D1REGS \ 650 : (REGNO) == REG_R2 ? D2REGS \ 651 : (REGNO) == REG_R3 ? D3REGS \ 652 : (REGNO) == REG_R4 ? D4REGS \ 653 : (REGNO) == REG_R5 ? D5REGS \ 654 : (REGNO) == REG_R6 ? D6REGS \ 655 : (REGNO) == REG_R7 ? D7REGS \ 656 : (REGNO) == REG_P0 ? P0REGS \ 657 : (REGNO) < REG_I0 ? PREGS \ 658 : (REGNO) == REG_ARGP ? PREGS \ 659 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 660 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 661 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 662 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 663 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 664 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 665 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 666 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 667 : (REGNO) == REG_CC ? CCREGS \ 668 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 669 : NO_REGS) 670 671 /* When this hook returns true for MODE, the compiler allows 672 registers explicitly used in the rtl to be used as spill registers 673 but prevents the compiler from extending the lifetime of these 674 registers. */ 675 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 676 677 /* Do not allow to store a value in REG_CC for any mode */ 678 /* Do not allow to store value in pregs if mode is not SI*/ 679 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 680 681 /* Return the maximum number of consecutive registers 682 needed to represent mode MODE in a register of class CLASS. */ 683 #define CLASS_MAX_NREGS(CLASS, MODE) \ 684 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 685 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 686 687 #define HARD_REGNO_NREGS(REGNO, MODE) \ 688 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ 689 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ 690 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) 691 692 /* A C expression that is nonzero if hard register TO can be 693 considered for use as a rename register for FROM register */ 694 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 695 696 /* A C expression that is nonzero if it is desirable to choose 697 register allocation so as to avoid move instructions between a 698 value of mode MODE1 and a value of mode MODE2. 699 700 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 701 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 702 MODE2)' must be zero. */ 703 #define MODES_TIEABLE_P(MODE1, MODE2) \ 704 ((MODE1) == (MODE2) \ 705 || ((GET_MODE_CLASS (MODE1) == MODE_INT \ 706 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \ 707 && (GET_MODE_CLASS (MODE2) == MODE_INT \ 708 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \ 709 && (MODE1) != BImode && (MODE2) != BImode \ 710 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 711 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)) 712 713 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 714 A C expression that places additional restrictions on the register 715 class to use when it is necessary to copy value X into a register 716 in class CLASS. The value is a register class; perhaps CLASS, or 717 perhaps another, smaller class. */ 718 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 719 (GET_CODE (X) == POST_INC \ 720 || GET_CODE (X) == POST_DEC \ 721 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) 722 723 /* Function Calling Conventions. */ 724 725 /* The type of the current function; normal functions are of type 726 SUBROUTINE. */ 727 typedef enum { 728 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 729 } e_funkind; 730 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN } 731 732 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 733 734 /* Flags for the call/call_value rtl operations set up by function_arg */ 735 #define CALL_NORMAL 0x00000000 /* no special processing */ 736 #define CALL_LONG 0x00000001 /* always call indirect */ 737 #define CALL_SHORT 0x00000002 /* always call by symbol */ 738 739 typedef struct { 740 int words; /* # words passed so far */ 741 int nregs; /* # registers available for passing */ 742 int *arg_regs; /* array of register -1 terminated */ 743 int call_cookie; /* Do special things for this call */ 744 } CUMULATIVE_ARGS; 745 746 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 747 748 749 /* Initialize a variable CUM of type CUMULATIVE_ARGS 750 for a call to a function whose data type is FNTYPE. 751 For a library call, FNTYPE is 0. */ 752 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 753 (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 754 755 /* Define how to find the value returned by a function. 756 VALTYPE is the data type of the value (as a tree). 757 If the precise function being called is known, FUNC is its FUNCTION_DECL; 758 otherwise, FUNC is 0. 759 */ 760 761 #define VALUE_REGNO(MODE) (REG_R0) 762 763 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 764 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 765 VALUE_REGNO(TYPE_MODE(VALTYPE))) 766 767 /* Define how to find the value returned by a library function 768 assuming the value has mode MODE. */ 769 770 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 771 772 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 773 774 #define DEFAULT_PCC_STRUCT_RETURN 0 775 776 /* Before the prologue, the return address is in the RETS register. */ 777 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 778 779 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 780 781 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 782 783 /* Call instructions don't modify the stack pointer on the Blackfin. */ 784 #define INCOMING_FRAME_SP_OFFSET 0 785 786 /* Describe how we implement __builtin_eh_return. */ 787 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 788 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 789 #define EH_RETURN_HANDLER_RTX \ 790 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \ 791 UNITS_PER_WORD)) 792 793 /* Addressing Modes */ 794 795 /* A number, the maximum number of registers that can appear in a 796 valid memory address. Note that it is up to you to specify a 797 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' 798 would ever accept. */ 799 #define MAX_REGS_PER_ADDRESS 1 800 801 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 802 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 803 804 #define HAVE_POST_INCREMENT 1 805 #define HAVE_POST_DECREMENT 1 806 #define HAVE_PRE_DECREMENT 1 807 808 /* `LEGITIMATE_PIC_OPERAND_P (X)' 809 A C expression that is nonzero if X is a legitimate immediate 810 operand on the target machine when generating position independent 811 code. You can assume that X satisfies `CONSTANT_P', so you need 812 not check this. You can also assume FLAG_PIC is true, so you need 813 not check it either. You need not define this macro if all 814 constants (including `SYMBOL_REF') can be immediate operands when 815 generating position independent code. */ 816 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 817 818 #define SYMBOLIC_CONST(X) \ 819 (GET_CODE (X) == SYMBOL_REF \ 820 || GET_CODE (X) == LABEL_REF \ 821 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 822 823 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 824 825 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 826 is done just by pretending it is already truncated. */ 827 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 828 829 /* Max number of bytes we can move from memory to memory 830 in one reasonably fast instruction. */ 831 #define MOVE_MAX UNITS_PER_WORD 832 833 /* If a memory-to-memory move would take MOVE_RATIO or more simple 834 move-instruction pairs, we will do a movmem or libcall instead. */ 835 836 #define MOVE_RATIO(speed) 5 837 838 /* STORAGE LAYOUT: target machine storage layout 839 Define this macro as a C expression which is nonzero if accessing 840 less than a word of memory (i.e. a `char' or a `short') is no 841 faster than accessing a word of memory, i.e., if such access 842 require more than one instruction or if there is no difference in 843 cost between byte and (aligned) word loads. 844 845 When this macro is not defined, the compiler will access a field by 846 finding the smallest containing object; when it is defined, a 847 fullword load will be used if alignment permits. Unless bytes 848 accesses are faster than word accesses, using word accesses is 849 preferable since it may eliminate subsequent memory access if 850 subsequent accesses occur to other fields in the same word of the 851 structure, but to different bytes. */ 852 #define SLOW_BYTE_ACCESS 0 853 #define SLOW_SHORT_ACCESS 0 854 855 /* Define this if most significant bit is lowest numbered 856 in instructions that operate on numbered bit-fields. */ 857 #define BITS_BIG_ENDIAN 0 858 859 /* Define this if most significant byte of a word is the lowest numbered. 860 We can't access bytes but if we could we would in the Big Endian order. */ 861 #define BYTES_BIG_ENDIAN 0 862 863 /* Define this if most significant word of a multiword number is numbered. */ 864 #define WORDS_BIG_ENDIAN 0 865 866 /* Width in bits of a "word", which is the contents of a machine register. 867 Note that this is not necessarily the width of data type `int'; 868 if using 16-bit ints on a 68000, this would still be 32. 869 But on a machine with 16-bit registers, this would be 16. */ 870 #define BITS_PER_WORD 32 871 872 /* Width of a word, in units (bytes). */ 873 #define UNITS_PER_WORD 4 874 875 /* Width in bits of a pointer. 876 See also the macro `Pmode1' defined below. */ 877 #define POINTER_SIZE 32 878 879 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 880 #define POINTER_BOUNDARY 32 881 882 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 883 #define PARM_BOUNDARY 32 884 885 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 886 #define STACK_BOUNDARY 32 887 888 /* Allocation boundary (in *bits*) for the code of a function. */ 889 #define FUNCTION_BOUNDARY 32 890 891 /* Alignment of field after `int : 0' in a structure. */ 892 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 893 894 /* No data type wants to be aligned rounder than this. */ 895 #define BIGGEST_ALIGNMENT 32 896 897 /* Define this if move instructions will actually fail to work 898 when given unaligned data. */ 899 #define STRICT_ALIGNMENT 1 900 901 /* (shell-command "rm c-decl.o stor-layout.o") 902 * never define PCC_BITFIELD_TYPE_MATTERS 903 * really cause some alignment problem 904 */ 905 906 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 907 BITS_PER_UNIT) 908 909 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 910 BITS_PER_UNIT) 911 912 913 /* what is the 'type' of size_t */ 914 #define SIZE_TYPE "long unsigned int" 915 916 /* Define this as 1 if `char' should by default be signed; else as 0. */ 917 #define DEFAULT_SIGNED_CHAR 1 918 #define FLOAT_TYPE_SIZE BITS_PER_WORD 919 #define SHORT_TYPE_SIZE 16 920 #define CHAR_TYPE_SIZE 8 921 #define INT_TYPE_SIZE 32 922 #define LONG_TYPE_SIZE 32 923 #define LONG_LONG_TYPE_SIZE 64 924 925 /* Note: Fix this to depend on target switch. -- lev */ 926 927 /* Note: Try to implement double and force long double. -- tonyko 928 * #define __DOUBLES_ARE_FLOATS__ 929 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 930 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 931 * #define DOUBLES_ARE_FLOATS 1 932 */ 933 934 #define DOUBLE_TYPE_SIZE 64 935 #define LONG_DOUBLE_TYPE_SIZE 64 936 937 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 938 A macro to update M and UNSIGNEDP when an object whose type is 939 TYPE and which has the specified mode and signedness is to be 940 stored in a register. This macro is only called when TYPE is a 941 scalar type. 942 943 On most RISC machines, which only have operations that operate on 944 a full register, define this macro to set M to `word_mode' if M is 945 an integer mode narrower than `BITS_PER_WORD'. In most cases, 946 only integer modes should be widened because wider-precision 947 floating-point operations are usually more expensive than their 948 narrower counterparts. 949 950 For most machines, the macro definition does not change UNSIGNEDP. 951 However, some machines, have instructions that preferentially 952 handle either signed or unsigned quantities of certain modes. For 953 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 954 instructions sign-extend the result to 64 bits. On such machines, 955 set UNSIGNEDP according to which kind of extension is more 956 efficient. 957 958 Do not define this macro if it would never modify M.*/ 959 960 #define BFIN_PROMOTE_MODE_P(MODE) \ 961 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 962 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 963 964 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 965 if (BFIN_PROMOTE_MODE_P(MODE)) \ 966 { \ 967 if (MODE == QImode) \ 968 UNSIGNEDP = 1; \ 969 else if (MODE == HImode) \ 970 UNSIGNEDP = 0; \ 971 (MODE) = SImode; \ 972 } 973 974 /* Describing Relative Costs of Operations */ 975 976 /* Do not put function addr into constant pool */ 977 #define NO_FUNCTION_CSE 1 978 979 /* Specify the machine mode that this machine uses 980 for the index in the tablejump instruction. */ 981 #define CASE_VECTOR_MODE SImode 982 983 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 984 985 /* Define if operations between registers always perform the operation 986 on the full register even if a narrower mode is specified. 987 #define WORD_REGISTER_OPERATIONS 1 988 */ 989 990 /* Evaluates to true if A and B are mac flags that can be used 991 together in a single multiply insn. That is the case if they are 992 both the same flag not involving M, or if one is a combination of 993 the other with M. */ 994 #define MACFLAGS_MATCH_P(A, B) \ 995 ((A) == (B) \ 996 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ 997 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ 998 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ 999 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) 1000 1001 /* Switch into a generic section. */ 1002 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 1003 1004 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 1005 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 1006 1007 typedef enum sections { 1008 CODE_DIR, 1009 DATA_DIR, 1010 LAST_SECT_NM 1011 } SECT_ENUM_T; 1012 1013 typedef enum directives { 1014 LONG_CONST_DIR, 1015 SHORT_CONST_DIR, 1016 BYTE_CONST_DIR, 1017 SPACE_DIR, 1018 INIT_DIR, 1019 LAST_DIR_NM 1020 } DIR_ENUM_T; 1021 1022 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ 1023 ((C) == ';' \ 1024 || ((C) == '|' && (STR)[1] == '|')) 1025 1026 #define TEXT_SECTION_ASM_OP ".text;" 1027 #define DATA_SECTION_ASM_OP ".data;" 1028 1029 #define ASM_APP_ON "" 1030 #define ASM_APP_OFF "" 1031 1032 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 1033 do { fputs (".global ", FILE); \ 1034 assemble_name (FILE, NAME); \ 1035 fputc (';',FILE); \ 1036 fputc ('\n',FILE); \ 1037 } while (0) 1038 1039 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1040 do { \ 1041 fputs (".type ", FILE); \ 1042 assemble_name (FILE, NAME); \ 1043 fputs (", STT_FUNC", FILE); \ 1044 fputc (';',FILE); \ 1045 fputc ('\n',FILE); \ 1046 ASM_OUTPUT_LABEL(FILE, NAME); \ 1047 } while (0) 1048 1049 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1050 do { assemble_name (FILE, NAME); \ 1051 fputs (":\n",FILE); \ 1052 } while (0) 1053 1054 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1055 do { fprintf (FILE, "_%s", NAME); \ 1056 } while (0) 1057 1058 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1059 do { char __buf[256]; \ 1060 fprintf (FILE, "\t.dd\t"); \ 1061 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1062 assemble_name (FILE, __buf); \ 1063 fputc (';', FILE); \ 1064 fputc ('\n', FILE); \ 1065 } while (0) 1066 1067 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1068 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1069 1070 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1071 do { \ 1072 char __buf[256]; \ 1073 fprintf (FILE, "\t.dd\t"); \ 1074 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1075 assemble_name (FILE, __buf); \ 1076 fputs (" - ", FILE); \ 1077 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1078 assemble_name (FILE, __buf); \ 1079 fputc (';', FILE); \ 1080 fputc ('\n', FILE); \ 1081 } while (0) 1082 1083 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1084 do { \ 1085 if ((LOG) != 0) \ 1086 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1087 } while (0) 1088 1089 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1090 do { \ 1091 asm_output_skip (FILE, SIZE); \ 1092 } while (0) 1093 1094 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1095 do { \ 1096 switch_to_section (data_section); \ 1097 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1098 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1099 ASM_OUTPUT_LABEL (FILE, NAME); \ 1100 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1101 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1102 } while (0) 1103 1104 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1105 do { \ 1106 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1107 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1108 1109 #define ASM_COMMENT_START "//" 1110 1111 #define PROFILE_BEFORE_PROLOGUE 1112 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1113 do { \ 1114 fprintf (FILE, "\t[--SP] = RETS;\n"); \ 1115 if (TARGET_LONG_CALLS) \ 1116 { \ 1117 fprintf (FILE, "\tP2.h = __mcount;\n"); \ 1118 fprintf (FILE, "\tP2.l = __mcount;\n"); \ 1119 fprintf (FILE, "\tCALL (P2);\n"); \ 1120 } \ 1121 else \ 1122 fprintf (FILE, "\tCALL __mcount;\n"); \ 1123 fprintf (FILE, "\tRETS = [SP++];\n"); \ 1124 } while(0) 1125 1126 #undef NO_PROFILE_COUNTERS 1127 #define NO_PROFILE_COUNTERS 1 1128 1129 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO]) 1130 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO]) 1131 1132 extern rtx bfin_cc_rtx, bfin_rets_rtx; 1133 1134 /* This works for GAS and some other assemblers. */ 1135 #define SET_ASM_OP ".set " 1136 1137 /* DBX register number for a given compiler register number */ 1138 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1139 1140 #define SIZE_ASM_OP "\t.size\t" 1141 1142 extern int splitting_for_sched, splitting_loops; 1143 1144 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') 1145 1146 #ifndef TARGET_SUPPORTS_SYNC_CALLS 1147 #define TARGET_SUPPORTS_SYNC_CALLS 0 1148 #endif 1149 1150 struct bfin_cpu 1151 { 1152 const char *name; 1153 bfin_cpu_t type; 1154 int si_revision; 1155 unsigned int workarounds; 1156 }; 1157 1158 extern const struct bfin_cpu bfin_cpus[]; 1159 1160 #endif /* _BFIN_CONFIG */ 1161
Indexes created Sun Apr 19 00:22:55 UTC 2026