bfin.h revision 1.8
1 /* Definitions for the Blackfin port. 2 Copyright (C) 2005-2017 Free Software Foundation, Inc. 3 Contributed by Analog Devices. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef _BFIN_CONFIG 22 #define _BFIN_CONFIG 23 24 #ifndef BFIN_OPTS_H 25 #include "config/bfin/bfin-opts.h" 26 #endif 27 28 #define OBJECT_FORMAT_ELF 29 30 #define BRT 1 31 #define BRF 0 32 33 /* Predefinition in the preprocessor for this target machine */ 34 #ifndef TARGET_CPU_CPP_BUILTINS 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do \ 37 { \ 38 builtin_define_std ("bfin"); \ 39 builtin_define_std ("BFIN"); \ 40 builtin_define ("__ADSPBLACKFIN__"); \ 41 builtin_define ("__ADSPLPBLACKFIN__"); \ 42 \ 43 switch (bfin_cpu_type) \ 44 { \ 45 case BFIN_CPU_UNKNOWN: \ 46 break; \ 47 case BFIN_CPU_BF512: \ 48 builtin_define ("__ADSPBF512__"); \ 49 builtin_define ("__ADSPBF51x__"); \ 50 break; \ 51 case BFIN_CPU_BF514: \ 52 builtin_define ("__ADSPBF514__"); \ 53 builtin_define ("__ADSPBF51x__"); \ 54 break; \ 55 case BFIN_CPU_BF516: \ 56 builtin_define ("__ADSPBF516__"); \ 57 builtin_define ("__ADSPBF51x__"); \ 58 break; \ 59 case BFIN_CPU_BF518: \ 60 builtin_define ("__ADSPBF518__"); \ 61 builtin_define ("__ADSPBF51x__"); \ 62 break; \ 63 case BFIN_CPU_BF522: \ 64 builtin_define ("__ADSPBF522__"); \ 65 builtin_define ("__ADSPBF52x__"); \ 66 break; \ 67 case BFIN_CPU_BF523: \ 68 builtin_define ("__ADSPBF523__"); \ 69 builtin_define ("__ADSPBF52x__"); \ 70 break; \ 71 case BFIN_CPU_BF524: \ 72 builtin_define ("__ADSPBF524__"); \ 73 builtin_define ("__ADSPBF52x__"); \ 74 break; \ 75 case BFIN_CPU_BF525: \ 76 builtin_define ("__ADSPBF525__"); \ 77 builtin_define ("__ADSPBF52x__"); \ 78 break; \ 79 case BFIN_CPU_BF526: \ 80 builtin_define ("__ADSPBF526__"); \ 81 builtin_define ("__ADSPBF52x__"); \ 82 break; \ 83 case BFIN_CPU_BF527: \ 84 builtin_define ("__ADSPBF527__"); \ 85 builtin_define ("__ADSPBF52x__"); \ 86 break; \ 87 case BFIN_CPU_BF531: \ 88 builtin_define ("__ADSPBF531__"); \ 89 break; \ 90 case BFIN_CPU_BF532: \ 91 builtin_define ("__ADSPBF532__"); \ 92 break; \ 93 case BFIN_CPU_BF533: \ 94 builtin_define ("__ADSPBF533__"); \ 95 break; \ 96 case BFIN_CPU_BF534: \ 97 builtin_define ("__ADSPBF534__"); \ 98 break; \ 99 case BFIN_CPU_BF536: \ 100 builtin_define ("__ADSPBF536__"); \ 101 break; \ 102 case BFIN_CPU_BF537: \ 103 builtin_define ("__ADSPBF537__"); \ 104 break; \ 105 case BFIN_CPU_BF538: \ 106 builtin_define ("__ADSPBF538__"); \ 107 break; \ 108 case BFIN_CPU_BF539: \ 109 builtin_define ("__ADSPBF539__"); \ 110 break; \ 111 case BFIN_CPU_BF542M: \ 112 builtin_define ("__ADSPBF542M__"); \ 113 /* FALLTHRU */ \ 114 case BFIN_CPU_BF542: \ 115 builtin_define ("__ADSPBF542__"); \ 116 builtin_define ("__ADSPBF54x__"); \ 117 break; \ 118 case BFIN_CPU_BF544M: \ 119 builtin_define ("__ADSPBF544M__"); \ 120 /* FALLTHRU */ \ 121 case BFIN_CPU_BF544: \ 122 builtin_define ("__ADSPBF544__"); \ 123 builtin_define ("__ADSPBF54x__"); \ 124 break; \ 125 case BFIN_CPU_BF547M: \ 126 builtin_define ("__ADSPBF547M__"); \ 127 /* FALLTHRU */ \ 128 case BFIN_CPU_BF547: \ 129 builtin_define ("__ADSPBF547__"); \ 130 builtin_define ("__ADSPBF54x__"); \ 131 break; \ 132 case BFIN_CPU_BF548M: \ 133 builtin_define ("__ADSPBF548M__"); \ 134 /* FALLTHRU */ \ 135 case BFIN_CPU_BF548: \ 136 builtin_define ("__ADSPBF548__"); \ 137 builtin_define ("__ADSPBF54x__"); \ 138 break; \ 139 case BFIN_CPU_BF549M: \ 140 builtin_define ("__ADSPBF549M__"); \ 141 /* FALLTHRU */ \ 142 case BFIN_CPU_BF549: \ 143 builtin_define ("__ADSPBF549__"); \ 144 builtin_define ("__ADSPBF54x__"); \ 145 break; \ 146 case BFIN_CPU_BF561: \ 147 builtin_define ("__ADSPBF561__"); \ 148 break; \ 149 case BFIN_CPU_BF592: \ 150 builtin_define ("__ADSPBF592__"); \ 151 builtin_define ("__ADSPBF59x__"); \ 152 break; \ 153 } \ 154 \ 155 if (bfin_si_revision != -1) \ 156 { \ 157 /* space of 0xnnnn and a NUL */ \ 158 char *buf = XALLOCAVEC (char, 7); \ 159 \ 160 sprintf (buf, "0x%04x", bfin_si_revision); \ 161 builtin_define_with_value ("__SILICON_REVISION__", buf, 0); \ 162 } \ 163 \ 164 if (bfin_workarounds) \ 165 builtin_define ("__WORKAROUNDS_ENABLED"); \ 166 if (ENABLE_WA_SPECULATIVE_LOADS) \ 167 builtin_define ("__WORKAROUND_SPECULATIVE_LOADS"); \ 168 if (ENABLE_WA_SPECULATIVE_SYNCS) \ 169 builtin_define ("__WORKAROUND_SPECULATIVE_SYNCS"); \ 170 if (ENABLE_WA_INDIRECT_CALLS) \ 171 builtin_define ("__WORKAROUND_INDIRECT_CALLS"); \ 172 if (ENABLE_WA_RETS) \ 173 builtin_define ("__WORKAROUND_RETS"); \ 174 \ 175 if (TARGET_FDPIC) \ 176 { \ 177 builtin_define ("__BFIN_FDPIC__"); \ 178 builtin_define ("__FDPIC__"); \ 179 } \ 180 if (TARGET_ID_SHARED_LIBRARY \ 181 && !TARGET_SEP_DATA) \ 182 builtin_define ("__ID_SHARED_LIB__"); \ 183 if (flag_no_builtin) \ 184 builtin_define ("__NO_BUILTIN"); \ 185 if (TARGET_MULTICORE) \ 186 builtin_define ("__BFIN_MULTICORE"); \ 187 if (TARGET_COREA) \ 188 builtin_define ("__BFIN_COREA"); \ 189 if (TARGET_COREB) \ 190 builtin_define ("__BFIN_COREB"); \ 191 if (TARGET_SDRAM) \ 192 builtin_define ("__BFIN_SDRAM"); \ 193 } \ 194 while (0) 195 #endif 196 197 #define DRIVER_SELF_SPECS SUBTARGET_DRIVER_SELF_SPECS "\ 198 %{mleaf-id-shared-library:%{!mid-shared-library:-mid-shared-library}} \ 199 %{mfdpic:%{!fpic:%{!fpie:%{!fPIC:%{!fPIE:\ 200 %{!fno-pic:%{!fno-pie:%{!fno-PIC:%{!fno-PIE:-fpie}}}}}}}}} \ 201 " 202 #ifndef SUBTARGET_DRIVER_SELF_SPECS 203 # define SUBTARGET_DRIVER_SELF_SPECS 204 #endif 205 206 #define LINK_GCC_C_SEQUENCE_SPEC "\ 207 %{mfast-fp:-lbffastfp} %G %L %{mfast-fp:-lbffastfp} %G \ 208 " 209 210 #undef ASM_SPEC 211 #define ASM_SPEC "\ 212 %{mno-fdpic:-mnopic} %{mfdpic}" 213 214 #define LINK_SPEC "\ 215 %{h*} %{v:-V} \ 216 %{mfdpic:-melf32bfinfd -z text} \ 217 %{static:-dn -Bstatic} \ 218 %{shared:-G -Bdynamic} \ 219 %{symbolic:-Bsymbolic} \ 220 -init __init -fini __fini " 221 222 /* Generate DSP instructions, like DSP halfword loads */ 223 #define TARGET_DSP (1) 224 225 #define TARGET_DEFAULT 0 226 227 /* Maximum number of library ids we permit */ 228 #define MAX_LIBRARY_ID 255 229 230 extern const char *bfin_library_id_string; 231 232 #define FUNCTION_MODE SImode 233 #define Pmode SImode 234 235 /* store-condition-codes instructions store 0 for false 236 This is the value stored for true. */ 237 #define STORE_FLAG_VALUE 1 238 239 /* Define this if pushing a word on the stack 240 makes the stack pointer a smaller address. */ 241 #define STACK_GROWS_DOWNWARD 1 242 243 #define STACK_PUSH_CODE PRE_DEC 244 245 /* Define this to nonzero if the nominal address of the stack frame 246 is at the high-address end of the local variables; 247 that is, each additional local variable allocated 248 goes at a more negative offset in the frame. */ 249 #define FRAME_GROWS_DOWNWARD 1 250 251 /* We define a dummy ARGP register; the parameters start at offset 0 from 252 it. */ 253 #define FIRST_PARM_OFFSET(DECL) 0 254 255 /* Offset within stack frame to start allocating local variables at. 256 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 257 first local allocated. Otherwise, it is the offset to the BEGINNING 258 of the first local allocated. */ 259 #define STARTING_FRAME_OFFSET 0 260 261 /* Register to use for pushing function arguments. */ 262 #define STACK_POINTER_REGNUM REG_P6 263 264 /* Base register for access to local variables of the function. */ 265 #define FRAME_POINTER_REGNUM REG_P7 266 267 /* A dummy register that will be eliminated to either FP or SP. */ 268 #define ARG_POINTER_REGNUM REG_ARGP 269 270 /* `PIC_OFFSET_TABLE_REGNUM' 271 The register number of the register used to address a table of 272 static data addresses in memory. In some cases this register is 273 defined by a processor's "application binary interface" (ABI). 274 When this macro is defined, RTL is generated for this register 275 once, as with the stack pointer and frame pointer registers. If 276 this macro is not defined, it is up to the machine-dependent files 277 to allocate such a register (if necessary). */ 278 #define PIC_OFFSET_TABLE_REGNUM (REG_P5) 279 280 #define FDPIC_FPTR_REGNO REG_P1 281 #define FDPIC_REGNO REG_P3 282 #define OUR_FDPIC_REG get_hard_reg_initial_val (SImode, FDPIC_REGNO) 283 284 /* A static chain register for nested functions. We need to use a 285 call-clobbered register for this. */ 286 #define STATIC_CHAIN_REGNUM REG_P2 287 288 /* Define this if functions should assume that stack space has been 289 allocated for arguments even when their values are passed in 290 registers. 291 292 The value of this macro is the size, in bytes, of the area reserved for 293 arguments passed in registers. 294 295 This space can either be allocated by the caller or be a part of the 296 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' 297 says which. */ 298 #define FIXED_STACK_AREA 12 299 #define REG_PARM_STACK_SPACE(FNDECL) FIXED_STACK_AREA 300 301 /* Define this if the above stack space is to be considered part of the 302 * space allocated by the caller. */ 303 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 304 305 /* Define this if the maximum size of all the outgoing args is to be 306 accumulated and pushed during the prologue. The amount can be 307 found in the variable crtl->outgoing_args_size. */ 308 #define ACCUMULATE_OUTGOING_ARGS 1 309 310 /*#define DATA_ALIGNMENT(TYPE, BASIC-ALIGN) for arrays.. */ 311 312 /* If defined, a C expression to compute the alignment for a local 313 variable. TYPE is the data type, and ALIGN is the alignment that 314 the object would ordinarily have. The value of this macro is used 315 instead of that alignment to align the object. 316 317 If this macro is not defined, then ALIGN is used. 318 319 One use of this macro is to increase alignment of medium-size 320 data to make it all fit in fewer cache lines. */ 321 322 #define LOCAL_ALIGNMENT(TYPE, ALIGN) bfin_local_alignment ((TYPE), (ALIGN)) 323 324 /* Make strings word-aligned so strcpy from constants will be faster. */ 325 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 326 (TREE_CODE (EXP) == STRING_CST \ 327 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 328 329 #define TRAMPOLINE_SIZE (TARGET_FDPIC ? 30 : 18) 330 331 /* Definitions for register eliminations. 333 334 This is an array of structures. Each structure initializes one pair 335 of eliminable registers. The "from" register number is given first, 336 followed by "to". Eliminations of the same "from" register are listed 337 in order of preference. 338 339 There are two registers that can always be eliminated on the i386. 340 The frame pointer and the arg pointer can be replaced by either the 341 hard frame pointer or to the stack pointer, depending upon the 342 circumstances. The hard frame pointer is not used before reload and 343 so it is not eligible for elimination. */ 344 345 #define ELIMINABLE_REGS \ 346 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 347 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM}, \ 348 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}} \ 349 350 /* Define the offset between two registers, one to be eliminated, and the other 351 its replacement, at the start of a routine. */ 352 353 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 354 ((OFFSET) = bfin_initial_elimination_offset ((FROM), (TO))) 355 356 /* This processor has 358 8 data register for doing arithmetic 359 8 pointer register for doing addressing, including 360 1 stack pointer P6 361 1 frame pointer P7 362 4 sets of indexing registers (I0-3, B0-3, L0-3, M0-3) 363 1 condition code flag register CC 364 5 return address registers RETS/I/X/N/E 365 1 arithmetic status register (ASTAT). */ 366 367 #define FIRST_PSEUDO_REGISTER 50 368 369 #define D_REGNO_P(X) ((X) <= REG_R7) 370 #define P_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_P7) 371 #define I_REGNO_P(X) ((X) >= REG_I0 && (X) <= REG_I3) 372 #define DP_REGNO_P(X) (D_REGNO_P (X) || P_REGNO_P (X)) 373 #define ADDRESS_REGNO_P(X) ((X) >= REG_P0 && (X) <= REG_M3) 374 #define DREG_P(X) (REG_P (X) && D_REGNO_P (REGNO (X))) 375 #define PREG_P(X) (REG_P (X) && P_REGNO_P (REGNO (X))) 376 #define IREG_P(X) (REG_P (X) && I_REGNO_P (REGNO (X))) 377 #define DPREG_P(X) (REG_P (X) && DP_REGNO_P (REGNO (X))) 378 379 #define REGISTER_NAMES { \ 380 "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", \ 381 "P0", "P1", "P2", "P3", "P4", "P5", "SP", "FP", \ 382 "I0", "I1", "I2", "I3", "B0", "B1", "B2", "B3", \ 383 "L0", "L1", "L2", "L3", "M0", "M1", "M2", "M3", \ 384 "A0", "A1", \ 385 "CC", \ 386 "RETS", "RETI", "RETX", "RETN", "RETE", "ASTAT", "SEQSTAT", "USP", \ 387 "ARGP", \ 388 "LT0", "LT1", "LC0", "LC1", "LB0", "LB1" \ 389 } 390 391 #define SHORT_REGISTER_NAMES { \ 392 "R0.L", "R1.L", "R2.L", "R3.L", "R4.L", "R5.L", "R6.L", "R7.L", \ 393 "P0.L", "P1.L", "P2.L", "P3.L", "P4.L", "P5.L", "SP.L", "FP.L", \ 394 "I0.L", "I1.L", "I2.L", "I3.L", "B0.L", "B1.L", "B2.L", "B3.L", \ 395 "L0.L", "L1.L", "L2.L", "L3.L", "M0.L", "M1.L", "M2.L", "M3.L", } 396 397 #define HIGH_REGISTER_NAMES { \ 398 "R0.H", "R1.H", "R2.H", "R3.H", "R4.H", "R5.H", "R6.H", "R7.H", \ 399 "P0.H", "P1.H", "P2.H", "P3.H", "P4.H", "P5.H", "SP.H", "FP.H", \ 400 "I0.H", "I1.H", "I2.H", "I3.H", "B0.H", "B1.H", "B2.H", "B3.H", \ 401 "L0.H", "L1.H", "L2.H", "L3.H", "M0.H", "M1.H", "M2.H", "M3.H", } 402 403 #define DREGS_PAIR_NAMES { \ 404 "R1:0.p", 0, "R3:2.p", 0, "R5:4.p", 0, "R7:6.p", 0, } 405 406 #define BYTE_REGISTER_NAMES { \ 407 "R0.B", "R1.B", "R2.B", "R3.B", "R4.B", "R5.B", "R6.B", "R7.B", } 408 409 410 /* 1 for registers that have pervasive standard uses 411 and are not available for the register allocator. */ 412 413 #define FIXED_REGISTERS \ 414 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 415 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, \ 416 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 417 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0, \ 418 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 419 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 420 /*lb0/1 */ \ 421 1, 1 \ 422 } 423 424 /* 1 for registers not available across function calls. 425 These must include the FIXED_REGISTERS and also any 426 registers that can be used without being saved. 427 The latter must include the registers where values are returned 428 and the register where structure-value addresses are passed. 429 Aside from that, you can include as many other registers as you like. */ 430 431 #define CALL_USED_REGISTERS \ 432 /*r0 r1 r2 r3 r4 r5 r6 r7 p0 p1 p2 p3 p4 p5 p6 p7 */ \ 433 { 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 0, 0, 0, 1, 0, \ 434 /*i0 i1 i2 i3 b0 b1 b2 b3 l0 l1 l2 l3 m0 m1 m2 m3 */ \ 435 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 436 /*a0 a1 cc rets/i/x/n/e astat seqstat usp argp lt0/1 lc0/1 */ \ 437 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 438 /*lb0/1 */ \ 439 1, 1 \ 440 } 441 442 /* Order in which to allocate registers. Each register must be 443 listed once, even those in FIXED_REGISTERS. List frame pointer 444 late and fixed registers last. Note that, in general, we prefer 445 registers listed in CALL_USED_REGISTERS, keeping the others 446 available for storage of persistent values. */ 447 448 #define REG_ALLOC_ORDER \ 449 { REG_R0, REG_R1, REG_R2, REG_R3, REG_R7, REG_R6, REG_R5, REG_R4, \ 450 REG_P2, REG_P1, REG_P0, REG_P5, REG_P4, REG_P3, REG_P6, REG_P7, \ 451 REG_A0, REG_A1, \ 452 REG_I0, REG_I1, REG_I2, REG_I3, REG_B0, REG_B1, REG_B2, REG_B3, \ 453 REG_L0, REG_L1, REG_L2, REG_L3, REG_M0, REG_M1, REG_M2, REG_M3, \ 454 REG_RETS, REG_RETI, REG_RETX, REG_RETN, REG_RETE, \ 455 REG_ASTAT, REG_SEQSTAT, REG_USP, \ 456 REG_CC, REG_ARGP, \ 457 REG_LT0, REG_LT1, REG_LC0, REG_LC1, REG_LB0, REG_LB1 \ 458 } 459 460 /* Define the classes of registers for register constraints in the 461 machine description. Also define ranges of constants. 462 463 One of the classes must always be named ALL_REGS and include all hard regs. 464 If there is more than one class, another class must be named NO_REGS 465 and contain no registers. 466 467 The name GENERAL_REGS must be the name of a class (or an alias for 468 another name such as ALL_REGS). This is the class of registers 469 that is allowed by "g" or "r" in a register constraint. 470 Also, registers outside this class are allocated only when 471 instructions express preferences for them. 472 473 The classes must be numbered in nondecreasing order; that is, 474 a larger-numbered class must never be contained completely 475 in a smaller-numbered class. 476 477 For any two classes, it is very desirable that there be another 478 class that represents their union. */ 479 480 481 enum reg_class 482 { 483 NO_REGS, 484 IREGS, 485 BREGS, 486 LREGS, 487 MREGS, 488 CIRCREGS, /* Circular buffering registers, Ix, Bx, Lx together form. See Automatic Circular Buffering. */ 489 DAGREGS, 490 EVEN_AREGS, 491 ODD_AREGS, 492 AREGS, 493 CCREGS, 494 EVEN_DREGS, 495 ODD_DREGS, 496 D0REGS, 497 D1REGS, 498 D2REGS, 499 D3REGS, 500 D4REGS, 501 D5REGS, 502 D6REGS, 503 D7REGS, 504 DREGS, 505 P0REGS, 506 FDPIC_REGS, 507 FDPIC_FPTR_REGS, 508 PREGS_CLOBBERED, 509 PREGS, 510 IPREGS, 511 DPREGS, 512 MOST_REGS, 513 LT_REGS, 514 LC_REGS, 515 LB_REGS, 516 PROLOGUE_REGS, 517 NON_A_CC_REGS, 518 ALL_REGS, LIM_REG_CLASSES 519 }; 520 521 #define N_REG_CLASSES ((int)LIM_REG_CLASSES) 522 523 #define GENERAL_REGS DPREGS 524 525 /* Give names of register classes as strings for dump file. */ 526 527 #define REG_CLASS_NAMES \ 528 { "NO_REGS", \ 529 "IREGS", \ 530 "BREGS", \ 531 "LREGS", \ 532 "MREGS", \ 533 "CIRCREGS", \ 534 "DAGREGS", \ 535 "EVEN_AREGS", \ 536 "ODD_AREGS", \ 537 "AREGS", \ 538 "CCREGS", \ 539 "EVEN_DREGS", \ 540 "ODD_DREGS", \ 541 "D0REGS", \ 542 "D1REGS", \ 543 "D2REGS", \ 544 "D3REGS", \ 545 "D4REGS", \ 546 "D5REGS", \ 547 "D6REGS", \ 548 "D7REGS", \ 549 "DREGS", \ 550 "P0REGS", \ 551 "FDPIC_REGS", \ 552 "FDPIC_FPTR_REGS", \ 553 "PREGS_CLOBBERED", \ 554 "PREGS", \ 555 "IPREGS", \ 556 "DPREGS", \ 557 "MOST_REGS", \ 558 "LT_REGS", \ 559 "LC_REGS", \ 560 "LB_REGS", \ 561 "PROLOGUE_REGS", \ 562 "NON_A_CC_REGS", \ 563 "ALL_REGS" } 564 565 /* An initializer containing the contents of the register classes, as integers 566 which are bit masks. The Nth integer specifies the contents of class N. 567 The way the integer MASK is interpreted is that register R is in the class 568 if `MASK & (1 << R)' is 1. 569 570 When the machine has more than 32 registers, an integer does not suffice. 571 Then the integers are replaced by sub-initializers, braced groupings 572 containing several integers. Each sub-initializer must be suitable as an 573 initializer for the type `HARD_REG_SET' which is defined in 574 `hard-reg-set.h'. */ 575 576 /* NOTE: DSP registers, IREGS - AREGS, are not GENERAL_REGS. We use 577 MOST_REGS as the union of DPREGS and DAGREGS. */ 578 579 #define REG_CLASS_CONTENTS \ 580 /* 31 - 0 63-32 */ \ 581 { { 0x00000000, 0 }, /* NO_REGS */ \ 582 { 0x000f0000, 0 }, /* IREGS */ \ 583 { 0x00f00000, 0 }, /* BREGS */ \ 584 { 0x0f000000, 0 }, /* LREGS */ \ 585 { 0xf0000000, 0 }, /* MREGS */ \ 586 { 0x0fff0000, 0 }, /* CIRCREGS */ \ 587 { 0xffff0000, 0 }, /* DAGREGS */ \ 588 { 0x00000000, 0x1 }, /* EVEN_AREGS */ \ 589 { 0x00000000, 0x2 }, /* ODD_AREGS */ \ 590 { 0x00000000, 0x3 }, /* AREGS */ \ 591 { 0x00000000, 0x4 }, /* CCREGS */ \ 592 { 0x00000055, 0 }, /* EVEN_DREGS */ \ 593 { 0x000000aa, 0 }, /* ODD_DREGS */ \ 594 { 0x00000001, 0 }, /* D0REGS */ \ 595 { 0x00000002, 0 }, /* D1REGS */ \ 596 { 0x00000004, 0 }, /* D2REGS */ \ 597 { 0x00000008, 0 }, /* D3REGS */ \ 598 { 0x00000010, 0 }, /* D4REGS */ \ 599 { 0x00000020, 0 }, /* D5REGS */ \ 600 { 0x00000040, 0 }, /* D6REGS */ \ 601 { 0x00000080, 0 }, /* D7REGS */ \ 602 { 0x000000ff, 0 }, /* DREGS */ \ 603 { 0x00000100, 0x000 }, /* P0REGS */ \ 604 { 0x00000800, 0x000 }, /* FDPIC_REGS */ \ 605 { 0x00000200, 0x000 }, /* FDPIC_FPTR_REGS */ \ 606 { 0x00004700, 0x800 }, /* PREGS_CLOBBERED */ \ 607 { 0x0000ff00, 0x800 }, /* PREGS */ \ 608 { 0x000fff00, 0x800 }, /* IPREGS */ \ 609 { 0x0000ffff, 0x800 }, /* DPREGS */ \ 610 { 0xffffffff, 0x800 }, /* MOST_REGS */\ 611 { 0x00000000, 0x3000 }, /* LT_REGS */\ 612 { 0x00000000, 0xc000 }, /* LC_REGS */\ 613 { 0x00000000, 0x30000 }, /* LB_REGS */\ 614 { 0x00000000, 0x3f7f8 }, /* PROLOGUE_REGS */\ 615 { 0xffffffff, 0x3fff8 }, /* NON_A_CC_REGS */\ 616 { 0xffffffff, 0x3ffff }} /* ALL_REGS */ 617 618 #define IREG_POSSIBLE_P(OUTER) \ 619 ((OUTER) == POST_INC || (OUTER) == PRE_INC \ 620 || (OUTER) == POST_DEC || (OUTER) == PRE_DEC \ 621 || (OUTER) == MEM || (OUTER) == ADDRESS) 622 623 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ 624 ((MODE) == HImode && IREG_POSSIBLE_P (OUTER) ? IPREGS : PREGS) 625 626 #define INDEX_REG_CLASS PREGS 627 628 #define REGNO_OK_FOR_BASE_STRICT_P(X, MODE, OUTER, INDEX) \ 629 (P_REGNO_P (X) || (X) == REG_ARGP \ 630 || (IREG_POSSIBLE_P (OUTER) && (MODE) == HImode \ 631 && I_REGNO_P (X))) 632 633 #define REGNO_OK_FOR_BASE_NONSTRICT_P(X, MODE, OUTER, INDEX) \ 634 ((X) >= FIRST_PSEUDO_REGISTER \ 635 || REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX)) 636 637 #ifdef REG_OK_STRICT 638 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 639 REGNO_OK_FOR_BASE_STRICT_P (X, MODE, OUTER, INDEX) 640 #else 641 #define REGNO_MODE_CODE_OK_FOR_BASE_P(X, MODE, AS, OUTER, INDEX) \ 642 REGNO_OK_FOR_BASE_NONSTRICT_P (X, MODE, OUTER, INDEX) 643 #endif 644 645 #define REGNO_OK_FOR_INDEX_P(X) 0 646 647 /* The same information, inverted: 648 Return the class number of the smallest class containing 649 reg number REGNO. This could be a conditional expression 650 or could index an array. */ 651 652 #define REGNO_REG_CLASS(REGNO) \ 653 ((REGNO) == REG_R0 ? D0REGS \ 654 : (REGNO) == REG_R1 ? D1REGS \ 655 : (REGNO) == REG_R2 ? D2REGS \ 656 : (REGNO) == REG_R3 ? D3REGS \ 657 : (REGNO) == REG_R4 ? D4REGS \ 658 : (REGNO) == REG_R5 ? D5REGS \ 659 : (REGNO) == REG_R6 ? D6REGS \ 660 : (REGNO) == REG_R7 ? D7REGS \ 661 : (REGNO) == REG_P0 ? P0REGS \ 662 : (REGNO) < REG_I0 ? PREGS \ 663 : (REGNO) == REG_ARGP ? PREGS \ 664 : (REGNO) >= REG_I0 && (REGNO) <= REG_I3 ? IREGS \ 665 : (REGNO) >= REG_L0 && (REGNO) <= REG_L3 ? LREGS \ 666 : (REGNO) >= REG_B0 && (REGNO) <= REG_B3 ? BREGS \ 667 : (REGNO) >= REG_M0 && (REGNO) <= REG_M3 ? MREGS \ 668 : (REGNO) == REG_A0 || (REGNO) == REG_A1 ? AREGS \ 669 : (REGNO) == REG_LT0 || (REGNO) == REG_LT1 ? LT_REGS \ 670 : (REGNO) == REG_LC0 || (REGNO) == REG_LC1 ? LC_REGS \ 671 : (REGNO) == REG_LB0 || (REGNO) == REG_LB1 ? LB_REGS \ 672 : (REGNO) == REG_CC ? CCREGS \ 673 : (REGNO) >= REG_RETS ? PROLOGUE_REGS \ 674 : NO_REGS) 675 676 /* When this hook returns true for MODE, the compiler allows 677 registers explicitly used in the rtl to be used as spill registers 678 but prevents the compiler from extending the lifetime of these 679 registers. */ 680 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 681 682 /* Do not allow to store a value in REG_CC for any mode */ 683 /* Do not allow to store value in pregs if mode is not SI*/ 684 #define HARD_REGNO_MODE_OK(REGNO, MODE) hard_regno_mode_ok((REGNO), (MODE)) 685 686 /* Return the maximum number of consecutive registers 687 needed to represent mode MODE in a register of class CLASS. */ 688 #define CLASS_MAX_NREGS(CLASS, MODE) \ 689 ((MODE) == V2PDImode && (CLASS) == AREGS ? 2 \ 690 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 691 692 #define HARD_REGNO_NREGS(REGNO, MODE) \ 693 ((MODE) == PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 1 \ 694 : (MODE) == V2PDImode && ((REGNO) == REG_A0 || (REGNO) == REG_A1) ? 2 \ 695 : CLASS_MAX_NREGS (GENERAL_REGS, MODE)) 696 697 /* A C expression that is nonzero if hard register TO can be 698 considered for use as a rename register for FROM register */ 699 #define HARD_REGNO_RENAME_OK(FROM, TO) bfin_hard_regno_rename_ok (FROM, TO) 700 701 /* A C expression that is nonzero if it is desirable to choose 702 register allocation so as to avoid move instructions between a 703 value of mode MODE1 and a value of mode MODE2. 704 705 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 706 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 707 MODE2)' must be zero. */ 708 #define MODES_TIEABLE_P(MODE1, MODE2) \ 709 ((MODE1) == (MODE2) \ 710 || ((GET_MODE_CLASS (MODE1) == MODE_INT \ 711 || GET_MODE_CLASS (MODE1) == MODE_FLOAT) \ 712 && (GET_MODE_CLASS (MODE2) == MODE_INT \ 713 || GET_MODE_CLASS (MODE2) == MODE_FLOAT) \ 714 && (MODE1) != BImode && (MODE2) != BImode \ 715 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 716 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD)) 717 718 /* `PREFERRED_RELOAD_CLASS (X, CLASS)' 719 A C expression that places additional restrictions on the register 720 class to use when it is necessary to copy value X into a register 721 in class CLASS. The value is a register class; perhaps CLASS, or 722 perhaps another, smaller class. */ 723 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 724 (GET_CODE (X) == POST_INC \ 725 || GET_CODE (X) == POST_DEC \ 726 || GET_CODE (X) == PRE_DEC ? PREGS : (CLASS)) 727 728 /* Function Calling Conventions. */ 729 730 /* The type of the current function; normal functions are of type 731 SUBROUTINE. */ 732 typedef enum { 733 SUBROUTINE, INTERRUPT_HANDLER, EXCPT_HANDLER, NMI_HANDLER 734 } e_funkind; 735 #define FUNCTION_RETURN_REGISTERS { REG_RETS, REG_RETI, REG_RETX, REG_RETN } 736 737 #define FUNCTION_ARG_REGISTERS { REG_R0, REG_R1, REG_R2, -1 } 738 739 /* Flags for the call/call_value rtl operations set up by function_arg */ 740 #define CALL_NORMAL 0x00000000 /* no special processing */ 741 #define CALL_LONG 0x00000001 /* always call indirect */ 742 #define CALL_SHORT 0x00000002 /* always call by symbol */ 743 744 typedef struct { 745 int words; /* # words passed so far */ 746 int nregs; /* # registers available for passing */ 747 int *arg_regs; /* array of register -1 terminated */ 748 int call_cookie; /* Do special things for this call */ 749 } CUMULATIVE_ARGS; 750 751 #define FUNCTION_ARG_REGNO_P(REGNO) function_arg_regno_p (REGNO) 752 753 754 /* Initialize a variable CUM of type CUMULATIVE_ARGS 755 for a call to a function whose data type is FNTYPE. 756 For a library call, FNTYPE is 0. */ 757 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,INDIRECT, N_NAMED_ARGS) \ 758 (init_cumulative_args (&CUM, FNTYPE, LIBNAME)) 759 760 /* Define how to find the value returned by a function. 761 VALTYPE is the data type of the value (as a tree). 762 If the precise function being called is known, FUNC is its FUNCTION_DECL; 763 otherwise, FUNC is 0. 764 */ 765 766 #define VALUE_REGNO(MODE) (REG_R0) 767 768 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 769 gen_rtx_REG (TYPE_MODE (VALTYPE), \ 770 VALUE_REGNO(TYPE_MODE(VALTYPE))) 771 772 /* Define how to find the value returned by a library function 773 assuming the value has mode MODE. */ 774 775 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, VALUE_REGNO(MODE)) 776 777 #define FUNCTION_VALUE_REGNO_P(N) ((N) == REG_R0) 778 779 #define DEFAULT_PCC_STRUCT_RETURN 0 780 781 /* Before the prologue, the return address is in the RETS register. */ 782 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, REG_RETS) 783 784 #define RETURN_ADDR_RTX(COUNT, FRAME) bfin_return_addr_rtx (COUNT) 785 786 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (REG_RETS) 787 788 /* Call instructions don't modify the stack pointer on the Blackfin. */ 789 #define INCOMING_FRAME_SP_OFFSET 0 790 791 /* Describe how we implement __builtin_eh_return. */ 792 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 793 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, REG_P2) 794 #define EH_RETURN_HANDLER_RTX \ 795 gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, \ 796 UNITS_PER_WORD)) 797 798 /* Addressing Modes */ 799 800 /* A number, the maximum number of registers that can appear in a 801 valid memory address. Note that it is up to you to specify a 802 value equal to the maximum number that `TARGET_LEGITIMATE_ADDRESS_P' 803 would ever accept. */ 804 #define MAX_REGS_PER_ADDRESS 1 805 806 #define LEGITIMATE_MODE_FOR_AUTOINC_P(MODE) \ 807 (GET_MODE_SIZE (MODE) <= 4 || (MODE) == PDImode) 808 809 #define HAVE_POST_INCREMENT 1 810 #define HAVE_POST_DECREMENT 1 811 #define HAVE_PRE_DECREMENT 1 812 813 /* `LEGITIMATE_PIC_OPERAND_P (X)' 814 A C expression that is nonzero if X is a legitimate immediate 815 operand on the target machine when generating position independent 816 code. You can assume that X satisfies `CONSTANT_P', so you need 817 not check this. You can also assume FLAG_PIC is true, so you need 818 not check it either. You need not define this macro if all 819 constants (including `SYMBOL_REF') can be immediate operands when 820 generating position independent code. */ 821 #define LEGITIMATE_PIC_OPERAND_P(X) ! SYMBOLIC_CONST (X) 822 823 #define SYMBOLIC_CONST(X) \ 824 (GET_CODE (X) == SYMBOL_REF \ 825 || GET_CODE (X) == LABEL_REF \ 826 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 827 828 #define NOTICE_UPDATE_CC(EXPR, INSN) 0 829 830 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 831 is done just by pretending it is already truncated. */ 832 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 833 834 /* Max number of bytes we can move from memory to memory 835 in one reasonably fast instruction. */ 836 #define MOVE_MAX UNITS_PER_WORD 837 838 /* If a memory-to-memory move would take MOVE_RATIO or more simple 839 move-instruction pairs, we will do a movmem or libcall instead. */ 840 841 #define MOVE_RATIO(speed) 5 842 843 /* STORAGE LAYOUT: target machine storage layout 844 Define this macro as a C expression which is nonzero if accessing 845 less than a word of memory (i.e. a `char' or a `short') is no 846 faster than accessing a word of memory, i.e., if such access 847 require more than one instruction or if there is no difference in 848 cost between byte and (aligned) word loads. 849 850 When this macro is not defined, the compiler will access a field by 851 finding the smallest containing object; when it is defined, a 852 fullword load will be used if alignment permits. Unless bytes 853 accesses are faster than word accesses, using word accesses is 854 preferable since it may eliminate subsequent memory access if 855 subsequent accesses occur to other fields in the same word of the 856 structure, but to different bytes. */ 857 #define SLOW_BYTE_ACCESS 0 858 #define SLOW_SHORT_ACCESS 0 859 860 /* Define this if most significant bit is lowest numbered 861 in instructions that operate on numbered bit-fields. */ 862 #define BITS_BIG_ENDIAN 0 863 864 /* Define this if most significant byte of a word is the lowest numbered. 865 We can't access bytes but if we could we would in the Big Endian order. */ 866 #define BYTES_BIG_ENDIAN 0 867 868 /* Define this if most significant word of a multiword number is numbered. */ 869 #define WORDS_BIG_ENDIAN 0 870 871 /* Width in bits of a "word", which is the contents of a machine register. 872 Note that this is not necessarily the width of data type `int'; 873 if using 16-bit ints on a 68000, this would still be 32. 874 But on a machine with 16-bit registers, this would be 16. */ 875 #define BITS_PER_WORD 32 876 877 /* Width of a word, in units (bytes). */ 878 #define UNITS_PER_WORD 4 879 880 /* Width in bits of a pointer. 881 See also the macro `Pmode1' defined below. */ 882 #define POINTER_SIZE 32 883 884 /* Allocation boundary (in *bits*) for storing pointers in memory. */ 885 #define POINTER_BOUNDARY 32 886 887 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 888 #define PARM_BOUNDARY 32 889 890 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 891 #define STACK_BOUNDARY 32 892 893 /* Allocation boundary (in *bits*) for the code of a function. */ 894 #define FUNCTION_BOUNDARY 32 895 896 /* Alignment of field after `int : 0' in a structure. */ 897 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 898 899 /* No data type wants to be aligned rounder than this. */ 900 #define BIGGEST_ALIGNMENT 32 901 902 /* Define this if move instructions will actually fail to work 903 when given unaligned data. */ 904 #define STRICT_ALIGNMENT 1 905 906 /* (shell-command "rm c-decl.o stor-layout.o") 907 * never define PCC_BITFIELD_TYPE_MATTERS 908 * really cause some alignment problem 909 */ 910 911 #define UNITS_PER_FLOAT ((FLOAT_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 912 BITS_PER_UNIT) 913 914 #define UNITS_PER_DOUBLE ((DOUBLE_TYPE_SIZE + BITS_PER_UNIT - 1) / \ 915 BITS_PER_UNIT) 916 917 918 /* what is the 'type' of size_t */ 919 #define SIZE_TYPE "long unsigned int" 920 921 /* Define this as 1 if `char' should by default be signed; else as 0. */ 922 #define DEFAULT_SIGNED_CHAR 1 923 #define FLOAT_TYPE_SIZE BITS_PER_WORD 924 #define SHORT_TYPE_SIZE 16 925 #define CHAR_TYPE_SIZE 8 926 #define INT_TYPE_SIZE 32 927 #define LONG_TYPE_SIZE 32 928 #define LONG_LONG_TYPE_SIZE 64 929 930 /* Note: Fix this to depend on target switch. -- lev */ 931 932 /* Note: Try to implement double and force long double. -- tonyko 933 * #define __DOUBLES_ARE_FLOATS__ 934 * #define DOUBLE_TYPE_SIZE FLOAT_TYPE_SIZE 935 * #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 936 * #define DOUBLES_ARE_FLOATS 1 937 */ 938 939 #define DOUBLE_TYPE_SIZE 64 940 #define LONG_DOUBLE_TYPE_SIZE 64 941 942 /* `PROMOTE_MODE (M, UNSIGNEDP, TYPE)' 943 A macro to update M and UNSIGNEDP when an object whose type is 944 TYPE and which has the specified mode and signedness is to be 945 stored in a register. This macro is only called when TYPE is a 946 scalar type. 947 948 On most RISC machines, which only have operations that operate on 949 a full register, define this macro to set M to `word_mode' if M is 950 an integer mode narrower than `BITS_PER_WORD'. In most cases, 951 only integer modes should be widened because wider-precision 952 floating-point operations are usually more expensive than their 953 narrower counterparts. 954 955 For most machines, the macro definition does not change UNSIGNEDP. 956 However, some machines, have instructions that preferentially 957 handle either signed or unsigned quantities of certain modes. For 958 example, on the DEC Alpha, 32-bit loads from memory and 32-bit add 959 instructions sign-extend the result to 64 bits. On such machines, 960 set UNSIGNEDP according to which kind of extension is more 961 efficient. 962 963 Do not define this macro if it would never modify M.*/ 964 965 #define BFIN_PROMOTE_MODE_P(MODE) \ 966 (!TARGET_DSP && GET_MODE_CLASS (MODE) == MODE_INT \ 967 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) 968 969 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 970 if (BFIN_PROMOTE_MODE_P(MODE)) \ 971 { \ 972 if (MODE == QImode) \ 973 UNSIGNEDP = 1; \ 974 else if (MODE == HImode) \ 975 UNSIGNEDP = 0; \ 976 (MODE) = SImode; \ 977 } 978 979 /* Describing Relative Costs of Operations */ 980 981 /* Do not put function addr into constant pool */ 982 #define NO_FUNCTION_CSE 1 983 984 /* Specify the machine mode that this machine uses 985 for the index in the tablejump instruction. */ 986 #define CASE_VECTOR_MODE SImode 987 988 #define JUMP_TABLES_IN_TEXT_SECTION flag_pic 989 990 /* Define if operations between registers always perform the operation 991 on the full register even if a narrower mode is specified. 992 #define WORD_REGISTER_OPERATIONS 1 993 */ 994 995 /* Evaluates to true if A and B are mac flags that can be used 996 together in a single multiply insn. That is the case if they are 997 both the same flag not involving M, or if one is a combination of 998 the other with M. */ 999 #define MACFLAGS_MATCH_P(A, B) \ 1000 ((A) == (B) \ 1001 || ((A) == MACFLAG_NONE && (B) == MACFLAG_M) \ 1002 || ((A) == MACFLAG_M && (B) == MACFLAG_NONE) \ 1003 || ((A) == MACFLAG_IS && (B) == MACFLAG_IS_M) \ 1004 || ((A) == MACFLAG_IS_M && (B) == MACFLAG_IS)) 1005 1006 /* Switch into a generic section. */ 1007 #define TARGET_ASM_NAMED_SECTION default_elf_asm_named_section 1008 1009 #define PRINT_OPERAND(FILE, RTX, CODE) print_operand (FILE, RTX, CODE) 1010 #define PRINT_OPERAND_ADDRESS(FILE, RTX) print_address_operand (FILE, RTX) 1011 1012 typedef enum sections { 1013 CODE_DIR, 1014 DATA_DIR, 1015 LAST_SECT_NM 1016 } SECT_ENUM_T; 1017 1018 typedef enum directives { 1019 LONG_CONST_DIR, 1020 SHORT_CONST_DIR, 1021 BYTE_CONST_DIR, 1022 SPACE_DIR, 1023 INIT_DIR, 1024 LAST_DIR_NM 1025 } DIR_ENUM_T; 1026 1027 #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) \ 1028 ((C) == ';' \ 1029 || ((C) == '|' && (STR)[1] == '|')) 1030 1031 #define TEXT_SECTION_ASM_OP ".text;" 1032 #define DATA_SECTION_ASM_OP ".data;" 1033 1034 #define ASM_APP_ON "" 1035 #define ASM_APP_OFF "" 1036 1037 #define ASM_GLOBALIZE_LABEL1(FILE, NAME) \ 1038 do { fputs (".global ", FILE); \ 1039 assemble_name (FILE, NAME); \ 1040 fputc (';',FILE); \ 1041 fputc ('\n',FILE); \ 1042 } while (0) 1043 1044 #define ASM_DECLARE_FUNCTION_NAME(FILE,NAME,DECL) \ 1045 do { \ 1046 fputs (".type ", FILE); \ 1047 assemble_name (FILE, NAME); \ 1048 fputs (", STT_FUNC", FILE); \ 1049 fputc (';',FILE); \ 1050 fputc ('\n',FILE); \ 1051 ASM_OUTPUT_LABEL(FILE, NAME); \ 1052 } while (0) 1053 1054 #define ASM_OUTPUT_LABEL(FILE, NAME) \ 1055 do { assemble_name (FILE, NAME); \ 1056 fputs (":\n",FILE); \ 1057 } while (0) 1058 1059 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1060 do { fprintf (FILE, "_%s", NAME); \ 1061 } while (0) 1062 1063 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1064 do { char __buf[256]; \ 1065 fprintf (FILE, "\t.dd\t"); \ 1066 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1067 assemble_name (FILE, __buf); \ 1068 fputc (';', FILE); \ 1069 fputc ('\n', FILE); \ 1070 } while (0) 1071 1072 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 1073 MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) 1074 1075 #define MY_ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1076 do { \ 1077 char __buf[256]; \ 1078 fprintf (FILE, "\t.dd\t"); \ 1079 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", VALUE); \ 1080 assemble_name (FILE, __buf); \ 1081 fputs (" - ", FILE); \ 1082 ASM_GENERATE_INTERNAL_LABEL (__buf, "L", REL); \ 1083 assemble_name (FILE, __buf); \ 1084 fputc (';', FILE); \ 1085 fputc ('\n', FILE); \ 1086 } while (0) 1087 1088 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1089 do { \ 1090 if ((LOG) != 0) \ 1091 fprintf (FILE, "\t.align %d\n", 1 << (LOG)); \ 1092 } while (0) 1093 1094 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1095 do { \ 1096 asm_output_skip (FILE, SIZE); \ 1097 } while (0) 1098 1099 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1100 do { \ 1101 switch_to_section (data_section); \ 1102 if ((SIZE) >= (unsigned int) 4 ) ASM_OUTPUT_ALIGN(FILE,2); \ 1103 ASM_OUTPUT_SIZE_DIRECTIVE (FILE, NAME, SIZE); \ 1104 ASM_OUTPUT_LABEL (FILE, NAME); \ 1105 fprintf (FILE, "%s %ld;\n", ASM_SPACE, \ 1106 (ROUNDED) > (unsigned int) 1 ? (ROUNDED) : 1); \ 1107 } while (0) 1108 1109 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1110 do { \ 1111 ASM_GLOBALIZE_LABEL1(FILE,NAME); \ 1112 ASM_OUTPUT_LOCAL (FILE, NAME, SIZE, ROUNDED); } while(0) 1113 1114 #define ASM_COMMENT_START "//" 1115 1116 #define PROFILE_BEFORE_PROLOGUE 1117 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1118 do { \ 1119 fprintf (FILE, "\t[--SP] = RETS;\n"); \ 1120 if (TARGET_LONG_CALLS) \ 1121 { \ 1122 fprintf (FILE, "\tP2.h = __mcount;\n"); \ 1123 fprintf (FILE, "\tP2.l = __mcount;\n"); \ 1124 fprintf (FILE, "\tCALL (P2);\n"); \ 1125 } \ 1126 else \ 1127 fprintf (FILE, "\tCALL __mcount;\n"); \ 1128 fprintf (FILE, "\tRETS = [SP++];\n"); \ 1129 } while(0) 1130 1131 #undef NO_PROFILE_COUNTERS 1132 #define NO_PROFILE_COUNTERS 1 1133 1134 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) fprintf (FILE, "\t[--SP] = %s;\n", reg_names[REGNO]) 1135 #define ASM_OUTPUT_REG_POP(FILE, REGNO) fprintf (FILE, "\t%s = [SP++];\n", reg_names[REGNO]) 1136 1137 extern rtx bfin_cc_rtx, bfin_rets_rtx; 1138 1139 /* This works for GAS and some other assemblers. */ 1140 #define SET_ASM_OP ".set " 1141 1142 /* DBX register number for a given compiler register number */ 1143 #define DBX_REGISTER_NUMBER(REGNO) (REGNO) 1144 1145 #define SIZE_ASM_OP "\t.size\t" 1146 1147 extern int splitting_for_sched, splitting_loops; 1148 1149 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) ((CHAR) == '!') 1150 1151 #ifndef TARGET_SUPPORTS_SYNC_CALLS 1152 #define TARGET_SUPPORTS_SYNC_CALLS 0 1153 #endif 1154 1155 struct bfin_cpu 1156 { 1157 const char *name; 1158 bfin_cpu_t type; 1159 int si_revision; 1160 unsigned int workarounds; 1161 }; 1162 1163 extern const struct bfin_cpu bfin_cpus[]; 1164 1165 #endif /* _BFIN_CONFIG */ 1166
Indexes created Sun Apr 19 00:22:55 UTC 2026