gcn.h revision 1.1
1 /* Copyright (C) 2016-2019 Free Software Foundation, Inc. 2 3 This file is free software; you can redistribute it and/or modify it under 4 the terms of the GNU General Public License as published by the Free 5 Software Foundation; either version 3 of the License, or (at your option) 6 any later version. 7 8 This file is distributed in the hope that it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 for more details. 12 13 You should have received a copy of the GNU General Public License 14 along with GCC; see the file COPYING3. If not see 15 <http://www.gnu.org/licenses/>. */ 16 17 #include "config/gcn/gcn-opts.h" 18 19 #define TARGET_CPU_CPP_BUILTINS() \ 20 do \ 21 { \ 22 builtin_define ("__AMDGCN__"); \ 23 if (TARGET_GCN3) \ 24 builtin_define ("__GCN3__"); \ 25 else if (TARGET_GCN5) \ 26 builtin_define ("__GCN5__"); \ 27 } \ 28 while(0) 29 30 /* Support for a compile-time default architecture and tuning. 31 The rules are: 32 --with-arch is ignored if -march is specified. 33 --with-tune is ignored if -mtune is specified. */ 34 #define OPTION_DEFAULT_SPECS \ 35 {"arch", "%{!march=*:-march=%(VALUE)}" }, \ 36 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" } 37 38 /* Default target_flags if no switches specified. */ 39 #ifndef TARGET_DEFAULT 40 #define TARGET_DEFAULT 0 41 #endif 42 43 44 /* Storage Layout */ 46 #define BITS_BIG_ENDIAN 0 47 #define BYTES_BIG_ENDIAN 0 48 #define WORDS_BIG_ENDIAN 0 49 50 #define BITS_PER_WORD 32 51 #define UNITS_PER_WORD (BITS_PER_WORD/BITS_PER_UNIT) 52 #define LIBGCC2_UNITS_PER_WORD 4 53 54 #define POINTER_SIZE 64 55 #define PARM_BOUNDARY 64 56 #define STACK_BOUNDARY 64 57 #define FUNCTION_BOUNDARY 32 58 #define BIGGEST_ALIGNMENT 64 59 #define EMPTY_FIELD_BOUNDARY 32 60 #define MAX_FIXED_MODE_SIZE 64 61 #define MAX_REGS_PER_ADDRESS 2 62 #define STACK_SIZE_MODE DImode 63 #define Pmode DImode 64 #define CASE_VECTOR_MODE DImode 65 #define FUNCTION_MODE QImode 66 67 #define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 68 #define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64) 69 #define STACK_SLOT_ALIGNMENT(TYPE,MODE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64) 70 #define STRICT_ALIGNMENT 1 71 72 /* Type Layout: match what x86_64 does. */ 73 #define INT_TYPE_SIZE 32 74 #define LONG_TYPE_SIZE 64 75 #define LONG_LONG_TYPE_SIZE 64 76 #define FLOAT_TYPE_SIZE 32 77 #define DOUBLE_TYPE_SIZE 64 78 #define LONG_DOUBLE_TYPE_SIZE 64 79 #define DEFAULT_SIGNED_CHAR 1 80 #define PCC_BITFIELD_TYPE_MATTERS 1 81 82 /* Frame Layout */ 83 #define FRAME_GROWS_DOWNWARD 0 84 #define ARGS_GROW_DOWNWARD 1 85 #define STACK_POINTER_OFFSET 0 86 #define FIRST_PARM_OFFSET(FNDECL) 0 87 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16) 88 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM) 89 #define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size) 90 #define ACCUMULATE_OUTGOING_ARGS 1 91 #define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \ 92 ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, LINK_REGNUM) : NULL_RTX) 93 94 /* Register Basics */ 96 #define FIRST_SGPR_REG 0 97 #define SGPR_REGNO(N) ((N)+FIRST_SGPR_REG) 98 #define LAST_SGPR_REG 101 99 100 #define FLAT_SCRATCH_REG 102 101 #define FLAT_SCRATCH_LO_REG 102 102 #define FLAT_SCRATCH_HI_REG 103 103 #define XNACK_MASK_REG 104 104 #define XNACK_MASK_LO_REG 104 105 #define XNACK_MASK_HI_REG 105 106 #define VCC_LO_REG 106 107 #define VCC_HI_REG 107 108 #define VCCZ_REG 108 109 #define TBA_REG 109 110 #define TBA_LO_REG 109 111 #define TBA_HI_REG 110 112 #define TMA_REG 111 113 #define TMA_LO_REG 111 114 #define TMA_HI_REG 112 115 #define TTMP0_REG 113 116 #define TTMP11_REG 124 117 #define M0_REG 125 118 #define EXEC_REG 126 119 #define EXEC_LO_REG 126 120 #define EXEC_HI_REG 127 121 #define EXECZ_REG 128 122 #define SCC_REG 129 123 /* 132-159 are reserved to simplify masks. */ 124 #define FIRST_VGPR_REG 160 125 #define VGPR_REGNO(N) ((N)+FIRST_VGPR_REG) 126 #define LAST_VGPR_REG 415 127 128 /* Frame Registers, and other registers */ 129 130 #define HARD_FRAME_POINTER_REGNUM 14 131 #define STACK_POINTER_REGNUM 16 132 #define LINK_REGNUM 18 133 #define EXEC_SAVE_REG 20 134 #define CC_SAVE_REG 22 135 #define RETURN_VALUE_REG 24 /* Must be divisible by 4. */ 136 #define STATIC_CHAIN_REGNUM 30 137 #define WORK_ITEM_ID_Z_REG 162 138 #define SOFT_ARG_REG 416 139 #define FRAME_POINTER_REGNUM 418 140 #define FIRST_PSEUDO_REGISTER 420 141 142 #define FIRST_PARM_REG 24 143 #define NUM_PARM_REGS 6 144 145 /* There is no arg pointer. Just choose random fixed register that does 146 not intefere with anything. */ 147 #define ARG_POINTER_REGNUM SOFT_ARG_REG 148 149 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 150 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 151 152 #define SGPR_OR_VGPR_REGNO_P(N) ((N)>=FIRST_VGPR_REG && (N) <= LAST_SGPR_REG) 153 #define SGPR_REGNO_P(N) ((N) <= LAST_SGPR_REG) 154 #define VGPR_REGNO_P(N) ((N)>=FIRST_VGPR_REG && (N) <= LAST_VGPR_REG) 155 #define SSRC_REGNO_P(N) ((N) <= SCC_REG && (N) != VCCZ_REG) 156 #define SDST_REGNO_P(N) ((N) <= EXEC_HI_REG && (N) != VCCZ_REG) 157 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 158 #define CC_REGNO_P(X) ((X) == SCC_REG || (X) == VCC_REG) 159 #define FUNCTION_ARG_REGNO_P(N) \ 160 ((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS)) 161 162 163 #define FIXED_REGISTERS { \ 165 /* Scalars. */ \ 166 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 167 /* fp sp lr. */ \ 168 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, \ 169 /* exec_save, cc_save */ \ 170 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 171 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 172 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 173 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 174 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 175 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 177 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 178 /* Special regs and padding. */ \ 179 /* flat xnack vcc tba tma ttmp */ \ 180 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 181 /* m0 exec scc */ \ 182 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, \ 183 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 184 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 185 /* VGRPs */ \ 186 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 187 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 188 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 189 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 190 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 191 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 195 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 197 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 199 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 201 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 202 /* Other registers. */ \ 203 1, 1, 1, 1 \ 204 } 205 206 #define CALL_USED_REGISTERS { \ 207 /* Scalars. */ \ 208 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 209 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 210 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 211 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 212 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 213 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 214 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 215 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 216 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 217 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 218 /* Special regs and padding. */ \ 219 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 220 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 221 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 222 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 223 /* VGRPs */ \ 224 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 225 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 226 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 227 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 228 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 229 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 235 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 240 /* Other registers. */ \ 241 1, 1, 1, 1 \ 242 } 243 244 245 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 247 gcn_hard_regno_rename_ok (FROM, TO) 248 249 #define HARD_REGNO_CALLER_SAVE_MODE(HARDREG, NREGS, MODE) \ 250 gcn_hard_regno_caller_save_mode ((HARDREG), (NREGS), (MODE)) 251 252 /* Register Classes */ 253 254 enum reg_class 255 { 256 NO_REGS, 257 258 /* SCC */ 259 SCC_CONDITIONAL_REG, 260 261 /* VCCZ */ 262 VCCZ_CONDITIONAL_REG, 263 264 /* VCC */ 265 VCC_CONDITIONAL_REG, 266 267 /* EXECZ */ 268 EXECZ_CONDITIONAL_REG, 269 270 /* SCC VCCZ EXECZ */ 271 ALL_CONDITIONAL_REGS, 272 273 /* EXEC */ 274 EXEC_MASK_REG, 275 276 /* SGPR0-101 */ 277 SGPR_REGS, 278 279 /* SGPR0-101 EXEC_LO/EXEC_HI */ 280 SGPR_EXEC_REGS, 281 282 /* SGPR0-101, FLAT_SCRATCH_LO/HI, VCC LO/HI, TBA LO/HI, TMA LO/HI, TTMP0-11, 283 M0, VCCZ, SCC 284 (EXEC_LO/HI, EXECZ excluded to prevent compiler misuse.) */ 285 SGPR_VOP_SRC_REGS, 286 287 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI 288 TMA LO/HI, TTMP0-11 */ 289 SGPR_MEM_SRC_REGS, 290 291 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI 292 TMA LO/HI, TTMP0-11, M0, EXEC LO/HI */ 293 SGPR_DST_REGS, 294 295 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI 296 TMA LO/HI, TTMP0-11 */ 297 SGPR_SRC_REGS, 298 GENERAL_REGS, 299 VGPR_REGS, 300 ALL_GPR_REGS, 301 SRCDST_REGS, 302 AFP_REGS, 303 ALL_REGS, 304 LIM_REG_CLASSES 305 }; 306 307 #define N_REG_CLASSES (int) LIM_REG_CLASSES 308 309 #define REG_CLASS_NAMES \ 310 { "NO_REGS", \ 311 "SCC_CONDITIONAL_REG", \ 312 "VCCZ_CONDITIONAL_REG", \ 313 "VCC_CONDITIONAL_REG", \ 314 "EXECZ_CONDITIONAL_REG", \ 315 "ALL_CONDITIONAL_REGS", \ 316 "EXEC_MASK_REG", \ 317 "SGPR_REGS", \ 318 "SGPR_EXEC_REGS", \ 319 "SGPR_VOP3A_SRC_REGS", \ 320 "SGPR_MEM_SRC_REGS", \ 321 "SGPR_DST_REGS", \ 322 "SGPR_SRC_REGS", \ 323 "GENERAL_REGS", \ 324 "VGPR_REGS", \ 325 "ALL_GPR_REGS", \ 326 "SRCDST_REGS", \ 327 "AFP_REGS", \ 328 "ALL_REGS" \ 329 } 330 331 #define NAMED_REG_MASK(N) (1<<((N)-3*32)) 332 #define NAMED_REG_MASK2(N) (1<<((N)-4*32)) 333 334 #define REG_CLASS_CONTENTS { \ 335 /* NO_REGS. */ \ 336 {0, 0, 0, 0, \ 337 0, 0, 0, 0, \ 338 0, 0, 0, 0, 0, 0}, \ 339 /* SCC_CONDITIONAL_REG. */ \ 340 {0, 0, 0, 0, \ 341 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 342 0, 0, 0, 0, 0}, \ 343 /* VCCZ_CONDITIONAL_REG. */ \ 344 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \ 345 0, 0, 0, 0, \ 346 0, 0, 0, 0, 0, 0}, \ 347 /* VCC_CONDITIONAL_REG. */ \ 348 {0, 0, 0, NAMED_REG_MASK (VCC_LO_REG)|NAMED_REG_MASK (VCC_HI_REG), \ 349 0, 0, 0, 0, \ 350 0, 0, 0, 0, 0, 0}, \ 351 /* EXECZ_CONDITIONAL_REG. */ \ 352 {0, 0, 0, 0, \ 353 NAMED_REG_MASK2 (EXECZ_REG), 0, 0, 0, \ 354 0, 0, 0, 0, 0}, \ 355 /* ALL_CONDITIONAL_REGS. */ \ 356 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \ 357 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 358 0, 0, 0, 0, 0, 0}, \ 359 /* EXEC_MASK_REG. */ \ 360 {0, 0, 0, NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \ 361 0, 0, 0, 0, \ 362 0, 0, 0, 0, 0, 0}, \ 363 /* SGPR_REGS. */ \ 364 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \ 365 0, 0, 0, 0, \ 366 0, 0, 0, 0, 0, 0}, \ 367 /* SGPR_EXEC_REGS. */ \ 368 {0xffffffff, 0xffffffff, 0xffffffff, \ 369 0xf1 | NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \ 370 0, 0, 0, 0, \ 371 0, 0, 0, 0, 0, 0}, \ 372 /* SGPR_VOP_SRC_REGS. */ \ 373 {0xffffffff, 0xffffffff, 0xffffffff, \ 374 0xffffffff \ 375 -NAMED_REG_MASK (EXEC_LO_REG) \ 376 -NAMED_REG_MASK (EXEC_HI_REG), \ 377 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 378 0, 0, 0, 0, 0, 0}, \ 379 /* SGPR_MEM_SRC_REGS. */ \ 380 {0xffffffff, 0xffffffff, 0xffffffff, \ 381 0xffffffff-NAMED_REG_MASK (VCCZ_REG)-NAMED_REG_MASK (M0_REG) \ 382 -NAMED_REG_MASK (EXEC_LO_REG)-NAMED_REG_MASK (EXEC_HI_REG), \ 383 0, 0, 0, 0, \ 384 0, 0, 0, 0, 0, 0}, \ 385 /* SGPR_DST_REGS. */ \ 386 {0xffffffff, 0xffffffff, 0xffffffff, \ 387 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \ 388 0, 0, 0, 0, \ 389 0, 0, 0, 0, 0, 0}, \ 390 /* SGPR_SRC_REGS. */ \ 391 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ 392 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 393 0, 0, 0, 0, 0, 0}, \ 394 /* GENERAL_REGS. */ \ 395 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \ 396 0, 0, 0, 0, \ 397 0, 0, 0, 0, 0, 0}, \ 398 /* VGPR_REGS. */ \ 399 {0, 0, 0, 0, \ 400 0, 0xffffffff, 0xffffffff, 0xffffffff, \ 401 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \ 402 /* ALL_GPR_REGS. */ \ 403 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \ 404 0, 0xffffffff, 0xffffffff, 0xffffffff, \ 405 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \ 406 /* SRCDST_REGS. */ \ 407 {0xffffffff, 0xffffffff, 0xffffffff, \ 408 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \ 409 0, 0xffffffff, 0xffffffff, 0xffffffff, \ 410 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \ 411 /* AFP_REGS. */ \ 412 {0, 0, 0, 0, \ 413 0, 0, 0, 0, \ 414 0, 0, 0, 0, 0, 0xf}, \ 415 /* ALL_REGS. */ \ 416 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ 417 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ 418 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0 }} 419 420 #define REGNO_REG_CLASS(REGNO) gcn_regno_reg_class (REGNO) 421 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ 422 gcn_mode_code_base_reg_class (MODE, AS, OUTER, INDEX) 423 #define REGNO_MODE_CODE_OK_FOR_BASE_P(NUM, MODE, AS, OUTER, INDEX) \ 424 gcn_regno_mode_code_ok_for_base_p (NUM, MODE, AS, OUTER, INDEX) 425 #define INDEX_REG_CLASS VGPR_REGS 426 #define REGNO_OK_FOR_INDEX_P(regno) regno_ok_for_index_p (regno) 427 428 429 /* Address spaces. */ 431 enum gcn_address_spaces 432 { 433 ADDR_SPACE_DEFAULT = 0, 434 ADDR_SPACE_FLAT, 435 ADDR_SPACE_SCALAR_FLAT, 436 ADDR_SPACE_FLAT_SCRATCH, 437 ADDR_SPACE_LDS, 438 ADDR_SPACE_GDS, 439 ADDR_SPACE_SCRATCH, 440 ADDR_SPACE_GLOBAL 441 }; 442 #define REGISTER_TARGET_PRAGMAS() do { \ 443 c_register_addr_space ("__flat", ADDR_SPACE_FLAT); \ 444 c_register_addr_space ("__flat_scratch", ADDR_SPACE_FLAT_SCRATCH); \ 445 c_register_addr_space ("__scalar_flat", ADDR_SPACE_SCALAR_FLAT); \ 446 c_register_addr_space ("__lds", ADDR_SPACE_LDS); \ 447 c_register_addr_space ("__gds", ADDR_SPACE_GDS); \ 448 c_register_addr_space ("__global", ADDR_SPACE_GLOBAL); \ 449 } while (0); 450 451 #define STACK_ADDR_SPACE \ 452 (TARGET_GCN5_PLUS ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT) 453 #define DEFAULT_ADDR_SPACE \ 454 ((cfun && cfun->machine && !cfun->machine->use_flat_addressing) \ 455 ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT) 456 #define AS_SCALAR_FLAT_P(AS) ((AS) == ADDR_SPACE_SCALAR_FLAT) 457 #define AS_FLAT_SCRATCH_P(AS) ((AS) == ADDR_SPACE_FLAT_SCRATCH) 458 #define AS_FLAT_P(AS) ((AS) == ADDR_SPACE_FLAT \ 459 || ((AS) == ADDR_SPACE_DEFAULT \ 460 && DEFAULT_ADDR_SPACE == ADDR_SPACE_FLAT)) 461 #define AS_LDS_P(AS) ((AS) == ADDR_SPACE_LDS) 462 #define AS_GDS_P(AS) ((AS) == ADDR_SPACE_GDS) 463 #define AS_SCRATCH_P(AS) ((AS) == ADDR_SPACE_SCRATCH) 464 #define AS_GLOBAL_P(AS) ((AS) == ADDR_SPACE_GLOBAL \ 465 || ((AS) == ADDR_SPACE_DEFAULT \ 466 && DEFAULT_ADDR_SPACE == ADDR_SPACE_GLOBAL)) 467 #define AS_ANY_FLAT_P(AS) (AS_FLAT_SCRATCH_P (AS) || AS_FLAT_P (AS)) 468 #define AS_ANY_DS_P(AS) (AS_LDS_P (AS) || AS_GDS_P (AS)) 469 470 471 /* Instruction Output */ 473 #define REGISTER_NAMES \ 474 {"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", \ 475 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", \ 476 "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", \ 477 "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", \ 478 "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", "s50", \ 479 "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59", "s60", \ 480 "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69", "s70", \ 481 "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", "s80", \ 482 "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89", "s90", \ 483 "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99", \ 484 "s100", "s101", \ 485 "flat_scratch_lo", "flat_scratch_hi", "xnack_mask_lo", "xnack_mask_hi", \ 486 "vcc_lo", "vcc_hi", "vccz", "tba_lo", "tba_hi", "tma_lo", "tma_hi", \ 487 "ttmp0", "ttmp1", "ttmp2", "ttmp3", "ttmp4", "ttmp5", "ttmp6", "ttmp7", \ 488 "ttmp8", "ttmp9", "ttmp10", "ttmp11", "m0", "exec_lo", "exec_hi", \ 489 "execz", "scc", \ 490 "res130", "res131", "res132", "res133", "res134", "res135", "res136", \ 491 "res137", "res138", "res139", "res140", "res141", "res142", "res143", \ 492 "res144", "res145", "res146", "res147", "res148", "res149", "res150", \ 493 "res151", "res152", "res153", "res154", "res155", "res156", "res157", \ 494 "res158", "res159", \ 495 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", \ 496 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", \ 497 "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", \ 498 "v31", "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", "v40", \ 499 "v41", "v42", "v43", "v44", "v45", "v46", "v47", "v48", "v49", "v50", \ 500 "v51", "v52", "v53", "v54", "v55", "v56", "v57", "v58", "v59", "v60", \ 501 "v61", "v62", "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", \ 502 "v71", "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", \ 503 "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", "v90", \ 504 "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", "v99", "v100", \ 505 "v101", "v102", "v103", "v104", "v105", "v106", "v107", "v108", "v109", \ 506 "v110", "v111", "v112", "v113", "v114", "v115", "v116", "v117", "v118", \ 507 "v119", "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", \ 508 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", "v136", \ 509 "v137", "v138", "v139", "v140", "v141", "v142", "v143", "v144", "v145", \ 510 "v146", "v147", "v148", "v149", "v150", "v151", "v152", "v153", "v154", \ 511 "v155", "v156", "v157", "v158", "v159", "v160", "v161", "v162", "v163", \ 512 "v164", "v165", "v166", "v167", "v168", "v169", "v170", "v171", "v172", \ 513 "v173", "v174", "v175", "v176", "v177", "v178", "v179", "v180", "v181", \ 514 "v182", "v183", "v184", "v185", "v186", "v187", "v188", "v189", "v190", \ 515 "v191", "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", \ 516 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", "v208", \ 517 "v209", "v210", "v211", "v212", "v213", "v214", "v215", "v216", "v217", \ 518 "v218", "v219", "v220", "v221", "v222", "v223", "v224", "v225", "v226", \ 519 "v227", "v228", "v229", "v230", "v231", "v232", "v233", "v234", "v235", \ 520 "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \ 521 "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \ 522 "v254", "v255", \ 523 "?ap0", "?ap1", "?fp0", "?fp1" } 524 525 #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) 526 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 527 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '^') 528 529 530 /* Register Arguments */ 532 533 #ifndef USED_FOR_TARGET 534 535 #define GCN_KERNEL_ARG_TYPES 19 536 struct GTY(()) gcn_kernel_args 537 { 538 long requested; 539 int reg[GCN_KERNEL_ARG_TYPES]; 540 int order[GCN_KERNEL_ARG_TYPES]; 541 int nargs, nsgprs; 542 }; 543 544 typedef struct gcn_args 545 { 546 /* True if this isn't a kernel (HSA runtime entrypoint). */ 547 bool normal_function; 548 tree fntype; 549 struct gcn_kernel_args args; 550 int num; 551 int offset; 552 int alignment; 553 } CUMULATIVE_ARGS; 554 #endif 555 556 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 557 gcn_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 558 (N_NAMED_ARGS) != -1) 559 560 561 #ifndef USED_FOR_TARGET 563 564 #include "hash-table.h" 565 #include "hash-map.h" 566 #include "vec.h" 567 568 struct GTY(()) machine_function 569 { 570 struct gcn_kernel_args args; 571 int kernarg_segment_alignment; 572 int kernarg_segment_byte_size; 573 /* Frame layout info for normal functions. */ 574 bool normal_function; 575 bool need_frame_pointer; 576 bool lr_needs_saving; 577 HOST_WIDE_INT outgoing_args_size; 578 HOST_WIDE_INT pretend_size; 579 HOST_WIDE_INT local_vars; 580 HOST_WIDE_INT callee_saves; 581 582 unsigned lds_allocated; 583 hash_map<tree, int> *lds_allocs; 584 585 vec<tree, va_gc> *reduc_decls; 586 587 bool use_flat_addressing; 588 }; 589 #endif 590 591 592 /* Codes for all the GCN builtins. */ 594 595 enum gcn_builtin_codes 596 { 597 #define DEF_BUILTIN(fcode, icode, name, type, params, expander) \ 598 GCN_BUILTIN_ ## fcode, 599 #define DEF_BUILTIN_BINOP_INT_FP(fcode, ic, name) \ 600 GCN_BUILTIN_ ## fcode ## _V64SI, \ 601 GCN_BUILTIN_ ## fcode ## _V64SI_unspec, 602 #include "gcn-builtins.def" 603 #undef DEF_BUILTIN 604 #undef DEF_BUILTIN_BINOP_INT_FP 605 GCN_BUILTIN_MAX 606 }; 607 608 609 /* Misc */ 611 612 /* We can load/store 128-bit quantities, but having this larger than 613 MAX_FIXED_MODE_SIZE (which we want to be 64 bits) causes problems. */ 614 #define MOVE_MAX 8 615 616 #define AVOID_CCMODE_COPIES 1 617 #define SLOW_BYTE_ACCESS 0 618 #define WORD_REGISTER_OPERATIONS 1 619 620 /* Definitions for register eliminations. 621 622 This is an array of structures. Each structure initializes one pair 623 of eliminable registers. The "from" register number is given first, 624 followed by "to". Eliminations of the same "from" register are listed 625 in order of preference. */ 626 627 #define ELIMINABLE_REGS \ 628 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 629 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 630 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 631 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} 632 633 /* Define the offset between two registers, one to be eliminated, and the 634 other its replacement, at the start of a routine. */ 635 636 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 637 ((OFFSET) = gcn_initial_elimination_offset ((FROM), (TO))) 638 639 640 /* Define this macro if it is advisable to hold scalars in registers 641 in a wider mode than that declared by the program. In such cases, 642 the value is constrained to be within the bounds of the declared 643 type, but kept valid in the wider mode. The signedness of the 644 extension may differ from that of the type. */ 645 646 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 647 if (GET_MODE_CLASS (MODE) == MODE_INT \ 648 && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \ 649 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 650 { \ 651 (MODE) = SImode; \ 652 } 653 654 /* This needs to match gcn_function_value. */ 655 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, SGPR_REGNO (RETURN_VALUE_REG)) 656 657 658 /* Costs. */ 660 661 /* Branches are to be dicouraged when theres an alternative. 662 FIXME: This number is plucked from the air. */ 663 #define BRANCH_COST(SPEED_P, PREDICABLE_P) 10 664 665 666 /* Profiling */ 668 #define FUNCTION_PROFILER(FILE, LABELNO) 669 #define NO_PROFILE_COUNTERS 1 670 #define PROFILE_BEFORE_PROLOGUE 0 671 672 /* Trampolines */ 673 #define TRAMPOLINE_SIZE 36 674 #define TRAMPOLINE_ALIGNMENT 64 675
Indexes created Sun Apr 12 00:22:20 UTC 2026