gcn.h revision 1.1.1.3
1 /* Copyright (C) 2016-2022 Free Software Foundation, Inc. 2 3 This file is free software; you can redistribute it and/or modify it under 4 the terms of the GNU General Public License as published by the Free 5 Software Foundation; either version 3 of the License, or (at your option) 6 any later version. 7 8 This file is distributed in the hope that it will be useful, but WITHOUT 9 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 11 for more details. 12 13 You should have received a copy of the GNU General Public License 14 along with GCC; see the file COPYING3. If not see 15 <http://www.gnu.org/licenses/>. */ 16 17 #include "config/gcn/gcn-opts.h" 18 19 #define TARGET_CPU_CPP_BUILTINS() \ 20 do \ 21 { \ 22 builtin_define ("__AMDGCN__"); \ 23 if (TARGET_GCN3) \ 24 builtin_define ("__GCN3__"); \ 25 else if (TARGET_GCN5) \ 26 builtin_define ("__GCN5__"); \ 27 } \ 28 while(0) 29 30 /* Support for a compile-time default architecture and tuning. 31 The rules are: 32 --with-arch is ignored if -march is specified. 33 --with-tune is ignored if -mtune is specified. */ 34 #define OPTION_DEFAULT_SPECS \ 35 {"arch", "%{!march=*:-march=%(VALUE)}" }, \ 36 {"tune", "%{!mtune=*:-mtune=%(VALUE)}" } 37 38 /* Default target_flags if no switches specified. */ 39 #ifndef TARGET_DEFAULT 40 #define TARGET_DEFAULT 0 41 #endif 42 43 44 /* Storage Layout */ 46 #define BITS_BIG_ENDIAN 0 47 #define BYTES_BIG_ENDIAN 0 48 #define WORDS_BIG_ENDIAN 0 49 50 #ifdef IN_LIBGCC2 51 /* We want DImode and TImode helpers. */ 52 #define UNITS_PER_WORD 8 53 #else 54 #define UNITS_PER_WORD 4 55 #endif 56 57 #define POINTER_SIZE 64 58 #define PARM_BOUNDARY 64 59 #define STACK_BOUNDARY 64 60 #define FUNCTION_BOUNDARY 32 61 #define BIGGEST_ALIGNMENT 64 62 #define EMPTY_FIELD_BOUNDARY 32 63 #define MAX_FIXED_MODE_SIZE 128 64 #define MAX_REGS_PER_ADDRESS 2 65 #define STACK_SIZE_MODE DImode 66 #define Pmode DImode 67 #define CASE_VECTOR_MODE DImode 68 #define FUNCTION_MODE QImode 69 70 #define DATA_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 128 ? (ALIGN) : 128) 71 #define LOCAL_ALIGNMENT(TYPE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64) 72 #define STACK_SLOT_ALIGNMENT(TYPE,MODE,ALIGN) ((ALIGN) > 64 ? (ALIGN) : 64) 73 #define STRICT_ALIGNMENT 1 74 75 /* Type Layout: match what x86_64 does. */ 76 #define INT_TYPE_SIZE 32 77 #define LONG_TYPE_SIZE 64 78 #define LONG_LONG_TYPE_SIZE 64 79 #define FLOAT_TYPE_SIZE 32 80 #define DOUBLE_TYPE_SIZE 64 81 #define LONG_DOUBLE_TYPE_SIZE 64 82 #define DEFAULT_SIGNED_CHAR 1 83 #define PCC_BITFIELD_TYPE_MATTERS 1 84 85 /* Frame Layout */ 86 #define FRAME_GROWS_DOWNWARD 0 87 #define ARGS_GROW_DOWNWARD 1 88 #define STACK_POINTER_OFFSET 0 89 #define FIRST_PARM_OFFSET(FNDECL) 0 90 #define DYNAMIC_CHAIN_ADDRESS(FP) plus_constant (Pmode, (FP), -16) 91 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LINK_REGNUM) 92 #define DWARF_FRAME_RETURN_COLUMN 16 93 #define STACK_DYNAMIC_OFFSET(FNDECL) (-crtl->outgoing_args_size) 94 #define ACCUMULATE_OUTGOING_ARGS 1 95 #define RETURN_ADDR_RTX(COUNT,FRAMEADDR) \ 96 ((COUNT) == 0 ? get_hard_reg_initial_val (Pmode, LINK_REGNUM) : NULL_RTX) 97 98 /* Register Basics */ 100 #define FIRST_SGPR_REG 0 101 #define SGPR_REGNO(N) ((N)+FIRST_SGPR_REG) 102 #define LAST_SGPR_REG 101 103 104 #define FLAT_SCRATCH_REG 102 105 #define FLAT_SCRATCH_LO_REG 102 106 #define FLAT_SCRATCH_HI_REG 103 107 #define XNACK_MASK_REG 104 108 #define XNACK_MASK_LO_REG 104 109 #define XNACK_MASK_HI_REG 105 110 #define VCC_LO_REG 106 111 #define VCC_HI_REG 107 112 #define VCCZ_REG 108 113 #define TBA_REG 109 114 #define TBA_LO_REG 109 115 #define TBA_HI_REG 110 116 #define TMA_REG 111 117 #define TMA_LO_REG 111 118 #define TMA_HI_REG 112 119 #define TTMP0_REG 113 120 #define TTMP11_REG 124 121 #define M0_REG 125 122 #define EXEC_REG 126 123 #define EXEC_LO_REG 126 124 #define EXEC_HI_REG 127 125 #define EXECZ_REG 128 126 #define SCC_REG 129 127 /* 132-159 are reserved to simplify masks. */ 128 #define FIRST_VGPR_REG 160 129 #define VGPR_REGNO(N) ((N)+FIRST_VGPR_REG) 130 #define LAST_VGPR_REG 415 131 132 /* Frame Registers, and other registers */ 133 134 #define HARD_FRAME_POINTER_REGNUM 14 135 #define STACK_POINTER_REGNUM 16 136 #define LINK_REGNUM 18 137 #define EXEC_SAVE_REG 20 138 #define CC_SAVE_REG 22 139 #define RETURN_VALUE_REG 24 /* Must be divisible by 4. */ 140 #define STATIC_CHAIN_REGNUM 30 141 #define WORK_ITEM_ID_Z_REG 162 142 #define SOFT_ARG_REG 416 143 #define FRAME_POINTER_REGNUM 418 144 #define DWARF_LINK_REGISTER 420 145 #define FIRST_PSEUDO_REGISTER 421 146 147 #define FIRST_PARM_REG 24 148 #define NUM_PARM_REGS 6 149 150 /* There is no arg pointer. Just choose random fixed register that does 151 not intefere with anything. */ 152 #define ARG_POINTER_REGNUM SOFT_ARG_REG 153 154 #define HARD_FRAME_POINTER_IS_ARG_POINTER 0 155 #define HARD_FRAME_POINTER_IS_FRAME_POINTER 0 156 157 #define SGPR_OR_VGPR_REGNO_P(N) ((N)>=FIRST_VGPR_REG && (N) <= LAST_SGPR_REG) 158 #define SGPR_REGNO_P(N) ((N) <= LAST_SGPR_REG) 159 #define VGPR_REGNO_P(N) ((N)>=FIRST_VGPR_REG && (N) <= LAST_VGPR_REG) 160 #define SSRC_REGNO_P(N) ((N) <= SCC_REG && (N) != VCCZ_REG) 161 #define SDST_REGNO_P(N) ((N) <= EXEC_HI_REG && (N) != VCCZ_REG) 162 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 163 #define CC_REGNO_P(X) ((X) == SCC_REG || (X) == VCC_REG) 164 #define FUNCTION_ARG_REGNO_P(N) \ 165 ((N) >= FIRST_PARM_REG && (N) < (FIRST_PARM_REG + NUM_PARM_REGS)) 166 167 168 #define FIXED_REGISTERS { \ 170 /* Scalars. */ \ 171 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, \ 172 /* fp sp lr. */ \ 173 1, 1, 0, 0, 0, 0, 1, 1, 0, 0, \ 174 /* exec_save, cc_save */ \ 175 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, \ 176 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 177 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 178 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 179 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 180 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 181 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 182 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 183 /* Special regs and padding. */ \ 184 /* flat xnack vcc tba tma ttmp */ \ 185 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 186 /* m0 exec scc */ \ 187 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, \ 188 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 189 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 190 /* VGRPs */ \ 191 0, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 192 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 193 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 194 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 195 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 196 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 197 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 198 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 199 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 200 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 201 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 202 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 203 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 204 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 205 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 206 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 207 /* Other registers. */ \ 208 1, 1, 1, 1, 1 \ 209 } 210 211 #define CALL_USED_REGISTERS { \ 212 /* Scalars. */ \ 213 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 214 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, \ 215 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 216 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 217 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 218 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 219 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 220 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 221 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 222 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \ 223 /* Special regs and padding. */ \ 224 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 225 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 226 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 227 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 228 /* VGRPs */ \ 229 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 230 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 231 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 232 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 233 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 234 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 235 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 236 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 237 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 238 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 239 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 240 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 241 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 242 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 243 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 244 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 245 /* Other registers. */ \ 246 1, 1, 1, 1, 1 \ 247 } 248 249 250 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 252 gcn_hard_regno_rename_ok (FROM, TO) 253 254 #define HARD_REGNO_CALLER_SAVE_MODE(HARDREG, NREGS, MODE) \ 255 gcn_hard_regno_caller_save_mode ((HARDREG), (NREGS), (MODE)) 256 257 /* Register Classes */ 258 259 enum reg_class 260 { 261 NO_REGS, 262 263 /* SCC */ 264 SCC_CONDITIONAL_REG, 265 266 /* VCCZ */ 267 VCCZ_CONDITIONAL_REG, 268 269 /* VCC */ 270 VCC_CONDITIONAL_REG, 271 272 /* EXECZ */ 273 EXECZ_CONDITIONAL_REG, 274 275 /* SCC VCCZ EXECZ */ 276 ALL_CONDITIONAL_REGS, 277 278 /* EXEC */ 279 EXEC_MASK_REG, 280 281 /* SGPR0-101 */ 282 SGPR_REGS, 283 284 /* SGPR0-101 EXEC_LO/EXEC_HI */ 285 SGPR_EXEC_REGS, 286 287 /* SGPR0-101, FLAT_SCRATCH_LO/HI, VCC LO/HI, TBA LO/HI, TMA LO/HI, TTMP0-11, 288 M0, VCCZ, SCC 289 (EXEC_LO/HI, EXECZ excluded to prevent compiler misuse.) */ 290 SGPR_VOP_SRC_REGS, 291 292 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI 293 TMA LO/HI, TTMP0-11 */ 294 SGPR_MEM_SRC_REGS, 295 296 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI 297 TMA LO/HI, TTMP0-11, M0, EXEC LO/HI */ 298 SGPR_DST_REGS, 299 300 /* SGPR0-101, FLAT_SCRATCH_LO/HI, XNACK_MASK_LO/HI, VCC LO/HI, TBA LO/HI 301 TMA LO/HI, TTMP0-11 */ 302 SGPR_SRC_REGS, 303 GENERAL_REGS, 304 VGPR_REGS, 305 ALL_GPR_REGS, 306 SRCDST_REGS, 307 AFP_REGS, 308 ALL_REGS, 309 LIM_REG_CLASSES 310 }; 311 312 #define N_REG_CLASSES (int) LIM_REG_CLASSES 313 314 #define REG_CLASS_NAMES \ 315 { "NO_REGS", \ 316 "SCC_CONDITIONAL_REG", \ 317 "VCCZ_CONDITIONAL_REG", \ 318 "VCC_CONDITIONAL_REG", \ 319 "EXECZ_CONDITIONAL_REG", \ 320 "ALL_CONDITIONAL_REGS", \ 321 "EXEC_MASK_REG", \ 322 "SGPR_REGS", \ 323 "SGPR_EXEC_REGS", \ 324 "SGPR_VOP3A_SRC_REGS", \ 325 "SGPR_MEM_SRC_REGS", \ 326 "SGPR_DST_REGS", \ 327 "SGPR_SRC_REGS", \ 328 "GENERAL_REGS", \ 329 "VGPR_REGS", \ 330 "ALL_GPR_REGS", \ 331 "SRCDST_REGS", \ 332 "AFP_REGS", \ 333 "ALL_REGS" \ 334 } 335 336 #define NAMED_REG_MASK(N) (1<<((N)-3*32)) 337 #define NAMED_REG_MASK2(N) (1<<((N)-4*32)) 338 339 #define REG_CLASS_CONTENTS { \ 340 /* NO_REGS. */ \ 341 {0, 0, 0, 0, \ 342 0, 0, 0, 0, \ 343 0, 0, 0, 0, 0, 0}, \ 344 /* SCC_CONDITIONAL_REG. */ \ 345 {0, 0, 0, 0, \ 346 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 347 0, 0, 0, 0, 0}, \ 348 /* VCCZ_CONDITIONAL_REG. */ \ 349 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \ 350 0, 0, 0, 0, \ 351 0, 0, 0, 0, 0, 0}, \ 352 /* VCC_CONDITIONAL_REG. */ \ 353 {0, 0, 0, NAMED_REG_MASK (VCC_LO_REG)|NAMED_REG_MASK (VCC_HI_REG), \ 354 0, 0, 0, 0, \ 355 0, 0, 0, 0, 0, 0}, \ 356 /* EXECZ_CONDITIONAL_REG. */ \ 357 {0, 0, 0, 0, \ 358 NAMED_REG_MASK2 (EXECZ_REG), 0, 0, 0, \ 359 0, 0, 0, 0, 0}, \ 360 /* ALL_CONDITIONAL_REGS. */ \ 361 {0, 0, 0, NAMED_REG_MASK (VCCZ_REG), \ 362 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 363 0, 0, 0, 0, 0, 0}, \ 364 /* EXEC_MASK_REG. */ \ 365 {0, 0, 0, NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \ 366 0, 0, 0, 0, \ 367 0, 0, 0, 0, 0, 0}, \ 368 /* SGPR_REGS. */ \ 369 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \ 370 0, 0, 0, 0, \ 371 0, 0, 0, 0, 0, 0}, \ 372 /* SGPR_EXEC_REGS. */ \ 373 {0xffffffff, 0xffffffff, 0xffffffff, \ 374 0xf1 | NAMED_REG_MASK (EXEC_LO_REG) | NAMED_REG_MASK (EXEC_HI_REG), \ 375 0, 0, 0, 0, \ 376 0, 0, 0, 0, 0, 0}, \ 377 /* SGPR_VOP_SRC_REGS. */ \ 378 {0xffffffff, 0xffffffff, 0xffffffff, \ 379 0xffffffff \ 380 -NAMED_REG_MASK (EXEC_LO_REG) \ 381 -NAMED_REG_MASK (EXEC_HI_REG), \ 382 NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 383 0, 0, 0, 0, 0, 0}, \ 384 /* SGPR_MEM_SRC_REGS. */ \ 385 {0xffffffff, 0xffffffff, 0xffffffff, \ 386 0xffffffff-NAMED_REG_MASK (VCCZ_REG)-NAMED_REG_MASK (M0_REG) \ 387 -NAMED_REG_MASK (EXEC_LO_REG)-NAMED_REG_MASK (EXEC_HI_REG), \ 388 0, 0, 0, 0, \ 389 0, 0, 0, 0, 0, 0}, \ 390 /* SGPR_DST_REGS. */ \ 391 {0xffffffff, 0xffffffff, 0xffffffff, \ 392 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \ 393 0, 0, 0, 0, \ 394 0, 0, 0, 0, 0, 0}, \ 395 /* SGPR_SRC_REGS. */ \ 396 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ 397 NAMED_REG_MASK2 (EXECZ_REG) | NAMED_REG_MASK2 (SCC_REG), 0, 0, 0, \ 398 0, 0, 0, 0, 0, 0}, \ 399 /* GENERAL_REGS. */ \ 400 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \ 401 0, 0, 0, 0, \ 402 0, 0, 0, 0, 0, 0}, \ 403 /* VGPR_REGS. */ \ 404 {0, 0, 0, 0, \ 405 0, 0xffffffff, 0xffffffff, 0xffffffff, \ 406 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \ 407 /* ALL_GPR_REGS. */ \ 408 {0xffffffff, 0xffffffff, 0xffffffff, 0xf1, \ 409 0, 0xffffffff, 0xffffffff, 0xffffffff, \ 410 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \ 411 /* SRCDST_REGS. */ \ 412 {0xffffffff, 0xffffffff, 0xffffffff, \ 413 0xffffffff-NAMED_REG_MASK (VCCZ_REG), \ 414 0, 0xffffffff, 0xffffffff, 0xffffffff, \ 415 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0}, \ 416 /* AFP_REGS. */ \ 417 {0, 0, 0, 0, \ 418 0, 0, 0, 0, \ 419 0, 0, 0, 0, 0, 0xf}, \ 420 /* ALL_REGS. */ \ 421 {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ 422 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, \ 423 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0 }} 424 425 #define REGNO_REG_CLASS(REGNO) gcn_regno_reg_class (REGNO) 426 #define MODE_CODE_BASE_REG_CLASS(MODE, AS, OUTER, INDEX) \ 427 gcn_mode_code_base_reg_class (MODE, AS, OUTER, INDEX) 428 #define REGNO_MODE_CODE_OK_FOR_BASE_P(NUM, MODE, AS, OUTER, INDEX) \ 429 gcn_regno_mode_code_ok_for_base_p (NUM, MODE, AS, OUTER, INDEX) 430 #define INDEX_REG_CLASS VGPR_REGS 431 #define REGNO_OK_FOR_INDEX_P(regno) regno_ok_for_index_p (regno) 432 433 434 /* Address spaces. */ 436 enum gcn_address_spaces 437 { 438 ADDR_SPACE_DEFAULT = 0, 439 ADDR_SPACE_FLAT, 440 ADDR_SPACE_SCALAR_FLAT, 441 ADDR_SPACE_FLAT_SCRATCH, 442 ADDR_SPACE_LDS, 443 ADDR_SPACE_GDS, 444 ADDR_SPACE_SCRATCH, 445 ADDR_SPACE_GLOBAL 446 }; 447 #define REGISTER_TARGET_PRAGMAS() do { \ 448 c_register_addr_space ("__flat", ADDR_SPACE_FLAT); \ 449 c_register_addr_space ("__flat_scratch", ADDR_SPACE_FLAT_SCRATCH); \ 450 c_register_addr_space ("__scalar_flat", ADDR_SPACE_SCALAR_FLAT); \ 451 c_register_addr_space ("__lds", ADDR_SPACE_LDS); \ 452 c_register_addr_space ("__gds", ADDR_SPACE_GDS); \ 453 c_register_addr_space ("__global", ADDR_SPACE_GLOBAL); \ 454 } while (0); 455 456 #define STACK_ADDR_SPACE \ 457 (TARGET_GCN5_PLUS ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT) 458 #define DEFAULT_ADDR_SPACE \ 459 ((cfun && cfun->machine && !cfun->machine->use_flat_addressing) \ 460 ? ADDR_SPACE_GLOBAL : ADDR_SPACE_FLAT) 461 #define AS_SCALAR_FLAT_P(AS) ((AS) == ADDR_SPACE_SCALAR_FLAT) 462 #define AS_FLAT_SCRATCH_P(AS) ((AS) == ADDR_SPACE_FLAT_SCRATCH) 463 #define AS_FLAT_P(AS) ((AS) == ADDR_SPACE_FLAT \ 464 || ((AS) == ADDR_SPACE_DEFAULT \ 465 && DEFAULT_ADDR_SPACE == ADDR_SPACE_FLAT)) 466 #define AS_LDS_P(AS) ((AS) == ADDR_SPACE_LDS) 467 #define AS_GDS_P(AS) ((AS) == ADDR_SPACE_GDS) 468 #define AS_SCRATCH_P(AS) ((AS) == ADDR_SPACE_SCRATCH) 469 #define AS_GLOBAL_P(AS) ((AS) == ADDR_SPACE_GLOBAL \ 470 || ((AS) == ADDR_SPACE_DEFAULT \ 471 && DEFAULT_ADDR_SPACE == ADDR_SPACE_GLOBAL)) 472 #define AS_ANY_FLAT_P(AS) (AS_FLAT_SCRATCH_P (AS) || AS_FLAT_P (AS)) 473 #define AS_ANY_DS_P(AS) (AS_LDS_P (AS) || AS_GDS_P (AS)) 474 475 476 /* Instruction Output */ 478 #define REGISTER_NAMES \ 479 {"s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", "s8", "s9", "s10", \ 480 "s11", "s12", "s13", "s14", "s15", "s16", "s17", "s18", "s19", "s20", \ 481 "s21", "s22", "s23", "s24", "s25", "s26", "s27", "s28", "s29", "s30", \ 482 "s31", "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39", "s40", \ 483 "s41", "s42", "s43", "s44", "s45", "s46", "s47", "s48", "s49", "s50", \ 484 "s51", "s52", "s53", "s54", "s55", "s56", "s57", "s58", "s59", "s60", \ 485 "s61", "s62", "s63", "s64", "s65", "s66", "s67", "s68", "s69", "s70", \ 486 "s71", "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79", "s80", \ 487 "s81", "s82", "s83", "s84", "s85", "s86", "s87", "s88", "s89", "s90", \ 488 "s91", "s92", "s93", "s94", "s95", "s96", "s97", "s98", "s99", \ 489 "s100", "s101", \ 490 "flat_scratch_lo", "flat_scratch_hi", "xnack_mask_lo", "xnack_mask_hi", \ 491 "vcc_lo", "vcc_hi", "vccz", "tba_lo", "tba_hi", "tma_lo", "tma_hi", \ 492 "ttmp0", "ttmp1", "ttmp2", "ttmp3", "ttmp4", "ttmp5", "ttmp6", "ttmp7", \ 493 "ttmp8", "ttmp9", "ttmp10", "ttmp11", "m0", "exec_lo", "exec_hi", \ 494 "execz", "scc", \ 495 "res130", "res131", "res132", "res133", "res134", "res135", "res136", \ 496 "res137", "res138", "res139", "res140", "res141", "res142", "res143", \ 497 "res144", "res145", "res146", "res147", "res148", "res149", "res150", \ 498 "res151", "res152", "res153", "res154", "res155", "res156", "res157", \ 499 "res158", "res159", \ 500 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", "v8", "v9", "v10", \ 501 "v11", "v12", "v13", "v14", "v15", "v16", "v17", "v18", "v19", "v20", \ 502 "v21", "v22", "v23", "v24", "v25", "v26", "v27", "v28", "v29", "v30", \ 503 "v31", "v32", "v33", "v34", "v35", "v36", "v37", "v38", "v39", "v40", \ 504 "v41", "v42", "v43", "v44", "v45", "v46", "v47", "v48", "v49", "v50", \ 505 "v51", "v52", "v53", "v54", "v55", "v56", "v57", "v58", "v59", "v60", \ 506 "v61", "v62", "v63", "v64", "v65", "v66", "v67", "v68", "v69", "v70", \ 507 "v71", "v72", "v73", "v74", "v75", "v76", "v77", "v78", "v79", "v80", \ 508 "v81", "v82", "v83", "v84", "v85", "v86", "v87", "v88", "v89", "v90", \ 509 "v91", "v92", "v93", "v94", "v95", "v96", "v97", "v98", "v99", "v100", \ 510 "v101", "v102", "v103", "v104", "v105", "v106", "v107", "v108", "v109", \ 511 "v110", "v111", "v112", "v113", "v114", "v115", "v116", "v117", "v118", \ 512 "v119", "v120", "v121", "v122", "v123", "v124", "v125", "v126", "v127", \ 513 "v128", "v129", "v130", "v131", "v132", "v133", "v134", "v135", "v136", \ 514 "v137", "v138", "v139", "v140", "v141", "v142", "v143", "v144", "v145", \ 515 "v146", "v147", "v148", "v149", "v150", "v151", "v152", "v153", "v154", \ 516 "v155", "v156", "v157", "v158", "v159", "v160", "v161", "v162", "v163", \ 517 "v164", "v165", "v166", "v167", "v168", "v169", "v170", "v171", "v172", \ 518 "v173", "v174", "v175", "v176", "v177", "v178", "v179", "v180", "v181", \ 519 "v182", "v183", "v184", "v185", "v186", "v187", "v188", "v189", "v190", \ 520 "v191", "v192", "v193", "v194", "v195", "v196", "v197", "v198", "v199", \ 521 "v200", "v201", "v202", "v203", "v204", "v205", "v206", "v207", "v208", \ 522 "v209", "v210", "v211", "v212", "v213", "v214", "v215", "v216", "v217", \ 523 "v218", "v219", "v220", "v221", "v222", "v223", "v224", "v225", "v226", \ 524 "v227", "v228", "v229", "v230", "v231", "v232", "v233", "v234", "v235", \ 525 "v236", "v237", "v238", "v239", "v240", "v241", "v242", "v243", "v244", \ 526 "v245", "v246", "v247", "v248", "v249", "v250", "v251", "v252", "v253", \ 527 "v254", "v255", \ 528 "?ap0", "?ap1", "?fp0", "?fp1", "?dwlr" } 529 530 #define PRINT_OPERAND(FILE, X, CODE) print_operand(FILE, X, CODE) 531 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 532 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) (CODE == '^') 533 534 535 /* Register Arguments */ 537 538 #ifndef USED_FOR_TARGET 539 540 #define GCN_KERNEL_ARG_TYPES 16 541 struct GTY(()) gcn_kernel_args 542 { 543 long requested; 544 int reg[GCN_KERNEL_ARG_TYPES]; 545 int order[GCN_KERNEL_ARG_TYPES]; 546 int nargs, nsgprs; 547 }; 548 549 typedef struct gcn_args 550 { 551 /* True if this isn't a kernel (HSA runtime entrypoint). */ 552 bool normal_function; 553 tree fntype; 554 struct gcn_kernel_args args; 555 int num; 556 int offset; 557 int alignment; 558 } CUMULATIVE_ARGS; 559 #endif 560 561 #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 562 gcn_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 563 (N_NAMED_ARGS) != -1) 564 565 566 #ifndef USED_FOR_TARGET 568 569 #include "hash-table.h" 570 #include "hash-map.h" 571 #include "vec.h" 572 573 struct GTY(()) machine_function 574 { 575 struct gcn_kernel_args args; 576 int kernarg_segment_alignment; 577 int kernarg_segment_byte_size; 578 /* Frame layout info for normal functions. */ 579 bool normal_function; 580 bool need_frame_pointer; 581 bool lr_needs_saving; 582 HOST_WIDE_INT outgoing_args_size; 583 HOST_WIDE_INT pretend_size; 584 HOST_WIDE_INT local_vars; 585 HOST_WIDE_INT callee_saves; 586 587 unsigned HOST_WIDE_INT reduction_base; 588 unsigned HOST_WIDE_INT reduction_limit; 589 590 bool use_flat_addressing; 591 }; 592 #endif 593 594 595 /* Codes for all the GCN builtins. */ 597 598 enum gcn_builtin_codes 599 { 600 #define DEF_BUILTIN(fcode, icode, name, type, params, expander) \ 601 GCN_BUILTIN_ ## fcode, 602 #define DEF_BUILTIN_BINOP_INT_FP(fcode, ic, name) \ 603 GCN_BUILTIN_ ## fcode ## _V64SI, \ 604 GCN_BUILTIN_ ## fcode ## _V64SI_unspec, 605 #include "gcn-builtins.def" 606 #undef DEF_BUILTIN 607 #undef DEF_BUILTIN_BINOP_INT_FP 608 GCN_BUILTIN_MAX 609 }; 610 611 612 /* Misc */ 614 615 /* We can load/store 128-bit quantities, but having this larger than 616 MAX_FIXED_MODE_SIZE (which we want to be 64 bits) causes problems. */ 617 #define MOVE_MAX 8 618 619 #define AVOID_CCMODE_COPIES 1 620 #define SLOW_BYTE_ACCESS 0 621 #define WORD_REGISTER_OPERATIONS 1 622 623 /* Flag values are either BImode or DImode, but either way the compiler 624 should assume that all the bits are live. */ 625 #define STORE_FLAG_VALUE -1 626 627 /* Definitions for register eliminations. 628 629 This is an array of structures. Each structure initializes one pair 630 of eliminable registers. The "from" register number is given first, 631 followed by "to". Eliminations of the same "from" register are listed 632 in order of preference. */ 633 634 #define ELIMINABLE_REGS \ 635 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 636 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 637 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 638 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }} 639 640 /* Define the offset between two registers, one to be eliminated, and the 641 other its replacement, at the start of a routine. */ 642 643 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 644 ((OFFSET) = gcn_initial_elimination_offset ((FROM), (TO))) 645 646 647 /* Define this macro if it is advisable to hold scalars in registers 648 in a wider mode than that declared by the program. In such cases, 649 the value is constrained to be within the bounds of the declared 650 type, but kept valid in the wider mode. The signedness of the 651 extension may differ from that of the type. */ 652 653 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 654 if (GET_MODE_CLASS (MODE) == MODE_INT \ 655 && (TYPE == NULL || TREE_CODE (TYPE) != VECTOR_TYPE) \ 656 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 657 { \ 658 (MODE) = SImode; \ 659 } 660 661 /* This needs to match gcn_function_value. */ 662 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, SGPR_REGNO (RETURN_VALUE_REG)) 663 664 /* The s_ff0 and s_flbit instructions return -1 if no input bits are set. */ 665 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2) 666 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 2) 667 668 669 /* Costs. */ 671 672 /* Branches are to be dicouraged when theres an alternative. 673 FIXME: This number is plucked from the air. */ 674 #define BRANCH_COST(SPEED_P, PREDICABLE_P) 10 675 676 677 /* Profiling */ 679 #define FUNCTION_PROFILER(FILE, LABELNO) 680 #define NO_PROFILE_COUNTERS 1 681 #define PROFILE_BEFORE_PROLOGUE 0 682 683 /* Trampolines */ 684 #define TRAMPOLINE_SIZE 36 685 #define TRAMPOLINE_ALIGNMENT 64 686
Indexes created Sun Apr 12 00:22:20 UTC 2026