h8300.cc revision 1.1
1 /* Subroutines for insn-output.cc for Renesas H8/300. 2 Copyright (C) 1992-2022 Free Software Foundation, Inc. 3 Contributed by Steve Chamberlain (sac (at) cygnus.com), 4 Jim Wilson (wilson (at) cygnus.com), and Doug Evans (dje (at) cygnus.com). 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #define IN_TARGET_CODE 1 23 24 #include "config.h" 25 #include "system.h" 26 #include "coretypes.h" 27 #include "backend.h" 28 #include "target.h" 29 #include "rtl.h" 30 #include "tree.h" 31 #include "df.h" 32 #include "memmodel.h" 33 #include "tm_p.h" 34 #include "stringpool.h" 35 #include "attribs.h" 36 #include "optabs.h" 37 #include "regs.h" 38 #include "emit-rtl.h" 39 #include "recog.h" 40 #include "diagnostic-core.h" 41 #include "alias.h" 42 #include "stor-layout.h" 43 #include "varasm.h" 44 #include "calls.h" 45 #include "conditions.h" 46 #include "output.h" 47 #include "insn-attr.h" 48 #include "flags.h" 49 #include "explow.h" 50 #include "expr.h" 51 #include "tm-constrs.h" 52 #include "builtins.h" 53 54 /* This file should be included last. */ 55 #include "target-def.h" 56 57 /* Classifies a h8300_src_operand or h8300_dst_operand. 58 59 H8OP_IMMEDIATE 60 A constant operand of some sort. 61 62 H8OP_REGISTER 63 An ordinary register. 64 65 H8OP_MEM_ABSOLUTE 66 A memory reference with a constant address. 67 68 H8OP_MEM_BASE 69 A memory reference with a register as its address. 70 71 H8OP_MEM_COMPLEX 72 Some other kind of memory reference. */ 73 enum h8300_operand_class 74 { 75 H8OP_IMMEDIATE, 76 H8OP_REGISTER, 77 H8OP_MEM_ABSOLUTE, 78 H8OP_MEM_BASE, 79 H8OP_MEM_COMPLEX, 80 NUM_H8OPS 81 }; 82 83 /* For a general two-operand instruction, element [X][Y] gives 84 the length of the opcode fields when the first operand has class 85 (X + 1) and the second has class Y. */ 86 typedef unsigned char h8300_length_table[NUM_H8OPS - 1][NUM_H8OPS]; 87 88 /* Forward declarations. */ 89 static const char *byte_reg (rtx, int); 90 static int h8300_interrupt_function_p (tree); 91 static int h8300_saveall_function_p (tree); 92 static int h8300_monitor_function_p (tree); 93 static int h8300_os_task_function_p (tree); 94 static void h8300_emit_stack_adjustment (int, HOST_WIDE_INT); 95 static HOST_WIDE_INT round_frame_size (HOST_WIDE_INT); 96 static unsigned int compute_saved_regs (void); 97 static const char *cond_string (enum rtx_code); 98 static unsigned int h8300_asm_insn_count (const char *); 99 static tree h8300_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 100 static tree h8300_handle_eightbit_data_attribute (tree *, tree, tree, int, bool *); 101 static tree h8300_handle_tiny_data_attribute (tree *, tree, tree, int, bool *); 102 static void h8300_print_operand_address (FILE *, machine_mode, rtx); 103 static void h8300_print_operand (FILE *, rtx, int); 104 static bool h8300_print_operand_punct_valid_p (unsigned char code); 105 static int h8300_register_move_cost (machine_mode, reg_class_t, reg_class_t); 106 static int h8300_and_costs (rtx); 107 static int h8300_shift_costs (rtx); 108 static void h8300_push_pop (int, int, bool, bool); 109 static int h8300_stack_offset_p (rtx, int); 110 static int h8300_ldm_stm_regno (rtx, int, int, int); 111 static void h8300_reorg (void); 112 static unsigned int h8300_constant_length (rtx); 113 static unsigned int h8300_displacement_length (rtx, int); 114 static unsigned int h8300_classify_operand (rtx, int, enum h8300_operand_class *); 115 static unsigned int h8300_length_from_table (rtx, rtx, const h8300_length_table *); 116 static unsigned int h8300_unary_length (rtx); 117 static unsigned int h8300_short_immediate_length (rtx); 118 static unsigned int h8300_bitfield_length (rtx, rtx); 119 static unsigned int h8300_binary_length (rtx_insn *, const h8300_length_table *); 120 static bool h8300_short_move_mem_p (rtx, enum rtx_code); 121 static unsigned int h8300_move_length (rtx *, const h8300_length_table *); 122 static bool h8300_hard_regno_scratch_ok (unsigned int); 123 static rtx h8300_get_index (rtx, machine_mode mode, int *); 124 125 /* CPU_TYPE, says what cpu we're compiling for. */ 126 int cpu_type; 127 128 /* True if a #pragma interrupt has been seen for the current function. */ 129 static int pragma_interrupt; 130 131 /* True if a #pragma saveall has been seen for the current function. */ 132 static int pragma_saveall; 133 134 static const char *const names_big[] = 135 { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc" }; 136 137 static const char *const names_extended[] = 138 { "er0", "er1", "er2", "er3", "er4", "er5", "er6", "er7", "cc" }; 139 140 static const char *const names_upper_extended[] = 141 { "e0", "e1", "e2", "e3", "e4", "e5", "e6", "e7", "cc" }; 142 143 /* Points to one of the above. */ 144 /* ??? The above could be put in an array indexed by CPU_TYPE. */ 145 const char * const *h8_reg_names; 146 147 /* Various operations needed by the following, indexed by CPU_TYPE. */ 148 149 const char *h8_push_op, *h8_pop_op, *h8_mov_op; 150 151 /* Value of MOVE_RATIO. */ 152 int h8300_move_ratio; 153 154 /* See below where shifts are handled for explanation of this enum. */ 156 157 enum shift_alg 158 { 159 SHIFT_INLINE, 160 SHIFT_ROT_AND, 161 SHIFT_SPECIAL, 162 SHIFT_LOOP 163 }; 164 165 /* Symbols of the various shifts which can be used as indices. */ 166 167 enum shift_type 168 { 169 SHIFT_ASHIFT, SHIFT_LSHIFTRT, SHIFT_ASHIFTRT 170 }; 171 172 /* Macros to keep the shift algorithm tables small. */ 173 #define INL SHIFT_INLINE 174 #define ROT SHIFT_ROT_AND 175 #define LOP SHIFT_LOOP 176 #define SPC SHIFT_SPECIAL 177 178 /* The shift algorithms for each machine, mode, shift type, and shift 179 count are defined below. The three tables below correspond to 180 QImode, HImode, and SImode, respectively. Each table is organized 181 by, in the order of indices, machine, shift type, and shift count. */ 182 183 static enum shift_alg shift_alg_qi[2][3][8] = { 184 { 185 /* TARGET_H8300H */ 186 /* 0 1 2 3 4 5 6 7 */ 187 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 188 { INL, INL, INL, INL, INL, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 189 { INL, INL, INL, INL, INL, LOP, LOP, SPC } /* SHIFT_ASHIFTRT */ 190 }, 191 { 192 /* TARGET_H8300S */ 193 /* 0 1 2 3 4 5 6 7 */ 194 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_ASHIFT */ 195 { INL, INL, INL, INL, INL, INL, ROT, ROT }, /* SHIFT_LSHIFTRT */ 196 { INL, INL, INL, INL, INL, INL, INL, SPC } /* SHIFT_ASHIFTRT */ 197 } 198 }; 199 200 static enum shift_alg shift_alg_hi[2][3][16] = { 201 { 202 /* TARGET_H8300H */ 203 /* 0 1 2 3 4 5 6 7 */ 204 /* 8 9 10 11 12 13 14 15 */ 205 { INL, INL, INL, INL, INL, INL, INL, SPC, 206 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 207 { INL, INL, INL, INL, INL, INL, INL, SPC, 208 SPC, SPC, SPC, SPC, SPC, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 209 { INL, INL, INL, INL, INL, INL, INL, SPC, 210 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 211 }, 212 { 213 /* TARGET_H8300S */ 214 /* 0 1 2 3 4 5 6 7 */ 215 /* 8 9 10 11 12 13 14 15 */ 216 { INL, INL, INL, INL, INL, INL, INL, INL, 217 SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_ASHIFT */ 218 { INL, INL, INL, INL, INL, INL, INL, INL, 219 SPC, SPC, SPC, SPC, ROT, ROT, ROT, ROT }, /* SHIFT_LSHIFTRT */ 220 { INL, INL, INL, INL, INL, INL, INL, INL, 221 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 222 } 223 }; 224 225 static enum shift_alg shift_alg_si[2][3][32] = { 226 { 227 /* TARGET_H8300H */ 228 /* 0 1 2 3 4 5 6 7 */ 229 /* 8 9 10 11 12 13 14 15 */ 230 /* 16 17 18 19 20 21 22 23 */ 231 /* 24 25 26 27 28 29 30 31 */ 232 { INL, INL, INL, INL, INL, INL, INL, LOP, 233 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 234 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 235 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 236 { INL, INL, INL, INL, INL, INL, INL, LOP, 237 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 238 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 239 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 240 { INL, INL, INL, INL, INL, INL, INL, LOP, 241 SPC, LOP, LOP, LOP, LOP, LOP, LOP, SPC, 242 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 243 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 244 }, 245 { 246 /* TARGET_H8300S */ 247 /* 0 1 2 3 4 5 6 7 */ 248 /* 8 9 10 11 12 13 14 15 */ 249 /* 16 17 18 19 20 21 22 23 */ 250 /* 24 25 26 27 28 29 30 31 */ 251 { INL, INL, INL, INL, INL, INL, INL, INL, 252 INL, INL, INL, INL, INL, INL, INL, SPC, 253 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 254 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFT */ 255 { INL, INL, INL, INL, INL, INL, INL, INL, 256 INL, INL, INL, INL, INL, INL, INL, SPC, 257 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 258 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_LSHIFTRT */ 259 { INL, INL, INL, INL, INL, INL, INL, INL, 260 INL, INL, INL, INL, INL, INL, INL, SPC, 261 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC, 262 SPC, SPC, SPC, SPC, SPC, SPC, SPC, SPC }, /* SHIFT_ASHIFTRT */ 263 } 264 }; 265 266 #undef INL 267 #undef ROT 268 #undef LOP 269 #undef SPC 270 271 enum h8_cpu 272 { 273 H8_300H, 274 H8_S 275 }; 276 277 /* Initialize various cpu specific globals at start up. */ 278 279 static void 280 h8300_option_override (void) 281 { 282 static const char *const h8_push_ops[2] = { "push" , "push.l" }; 283 static const char *const h8_pop_ops[2] = { "pop" , "pop.l" }; 284 static const char *const h8_mov_ops[2] = { "mov.w", "mov.l" }; 285 286 /* For this we treat the H8/300H and H8S the same. */ 287 cpu_type = (int) CPU_H8300H; 288 h8_reg_names = names_extended; 289 h8_push_op = h8_push_ops[cpu_type]; 290 h8_pop_op = h8_pop_ops[cpu_type]; 291 h8_mov_op = h8_mov_ops[cpu_type]; 292 293 /* If we're compiling for the H8/S, then turn off H8/300H. */ 294 if (TARGET_H8300S) 295 target_flags &= ~MASK_H8300H; 296 297 if (!TARGET_H8300S && TARGET_MAC) 298 { 299 error ("%<-ms2600%> is used without %<-ms%>"); 300 target_flags |= MASK_H8300S_1; 301 } 302 303 if (! TARGET_H8300S && TARGET_EXR) 304 { 305 error ("%<-mexr%> is used without %<-ms%>"); 306 target_flags |= MASK_H8300S_1; 307 } 308 309 if ((!TARGET_H8300S && TARGET_EXR) && (!TARGET_H8300SX && TARGET_EXR)) 310 { 311 error ("%<-mexr%> is used without %<-ms%> or %<-msx%>"); 312 target_flags |= MASK_H8300S_1; 313 } 314 315 if ((!TARGET_H8300S && TARGET_NEXR) && (!TARGET_H8300SX && TARGET_NEXR)) 316 { 317 warning (OPT_mno_exr, "%<-mno-exr%> is valid only with %<-ms%> or " 318 "%<-msx%> - option ignored"); 319 } 320 321 #ifdef H8300_LINUX 322 if ((TARGET_NORMAL_MODE)) 323 { 324 error ("%<-mn%> is not supported for linux targets"); 325 target_flags ^= MASK_NORMAL_MODE; 326 } 327 #endif 328 329 /* Some of the shifts are optimized for speed by default. 330 See http://gcc.gnu.org/ml/gcc-patches/2002-07/msg01858.html 331 If optimizing for size, change shift_alg for those shift to 332 SHIFT_LOOP. */ 333 if (optimize_size) 334 { 335 /* H8/300H */ 336 shift_alg_hi[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 337 shift_alg_hi[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 338 339 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 340 shift_alg_hi[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 341 342 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 343 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 344 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 345 shift_alg_hi[H8_300H][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 346 347 shift_alg_si[H8_300H][SHIFT_ASHIFT][5] = SHIFT_LOOP; 348 shift_alg_si[H8_300H][SHIFT_ASHIFT][6] = SHIFT_LOOP; 349 shift_alg_si[H8_300H][SHIFT_ASHIFT][20] = SHIFT_LOOP; 350 shift_alg_si[H8_300H][SHIFT_ASHIFT][21] = SHIFT_LOOP; 351 shift_alg_si[H8_300H][SHIFT_ASHIFT][22] = SHIFT_LOOP; 352 shift_alg_si[H8_300H][SHIFT_ASHIFT][23] = SHIFT_LOOP; 353 shift_alg_si[H8_300H][SHIFT_ASHIFT][25] = SHIFT_LOOP; 354 shift_alg_si[H8_300H][SHIFT_ASHIFT][26] = SHIFT_LOOP; 355 shift_alg_si[H8_300H][SHIFT_ASHIFT][27] = SHIFT_LOOP; 356 357 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][5] = SHIFT_LOOP; 358 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][6] = SHIFT_LOOP; 359 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][20] = SHIFT_LOOP; 360 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][21] = SHIFT_LOOP; 361 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][22] = SHIFT_LOOP; 362 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][23] = SHIFT_LOOP; 363 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][25] = SHIFT_LOOP; 364 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][26] = SHIFT_LOOP; 365 shift_alg_si[H8_300H][SHIFT_LSHIFTRT][27] = SHIFT_LOOP; 366 367 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][5] = SHIFT_LOOP; 368 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][6] = SHIFT_LOOP; 369 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][20] = SHIFT_LOOP; 370 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][21] = SHIFT_LOOP; 371 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][22] = SHIFT_LOOP; 372 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][23] = SHIFT_LOOP; 373 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][25] = SHIFT_LOOP; 374 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][26] = SHIFT_LOOP; 375 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][27] = SHIFT_LOOP; 376 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][28] = SHIFT_LOOP; 377 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][29] = SHIFT_LOOP; 378 shift_alg_si[H8_300H][SHIFT_ASHIFTRT][30] = SHIFT_LOOP; 379 380 /* H8S */ 381 shift_alg_hi[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 382 383 shift_alg_si[H8_S][SHIFT_ASHIFT][11] = SHIFT_LOOP; 384 shift_alg_si[H8_S][SHIFT_ASHIFT][12] = SHIFT_LOOP; 385 shift_alg_si[H8_S][SHIFT_ASHIFT][13] = SHIFT_LOOP; 386 shift_alg_si[H8_S][SHIFT_ASHIFT][14] = SHIFT_LOOP; 387 shift_alg_si[H8_S][SHIFT_ASHIFT][22] = SHIFT_LOOP; 388 shift_alg_si[H8_S][SHIFT_ASHIFT][23] = SHIFT_LOOP; 389 shift_alg_si[H8_S][SHIFT_ASHIFT][26] = SHIFT_LOOP; 390 shift_alg_si[H8_S][SHIFT_ASHIFT][27] = SHIFT_LOOP; 391 392 shift_alg_si[H8_S][SHIFT_LSHIFTRT][11] = SHIFT_LOOP; 393 shift_alg_si[H8_S][SHIFT_LSHIFTRT][12] = SHIFT_LOOP; 394 shift_alg_si[H8_S][SHIFT_LSHIFTRT][13] = SHIFT_LOOP; 395 shift_alg_si[H8_S][SHIFT_LSHIFTRT][14] = SHIFT_LOOP; 396 shift_alg_si[H8_S][SHIFT_LSHIFTRT][22] = SHIFT_LOOP; 397 shift_alg_si[H8_S][SHIFT_LSHIFTRT][23] = SHIFT_LOOP; 398 shift_alg_si[H8_S][SHIFT_LSHIFTRT][26] = SHIFT_LOOP; 399 shift_alg_si[H8_S][SHIFT_LSHIFTRT][27] = SHIFT_LOOP; 400 401 shift_alg_si[H8_S][SHIFT_ASHIFTRT][11] = SHIFT_LOOP; 402 shift_alg_si[H8_S][SHIFT_ASHIFTRT][12] = SHIFT_LOOP; 403 shift_alg_si[H8_S][SHIFT_ASHIFTRT][13] = SHIFT_LOOP; 404 shift_alg_si[H8_S][SHIFT_ASHIFTRT][14] = SHIFT_LOOP; 405 shift_alg_si[H8_S][SHIFT_ASHIFTRT][22] = SHIFT_LOOP; 406 shift_alg_si[H8_S][SHIFT_ASHIFTRT][23] = SHIFT_LOOP; 407 shift_alg_si[H8_S][SHIFT_ASHIFTRT][26] = SHIFT_LOOP; 408 shift_alg_si[H8_S][SHIFT_ASHIFTRT][27] = SHIFT_LOOP; 409 shift_alg_si[H8_S][SHIFT_ASHIFTRT][28] = SHIFT_LOOP; 410 shift_alg_si[H8_S][SHIFT_ASHIFTRT][29] = SHIFT_LOOP; 411 shift_alg_si[H8_S][SHIFT_ASHIFTRT][30] = SHIFT_LOOP; 412 } 413 414 /* Work out a value for MOVE_RATIO. */ 415 if (!TARGET_H8300SX) 416 { 417 /* Memory-memory moves are quite expensive without the 418 h8sx instructions. */ 419 h8300_move_ratio = 3; 420 } 421 else if (flag_omit_frame_pointer) 422 { 423 /* movmd sequences are fairly cheap when er6 isn't fixed. They can 424 sometimes be as short as two individual memory-to-memory moves, 425 but since they use all the call-saved registers, it seems better 426 to allow up to three moves here. */ 427 h8300_move_ratio = 4; 428 } 429 else if (optimize_size) 430 { 431 /* In this case we don't use movmd sequences since they tend 432 to be longer than calls to memcpy(). Memory-to-memory 433 moves are cheaper than for !TARGET_H8300SX, so it makes 434 sense to have a slightly higher threshold. */ 435 h8300_move_ratio = 4; 436 } 437 else 438 { 439 /* We use movmd sequences for some moves since it can be quicker 440 than calling memcpy(). The sequences will need to save and 441 restore er6 though, so bump up the cost. */ 442 h8300_move_ratio = 6; 443 } 444 445 /* This target defaults to strict volatile bitfields. */ 446 if (flag_strict_volatile_bitfields < 0 && abi_version_at_least(2)) 447 flag_strict_volatile_bitfields = 1; 448 } 449 450 /* Return the byte register name for a register rtx X. B should be 0 451 if you want a lower byte register. B should be 1 if you want an 452 upper byte register. */ 453 454 static const char * 455 byte_reg (rtx x, int b) 456 { 457 static const char *const names_small[] = { 458 "r0l", "r0h", "r1l", "r1h", "r2l", "r2h", "r3l", "r3h", 459 "r4l", "r4h", "r5l", "r5h", "r6l", "r6h", "r7l", "r7h" 460 }; 461 462 gcc_assert (REG_P (x)); 463 464 return names_small[REGNO (x) * 2 + b]; 465 } 466 467 /* REGNO must be saved/restored across calls if this macro is true. */ 468 469 #define WORD_REG_USED(regno) \ 470 (regno < SP_REG \ 471 /* No need to save registers if this function will not return. */ \ 472 && ! TREE_THIS_VOLATILE (current_function_decl) \ 473 && (h8300_saveall_function_p (current_function_decl) \ 474 /* Save any call saved register that was used. */ \ 475 || (df_regs_ever_live_p (regno) \ 476 && !call_used_or_fixed_reg_p (regno)) \ 477 /* Save the frame pointer if it was used. */ \ 478 || (regno == HARD_FRAME_POINTER_REGNUM && df_regs_ever_live_p (regno)) \ 479 /* Save any register used in an interrupt handler. */ \ 480 || (h8300_current_function_interrupt_function_p () \ 481 && df_regs_ever_live_p (regno)) \ 482 /* Save call clobbered registers in non-leaf interrupt \ 483 handlers. */ \ 484 || (h8300_current_function_interrupt_function_p () \ 485 && call_used_or_fixed_reg_p (regno) \ 486 && !crtl->is_leaf))) 487 488 /* We use this to wrap all emitted insns in the prologue. */ 489 static rtx_insn * 490 F (rtx_insn *x, bool set_it) 491 { 492 if (set_it) 493 RTX_FRAME_RELATED_P (x) = 1; 494 return x; 495 } 496 497 /* Mark all the subexpressions of the PARALLEL rtx PAR as 498 frame-related. Return PAR. 499 500 dwarf2out.cc:dwarf2out_frame_debug_expr ignores sub-expressions of a 501 PARALLEL rtx other than the first if they do not have the 502 FRAME_RELATED flag set on them. */ 503 static rtx 504 Fpa (rtx par) 505 { 506 int len = XVECLEN (par, 0); 507 int i; 508 509 for (i = 0; i < len; i++) 510 RTX_FRAME_RELATED_P (XVECEXP (par, 0, i)) = 1; 511 512 return par; 513 } 514 515 /* Output assembly language to FILE for the operation OP with operand size 516 SIZE to adjust the stack pointer. */ 517 518 static void 519 h8300_emit_stack_adjustment (int sign, HOST_WIDE_INT size) 520 { 521 /* If the frame size is 0, we don't have anything to do. */ 522 if (size == 0) 523 return; 524 525 /* The stack adjustment made here is further optimized by the 526 splitter. In case of H8/300, the splitter always splits the 527 addition emitted here to make the adjustment interrupt-safe. 528 FIXME: We don't always tag those, because we don't know what 529 the splitter will do. */ 530 if (Pmode == HImode) 531 { 532 rtx_insn *x = emit_insn (gen_addhi3 (stack_pointer_rtx, 533 stack_pointer_rtx, 534 GEN_INT (sign * size))); 535 if (size < 4) 536 F (x, 0); 537 } 538 else 539 F (emit_insn (gen_addsi3 (stack_pointer_rtx, 540 stack_pointer_rtx, GEN_INT (sign * size))), 0); 541 } 542 543 /* Round up frame size SIZE. */ 544 545 static HOST_WIDE_INT 546 round_frame_size (HOST_WIDE_INT size) 547 { 548 return ((size + STACK_BOUNDARY / BITS_PER_UNIT - 1) 549 & -STACK_BOUNDARY / BITS_PER_UNIT); 550 } 551 552 /* Compute which registers to push/pop. 553 Return a bit vector of registers. */ 554 555 static unsigned int 556 compute_saved_regs (void) 557 { 558 unsigned int saved_regs = 0; 559 int regno; 560 561 /* Construct a bit vector of registers to be pushed/popped. */ 562 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 563 { 564 if (WORD_REG_USED (regno)) 565 saved_regs |= 1 << regno; 566 } 567 568 /* Don't push/pop the frame pointer as it is treated separately. */ 569 if (frame_pointer_needed) 570 saved_regs &= ~(1 << HARD_FRAME_POINTER_REGNUM); 571 572 return saved_regs; 573 } 574 575 /* Emit an insn to push register RN. */ 576 577 static rtx 578 push (int rn) 579 { 580 rtx reg = gen_rtx_REG (word_mode, rn); 581 rtx x; 582 583 if (!TARGET_NORMAL_MODE) 584 x = gen_push_h8300hs_advanced (reg); 585 else 586 x = gen_push_h8300hs_normal (reg); 587 x = F (emit_insn (x), 0); 588 add_reg_note (x, REG_INC, stack_pointer_rtx); 589 return x; 590 } 591 592 /* Emit an insn to pop register RN. */ 593 594 static rtx 595 pop (int rn) 596 { 597 rtx reg = gen_rtx_REG (word_mode, rn); 598 rtx x; 599 600 if (!TARGET_NORMAL_MODE) 601 x = gen_pop_h8300hs_advanced (reg); 602 else 603 x = gen_pop_h8300hs_normal (reg); 604 x = emit_insn (x); 605 add_reg_note (x, REG_INC, stack_pointer_rtx); 606 return x; 607 } 608 609 /* Emit an instruction to push or pop NREGS consecutive registers 610 starting at register REGNO. POP_P selects a pop rather than a 611 push and RETURN_P is true if the instruction should return. 612 613 It must be possible to do the requested operation in a single 614 instruction. If NREGS == 1 && !RETURN_P, use a normal push 615 or pop insn. Otherwise emit a parallel of the form: 616 617 (parallel 618 [(return) ;; if RETURN_P 619 (save or restore REGNO) 620 (save or restore REGNO + 1) 621 ... 622 (save or restore REGNO + NREGS - 1) 623 (set sp (plus sp (const_int adjust)))] */ 624 625 static void 626 h8300_push_pop (int regno, int nregs, bool pop_p, bool return_p) 627 { 628 int i, j; 629 rtvec vec; 630 rtx sp, offset, x; 631 632 /* See whether we can use a simple push or pop. */ 633 if (!return_p && nregs == 1) 634 { 635 if (pop_p) 636 pop (regno); 637 else 638 push (regno); 639 return; 640 } 641 642 /* We need one element for the return insn, if present, one for each 643 register, and one for stack adjustment. */ 644 vec = rtvec_alloc ((return_p ? 1 : 0) + nregs + 1); 645 sp = stack_pointer_rtx; 646 i = 0; 647 648 /* Add the return instruction. */ 649 if (return_p) 650 { 651 RTVEC_ELT (vec, i) = ret_rtx; 652 i++; 653 } 654 655 /* Add the register moves. */ 656 for (j = 0; j < nregs; j++) 657 { 658 rtx lhs, rhs; 659 660 if (pop_p) 661 { 662 /* Register REGNO + NREGS - 1 is popped first. Before the 663 stack adjustment, its slot is at address @sp. */ 664 lhs = gen_rtx_REG (SImode, regno + j); 665 rhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, 666 (nregs - j - 1) * 4)); 667 } 668 else 669 { 670 /* Register REGNO is pushed first and will be stored at @(-4,sp). */ 671 lhs = gen_rtx_MEM (SImode, plus_constant (Pmode, sp, (j + 1) * -4)); 672 rhs = gen_rtx_REG (SImode, regno + j); 673 } 674 RTVEC_ELT (vec, i + j) = gen_rtx_SET (lhs, rhs); 675 } 676 677 /* Add the stack adjustment. */ 678 offset = GEN_INT ((pop_p ? nregs : -nregs) * 4); 679 RTVEC_ELT (vec, i + j) = gen_rtx_SET (sp, gen_rtx_PLUS (Pmode, sp, offset)); 680 681 x = gen_rtx_PARALLEL (VOIDmode, vec); 682 if (!pop_p) 683 x = Fpa (x); 684 685 if (return_p) 686 emit_jump_insn (x); 687 else 688 emit_insn (x); 689 } 690 691 /* Return true if X has the value sp + OFFSET. */ 692 693 static int 694 h8300_stack_offset_p (rtx x, int offset) 695 { 696 if (offset == 0) 697 return x == stack_pointer_rtx; 698 699 return (GET_CODE (x) == PLUS 700 && XEXP (x, 0) == stack_pointer_rtx 701 && GET_CODE (XEXP (x, 1)) == CONST_INT 702 && INTVAL (XEXP (x, 1)) == offset); 703 } 704 705 /* A subroutine of h8300_ldm_stm_parallel. X is one pattern in 706 something that may be an ldm or stm instruction. If it fits 707 the required template, return the register it loads or stores, 708 otherwise return -1. 709 710 LOAD_P is true if X should be a load, false if it should be a store. 711 NREGS is the number of registers that the whole instruction is expected 712 to load or store. INDEX is the index of the register that X should 713 load or store, relative to the lowest-numbered register. */ 714 715 static int 716 h8300_ldm_stm_regno (rtx x, int load_p, int index, int nregs) 717 { 718 int regindex, memindex, offset; 719 720 if (load_p) 721 regindex = 0, memindex = 1, offset = (nregs - index - 1) * 4; 722 else 723 memindex = 0, regindex = 1, offset = (index + 1) * -4; 724 725 if (GET_CODE (x) == SET 726 && GET_CODE (XEXP (x, regindex)) == REG 727 && GET_CODE (XEXP (x, memindex)) == MEM 728 && h8300_stack_offset_p (XEXP (XEXP (x, memindex), 0), offset)) 729 return REGNO (XEXP (x, regindex)); 730 731 return -1; 732 } 733 734 /* Return true if the elements of VEC starting at FIRST describe an 735 ldm or stm instruction (LOAD_P says which). */ 736 737 int 738 h8300_ldm_stm_parallel (rtvec vec, int load_p, int first) 739 { 740 rtx last; 741 int nregs, i, regno, adjust; 742 743 /* There must be a stack adjustment, a register move, and at least one 744 other operation (a return or another register move). */ 745 if (GET_NUM_ELEM (vec) < 3) 746 return false; 747 748 /* Get the range of registers to be pushed or popped. */ 749 nregs = GET_NUM_ELEM (vec) - first - 1; 750 regno = h8300_ldm_stm_regno (RTVEC_ELT (vec, first), load_p, 0, nregs); 751 752 /* Check that the call to h8300_ldm_stm_regno succeeded and 753 that we're only dealing with GPRs. */ 754 if (regno < 0 || regno + nregs > 8) 755 return false; 756 757 /* 2-register h8s instructions must start with an even-numbered register. 758 3- and 4-register instructions must start with er0 or er4. */ 759 if (!TARGET_H8300SX) 760 { 761 if ((regno & 1) != 0) 762 return false; 763 if (nregs > 2 && (regno & 3) != 0) 764 return false; 765 } 766 767 /* Check the other loads or stores. */ 768 for (i = 1; i < nregs; i++) 769 if (h8300_ldm_stm_regno (RTVEC_ELT (vec, first + i), load_p, i, nregs) 770 != regno + i) 771 return false; 772 773 /* Check the stack adjustment. */ 774 last = RTVEC_ELT (vec, first + nregs); 775 adjust = (load_p ? nregs : -nregs) * 4; 776 return (GET_CODE (last) == SET 777 && SET_DEST (last) == stack_pointer_rtx 778 && h8300_stack_offset_p (SET_SRC (last), adjust)); 779 } 780 781 /* This is what the stack looks like after the prolog of 782 a function with a frame has been set up: 783 784 <args> 785 PC 786 FP <- fp 787 <locals> 788 <saved registers> <- sp 789 790 This is what the stack looks like after the prolog of 791 a function which doesn't have a frame: 792 793 <args> 794 PC 795 <locals> 796 <saved registers> <- sp 797 */ 798 799 /* Generate RTL code for the function prologue. */ 800 801 void 802 h8300_expand_prologue (void) 803 { 804 int regno; 805 int saved_regs; 806 int n_regs; 807 808 /* If the current function has the OS_Task attribute set, then 809 we have a naked prologue. */ 810 if (h8300_os_task_function_p (current_function_decl)) 811 return; 812 813 if (h8300_monitor_function_p (current_function_decl)) 814 /* The monitor function act as normal functions, which means it 815 can accept parameters and return values. In addition to this, 816 interrupts are masked in prologue and return with "rte" in epilogue. */ 817 emit_insn (gen_monitor_prologue ()); 818 819 if (frame_pointer_needed) 820 { 821 /* Push fp. */ 822 push (HARD_FRAME_POINTER_REGNUM); 823 F (emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx), 0); 824 } 825 826 /* Push the rest of the registers in ascending order. */ 827 saved_regs = compute_saved_regs (); 828 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno += n_regs) 829 { 830 n_regs = 1; 831 if (saved_regs & (1 << regno)) 832 { 833 if (TARGET_H8300S) 834 { 835 /* See how many registers we can push at the same time. */ 836 if ((TARGET_H8300SX || (regno & 3) == 0) 837 && ((saved_regs >> regno) & 0x0f) == 0x0f) 838 n_regs = 4; 839 840 else if ((TARGET_H8300SX || (regno & 3) == 0) 841 && ((saved_regs >> regno) & 0x07) == 0x07) 842 n_regs = 3; 843 844 else if ((TARGET_H8300SX || (regno & 1) == 0) 845 && ((saved_regs >> regno) & 0x03) == 0x03) 846 n_regs = 2; 847 } 848 849 h8300_push_pop (regno, n_regs, false, false); 850 } 851 } 852 853 /* Leave room for locals. */ 854 h8300_emit_stack_adjustment (-1, round_frame_size (get_frame_size ())); 855 856 if (flag_stack_usage_info) 857 current_function_static_stack_size 858 = round_frame_size (get_frame_size ()) 859 + (__builtin_popcount (saved_regs) * UNITS_PER_WORD) 860 + (frame_pointer_needed ? UNITS_PER_WORD : 0); 861 } 862 863 /* Return nonzero if we can use "rts" for the function currently being 864 compiled. */ 865 866 int 867 h8300_can_use_return_insn_p (void) 868 { 869 return (reload_completed 870 && !frame_pointer_needed 871 && get_frame_size () == 0 872 && compute_saved_regs () == 0); 873 } 874 875 /* Generate RTL code for the function epilogue. */ 876 877 void 878 h8300_expand_epilogue (bool sibcall_p) 879 { 880 int regno; 881 int saved_regs; 882 int n_regs; 883 HOST_WIDE_INT frame_size; 884 bool returned_p; 885 886 if (h8300_os_task_function_p (current_function_decl)) 887 /* OS_Task epilogues are nearly naked -- they just have an 888 rts instruction. */ 889 return; 890 891 frame_size = round_frame_size (get_frame_size ()); 892 returned_p = false; 893 894 /* Deallocate locals. */ 895 h8300_emit_stack_adjustment (1, frame_size); 896 897 /* Pop the saved registers in descending order. */ 898 saved_regs = compute_saved_regs (); 899 for (regno = FIRST_PSEUDO_REGISTER - 1; regno >= 0; regno -= n_regs) 900 { 901 n_regs = 1; 902 if (saved_regs & (1 << regno)) 903 { 904 if (TARGET_H8300S) 905 { 906 /* See how many registers we can pop at the same time. */ 907 if ((TARGET_H8300SX || (regno & 3) == 3) 908 && ((saved_regs << 3 >> regno) & 0x0f) == 0x0f) 909 n_regs = 4; 910 911 else if ((TARGET_H8300SX || (regno & 3) == 2) 912 && ((saved_regs << 2 >> regno) & 0x07) == 0x07) 913 n_regs = 3; 914 915 else if ((TARGET_H8300SX || (regno & 1) == 1) 916 && ((saved_regs << 1 >> regno) & 0x03) == 0x03) 917 n_regs = 2; 918 } 919 920 /* See if this pop would be the last insn before the return. 921 If so, use rte/l or rts/l instead of pop or ldm.l. */ 922 if (TARGET_H8300SX 923 && !sibcall_p 924 && !frame_pointer_needed 925 && frame_size == 0 926 && (saved_regs & ((1 << (regno - n_regs + 1)) - 1)) == 0) 927 returned_p = true; 928 929 h8300_push_pop (regno - n_regs + 1, n_regs, true, returned_p); 930 } 931 } 932 933 /* Pop frame pointer if we had one. */ 934 if (frame_pointer_needed) 935 { 936 if (TARGET_H8300SX && !sibcall_p) 937 returned_p = true; 938 h8300_push_pop (HARD_FRAME_POINTER_REGNUM, 1, true, returned_p); 939 } 940 941 if (!returned_p && !sibcall_p) 942 emit_jump_insn (ret_rtx); 943 } 944 945 /* Return nonzero if the current function is an interrupt 946 function. */ 947 948 int 949 h8300_current_function_interrupt_function_p (void) 950 { 951 return (h8300_interrupt_function_p (current_function_decl)); 952 } 953 954 int 955 h8300_current_function_monitor_function_p () 956 { 957 return (h8300_monitor_function_p (current_function_decl)); 958 } 959 960 /* Output assembly code for the start of the file. */ 961 962 static void 963 h8300_file_start (void) 964 { 965 default_file_start (); 966 967 if (TARGET_H8300SX) 968 fputs (TARGET_NORMAL_MODE ? "\t.h8300sxn\n" : "\t.h8300sx\n", asm_out_file); 969 else if (TARGET_H8300S) 970 fputs (TARGET_NORMAL_MODE ? "\t.h8300sn\n" : "\t.h8300s\n", asm_out_file); 971 else if (TARGET_H8300H) 972 fputs (TARGET_NORMAL_MODE ? "\t.h8300hn\n" : "\t.h8300h\n", asm_out_file); 973 } 974 975 /* Output assembly language code for the end of file. */ 976 977 static void 978 h8300_file_end (void) 979 { 980 fputs ("\t.end\n", asm_out_file); 981 } 982 983 /* Split an add of a small constant into two adds/subs insns. 985 986 If USE_INCDEC_P is nonzero, we generate the last insn using inc/dec 987 instead of adds/subs. */ 988 989 void 990 split_adds_subs (machine_mode mode, rtx *operands) 991 { 992 HOST_WIDE_INT val = INTVAL (operands[1]); 993 rtx reg = operands[0]; 994 HOST_WIDE_INT sign = 1; 995 HOST_WIDE_INT amount; 996 rtx (*gen_add) (rtx, rtx, rtx); 997 998 /* Force VAL to be positive so that we do not have to consider the 999 sign. */ 1000 if (val < 0) 1001 { 1002 val = -val; 1003 sign = -1; 1004 } 1005 1006 switch (mode) 1007 { 1008 case E_HImode: 1009 gen_add = gen_addhi3; 1010 break; 1011 1012 case E_SImode: 1013 gen_add = gen_addsi3; 1014 break; 1015 1016 default: 1017 gcc_unreachable (); 1018 } 1019 1020 /* Try different amounts in descending order. */ 1021 for (amount = 4; amount > 0; amount /= 2) 1022 { 1023 for (; val >= amount; val -= amount) 1024 emit_insn (gen_add (reg, reg, GEN_INT (sign * amount))); 1025 } 1026 1027 return; 1028 } 1029 1030 /* Handle machine specific pragmas for compatibility with existing 1031 compilers for the H8/300. 1032 1033 pragma saveall generates prologue/epilogue code which saves and 1034 restores all the registers on function entry. 1035 1036 pragma interrupt saves and restores all registers, and exits with 1037 an rte instruction rather than an rts. A pointer to a function 1038 with this attribute may be safely used in an interrupt vector. */ 1039 1040 void 1041 h8300_pr_interrupt (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1042 { 1043 pragma_interrupt = 1; 1044 } 1045 1046 void 1047 h8300_pr_saveall (struct cpp_reader *pfile ATTRIBUTE_UNUSED) 1048 { 1049 pragma_saveall = 1; 1050 } 1051 1052 /* If the next function argument ARG is to be passed in a register, return 1053 a reg RTX for the hard register in which to pass the argument. CUM 1054 represents the state after the last argument. If the argument is to 1055 be pushed, NULL_RTX is returned. 1056 1057 On the H8/300 all normal args are pushed, unless -mquickcall in which 1058 case the first 3 arguments are passed in registers. */ 1059 1060 static rtx 1061 h8300_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) 1062 { 1063 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1064 1065 static const char *const hand_list[] = { 1066 "__main", 1067 "__cmpsi2", 1068 "__divhi3", 1069 "__modhi3", 1070 "__udivhi3", 1071 "__umodhi3", 1072 "__divsi3", 1073 "__modsi3", 1074 "__udivsi3", 1075 "__umodsi3", 1076 "__mulhi3", 1077 "__mulsi3", 1078 "__reg_memcpy", 1079 "__reg_memset", 1080 "__ucmpsi2", 1081 0, 1082 }; 1083 1084 rtx result = NULL_RTX; 1085 const char *fname; 1086 int regpass = 0; 1087 1088 /* Never pass unnamed arguments in registers. */ 1089 if (!arg.named) 1090 return NULL_RTX; 1091 1092 /* Pass 3 regs worth of data in regs when user asked on the command line. */ 1093 if (TARGET_QUICKCALL) 1094 regpass = 3; 1095 1096 /* If calling hand written assembler, use 4 regs of args. */ 1097 if (cum->libcall) 1098 { 1099 const char * const *p; 1100 1101 fname = XSTR (cum->libcall, 0); 1102 1103 /* See if this libcall is one of the hand coded ones. */ 1104 for (p = hand_list; *p && strcmp (*p, fname) != 0; p++) 1105 ; 1106 1107 if (*p) 1108 regpass = 4; 1109 } 1110 1111 if (regpass) 1112 { 1113 int size = arg.promoted_size_in_bytes (); 1114 if (size + cum->nbytes <= regpass * UNITS_PER_WORD 1115 && cum->nbytes / UNITS_PER_WORD <= 3) 1116 result = gen_rtx_REG (arg.mode, cum->nbytes / UNITS_PER_WORD); 1117 } 1118 1119 return result; 1120 } 1121 1122 /* Update the data in CUM to advance over argument ARG. */ 1123 1124 static void 1125 h8300_function_arg_advance (cumulative_args_t cum_v, 1126 const function_arg_info &arg) 1127 { 1128 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1129 1130 cum->nbytes += ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1) 1131 & -UNITS_PER_WORD); 1132 } 1133 1134 1135 /* Implements TARGET_REGISTER_MOVE_COST. 1137 1138 Any SI register-to-register move may need to be reloaded, 1139 so inmplement h8300_register_move_cost to return > 2 so that reload never 1140 shortcuts. */ 1141 1142 static int 1143 h8300_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 1144 reg_class_t from, reg_class_t to) 1145 { 1146 if (from == MAC_REGS || to == MAC_REG) 1147 return 6; 1148 else 1149 return 3; 1150 } 1151 1152 /* Compute the cost of an and insn. */ 1153 1154 static int 1155 h8300_and_costs (rtx x) 1156 { 1157 rtx operands[4]; 1158 1159 if (GET_MODE (x) == QImode) 1160 return 1; 1161 1162 if (GET_MODE (x) != HImode 1163 && GET_MODE (x) != SImode) 1164 return 100; 1165 1166 operands[0] = NULL; 1167 operands[1] = XEXP (x, 0); 1168 operands[2] = XEXP (x, 1); 1169 operands[3] = x; 1170 return compute_logical_op_length (GET_MODE (x), AND, operands, NULL) / 2; 1171 } 1172 1173 /* Compute the cost of a shift insn. */ 1174 1175 static int 1176 h8300_shift_costs (rtx x) 1177 { 1178 rtx operands[3]; 1179 1180 if (GET_MODE (x) != QImode 1181 && GET_MODE (x) != HImode 1182 && GET_MODE (x) != SImode) 1183 return 100; 1184 1185 operands[0] = gen_rtx_REG (GET_MODE (x), 0); 1186 operands[1] = NULL; 1187 operands[2] = XEXP (x, 1); 1188 return compute_a_shift_length (operands, GET_CODE (x)) / 2; 1189 } 1190 1191 /* Worker function for TARGET_RTX_COSTS. */ 1192 1193 static bool 1194 h8300_rtx_costs (rtx x, machine_mode mode ATTRIBUTE_UNUSED, int outer_code, 1195 int opno ATTRIBUTE_UNUSED, int *total, bool speed) 1196 { 1197 int code = GET_CODE (x); 1198 1199 if (TARGET_H8300SX && outer_code == MEM) 1200 { 1201 /* Estimate the number of execution states needed to calculate 1202 the address. */ 1203 if (register_operand (x, VOIDmode) 1204 || GET_CODE (x) == POST_INC 1205 || GET_CODE (x) == POST_DEC 1206 || CONSTANT_P (x)) 1207 *total = 0; 1208 else 1209 *total = COSTS_N_INSNS (1); 1210 return true; 1211 } 1212 1213 switch (code) 1214 { 1215 case CONST_INT: 1216 { 1217 HOST_WIDE_INT n = INTVAL (x); 1218 1219 if (TARGET_H8300SX) 1220 { 1221 /* Constant operands need the same number of processor 1222 states as register operands. Although we could try to 1223 use a size-based cost for !speed, the lack of 1224 of a mode makes the results very unpredictable. */ 1225 *total = 0; 1226 return true; 1227 } 1228 if (n >= -4 && n <= 4) 1229 { 1230 switch ((int) n) 1231 { 1232 case 0: 1233 *total = 0; 1234 return true; 1235 case 1: 1236 case 2: 1237 case -1: 1238 case -2: 1239 *total = 0 + (outer_code == SET); 1240 return true; 1241 case 4: 1242 case -4: 1243 *total = 0 + (outer_code == SET); 1244 return true; 1245 } 1246 } 1247 *total = 1; 1248 return true; 1249 } 1250 1251 case CONST: 1252 case LABEL_REF: 1253 case SYMBOL_REF: 1254 if (TARGET_H8300SX) 1255 { 1256 /* See comment for CONST_INT. */ 1257 *total = 0; 1258 return true; 1259 } 1260 *total = 3; 1261 return true; 1262 1263 case CONST_DOUBLE: 1264 *total = 20; 1265 return true; 1266 1267 case COMPARE: 1268 case NE: 1269 case EQ: 1270 case GE: 1271 case GT: 1272 case LE: 1273 case LT: 1274 case GEU: 1275 case GTU: 1276 case LEU: 1277 case LTU: 1278 if (XEXP (x, 1) == const0_rtx) 1279 *total = 0; 1280 return false; 1281 1282 case AND: 1283 if (!h8300_dst_operand (XEXP (x, 0), VOIDmode) 1284 || !h8300_src_operand (XEXP (x, 1), VOIDmode)) 1285 return false; 1286 *total = COSTS_N_INSNS (h8300_and_costs (x)); 1287 return true; 1288 1289 /* We say that MOD and DIV are so expensive because otherwise we'll 1290 generate some really horrible code for division of a power of two. */ 1291 case MOD: 1292 case DIV: 1293 case UMOD: 1294 case UDIV: 1295 if (TARGET_H8300SX) 1296 switch (GET_MODE (x)) 1297 { 1298 case E_QImode: 1299 case E_HImode: 1300 *total = COSTS_N_INSNS (!speed ? 4 : 10); 1301 return false; 1302 1303 case E_SImode: 1304 *total = COSTS_N_INSNS (!speed ? 4 : 18); 1305 return false; 1306 1307 default: 1308 break; 1309 } 1310 *total = COSTS_N_INSNS (12); 1311 return true; 1312 1313 case MULT: 1314 if (TARGET_H8300SX) 1315 switch (GET_MODE (x)) 1316 { 1317 case E_QImode: 1318 case E_HImode: 1319 *total = COSTS_N_INSNS (2); 1320 return false; 1321 1322 case E_SImode: 1323 *total = COSTS_N_INSNS (5); 1324 return false; 1325 1326 default: 1327 break; 1328 } 1329 *total = COSTS_N_INSNS (4); 1330 return true; 1331 1332 case ASHIFT: 1333 case ASHIFTRT: 1334 case LSHIFTRT: 1335 if (h8sx_binary_shift_operator (x, VOIDmode)) 1336 { 1337 *total = COSTS_N_INSNS (2); 1338 return false; 1339 } 1340 else if (h8sx_unary_shift_operator (x, VOIDmode)) 1341 { 1342 *total = COSTS_N_INSNS (1); 1343 return false; 1344 } 1345 *total = COSTS_N_INSNS (h8300_shift_costs (x)); 1346 return true; 1347 1348 case ROTATE: 1349 case ROTATERT: 1350 if (GET_MODE (x) == HImode) 1351 *total = 2; 1352 else 1353 *total = 8; 1354 return true; 1355 1356 default: 1357 *total = COSTS_N_INSNS (1); 1358 return false; 1359 } 1360 } 1361 1362 /* Documentation for the machine specific operand escapes: 1364 1365 'E' like s but negative. 1366 'F' like t but negative. 1367 'G' constant just the negative 1368 'R' print operand as a byte:8 address if appropriate, else fall back to 1369 'X' handling. 1370 'S' print operand as a long word 1371 'T' print operand as a word 1372 'V' find the set bit, and print its number. 1373 'W' find the clear bit, and print its number. 1374 'X' print operand as a byte 1375 'Y' print either l or h depending on whether last 'Z' operand < 8 or >= 8. 1376 If this operand isn't a register, fall back to 'R' handling. 1377 'Z' print int & 7. 1378 'c' print the opcode corresponding to rtl 1379 'e' first word of 32-bit value - if reg, then least reg. if mem 1380 then least. if const then most sig word 1381 'f' second word of 32-bit value - if reg, then biggest reg. if mem 1382 then +2. if const then least sig word 1383 'j' print operand as condition code. 1384 'k' print operand as reverse condition code. 1385 'm' convert an integer operand to a size suffix (.b, .w or .l) 1386 'o' print an integer without a leading '#' 1387 's' print as low byte of 16-bit value 1388 't' print as high byte of 16-bit value 1389 'w' print as low byte of 32-bit value 1390 'x' print as 2nd byte of 32-bit value 1391 'y' print as 3rd byte of 32-bit value 1392 'z' print as msb of 32-bit value 1393 */ 1394 1395 /* Return assembly language string which identifies a comparison type. */ 1396 1397 static const char * 1398 cond_string (enum rtx_code code) 1399 { 1400 switch (code) 1401 { 1402 case NE: 1403 return "ne"; 1404 case EQ: 1405 return "eq"; 1406 case GE: 1407 return "ge"; 1408 case GT: 1409 return "gt"; 1410 case LE: 1411 return "le"; 1412 case LT: 1413 return "lt"; 1414 case GEU: 1415 return "hs"; 1416 case GTU: 1417 return "hi"; 1418 case LEU: 1419 return "ls"; 1420 case LTU: 1421 return "lo"; 1422 default: 1423 gcc_unreachable (); 1424 } 1425 } 1426 1427 /* Print operand X using operand code CODE to assembly language output file 1428 FILE. */ 1429 1430 static void 1431 h8300_print_operand (FILE *file, rtx x, int code) 1432 { 1433 /* This is used for communication between codes V,W,Z and Y. */ 1434 static int bitint; 1435 1436 switch (code) 1437 { 1438 case 'C': 1439 if (h8300_constant_length (x) == 2) 1440 fprintf (file, ":16"); 1441 else 1442 fprintf (file, ":32"); 1443 return; 1444 case 'E': 1445 switch (GET_CODE (x)) 1446 { 1447 case REG: 1448 fprintf (file, "%sl", names_big[REGNO (x)]); 1449 break; 1450 case CONST_INT: 1451 fprintf (file, "#%ld", (-INTVAL (x)) & 0xff); 1452 break; 1453 default: 1454 gcc_unreachable (); 1455 } 1456 break; 1457 case 'F': 1458 switch (GET_CODE (x)) 1459 { 1460 case REG: 1461 fprintf (file, "%sh", names_big[REGNO (x)]); 1462 break; 1463 case CONST_INT: 1464 fprintf (file, "#%ld", ((-INTVAL (x)) & 0xff00) >> 8); 1465 break; 1466 default: 1467 gcc_unreachable (); 1468 } 1469 break; 1470 case 'G': 1471 gcc_assert (GET_CODE (x) == CONST_INT); 1472 fprintf (file, "#%ld", 0xff & (-INTVAL (x))); 1473 break; 1474 case 'S': 1475 if (GET_CODE (x) == REG) 1476 fprintf (file, "%s", names_extended[REGNO (x)]); 1477 else 1478 goto def; 1479 break; 1480 case 'T': 1481 if (GET_CODE (x) == REG) 1482 fprintf (file, "%s", names_big[REGNO (x)]); 1483 else 1484 goto def; 1485 break; 1486 case 'V': 1487 bitint = (INTVAL (x) & 0xffff); 1488 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1) 1489 bitint = exact_log2 (bitint & 0xff); 1490 else 1491 bitint = exact_log2 ((bitint >> 8) & 0xff); 1492 gcc_assert (bitint >= 0); 1493 fprintf (file, "#%d", bitint); 1494 break; 1495 case 'W': 1496 bitint = ((~INTVAL (x)) & 0xffff); 1497 if ((exact_log2 ((bitint >> 8) & 0xff)) == -1 ) 1498 bitint = exact_log2 (bitint & 0xff); 1499 else 1500 bitint = (exact_log2 ((bitint >> 8) & 0xff)); 1501 gcc_assert (bitint >= 0); 1502 fprintf (file, "#%d", bitint); 1503 break; 1504 case 'R': 1505 case 'X': 1506 if (GET_CODE (x) == REG) 1507 fprintf (file, "%s", byte_reg (x, 0)); 1508 else 1509 goto def; 1510 break; 1511 case 'Y': 1512 gcc_assert (bitint >= 0); 1513 if (GET_CODE (x) == REG) 1514 fprintf (file, "%s%c", names_big[REGNO (x)], bitint > 7 ? 'h' : 'l'); 1515 else 1516 h8300_print_operand (file, x, 'R'); 1517 bitint = -1; 1518 break; 1519 case 'Z': 1520 bitint = INTVAL (x); 1521 fprintf (file, "#%d", bitint & 7); 1522 break; 1523 case 'c': 1524 switch (GET_CODE (x)) 1525 { 1526 case IOR: 1527 fprintf (file, "or"); 1528 break; 1529 case XOR: 1530 fprintf (file, "xor"); 1531 break; 1532 case AND: 1533 fprintf (file, "and"); 1534 break; 1535 default: 1536 break; 1537 } 1538 break; 1539 case 'e': 1540 switch (GET_CODE (x)) 1541 { 1542 case REG: 1543 fprintf (file, "%s", names_upper_extended[REGNO (x)]); 1544 break; 1545 case MEM: 1546 h8300_print_operand (file, x, 0); 1547 break; 1548 case CONST_INT: 1549 fprintf (file, "#%ld", ((INTVAL (x) >> 16) & 0xffff)); 1550 break; 1551 case CONST_DOUBLE: 1552 { 1553 long val; 1554 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1555 fprintf (file, "#%ld", ((val >> 16) & 0xffff)); 1556 break; 1557 } 1558 default: 1559 gcc_unreachable (); 1560 break; 1561 } 1562 break; 1563 case 'f': 1564 switch (GET_CODE (x)) 1565 { 1566 case REG: 1567 fprintf (file, "%s", names_big[REGNO (x)]); 1568 break; 1569 case MEM: 1570 x = adjust_address (x, HImode, 2); 1571 h8300_print_operand (file, x, 0); 1572 break; 1573 case CONST_INT: 1574 fprintf (file, "#%ld", INTVAL (x) & 0xffff); 1575 break; 1576 case CONST_DOUBLE: 1577 { 1578 long val; 1579 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1580 fprintf (file, "#%ld", (val & 0xffff)); 1581 break; 1582 } 1583 default: 1584 gcc_unreachable (); 1585 } 1586 break; 1587 case 'j': 1588 if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1589 fputs ("mi", file); 1590 else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1591 fputs ("pl", file); 1592 else 1593 fputs (cond_string (GET_CODE (x)), file); 1594 break; 1595 case 'k': 1596 if (GET_CODE (x) == LT && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1597 fputs ("pl", file); 1598 else if (GET_CODE (x) == GE && GET_MODE (XEXP (x, 0)) == E_CCZNmode) 1599 fputs ("mi", file); 1600 else 1601 fputs (cond_string (reverse_condition (GET_CODE (x))), file); 1602 break; 1603 case 'm': 1604 gcc_assert (GET_CODE (x) == CONST_INT); 1605 switch (INTVAL (x)) 1606 { 1607 case 1: 1608 fputs (".b", file); 1609 break; 1610 1611 case 2: 1612 fputs (".w", file); 1613 break; 1614 1615 case 4: 1616 fputs (".l", file); 1617 break; 1618 1619 default: 1620 gcc_unreachable (); 1621 } 1622 break; 1623 case 'o': 1624 h8300_print_operand_address (file, VOIDmode, x); 1625 break; 1626 case 's': 1627 if (GET_CODE (x) == CONST_INT) 1628 fprintf (file, "#%ld", (INTVAL (x)) & 0xff); 1629 else if (GET_CODE (x) == REG) 1630 fprintf (file, "%s", byte_reg (x, 0)); 1631 else 1632 output_operand_lossage ("Expected register or constant integer."); 1633 break; 1634 case 't': 1635 if (GET_CODE (x) == CONST_INT) 1636 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1637 else if (GET_CODE (x) == REG) 1638 fprintf (file, "%s", byte_reg (x, 1)); 1639 else 1640 output_operand_lossage ("Expected register or constant integer."); 1641 break; 1642 case 'w': 1643 if (GET_CODE (x) == CONST_INT) 1644 fprintf (file, "#%ld", INTVAL (x) & 0xff); 1645 else if (GET_CODE (x) == REG) 1646 fprintf (file, "%s", byte_reg (x, 0)); 1647 else 1648 output_operand_lossage ("Expected register or constant integer."); 1649 break; 1650 case 'x': 1651 if (GET_CODE (x) == CONST_INT) 1652 fprintf (file, "#%ld", (INTVAL (x) >> 8) & 0xff); 1653 else if (GET_CODE (x) == REG) 1654 fprintf (file, "%s", byte_reg (x, 1)); 1655 else 1656 output_operand_lossage ("Expected register or constant integer."); 1657 break; 1658 case 'y': 1659 if (GET_CODE (x) == CONST_INT) 1660 fprintf (file, "#%ld", (INTVAL (x) >> 16) & 0xff); 1661 else if (GET_CODE (x) == REG) 1662 fprintf (file, "%s", byte_reg (x, 0)); 1663 else 1664 output_operand_lossage ("Expected register or constant integer."); 1665 break; 1666 case 'z': 1667 if (GET_CODE (x) == CONST_INT) 1668 fprintf (file, "#%ld", (INTVAL (x) >> 24) & 0xff); 1669 else if (GET_CODE (x) == REG) 1670 fprintf (file, "%s", byte_reg (x, 1)); 1671 else 1672 output_operand_lossage ("Expected register or constant integer."); 1673 break; 1674 1675 default: 1676 def: 1677 switch (GET_CODE (x)) 1678 { 1679 case REG: 1680 switch (GET_MODE (x)) 1681 { 1682 case E_QImode: 1683 #if 0 /* Is it asm ("mov.b %0,r2l", ...) */ 1684 fprintf (file, "%s", byte_reg (x, 0)); 1685 #else /* ... or is it asm ("mov.b %0l,r2l", ...) */ 1686 fprintf (file, "%s", names_big[REGNO (x)]); 1687 #endif 1688 break; 1689 case E_HImode: 1690 fprintf (file, "%s", names_big[REGNO (x)]); 1691 break; 1692 case E_SImode: 1693 case E_SFmode: 1694 fprintf (file, "%s", names_extended[REGNO (x)]); 1695 break; 1696 default: 1697 gcc_unreachable (); 1698 } 1699 break; 1700 1701 case MEM: 1702 { 1703 rtx addr = XEXP (x, 0); 1704 1705 fprintf (file, "@"); 1706 output_address (GET_MODE (x), addr); 1707 1708 /* Add a length suffix to constant addresses. Although this 1709 is often unnecessary, it helps to avoid ambiguity in the 1710 syntax of mova. If we wrote an insn like: 1711 1712 mova/w.l @(1,@foo.b),er0 1713 1714 then .b would be considered part of the symbol name. 1715 Adding a length after foo will avoid this. */ 1716 if (CONSTANT_P (addr)) 1717 switch (code) 1718 { 1719 case 'R': 1720 /* Used for mov.b and bit operations. */ 1721 if (h8300_eightbit_constant_address_p (addr)) 1722 { 1723 fprintf (file, ":8"); 1724 break; 1725 } 1726 1727 /* FALLTHRU */ 1728 1729 /* We should not get here if we are processing bit 1730 operations on H8/300 or H8/300H because 'U' 1731 constraint does not allow bit operations on the 1732 tiny area on these machines. */ 1733 1734 case 'X': 1735 case 'T': 1736 case 'S': 1737 if (h8300_constant_length (addr) == 2) 1738 fprintf (file, ":16"); 1739 else 1740 fprintf (file, ":32"); 1741 break; 1742 default: 1743 break; 1744 } 1745 } 1746 break; 1747 1748 case CONST_INT: 1749 case SYMBOL_REF: 1750 case CONST: 1751 case LABEL_REF: 1752 fprintf (file, "#"); 1753 h8300_print_operand_address (file, VOIDmode, x); 1754 break; 1755 case CONST_DOUBLE: 1756 { 1757 long val; 1758 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), val); 1759 fprintf (file, "#%ld", val); 1760 break; 1761 } 1762 default: 1763 break; 1764 } 1765 } 1766 } 1767 1768 /* Implements TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 1769 1770 static bool 1771 h8300_print_operand_punct_valid_p (unsigned char code) 1772 { 1773 return (code == '#'); 1774 } 1775 1776 /* Output assembly language output for the address ADDR to FILE. */ 1777 1778 static void 1779 h8300_print_operand_address (FILE *file, machine_mode mode, rtx addr) 1780 { 1781 rtx index; 1782 int size; 1783 1784 switch (GET_CODE (addr)) 1785 { 1786 case REG: 1787 fprintf (file, "%s", h8_reg_names[REGNO (addr)]); 1788 break; 1789 1790 case PRE_DEC: 1791 fprintf (file, "-%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1792 break; 1793 1794 case POST_INC: 1795 fprintf (file, "%s+", h8_reg_names[REGNO (XEXP (addr, 0))]); 1796 break; 1797 1798 case PRE_INC: 1799 fprintf (file, "+%s", h8_reg_names[REGNO (XEXP (addr, 0))]); 1800 break; 1801 1802 case POST_DEC: 1803 fprintf (file, "%s-", h8_reg_names[REGNO (XEXP (addr, 0))]); 1804 break; 1805 1806 case PLUS: 1807 fprintf (file, "("); 1808 1809 index = h8300_get_index (XEXP (addr, 0), VOIDmode, &size); 1810 if (GET_CODE (index) == REG) 1811 { 1812 /* reg,foo */ 1813 h8300_print_operand_address (file, mode, XEXP (addr, 1)); 1814 fprintf (file, ","); 1815 switch (size) 1816 { 1817 case 0: 1818 h8300_print_operand_address (file, mode, index); 1819 break; 1820 1821 case 1: 1822 h8300_print_operand (file, index, 'X'); 1823 fputs (".b", file); 1824 break; 1825 1826 case 2: 1827 h8300_print_operand (file, index, 'T'); 1828 fputs (".w", file); 1829 break; 1830 1831 case 4: 1832 h8300_print_operand (file, index, 'S'); 1833 fputs (".l", file); 1834 break; 1835 } 1836 /* h8300_print_operand_address (file, XEXP (addr, 0)); */ 1837 } 1838 else 1839 { 1840 /* foo+k */ 1841 h8300_print_operand_address (file, mode, XEXP (addr, 0)); 1842 fprintf (file, "+"); 1843 h8300_print_operand_address (file, mode, XEXP (addr, 1)); 1844 } 1845 fprintf (file, ")"); 1846 break; 1847 1848 case CONST_INT: 1849 { 1850 int n = INTVAL (addr); 1851 fprintf (file, "%d", n); 1852 break; 1853 } 1854 1855 default: 1856 output_addr_const (file, addr); 1857 break; 1858 } 1859 } 1860 1861 /* Output all insn addresses and their sizes into the assembly language 1863 output file. This is helpful for debugging whether the length attributes 1864 in the md file are correct. This is not meant to be a user selectable 1865 option. */ 1866 1867 void 1868 final_prescan_insn (rtx_insn *insn, rtx *operand ATTRIBUTE_UNUSED, 1869 int num_operands ATTRIBUTE_UNUSED) 1870 { 1871 /* This holds the last insn address. */ 1872 static int last_insn_address = 0; 1873 1874 const int uid = INSN_UID (insn); 1875 1876 if (TARGET_ADDRESSES) 1877 { 1878 fprintf (asm_out_file, "; 0x%x %d\n", INSN_ADDRESSES (uid), 1879 INSN_ADDRESSES (uid) - last_insn_address); 1880 last_insn_address = INSN_ADDRESSES (uid); 1881 } 1882 } 1883 1884 /* Prepare for an SI sized move. */ 1885 1886 int 1887 h8300_expand_movsi (rtx operands[]) 1888 { 1889 rtx src = operands[1]; 1890 rtx dst = operands[0]; 1891 if (!reload_in_progress && !reload_completed) 1892 { 1893 if (!register_operand (dst, GET_MODE (dst))) 1894 { 1895 rtx tmp = gen_reg_rtx (GET_MODE (dst)); 1896 emit_move_insn (tmp, src); 1897 operands[1] = tmp; 1898 } 1899 } 1900 return 0; 1901 } 1902 1903 /* Given FROM and TO register numbers, say whether this elimination is allowed. 1904 Frame pointer elimination is automatically handled. 1905 1906 For the h8300, if frame pointer elimination is being done, we would like to 1907 convert ap and rp into sp, not fp. 1908 1909 All other eliminations are valid. */ 1910 1911 static bool 1912 h8300_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 1913 { 1914 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); 1915 } 1916 1917 /* Conditionally modify register usage based on target flags. */ 1918 1919 static void 1920 h8300_conditional_register_usage (void) 1921 { 1922 if (!TARGET_MAC) 1923 fixed_regs[MAC_REG] = call_used_regs[MAC_REG] = 1; 1924 } 1925 1926 /* Function for INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET). 1927 Define the offset between two registers, one to be eliminated, and 1928 the other its replacement, at the start of a routine. */ 1929 1930 int 1931 h8300_initial_elimination_offset (int from, int to) 1932 { 1933 /* The number of bytes that the return address takes on the stack. */ 1934 int pc_size = POINTER_SIZE / BITS_PER_UNIT; 1935 1936 /* The number of bytes that the saved frame pointer takes on the stack. */ 1937 int fp_size = frame_pointer_needed * UNITS_PER_WORD; 1938 1939 /* The number of bytes that the saved registers, excluding the frame 1940 pointer, take on the stack. */ 1941 int saved_regs_size = 0; 1942 1943 /* The number of bytes that the locals takes on the stack. */ 1944 int frame_size = round_frame_size (get_frame_size ()); 1945 1946 int regno; 1947 1948 for (regno = 0; regno <= HARD_FRAME_POINTER_REGNUM; regno++) 1949 if (WORD_REG_USED (regno)) 1950 saved_regs_size += UNITS_PER_WORD; 1951 1952 /* Adjust saved_regs_size because the above loop took the frame 1953 pointer int account. */ 1954 saved_regs_size -= fp_size; 1955 1956 switch (to) 1957 { 1958 case HARD_FRAME_POINTER_REGNUM: 1959 switch (from) 1960 { 1961 case ARG_POINTER_REGNUM: 1962 return pc_size + fp_size; 1963 case RETURN_ADDRESS_POINTER_REGNUM: 1964 return fp_size; 1965 case FRAME_POINTER_REGNUM: 1966 return -saved_regs_size; 1967 default: 1968 gcc_unreachable (); 1969 } 1970 break; 1971 case STACK_POINTER_REGNUM: 1972 switch (from) 1973 { 1974 case ARG_POINTER_REGNUM: 1975 return pc_size + saved_regs_size + frame_size; 1976 case RETURN_ADDRESS_POINTER_REGNUM: 1977 return saved_regs_size + frame_size; 1978 case FRAME_POINTER_REGNUM: 1979 return frame_size; 1980 default: 1981 gcc_unreachable (); 1982 } 1983 break; 1984 default: 1985 gcc_unreachable (); 1986 } 1987 gcc_unreachable (); 1988 } 1989 1990 /* Worker function for RETURN_ADDR_RTX. */ 1991 1992 rtx 1993 h8300_return_addr_rtx (int count, rtx frame) 1994 { 1995 rtx ret; 1996 1997 if (count == 0) 1998 ret = gen_rtx_MEM (Pmode, 1999 gen_rtx_REG (Pmode, RETURN_ADDRESS_POINTER_REGNUM)); 2000 else if (flag_omit_frame_pointer) 2001 return (rtx) 0; 2002 else 2003 ret = gen_rtx_MEM (Pmode, 2004 memory_address (Pmode, 2005 plus_constant (Pmode, frame, 2006 UNITS_PER_WORD))); 2007 set_mem_alias_set (ret, get_frame_alias_set ()); 2008 return ret; 2009 } 2010 2011 2012 machine_mode 2013 h8300_select_cc_mode (enum rtx_code cond, rtx op0, rtx op1) 2014 { 2015 if (op1 == const0_rtx 2016 && (cond == EQ || cond == NE || cond == LT || cond == GE) 2017 && (GET_CODE (op0) == PLUS || GET_CODE (op0) == MINUS 2018 || GET_CODE (op0) == NEG || GET_CODE (op0) == AND 2019 || GET_CODE (op0) == IOR || GET_CODE (op0) == XOR 2020 || GET_CODE (op0) == NOT || GET_CODE (op0) == ASHIFT 2021 || GET_CODE (op0) == ASHIFTRT || GET_CODE (op0) == LSHIFTRT 2022 || GET_CODE (op0) == MULT || GET_CODE (op0) == SYMBOL_REF 2023 || GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND 2024 || REG_P (op0) || MEM_P (op0))) 2025 return CCZNmode; 2026 2027 return CCmode; 2028 } 2029 2030 2031 /* Given that X occurs in an address of the form (plus X constant), 2033 return the part of X that is expected to be a register. There are 2034 four kinds of addressing mode to recognize: 2035 2036 @(dd,Rn) 2037 @(dd,RnL.b) 2038 @(dd,Rn.w) 2039 @(dd,ERn.l) 2040 2041 If SIZE is nonnull, and the address is one of the last three forms, 2042 set *SIZE to the index multiplication factor. Set it to 0 for 2043 plain @(dd,Rn) addresses. 2044 2045 MODE is the mode of the value being accessed. It can be VOIDmode 2046 if the address is known to be valid, but its mode is unknown. */ 2047 2048 static rtx 2049 h8300_get_index (rtx x, machine_mode mode, int *size) 2050 { 2051 int dummy, factor; 2052 2053 if (size == 0) 2054 size = &dummy; 2055 2056 factor = (mode == VOIDmode ? 0 : GET_MODE_SIZE (mode)); 2057 if (TARGET_H8300SX 2058 && factor <= 4 2059 && (mode == VOIDmode 2060 || GET_MODE_CLASS (mode) == MODE_INT 2061 || GET_MODE_CLASS (mode) == MODE_FLOAT)) 2062 { 2063 if (factor <= 1 && GET_CODE (x) == ZERO_EXTEND) 2064 { 2065 /* When accessing byte-sized values, the index can be 2066 a zero-extended QImode or HImode register. */ 2067 *size = GET_MODE_SIZE (GET_MODE (XEXP (x, 0))); 2068 return XEXP (x, 0); 2069 } 2070 else 2071 { 2072 /* We're looking for addresses of the form: 2073 2074 (mult X I) 2075 or (mult (zero_extend X) I) 2076 2077 where I is the size of the operand being accessed. 2078 The canonical form of the second expression is: 2079 2080 (and (mult (subreg X) I) J) 2081 2082 where J == GET_MODE_MASK (GET_MODE (X)) * I. */ 2083 rtx index; 2084 2085 if (GET_CODE (x) == AND 2086 && GET_CODE (XEXP (x, 1)) == CONST_INT 2087 && (factor == 0 2088 || INTVAL (XEXP (x, 1)) == 0xff * factor 2089 || INTVAL (XEXP (x, 1)) == 0xffff * factor)) 2090 { 2091 index = XEXP (x, 0); 2092 *size = (INTVAL (XEXP (x, 1)) >= 0xffff ? 2 : 1); 2093 } 2094 else 2095 { 2096 index = x; 2097 *size = 4; 2098 } 2099 2100 if (GET_CODE (index) == MULT 2101 && GET_CODE (XEXP (index, 1)) == CONST_INT 2102 && (factor == 0 || factor == INTVAL (XEXP (index, 1)))) 2103 return XEXP (index, 0); 2104 } 2105 } 2106 *size = 0; 2107 return x; 2108 } 2109 2110 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. 2112 2113 On the H8/300, the predecrement and postincrement address depend thus 2114 (the amount of decrement or increment being the length of the operand). */ 2115 2116 static bool 2117 h8300_mode_dependent_address_p (const_rtx addr, 2118 addr_space_t as ATTRIBUTE_UNUSED) 2119 { 2120 if (GET_CODE (addr) == PLUS 2121 && h8300_get_index (XEXP (addr, 0), VOIDmode, 0) != XEXP (addr, 0)) 2122 return true; 2123 2124 return false; 2125 } 2126 2127 static const h8300_length_table addb_length_table = 2129 { 2130 /* #xx Rs @aa @Rs @xx */ 2131 { 2, 2, 4, 4, 4 }, /* add.b xx,Rd */ 2132 { 4, 4, 4, 4, 6 }, /* add.b xx,@aa */ 2133 { 4, 4, 4, 4, 6 }, /* add.b xx,@Rd */ 2134 { 6, 4, 4, 4, 6 } /* add.b xx,@xx */ 2135 }; 2136 2137 static const h8300_length_table addw_length_table = 2138 { 2139 /* #xx Rs @aa @Rs @xx */ 2140 { 2, 2, 4, 4, 4 }, /* add.w xx,Rd */ 2141 { 4, 4, 4, 4, 6 }, /* add.w xx,@aa */ 2142 { 4, 4, 4, 4, 6 }, /* add.w xx,@Rd */ 2143 { 4, 4, 4, 4, 6 } /* add.w xx,@xx */ 2144 }; 2145 2146 static const h8300_length_table addl_length_table = 2147 { 2148 /* #xx Rs @aa @Rs @xx */ 2149 { 2, 2, 4, 4, 4 }, /* add.l xx,Rd */ 2150 { 4, 4, 6, 6, 6 }, /* add.l xx,@aa */ 2151 { 4, 4, 6, 6, 6 }, /* add.l xx,@Rd */ 2152 { 4, 4, 6, 6, 6 } /* add.l xx,@xx */ 2153 }; 2154 2155 #define logicb_length_table addb_length_table 2156 #define logicw_length_table addw_length_table 2157 2158 static const h8300_length_table logicl_length_table = 2159 { 2160 /* #xx Rs @aa @Rs @xx */ 2161 { 2, 4, 4, 4, 4 }, /* and.l xx,Rd */ 2162 { 4, 4, 6, 6, 6 }, /* and.l xx,@aa */ 2163 { 4, 4, 6, 6, 6 }, /* and.l xx,@Rd */ 2164 { 4, 4, 6, 6, 6 } /* and.l xx,@xx */ 2165 }; 2166 2167 static const h8300_length_table movb_length_table = 2168 { 2169 /* #xx Rs @aa @Rs @xx */ 2170 { 2, 2, 2, 2, 4 }, /* mov.b xx,Rd */ 2171 { 4, 2, 4, 4, 4 }, /* mov.b xx,@aa */ 2172 { 4, 2, 4, 4, 4 }, /* mov.b xx,@Rd */ 2173 { 4, 4, 4, 4, 4 } /* mov.b xx,@xx */ 2174 }; 2175 2176 #define movw_length_table movb_length_table 2177 2178 static const h8300_length_table movl_length_table = 2179 { 2180 /* #xx Rs @aa @Rs @xx */ 2181 { 2, 2, 4, 4, 4 }, /* mov.l xx,Rd */ 2182 { 4, 4, 4, 4, 4 }, /* mov.l xx,@aa */ 2183 { 4, 4, 4, 4, 4 }, /* mov.l xx,@Rd */ 2184 { 4, 4, 4, 4, 4 } /* mov.l xx,@xx */ 2185 }; 2186 2187 /* Return the size of the given address or displacement constant. */ 2188 2189 static unsigned int 2190 h8300_constant_length (rtx constant) 2191 { 2192 /* Check for (@d:16,Reg). */ 2193 if (GET_CODE (constant) == CONST_INT 2194 && IN_RANGE (INTVAL (constant), -0x8000, 0x7fff)) 2195 return 2; 2196 2197 /* Check for (@d:16,Reg) in cases where the displacement is 2198 an absolute address. */ 2199 if (Pmode == HImode || h8300_tiny_constant_address_p (constant)) 2200 return 2; 2201 2202 return 4; 2203 } 2204 2205 /* Return the size of a displacement field in address ADDR, which should 2206 have the form (plus X constant). SIZE is the number of bytes being 2207 accessed. */ 2208 2209 static unsigned int 2210 h8300_displacement_length (rtx addr, int size) 2211 { 2212 rtx offset; 2213 2214 offset = XEXP (addr, 1); 2215 2216 /* Check for @(d:2,Reg). */ 2217 if (register_operand (XEXP (addr, 0), VOIDmode) 2218 && GET_CODE (offset) == CONST_INT 2219 && (INTVAL (offset) == size 2220 || INTVAL (offset) == size * 2 2221 || INTVAL (offset) == size * 3)) 2222 return 0; 2223 2224 return h8300_constant_length (offset); 2225 } 2226 2227 /* Store the class of operand OP in *OPCLASS and return the length of any 2228 extra operand fields. SIZE is the number of bytes in OP. OPCLASS 2229 can be null if only the length is needed. */ 2230 2231 static unsigned int 2232 h8300_classify_operand (rtx op, int size, enum h8300_operand_class *opclass) 2233 { 2234 enum h8300_operand_class dummy; 2235 2236 if (opclass == 0) 2237 opclass = &dummy; 2238 2239 if (CONSTANT_P (op)) 2240 { 2241 *opclass = H8OP_IMMEDIATE; 2242 2243 /* Byte-sized immediates are stored in the opcode fields. */ 2244 if (size == 1) 2245 return 0; 2246 2247 /* If this is a 32-bit instruction, see whether the constant 2248 will fit into a 16-bit immediate field. */ 2249 if (TARGET_H8300SX 2250 && size == 4 2251 && GET_CODE (op) == CONST_INT 2252 && IN_RANGE (INTVAL (op), 0, 0xffff)) 2253 return 2; 2254 2255 return size; 2256 } 2257 else if (GET_CODE (op) == MEM) 2258 { 2259 op = XEXP (op, 0); 2260 if (CONSTANT_P (op)) 2261 { 2262 *opclass = H8OP_MEM_ABSOLUTE; 2263 return h8300_constant_length (op); 2264 } 2265 else if (GET_CODE (op) == PLUS && CONSTANT_P (XEXP (op, 1))) 2266 { 2267 *opclass = H8OP_MEM_COMPLEX; 2268 return h8300_displacement_length (op, size); 2269 } 2270 else if (GET_RTX_CLASS (GET_CODE (op)) == RTX_AUTOINC) 2271 { 2272 *opclass = H8OP_MEM_COMPLEX; 2273 return 0; 2274 } 2275 else if (register_operand (op, VOIDmode)) 2276 { 2277 *opclass = H8OP_MEM_BASE; 2278 return 0; 2279 } 2280 } 2281 gcc_assert (register_operand (op, VOIDmode)); 2282 *opclass = H8OP_REGISTER; 2283 return 0; 2284 } 2285 2286 /* Return the length of the instruction described by TABLE given that 2287 its operands are OP1 and OP2. OP1 must be an h8300_dst_operand 2288 and OP2 must be an h8300_src_operand. */ 2289 2290 static unsigned int 2291 h8300_length_from_table (rtx op1, rtx op2, const h8300_length_table *table) 2292 { 2293 enum h8300_operand_class op1_class, op2_class; 2294 unsigned int size, immediate_length; 2295 2296 size = GET_MODE_SIZE (GET_MODE (op1)); 2297 immediate_length = (h8300_classify_operand (op1, size, &op1_class) 2298 + h8300_classify_operand (op2, size, &op2_class)); 2299 return immediate_length + (*table)[op1_class - 1][op2_class]; 2300 } 2301 2302 /* Return the length of a unary instruction such as neg or not given that 2303 its operand is OP. */ 2304 2305 unsigned int 2306 h8300_unary_length (rtx op) 2307 { 2308 enum h8300_operand_class opclass; 2309 unsigned int size, operand_length; 2310 2311 size = GET_MODE_SIZE (GET_MODE (op)); 2312 operand_length = h8300_classify_operand (op, size, &opclass); 2313 switch (opclass) 2314 { 2315 case H8OP_REGISTER: 2316 return 2; 2317 2318 case H8OP_MEM_BASE: 2319 return (size == 4 ? 6 : 4); 2320 2321 case H8OP_MEM_ABSOLUTE: 2322 return operand_length + (size == 4 ? 6 : 4); 2323 2324 case H8OP_MEM_COMPLEX: 2325 return operand_length + 6; 2326 2327 default: 2328 gcc_unreachable (); 2329 } 2330 } 2331 2332 /* Likewise short immediate instructions such as add.w #xx:3,OP. */ 2333 2334 static unsigned int 2335 h8300_short_immediate_length (rtx op) 2336 { 2337 enum h8300_operand_class opclass; 2338 unsigned int size, operand_length; 2339 2340 size = GET_MODE_SIZE (GET_MODE (op)); 2341 operand_length = h8300_classify_operand (op, size, &opclass); 2342 2343 switch (opclass) 2344 { 2345 case H8OP_REGISTER: 2346 return 2; 2347 2348 case H8OP_MEM_BASE: 2349 case H8OP_MEM_ABSOLUTE: 2350 case H8OP_MEM_COMPLEX: 2351 return 4 + operand_length; 2352 2353 default: 2354 gcc_unreachable (); 2355 } 2356 } 2357 2358 /* Likewise bitfield load and store instructions. */ 2359 2360 static unsigned int 2361 h8300_bitfield_length (rtx op, rtx op2) 2362 { 2363 enum h8300_operand_class opclass; 2364 unsigned int size, operand_length; 2365 2366 if (GET_CODE (op) == REG) 2367 op = op2; 2368 gcc_assert (GET_CODE (op) != REG); 2369 2370 size = GET_MODE_SIZE (GET_MODE (op)); 2371 operand_length = h8300_classify_operand (op, size, &opclass); 2372 2373 switch (opclass) 2374 { 2375 case H8OP_MEM_BASE: 2376 case H8OP_MEM_ABSOLUTE: 2377 case H8OP_MEM_COMPLEX: 2378 return 4 + operand_length; 2379 2380 default: 2381 gcc_unreachable (); 2382 } 2383 } 2384 2385 /* Calculate the length of general binary instruction INSN using TABLE. */ 2386 2387 static unsigned int 2388 h8300_binary_length (rtx_insn *insn, const h8300_length_table *table) 2389 { 2390 rtx set; 2391 rtx pattern; 2392 2393 if (GET_CODE (insn) != INSN) 2394 gcc_unreachable (); 2395 2396 pattern = PATTERN (insn); 2397 if (GET_CODE (pattern) == PARALLEL 2398 && GET_CODE (XVECEXP (pattern, 0, 0)) == SET 2399 && GET_CODE (SET_SRC (XVECEXP (pattern, 0, 0))) == COMPARE) 2400 set = XVECEXP (pattern, 0, 1); 2401 else 2402 set = single_set (insn); 2403 gcc_assert (set); 2404 2405 if (BINARY_P (SET_SRC (set))) 2406 return h8300_length_from_table (XEXP (SET_SRC (set), 0), 2407 XEXP (SET_SRC (set), 1), table); 2408 else 2409 { 2410 gcc_assert (GET_RTX_CLASS (GET_CODE (SET_SRC (set))) == RTX_TERNARY); 2411 return h8300_length_from_table (XEXP (XEXP (SET_SRC (set), 1), 0), 2412 XEXP (XEXP (SET_SRC (set), 1), 1), 2413 table); 2414 } 2415 } 2416 2417 /* Subroutine of h8300_move_length. Return true if OP is 1- or 2-byte 2418 memory reference and either (1) it has the form @(d:16,Rn) or 2419 (2) its address has the code given by INC_CODE. */ 2420 2421 static bool 2422 h8300_short_move_mem_p (rtx op, enum rtx_code inc_code) 2423 { 2424 rtx addr; 2425 unsigned int size; 2426 2427 if (GET_CODE (op) != MEM) 2428 return false; 2429 2430 addr = XEXP (op, 0); 2431 size = GET_MODE_SIZE (GET_MODE (op)); 2432 if (size != 1 && size != 2) 2433 return false; 2434 2435 return (GET_CODE (addr) == inc_code 2436 || (GET_CODE (addr) == PLUS 2437 && GET_CODE (XEXP (addr, 0)) == REG 2438 && h8300_displacement_length (addr, size) == 2)); 2439 } 2440 2441 /* Calculate the length of move instruction INSN using the given length 2442 table. Although the tables are correct for most cases, there is some 2443 irregularity in the length of mov.b and mov.w. The following forms: 2444 2445 mov @ERs+, Rd 2446 mov @(d:16,ERs), Rd 2447 mov Rs, @-ERd 2448 mov Rs, @(d:16,ERd) 2449 2450 are two bytes shorter than most other "mov Rs, @complex" or 2451 "mov @complex,Rd" combinations. */ 2452 2453 static unsigned int 2454 h8300_move_length (rtx *operands, const h8300_length_table *table) 2455 { 2456 unsigned int size; 2457 2458 size = h8300_length_from_table (operands[0], operands[1], table); 2459 if (REG_P (operands[0]) && h8300_short_move_mem_p (operands[1], POST_INC)) 2460 size -= 2; 2461 if (REG_P (operands[1]) && h8300_short_move_mem_p (operands[0], PRE_DEC)) 2462 size -= 2; 2463 return size; 2464 } 2465 2466 /* Return the length of a mova instruction with the given operands. 2467 DEST is the register destination, SRC is the source address and 2468 OFFSET is the 16-bit or 32-bit displacement. */ 2469 2470 static unsigned int 2471 h8300_mova_length (rtx dest, rtx src, rtx offset) 2472 { 2473 unsigned int size; 2474 2475 size = (2 2476 + h8300_constant_length (offset) 2477 + h8300_classify_operand (src, GET_MODE_SIZE (GET_MODE (src)), 0)); 2478 if (!REG_P (dest) || !REG_P (src) || REGNO (src) != REGNO (dest)) 2479 size += 2; 2480 return size; 2481 } 2482 2483 /* Compute the length of INSN based on its length_table attribute. 2484 OPERANDS is the array of its operands. */ 2485 2486 unsigned int 2487 h8300_insn_length_from_table (rtx_insn *insn, rtx * operands) 2488 { 2489 switch (get_attr_length_table (insn)) 2490 { 2491 case LENGTH_TABLE_NONE: 2492 gcc_unreachable (); 2493 2494 case LENGTH_TABLE_ADD: 2495 if (GET_MODE (operands[0]) == QImode) 2496 return h8300_binary_length (insn, &addb_length_table); 2497 else if (GET_MODE (operands[0]) == HImode) 2498 return h8300_binary_length (insn, &addw_length_table); 2499 else if (GET_MODE (operands[0]) == SImode) 2500 return h8300_binary_length (insn, &addl_length_table); 2501 gcc_unreachable (); 2502 2503 case LENGTH_TABLE_LOGICB: 2504 return h8300_binary_length (insn, &logicb_length_table); 2505 2506 case LENGTH_TABLE_MOVB: 2507 return h8300_move_length (operands, &movb_length_table); 2508 2509 case LENGTH_TABLE_MOVW: 2510 return h8300_move_length (operands, &movw_length_table); 2511 2512 case LENGTH_TABLE_MOVL: 2513 return h8300_move_length (operands, &movl_length_table); 2514 2515 case LENGTH_TABLE_MOVA: 2516 return h8300_mova_length (operands[0], operands[1], operands[2]); 2517 2518 case LENGTH_TABLE_MOVA_ZERO: 2519 return h8300_mova_length (operands[0], operands[1], const0_rtx); 2520 2521 case LENGTH_TABLE_UNARY: 2522 return h8300_unary_length (operands[0]); 2523 2524 case LENGTH_TABLE_MOV_IMM4: 2525 return 2 + h8300_classify_operand (operands[0], 0, 0); 2526 2527 case LENGTH_TABLE_SHORT_IMMEDIATE: 2528 return h8300_short_immediate_length (operands[0]); 2529 2530 case LENGTH_TABLE_BITFIELD: 2531 return h8300_bitfield_length (operands[0], operands[1]); 2532 2533 case LENGTH_TABLE_BITBRANCH: 2534 return h8300_bitfield_length (operands[1], operands[2]) - 2; 2535 2536 default: 2537 gcc_unreachable (); 2538 } 2539 } 2540 2541 /* Return true if LHS and RHS are memory references that can be mapped 2542 to the same h8sx assembly operand. LHS appears as the destination of 2543 an instruction and RHS appears as a source. 2544 2545 Three cases are allowed: 2546 2547 - RHS is @+Rn or @-Rn, LHS is @Rn 2548 - RHS is @Rn, LHS is @Rn+ or @Rn- 2549 - RHS and LHS have the same address and neither has side effects. */ 2550 2551 bool 2552 h8sx_mergeable_memrefs_p (rtx lhs, rtx rhs) 2553 { 2554 if (GET_CODE (rhs) == MEM && GET_CODE (lhs) == MEM) 2555 { 2556 rhs = XEXP (rhs, 0); 2557 lhs = XEXP (lhs, 0); 2558 2559 if (GET_CODE (rhs) == PRE_INC || GET_CODE (rhs) == PRE_DEC) 2560 return rtx_equal_p (XEXP (rhs, 0), lhs); 2561 2562 if (GET_CODE (lhs) == POST_INC || GET_CODE (lhs) == POST_DEC) 2563 return rtx_equal_p (rhs, XEXP (lhs, 0)); 2564 2565 if (rtx_equal_p (rhs, lhs)) 2566 return true; 2567 } 2568 return false; 2569 } 2570 2571 /* Return true if OPERANDS[1] can be mapped to the same assembly 2572 operand as OPERANDS[0]. */ 2573 2574 bool 2575 h8300_operands_match_p (rtx *operands) 2576 { 2577 if (register_operand (operands[0], VOIDmode) 2578 && register_operand (operands[1], VOIDmode)) 2579 return true; 2580 2581 if (h8sx_mergeable_memrefs_p (operands[0], operands[1])) 2582 return true; 2583 2584 return false; 2585 } 2586 2587 /* Return the length of mov instruction. */ 2589 2590 unsigned int 2591 compute_mov_length (rtx *operands) 2592 { 2593 /* If the mov instruction involves a memory operand, we compute the 2594 length, assuming the largest addressing mode is used, and then 2595 adjust later in the function. Otherwise, we compute and return 2596 the exact length in one step. */ 2597 machine_mode mode = GET_MODE (operands[0]); 2598 rtx dest = operands[0]; 2599 rtx src = operands[1]; 2600 rtx addr; 2601 2602 if (GET_CODE (src) == MEM) 2603 addr = XEXP (src, 0); 2604 else if (GET_CODE (dest) == MEM) 2605 addr = XEXP (dest, 0); 2606 else 2607 addr = NULL_RTX; 2608 2609 unsigned int base_length; 2610 2611 switch (mode) 2612 { 2613 case E_QImode: 2614 if (addr == NULL_RTX) 2615 return 2; 2616 2617 /* The eightbit addressing is available only in QImode, so 2618 go ahead and take care of it. */ 2619 if (h8300_eightbit_constant_address_p (addr)) 2620 return 2; 2621 2622 base_length = 8; 2623 break; 2624 2625 case E_HImode: 2626 if (addr == NULL_RTX) 2627 { 2628 if (REG_P (src)) 2629 return 2; 2630 2631 if (src == const0_rtx) 2632 return 2; 2633 2634 return 4; 2635 } 2636 2637 base_length = 8; 2638 break; 2639 2640 case E_SImode: 2641 if (addr == NULL_RTX) 2642 { 2643 if (REG_P (src)) 2644 { 2645 if (REGNO (src) == MAC_REG || REGNO (dest) == MAC_REG) 2646 return 4; 2647 else 2648 return 2; 2649 } 2650 2651 if (GET_CODE (src) == CONST_INT) 2652 { 2653 int val = INTVAL (src); 2654 2655 if (val == 0) 2656 return 2; 2657 2658 if (val == (val & 0x00ff) || val == (val & 0xff00)) 2659 return 4; 2660 2661 switch (val & 0xffffffff) 2662 { 2663 case 0xffffffff: 2664 case 0xfffffffe: 2665 case 0xfffffffc: 2666 case 0x0000ffff: 2667 case 0x0000fffe: 2668 case 0xffff0000: 2669 case 0xfffe0000: 2670 case 0x00010000: 2671 case 0x00020000: 2672 return 4; 2673 } 2674 } 2675 return 6; 2676 } 2677 2678 base_length = 10; 2679 break; 2680 2681 case E_SFmode: 2682 if (addr == NULL_RTX) 2683 { 2684 if (REG_P (src)) 2685 return 2; 2686 2687 if (satisfies_constraint_G (src)) 2688 return 2; 2689 2690 return 6; 2691 } 2692 2693 base_length = 10; 2694 break; 2695 2696 default: 2697 gcc_unreachable (); 2698 } 2699 2700 /* Adjust the length based on the addressing mode used. 2701 Specifically, we subtract the difference between the actual 2702 length and the longest one, which is @(d:24,ERs). */ 2703 2704 /* @ERs+ and @-ERd are 6 bytes shorter than the longest. */ 2705 if (GET_CODE (addr) == PRE_DEC 2706 || GET_CODE (addr) == POST_INC) 2707 return base_length - 6; 2708 2709 /* @ERs and @ERd are 6 bytes shorter than the longest. */ 2710 if (GET_CODE (addr) == REG) 2711 return base_length - 6; 2712 2713 /* @(d:16,ERs) and @(d:16,ERd) are 4 bytes shorter than the 2714 longest. */ 2715 if (GET_CODE (addr) == PLUS 2716 && GET_CODE (XEXP (addr, 0)) == REG 2717 && GET_CODE (XEXP (addr, 1)) == CONST_INT 2718 && INTVAL (XEXP (addr, 1)) > -32768 2719 && INTVAL (XEXP (addr, 1)) < 32767) 2720 return base_length - 4; 2721 2722 /* @aa:16 is 4 bytes shorter than the longest. */ 2723 if (h8300_tiny_constant_address_p (addr)) 2724 return base_length - 4; 2725 2726 /* @aa:24 is 2 bytes shorter than the longest. */ 2727 if (CONSTANT_P (addr)) 2728 return base_length - 2; 2729 2730 return base_length; 2731 } 2732 2733 /* Output an addition insn. */ 2735 2736 const char * 2737 output_plussi (rtx *operands, bool need_flags) 2738 { 2739 machine_mode mode = GET_MODE (operands[0]); 2740 2741 gcc_assert (mode == SImode); 2742 2743 if (GET_CODE (operands[2]) == CONST_INT 2744 && register_operand (operands[1], VOIDmode)) 2745 { 2746 HOST_WIDE_INT intval = INTVAL (operands[2]); 2747 2748 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2749 return "add.l\t%S2,%S0"; 2750 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2751 return "sub.l\t%G2,%S0"; 2752 2753 /* See if we can finish with 2 bytes. */ 2754 2755 switch ((unsigned int) intval & 0xffffffff) 2756 { 2757 /* INC/DEC set the flags, but adds/subs do not. So if we 2758 need flags, use the former and not the latter. */ 2759 case 0x00000001: 2760 if (need_flags) 2761 return "inc.l\t#1,%S0"; 2762 else 2763 return "adds\t%2,%S0"; 2764 case 0x00000002: 2765 if (need_flags) 2766 return "inc.l\t#2,%S0"; 2767 else 2768 return "adds\t%2,%S0"; 2769 case 0xffffffff: 2770 if (need_flags) 2771 return "dec.l\t#1,%S0"; 2772 else 2773 return "subs\t%G2,%S0"; 2774 case 0xfffffffe: 2775 if (need_flags) 2776 return "dec.l\t#2,%S0"; 2777 else 2778 return "subs\t%G2,%S0"; 2779 2780 /* These six cases have optimized paths when we do not 2781 need flags. Otherwise we let them fallthru. */ 2782 case 0x00000004: 2783 if (!need_flags) 2784 return "adds\t%2,%S0"; 2785 2786 /* FALLTHRU */ 2787 2788 case 0xfffffffc: 2789 if (!need_flags) 2790 return "subs\t%G2,%S0"; 2791 2792 /* FALLTHRU */ 2793 2794 case 0x00010000: 2795 case 0x00020000: 2796 if (!need_flags) 2797 { 2798 operands[2] = GEN_INT (intval >> 16); 2799 return "inc.w\t%2,%e0"; 2800 } 2801 2802 /* FALLTHRU */ 2803 2804 case 0xffff0000: 2805 case 0xfffe0000: 2806 if (!need_flags) 2807 { 2808 operands[2] = GEN_INT (intval >> 16); 2809 return "dec.w\t%G2,%e0"; 2810 } 2811 2812 /* FALLTHRU */ 2813 2814 } 2815 2816 /* See if we can finish with 4 bytes. */ 2817 if ((intval & 0xffff) == 0) 2818 { 2819 operands[2] = GEN_INT (intval >> 16); 2820 return "add.w\t%2,%e0"; 2821 } 2822 } 2823 2824 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 2825 { 2826 operands[2] = GEN_INT (-INTVAL (operands[2])); 2827 return "sub.l\t%S2,%S0"; 2828 } 2829 return "add.l\t%S2,%S0"; 2830 } 2831 2832 /* ??? It would be much easier to add the h8sx stuff if a single function 2833 classified the addition as either inc/dec, adds/subs, add.w or add.l. */ 2834 /* Compute the length of an addition insn. */ 2835 2836 unsigned int 2837 compute_plussi_length (rtx *operands, bool need_flags) 2838 { 2839 machine_mode mode = GET_MODE (operands[0]); 2840 2841 gcc_assert (mode == SImode); 2842 2843 if (GET_CODE (operands[2]) == CONST_INT 2844 && register_operand (operands[1], VOIDmode)) 2845 { 2846 HOST_WIDE_INT intval = INTVAL (operands[2]); 2847 2848 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2849 return 2; 2850 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2851 return 2; 2852 2853 /* See if we can finish with 2 bytes. */ 2854 2855 switch ((unsigned int) intval & 0xffffffff) 2856 { 2857 case 0x00000001: 2858 case 0x00000002: 2859 return 2; 2860 case 0x00000004: 2861 if (need_flags) 2862 return 6; 2863 else 2864 return 2; 2865 2866 case 0xffffffff: 2867 case 0xfffffffe: 2868 return 2; 2869 case 0xfffffffc: 2870 if (need_flags) 2871 return 6; 2872 else 2873 return 2; 2874 2875 case 0x00010000: 2876 case 0x00020000: 2877 if (!need_flags) 2878 return 2; 2879 2880 /* FALLTHRU */ 2881 2882 case 0xffff0000: 2883 case 0xfffe0000: 2884 if (!need_flags) 2885 return 2; 2886 2887 /* FALLTHRU */ 2888 2889 } 2890 2891 /* See if we can finish with 4 bytes. */ 2892 if ((intval & 0xffff) == 0) 2893 return 4; 2894 } 2895 2896 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 2897 return h8300_length_from_table (operands[0], 2898 GEN_INT (-INTVAL (operands[2])), 2899 &addl_length_table); 2900 else 2901 return h8300_length_from_table (operands[0], operands[2], 2902 &addl_length_table); 2903 } 2904 2905 /* Compute which flag bits are valid after an addition insn. */ 2906 2907 enum attr_old_cc 2908 compute_plussi_cc (rtx *operands) 2909 { 2910 machine_mode mode = GET_MODE (operands[0]); 2911 2912 gcc_assert (mode == SImode); 2913 2914 if (GET_CODE (operands[2]) == CONST_INT 2915 && register_operand (operands[1], VOIDmode)) 2916 { 2917 HOST_WIDE_INT intval = INTVAL (operands[2]); 2918 2919 if (TARGET_H8300SX && (intval >= 1 && intval <= 7)) 2920 return OLD_CC_SET_ZN; 2921 if (TARGET_H8300SX && (intval >= -7 && intval <= -1)) 2922 return OLD_CC_SET_ZN; 2923 2924 /* See if we can finish with 2 bytes. */ 2925 2926 switch ((unsigned int) intval & 0xffffffff) 2927 { 2928 case 0x00000001: 2929 case 0x00000002: 2930 case 0x00000004: 2931 return OLD_CC_NONE_0HIT; 2932 2933 case 0xffffffff: 2934 case 0xfffffffe: 2935 case 0xfffffffc: 2936 return OLD_CC_NONE_0HIT; 2937 2938 case 0x00010000: 2939 case 0x00020000: 2940 return OLD_CC_CLOBBER; 2941 2942 case 0xffff0000: 2943 case 0xfffe0000: 2944 return OLD_CC_CLOBBER; 2945 } 2946 2947 /* See if we can finish with 4 bytes. */ 2948 if ((intval & 0xffff) == 0) 2949 return OLD_CC_CLOBBER; 2950 } 2951 2952 return OLD_CC_SET_ZN; 2953 } 2954 2955 /* Output a logical insn. */ 2957 2958 const char * 2959 output_logical_op (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn) 2960 { 2961 /* Pretend that every byte is affected if both operands are registers. */ 2962 const unsigned HOST_WIDE_INT intval = 2963 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 2964 /* Always use the full instruction if the 2965 first operand is in memory. It is better 2966 to use define_splits to generate the shorter 2967 sequence where valid. */ 2968 && register_operand (operands[1], VOIDmode) 2969 ? INTVAL (operands[2]) : 0x55555555); 2970 /* The determinant of the algorithm. If we perform an AND, 0 2971 affects a bit. Otherwise, 1 affects a bit. */ 2972 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 2973 /* Break up DET into pieces. */ 2974 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 2975 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 2976 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 2977 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 2978 int lower_half_easy_p = 0; 2979 int upper_half_easy_p = 0; 2980 /* The name of an insn. */ 2981 const char *opname; 2982 char insn_buf[100]; 2983 2984 /* INSN is the current insn, we examine its overall form to see if we're 2985 supposed to set or clobber the condition codes. 2986 2987 This is important to know. If we are setting condition codes, then we 2988 must do the operation in MODE and not in some smaller size. 2989 2990 The key is to look at the second object in the PARALLEL. If it is not 2991 a CLOBBER, then we care about the condition codes. */ 2992 rtx pattern = PATTERN (insn); 2993 gcc_assert (GET_CODE (pattern) == PARALLEL); 2994 rtx second_op = XVECEXP (pattern, 0, 1); 2995 bool cc_meaningful = (GET_CODE (second_op) != CLOBBER); 2996 2997 switch (code) 2998 { 2999 case AND: 3000 opname = "and"; 3001 break; 3002 case IOR: 3003 opname = "or"; 3004 break; 3005 case XOR: 3006 opname = "xor"; 3007 break; 3008 default: 3009 gcc_unreachable (); 3010 } 3011 3012 switch (mode) 3013 { 3014 case E_QImode: 3015 sprintf (insn_buf, "%s.b\t%%X2,%%X0", opname); 3016 output_asm_insn (insn_buf, operands); 3017 break; 3018 case E_HImode: 3019 /* First, see if we can (or must) finish with one insn. */ 3020 if (cc_meaningful 3021 || (b0 != 0 && b1 != 0)) 3022 { 3023 sprintf (insn_buf, "%s.w\t%%T2,%%T0", opname); 3024 output_asm_insn (insn_buf, operands); 3025 } 3026 else 3027 { 3028 /* Take care of the lower byte. */ 3029 if (b0 != 0) 3030 { 3031 sprintf (insn_buf, "%s\t%%s2,%%s0", opname); 3032 output_asm_insn (insn_buf, operands); 3033 } 3034 /* Take care of the upper byte. */ 3035 if (b1 != 0) 3036 { 3037 sprintf (insn_buf, "%s\t%%t2,%%t0", opname); 3038 output_asm_insn (insn_buf, operands); 3039 } 3040 } 3041 break; 3042 case E_SImode: 3043 /* Determine if the lower half can be taken care of in no more 3044 than two bytes. */ 3045 lower_half_easy_p = (b0 == 0 3046 || b1 == 0 3047 || (code != IOR && w0 == 0xffff)); 3048 3049 /* Determine if the upper half can be taken care of in no more 3050 than two bytes. */ 3051 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3052 || (code == AND && w1 == 0xff00)); 3053 3054 /* Check if doing everything with one insn is no worse than 3055 using multiple insns. */ 3056 if (cc_meaningful 3057 || (w0 != 0 && w1 != 0 3058 && !(lower_half_easy_p && upper_half_easy_p) 3059 && !(code == IOR && w1 == 0xffff 3060 && (w0 & 0x8000) != 0 && lower_half_easy_p))) 3061 { 3062 sprintf (insn_buf, "%s.l\t%%S2,%%S0", opname); 3063 output_asm_insn (insn_buf, operands); 3064 } 3065 else 3066 { 3067 /* Take care of the lower and upper words individually. For 3068 each word, we try different methods in the order of 3069 3070 1) the special insn (in case of AND or XOR), 3071 2) the word-wise insn, and 3072 3) The byte-wise insn. */ 3073 if (w0 == 0xffff && (code != IOR)) 3074 output_asm_insn ((code == AND) 3075 ? "sub.w\t%f0,%f0" : "not.w\t%f0", 3076 operands); 3077 else if ((b0 != 0) && (b1 != 0)) 3078 { 3079 sprintf (insn_buf, "%s.w\t%%f2,%%f0", opname); 3080 output_asm_insn (insn_buf, operands); 3081 } 3082 else 3083 { 3084 if (b0 != 0) 3085 { 3086 sprintf (insn_buf, "%s\t%%w2,%%w0", opname); 3087 output_asm_insn (insn_buf, operands); 3088 } 3089 if (b1 != 0) 3090 { 3091 sprintf (insn_buf, "%s\t%%x2,%%x0", opname); 3092 output_asm_insn (insn_buf, operands); 3093 } 3094 } 3095 3096 if ((w1 == 0xffff) && (code != IOR)) 3097 output_asm_insn ((code == AND) 3098 ? "sub.w\t%e0,%e0" : "not.w\t%e0", 3099 operands); 3100 else if (code == IOR 3101 && w1 == 0xffff 3102 && (w0 & 0x8000) != 0) 3103 { 3104 output_asm_insn ("exts.l\t%S0", operands); 3105 } 3106 else if (code == AND 3107 && w1 == 0xff00) 3108 { 3109 output_asm_insn ("extu.w\t%e0", operands); 3110 } 3111 else 3112 { 3113 if (w1 != 0) 3114 { 3115 sprintf (insn_buf, "%s.w\t%%e2,%%e0", opname); 3116 output_asm_insn (insn_buf, operands); 3117 } 3118 } 3119 } 3120 break; 3121 default: 3122 gcc_unreachable (); 3123 } 3124 return ""; 3125 } 3126 3127 /* Compute the length of a logical insn. */ 3128 3129 unsigned int 3130 compute_logical_op_length (machine_mode mode, rtx_code code, rtx *operands, rtx_insn *insn) 3131 { 3132 /* Pretend that every byte is affected if both operands are registers. */ 3133 const unsigned HOST_WIDE_INT intval = 3134 (unsigned HOST_WIDE_INT) ((GET_CODE (operands[2]) == CONST_INT) 3135 /* Always use the full instruction if the 3136 first operand is in memory. It is better 3137 to use define_splits to generate the shorter 3138 sequence where valid. */ 3139 && register_operand (operands[1], VOIDmode) 3140 ? INTVAL (operands[2]) : 0x55555555); 3141 /* The determinant of the algorithm. If we perform an AND, 0 3142 affects a bit. Otherwise, 1 affects a bit. */ 3143 const unsigned HOST_WIDE_INT det = (code != AND) ? intval : ~intval; 3144 /* Break up DET into pieces. */ 3145 const unsigned HOST_WIDE_INT b0 = (det >> 0) & 0xff; 3146 const unsigned HOST_WIDE_INT b1 = (det >> 8) & 0xff; 3147 const unsigned HOST_WIDE_INT w0 = (det >> 0) & 0xffff; 3148 const unsigned HOST_WIDE_INT w1 = (det >> 16) & 0xffff; 3149 int lower_half_easy_p = 0; 3150 int upper_half_easy_p = 0; 3151 /* Insn length. */ 3152 unsigned int length = 0; 3153 3154 /* INSN is the current insn, we examine its overall form to see if we're 3155 supposed to set or clobber the condition codes. 3156 3157 This is important to know. If we are setting condition codes, then we 3158 must do the operation in MODE and not in some smaller size. 3159 3160 The key is to look at the second object in the PARALLEL. If it is not 3161 a CLOBBER, then we care about the condition codes. */ 3162 bool cc_meaningful = false; 3163 if (insn) 3164 { 3165 rtx pattern = PATTERN (insn); 3166 gcc_assert (GET_CODE (pattern) == PARALLEL); 3167 rtx second_op = XVECEXP (pattern, 0, 1); 3168 cc_meaningful = (GET_CODE (second_op) != CLOBBER); 3169 } 3170 3171 switch (mode) 3172 { 3173 case E_QImode: 3174 return 2; 3175 3176 case E_HImode: 3177 /* First, see if we can finish with one insn. */ 3178 if (cc_meaningful 3179 || (b0 != 0 && b1 != 0)) 3180 { 3181 length = h8300_length_from_table (operands[1], operands[2], 3182 &logicw_length_table); 3183 } 3184 else 3185 { 3186 /* Take care of the lower byte. */ 3187 if (b0 != 0) 3188 length += 2; 3189 3190 /* Take care of the upper byte. */ 3191 if (b1 != 0) 3192 length += 2; 3193 } 3194 break; 3195 case E_SImode: 3196 /* Determine if the lower half can be taken care of in no more 3197 than two bytes. */ 3198 lower_half_easy_p = (b0 == 0 3199 || b1 == 0 3200 || (code != IOR && w0 == 0xffff)); 3201 3202 /* Determine if the upper half can be taken care of in no more 3203 than two bytes. */ 3204 upper_half_easy_p = ((code != IOR && w1 == 0xffff) 3205 || (code == AND && w1 == 0xff00)); 3206 3207 /* Check if doing everything with one insn is no worse than 3208 using multiple insns. */ 3209 if (cc_meaningful 3210 || (w0 != 0 && w1 != 0 3211 && !(lower_half_easy_p && upper_half_easy_p) 3212 && !(code == IOR && w1 == 0xffff 3213 && (w0 & 0x8000) != 0 && lower_half_easy_p))) 3214 { 3215 length = h8300_length_from_table (operands[1], operands[2], 3216 &logicl_length_table); 3217 } 3218 else 3219 { 3220 /* Take care of the lower and upper words individually. For 3221 each word, we try different methods in the order of 3222 3223 1) the special insn (in case of AND or XOR), 3224 2) the word-wise insn, and 3225 3) The byte-wise insn. */ 3226 if (w0 == 0xffff && (code != IOR)) 3227 { 3228 length += 2; 3229 } 3230 else if ((b0 != 0) && (b1 != 0)) 3231 { 3232 length += 4; 3233 } 3234 else 3235 { 3236 if (b0 != 0) 3237 length += 2; 3238 3239 if (b1 != 0) 3240 length += 2; 3241 } 3242 3243 if (w1 == 0xffff && (code != IOR)) 3244 { 3245 length += 2; 3246 } 3247 else if (code == IOR 3248 && w1 == 0xffff 3249 && (w0 & 0x8000) != 0) 3250 { 3251 length += 2; 3252 } 3253 else if (code == AND && w1 == 0xff00) 3254 { 3255 length += 2; 3256 } 3257 else 3258 { 3259 if (w1 != 0) 3260 length += 4; 3261 } 3262 } 3263 break; 3264 default: 3265 gcc_unreachable (); 3266 } 3267 return length; 3268 } 3269 3270 #if 0 3271 3272 /* Expand a conditional store. */ 3274 3275 void 3276 h8300_expand_store (rtx operands[]) 3277 { 3278 rtx dest = operands[0]; 3279 enum rtx_code code = GET_CODE (operands[1]); 3280 rtx op0 = operands[2]; 3281 rtx op1 = operands[3]; 3282 rtx tmp; 3283 3284 tmp = gen_rtx_COMPARE (VOIDmode, op0, op1); 3285 emit_insn (gen_rtx_SET (cc0_rtx, tmp)); 3286 3287 tmp = gen_rtx_fmt_ee (code, GET_MODE (dest), cc0_rtx, const0_rtx); 3288 emit_insn (gen_rtx_SET (dest, tmp)); 3289 } 3290 #endif 3291 3292 /* Shifts. 3294 3295 We devote a fair bit of code to getting efficient shifts since we 3296 can only shift one bit at a time on the H8/300 and H8/300H and only 3297 one or two bits at a time on the H8S. 3298 3299 All shift code falls into one of the following ways of 3300 implementation: 3301 3302 o SHIFT_INLINE: Emit straight line code for the shift; this is used 3303 when a straight line shift is about the same size or smaller than 3304 a loop. 3305 3306 o SHIFT_ROT_AND: Rotate the value the opposite direction, then mask 3307 off the bits we don't need. This is used when only a few of the 3308 bits in the original value will survive in the shifted value. 3309 3310 o SHIFT_SPECIAL: Often it's possible to move a byte or a word to 3311 simulate a shift by 8, 16, or 24 bits. Once moved, a few inline 3312 shifts can be added if the shift count is slightly more than 8 or 3313 16. This case also includes other oddballs that are not worth 3314 explaining here. 3315 3316 o SHIFT_LOOP: Emit a loop using one (or two on H8S) bit shifts. 3317 3318 For each shift count, we try to use code that has no trade-off 3319 between code size and speed whenever possible. 3320 3321 If the trade-off is unavoidable, we try to be reasonable. 3322 Specifically, the fastest version is one instruction longer than 3323 the shortest version, we take the fastest version. We also provide 3324 the use a way to switch back to the shortest version with -Os. 3325 3326 For the details of the shift algorithms for various shift counts, 3327 refer to shift_alg_[qhs]i. */ 3328 3329 /* Classify a shift with the given mode and code. OP is the shift amount. */ 3330 3331 enum h8sx_shift_type 3332 h8sx_classify_shift (machine_mode mode, enum rtx_code code, rtx op) 3333 { 3334 if (!TARGET_H8300SX) 3335 return H8SX_SHIFT_NONE; 3336 3337 switch (code) 3338 { 3339 case ASHIFT: 3340 case LSHIFTRT: 3341 /* Check for variable shifts (shll Rs,Rd and shlr Rs,Rd). */ 3342 if (GET_CODE (op) != CONST_INT) 3343 return H8SX_SHIFT_BINARY; 3344 3345 /* Reject out-of-range shift amounts. */ 3346 if (INTVAL (op) <= 0 || INTVAL (op) >= GET_MODE_BITSIZE (mode)) 3347 return H8SX_SHIFT_NONE; 3348 3349 /* Power-of-2 shifts are effectively unary operations. */ 3350 if (exact_log2 (INTVAL (op)) >= 0) 3351 return H8SX_SHIFT_UNARY; 3352 3353 return H8SX_SHIFT_BINARY; 3354 3355 case ASHIFTRT: 3356 if (op == const1_rtx || op == const2_rtx) 3357 return H8SX_SHIFT_UNARY; 3358 return H8SX_SHIFT_NONE; 3359 3360 case ROTATE: 3361 if (GET_CODE (op) == CONST_INT 3362 && (INTVAL (op) == 1 3363 || INTVAL (op) == 2 3364 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 2 3365 || INTVAL (op) == GET_MODE_BITSIZE (mode) - 1)) 3366 return H8SX_SHIFT_UNARY; 3367 return H8SX_SHIFT_NONE; 3368 3369 default: 3370 return H8SX_SHIFT_NONE; 3371 } 3372 } 3373 3374 /* Return the asm template for a single h8sx shift instruction. 3375 OPERANDS[0] and OPERANDS[1] are the destination, OPERANDS[2] 3376 is the source and OPERANDS[3] is the shift. SUFFIX is the 3377 size suffix ('b', 'w' or 'l') and OPTYPE is the h8300_print_operand 3378 prefix for the destination operand. */ 3379 3380 const char * 3381 output_h8sx_shift (rtx *operands, int suffix, int optype) 3382 { 3383 static char buffer[16]; 3384 const char *stem; 3385 3386 switch (GET_CODE (operands[3])) 3387 { 3388 case ASHIFT: 3389 stem = "shll"; 3390 break; 3391 3392 case ASHIFTRT: 3393 stem = "shar"; 3394 break; 3395 3396 case LSHIFTRT: 3397 stem = "shlr"; 3398 break; 3399 3400 case ROTATE: 3401 stem = "rotl"; 3402 if (INTVAL (operands[2]) > 2) 3403 { 3404 /* This is really a right rotate. */ 3405 operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[0])) 3406 - INTVAL (operands[2])); 3407 stem = "rotr"; 3408 } 3409 break; 3410 3411 default: 3412 gcc_unreachable (); 3413 } 3414 if (operands[2] == const1_rtx) 3415 sprintf (buffer, "%s.%c\t%%%c0", stem, suffix, optype); 3416 else 3417 sprintf (buffer, "%s.%c\t%%X2,%%%c0", stem, suffix, optype); 3418 return buffer; 3419 } 3420 3421 /* Emit code to do shifts. */ 3422 3423 bool 3424 expand_a_shift (machine_mode mode, enum rtx_code code, rtx operands[]) 3425 { 3426 switch (h8sx_classify_shift (mode, code, operands[2])) 3427 { 3428 case H8SX_SHIFT_BINARY: 3429 operands[1] = force_reg (mode, operands[1]); 3430 return false; 3431 3432 case H8SX_SHIFT_UNARY: 3433 return false; 3434 3435 case H8SX_SHIFT_NONE: 3436 break; 3437 } 3438 3439 /* Need a loop to get all the bits we want - we generate the 3440 code at emit time, but need to allocate a scratch reg now. */ 3441 emit_move_insn (copy_rtx (operands[0]), operands[1]); 3442 if (operands[2] == CONST0_RTX (QImode)) 3443 ; 3444 else if (GET_CODE (operands[2]) == CONST_INT 3445 && !h8300_shift_needs_scratch_p (INTVAL (operands[2]), mode, code)) 3446 emit_insn (gen_rtx_SET (copy_rtx (operands[0]), 3447 gen_rtx_fmt_ee (code, mode, 3448 copy_rtx (operands[1]), operands[2]))); 3449 else 3450 emit_insn (gen_rtx_PARALLEL 3451 (VOIDmode, 3452 gen_rtvec (2, 3453 gen_rtx_SET (copy_rtx (operands[0]), 3454 gen_rtx_fmt_ee (code, mode, 3455 copy_rtx (operands[0]), operands[2])), 3456 gen_rtx_CLOBBER (VOIDmode, 3457 gen_rtx_SCRATCH (QImode))))); 3458 return true; 3459 } 3460 3461 /* Symbols of the various modes which can be used as indices. */ 3462 3463 enum shift_mode 3464 { 3465 QIshift, HIshift, SIshift 3466 }; 3467 3468 /* For single bit shift insns, record assembler and what bits of the 3469 condition code are valid afterwards (represented as various OLD_CC_FOO 3470 bits, 0 means CC isn't left in a usable state). */ 3471 3472 struct shift_insn 3473 { 3474 const char *const assembler; 3475 const enum attr_old_cc cc_valid; 3476 }; 3477 3478 /* Assembler instruction shift table. 3479 3480 These tables are used to look up the basic shifts. 3481 They are indexed by cpu, shift_type, and mode. */ 3482 3483 static const struct shift_insn shift_one[2][3][3] = 3484 { 3485 /* H8/300 */ 3486 { 3487 /* SHIFT_ASHIFT */ 3488 { 3489 { "shll\t%X0", OLD_CC_SET_ZNV }, 3490 { "add.w\t%T0,%T0", OLD_CC_SET_ZN }, 3491 { "add.w\t%f0,%f0\n\taddx\t%y0,%y0\n\taddx\t%z0,%z0", OLD_CC_CLOBBER } 3492 }, 3493 /* SHIFT_LSHIFTRT */ 3494 { 3495 { "shlr\t%X0", OLD_CC_SET_ZNV }, 3496 { "shlr\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER }, 3497 { "shlr\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER } 3498 }, 3499 /* SHIFT_ASHIFTRT */ 3500 { 3501 { "shar\t%X0", OLD_CC_SET_ZNV }, 3502 { "shar\t%t0\n\trotxr\t%s0", OLD_CC_CLOBBER }, 3503 { "shar\t%z0\n\trotxr\t%y0\n\trotxr\t%x0\n\trotxr\t%w0", OLD_CC_CLOBBER } 3504 } 3505 }, 3506 /* H8/300H */ 3507 { 3508 /* SHIFT_ASHIFT */ 3509 { 3510 { "shll.b\t%X0", OLD_CC_SET_ZNV }, 3511 { "shll.w\t%T0", OLD_CC_SET_ZNV }, 3512 { "shll.l\t%S0", OLD_CC_SET_ZNV } 3513 }, 3514 /* SHIFT_LSHIFTRT */ 3515 { 3516 { "shlr.b\t%X0", OLD_CC_SET_ZNV }, 3517 { "shlr.w\t%T0", OLD_CC_SET_ZNV }, 3518 { "shlr.l\t%S0", OLD_CC_SET_ZNV } 3519 }, 3520 /* SHIFT_ASHIFTRT */ 3521 { 3522 { "shar.b\t%X0", OLD_CC_SET_ZNV }, 3523 { "shar.w\t%T0", OLD_CC_SET_ZNV }, 3524 { "shar.l\t%S0", OLD_CC_SET_ZNV } 3525 } 3526 } 3527 }; 3528 3529 static const struct shift_insn shift_two[3][3] = 3530 { 3531 /* SHIFT_ASHIFT */ 3532 { 3533 { "shll.b\t#2,%X0", OLD_CC_SET_ZNV }, 3534 { "shll.w\t#2,%T0", OLD_CC_SET_ZNV }, 3535 { "shll.l\t#2,%S0", OLD_CC_SET_ZNV } 3536 }, 3537 /* SHIFT_LSHIFTRT */ 3538 { 3539 { "shlr.b\t#2,%X0", OLD_CC_SET_ZNV }, 3540 { "shlr.w\t#2,%T0", OLD_CC_SET_ZNV }, 3541 { "shlr.l\t#2,%S0", OLD_CC_SET_ZNV } 3542 }, 3543 /* SHIFT_ASHIFTRT */ 3544 { 3545 { "shar.b\t#2,%X0", OLD_CC_SET_ZNV }, 3546 { "shar.w\t#2,%T0", OLD_CC_SET_ZNV }, 3547 { "shar.l\t#2,%S0", OLD_CC_SET_ZNV } 3548 } 3549 }; 3550 3551 /* Rotates are organized by which shift they'll be used in implementing. 3552 There's no need to record whether the cc is valid afterwards because 3553 it is the AND insn that will decide this. */ 3554 3555 static const char *const rotate_one[2][3][3] = 3556 { 3557 /* H8/300 */ 3558 { 3559 /* SHIFT_ASHIFT */ 3560 { 3561 "rotr\t%X0", 3562 "shlr\t%t0\n\trotxr\t%s0\n\tbst\t#7,%t0", 3563 0 3564 }, 3565 /* SHIFT_LSHIFTRT */ 3566 { 3567 "rotl\t%X0", 3568 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3569 0 3570 }, 3571 /* SHIFT_ASHIFTRT */ 3572 { 3573 "rotl\t%X0", 3574 "shll\t%s0\n\trotxl\t%t0\n\tbst\t#0,%s0", 3575 0 3576 } 3577 }, 3578 /* H8/300H */ 3579 { 3580 /* SHIFT_ASHIFT */ 3581 { 3582 "rotr.b\t%X0", 3583 "rotr.w\t%T0", 3584 "rotr.l\t%S0" 3585 }, 3586 /* SHIFT_LSHIFTRT */ 3587 { 3588 "rotl.b\t%X0", 3589 "rotl.w\t%T0", 3590 "rotl.l\t%S0" 3591 }, 3592 /* SHIFT_ASHIFTRT */ 3593 { 3594 "rotl.b\t%X0", 3595 "rotl.w\t%T0", 3596 "rotl.l\t%S0" 3597 } 3598 } 3599 }; 3600 3601 static const char *const rotate_two[3][3] = 3602 { 3603 /* SHIFT_ASHIFT */ 3604 { 3605 "rotr.b\t#2,%X0", 3606 "rotr.w\t#2,%T0", 3607 "rotr.l\t#2,%S0" 3608 }, 3609 /* SHIFT_LSHIFTRT */ 3610 { 3611 "rotl.b\t#2,%X0", 3612 "rotl.w\t#2,%T0", 3613 "rotl.l\t#2,%S0" 3614 }, 3615 /* SHIFT_ASHIFTRT */ 3616 { 3617 "rotl.b\t#2,%X0", 3618 "rotl.w\t#2,%T0", 3619 "rotl.l\t#2,%S0" 3620 } 3621 }; 3622 3623 struct shift_info { 3624 /* Shift algorithm. */ 3625 enum shift_alg alg; 3626 3627 /* The number of bits to be shifted by shift1 and shift2. Valid 3628 when ALG is SHIFT_SPECIAL. */ 3629 unsigned int remainder; 3630 3631 /* Special insn for a shift. Valid when ALG is SHIFT_SPECIAL. */ 3632 const char *special; 3633 3634 /* Insn for a one-bit shift. Valid when ALG is either SHIFT_INLINE 3635 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 3636 const char *shift1; 3637 3638 /* Insn for a two-bit shift. Valid when ALG is either SHIFT_INLINE 3639 or SHIFT_SPECIAL, and REMAINDER is nonzero. */ 3640 const char *shift2; 3641 3642 /* CC status for SHIFT_INLINE. */ 3643 enum attr_old_cc cc_inline; 3644 3645 /* CC status for SHIFT_SPECIAL. */ 3646 enum attr_old_cc cc_special; 3647 }; 3648 3649 static void get_shift_alg (enum shift_type, 3650 enum shift_mode, unsigned int, 3651 struct shift_info *); 3652 3653 /* Given SHIFT_TYPE, SHIFT_MODE, and shift count COUNT, determine the 3654 best algorithm for doing the shift. The assembler code is stored 3655 in the pointers in INFO. We achieve the maximum efficiency in most 3656 cases. 3657 3658 We first determine the strategy of the shift algorithm by a table 3659 lookup. If that tells us to use a hand crafted assembly code, we 3660 go into the big switch statement to find what that is. Otherwise, 3661 we resort to a generic way, such as inlining. In either case, the 3662 result is returned through INFO. */ 3663 3664 static void 3665 get_shift_alg (enum shift_type shift_type, enum shift_mode shift_mode, 3666 unsigned int count, struct shift_info *info) 3667 { 3668 enum h8_cpu cpu; 3669 3670 if (TARGET_H8300S) 3671 cpu = H8_S; 3672 else 3673 cpu = H8_300H; 3674 3675 /* Find the shift algorithm. */ 3676 info->alg = SHIFT_LOOP; 3677 switch (shift_mode) 3678 { 3679 case QIshift: 3680 if (count < GET_MODE_BITSIZE (QImode)) 3681 info->alg = shift_alg_qi[cpu][shift_type][count]; 3682 break; 3683 3684 case HIshift: 3685 if (count < GET_MODE_BITSIZE (HImode)) 3686 info->alg = shift_alg_hi[cpu][shift_type][count]; 3687 break; 3688 3689 case SIshift: 3690 if (count < GET_MODE_BITSIZE (SImode)) 3691 info->alg = shift_alg_si[cpu][shift_type][count]; 3692 break; 3693 3694 default: 3695 gcc_unreachable (); 3696 } 3697 3698 /* Fill in INFO. Return unless we have SHIFT_SPECIAL. */ 3699 switch (info->alg) 3700 { 3701 case SHIFT_INLINE: 3702 info->remainder = count; 3703 /* Fall through. */ 3704 3705 case SHIFT_LOOP: 3706 /* It is up to the caller to know that looping clobbers cc. */ 3707 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 3708 info->shift2 = shift_two[shift_type][shift_mode].assembler; 3709 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 3710 goto end; 3711 3712 case SHIFT_ROT_AND: 3713 info->shift1 = rotate_one[cpu_type][shift_type][shift_mode]; 3714 info->shift2 = rotate_two[shift_type][shift_mode]; 3715 info->cc_inline = OLD_CC_CLOBBER; 3716 goto end; 3717 3718 case SHIFT_SPECIAL: 3719 /* REMAINDER is 0 for most cases, so initialize it to 0. */ 3720 info->remainder = 0; 3721 info->shift1 = shift_one[cpu_type][shift_type][shift_mode].assembler; 3722 info->shift2 = shift_two[shift_type][shift_mode].assembler; 3723 info->cc_inline = shift_one[cpu_type][shift_type][shift_mode].cc_valid; 3724 info->cc_special = OLD_CC_CLOBBER; 3725 break; 3726 } 3727 3728 /* Here we only deal with SHIFT_SPECIAL. */ 3729 switch (shift_mode) 3730 { 3731 case QIshift: 3732 /* For ASHIFTRT by 7 bits, the sign bit is simply replicated 3733 through the entire value. */ 3734 gcc_assert (shift_type == SHIFT_ASHIFTRT && count == 7); 3735 info->special = "shll\t%X0\n\tsubx\t%X0,%X0"; 3736 goto end; 3737 3738 case HIshift: 3739 if (count == 7) 3740 { 3741 switch (shift_type) 3742 { 3743 case SHIFT_ASHIFT: 3744 info->special = "shar.b\t%t0\n\tmov.b\t%s0,%t0\n\trotxr.w\t%T0\n\tand.b\t#0x80,%s0"; 3745 goto end; 3746 case SHIFT_LSHIFTRT: 3747 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.w\t%T0\n\tand.b\t#0x01,%t0"; 3748 goto end; 3749 case SHIFT_ASHIFTRT: 3750 info->special = "shal.b\t%s0\n\tmov.b\t%t0,%s0\n\trotxl.b\t%s0\n\tsubx\t%t0,%t0"; 3751 goto end; 3752 } 3753 } 3754 else if ((count >= 8 && count <= 13) 3755 || (TARGET_H8300S && count == 14)) 3756 { 3757 info->remainder = count - 8; 3758 3759 switch (shift_type) 3760 { 3761 case SHIFT_ASHIFT: 3762 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0"; 3763 goto end; 3764 case SHIFT_LSHIFTRT: 3765 info->special = "mov.b\t%t0,%s0\n\textu.w\t%T0"; 3766 info->cc_special = OLD_CC_SET_ZNV; 3767 goto end; 3768 case SHIFT_ASHIFTRT: 3769 info->special = "mov.b\t%t0,%s0\n\texts.w\t%T0"; 3770 info->cc_special = OLD_CC_SET_ZNV; 3771 goto end; 3772 } 3773 } 3774 else if (count == 14) 3775 { 3776 switch (shift_type) 3777 { 3778 case SHIFT_ASHIFT: 3779 case SHIFT_LSHIFTRT: 3780 goto end; 3781 goto end; 3782 case SHIFT_ASHIFTRT: 3783 if (TARGET_H8300H) 3784 { 3785 info->special = "shll.b\t%t0\n\tsubx.b\t%s0,%s0\n\tshll.b\t%t0\n\trotxl.b\t%s0\n\texts.w\t%T0"; 3786 info->cc_special = OLD_CC_SET_ZNV; 3787 } 3788 else /* TARGET_H8300S */ 3789 gcc_unreachable (); 3790 goto end; 3791 } 3792 } 3793 else if (count == 15) 3794 { 3795 switch (shift_type) 3796 { 3797 case SHIFT_ASHIFT: 3798 info->special = "bld\t#0,%s0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#7,%t0"; 3799 goto end; 3800 case SHIFT_LSHIFTRT: 3801 info->special = "bld\t#7,%t0\n\txor\t%s0,%s0\n\txor\t%t0,%t0\n\tbst\t#0,%s0"; 3802 goto end; 3803 case SHIFT_ASHIFTRT: 3804 info->special = "shll\t%t0\n\tsubx\t%t0,%t0\n\tmov.b\t%t0,%s0"; 3805 goto end; 3806 } 3807 } 3808 gcc_unreachable (); 3809 3810 case SIshift: 3811 if (count == 8) 3812 { 3813 switch (shift_type) 3814 { 3815 case SHIFT_ASHIFT: 3816 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%s3,%t3\n\tmov.b\t%t0,%s3\n\tmov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f3,%e0"; 3817 goto end; 3818 case SHIFT_LSHIFTRT: 3819 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\textu.w\t%f3\n\tmov.w\t%f3,%e0"; 3820 goto end; 3821 case SHIFT_ASHIFTRT: 3822 info->special = "mov.w\t%e0,%f3\n\tmov.b\t%t0,%s0\n\tmov.b\t%s3,%t0\n\tmov.b\t%t3,%s3\n\texts.w\t%f3\n\tmov.w\t%f3,%e0"; 3823 goto end; 3824 } 3825 } 3826 else if (count == 15) 3827 { 3828 /* The basic idea here is to use the shift-by-16 idiom to make things 3829 small and efficient. Of course, that loses one bit that we need, 3830 so we stuff the bit into C, shift by 16, then rotate the bit 3831 back in. */ 3832 switch (shift_type) 3833 { 3834 case SHIFT_ASHIFT: 3835 info->special = "shlr.w\t%e0\n\tmov.w\t%f0,%e0\n\txor.w\t%f0,%f0\n\trotxr.l\t%S0"; 3836 info->cc_special = OLD_CC_SET_ZNV; 3837 goto end; 3838 case SHIFT_LSHIFTRT: 3839 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\txor.w\t%e0,%e0\n\trotxl.l\t%S0"; 3840 info->cc_special = OLD_CC_SET_ZNV; 3841 goto end; 3842 case SHIFT_ASHIFTRT: 3843 info->special = "shll.w\t%f0\n\tmov.w\t%e0,%f0\n\texts.l\t%S0\n\trotxl.l\t%S0"; 3844 info->cc_special = OLD_CC_SET_ZNV; 3845 goto end; 3846 } 3847 } 3848 else if (count >= 16 && count <= 23) 3849 { 3850 info->remainder = count - 16; 3851 3852 switch (shift_type) 3853 { 3854 case SHIFT_ASHIFT: 3855 info->special = "mov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 3856 goto end; 3857 case SHIFT_LSHIFTRT: 3858 info->special = "mov.w\t%e0,%f0\n\textu.l\t%S0"; 3859 info->cc_special = OLD_CC_SET_ZNV; 3860 goto end; 3861 case SHIFT_ASHIFTRT: 3862 info->special = "mov.w\t%e0,%f0\n\texts.l\t%S0"; 3863 info->cc_special = OLD_CC_SET_ZNV; 3864 goto end; 3865 } 3866 } 3867 else if (TARGET_H8300S && count == 27) 3868 { 3869 switch (shift_type) 3870 { 3871 case SHIFT_ASHIFT: 3872 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3873 goto end; 3874 case SHIFT_LSHIFTRT: 3875 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3876 goto end; 3877 case SHIFT_ASHIFTRT: 3878 info->remainder = count - 24; 3879 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3880 info->cc_special = OLD_CC_SET_ZNV; 3881 goto end; 3882 } 3883 } 3884 else if (count >= 24 && count <= 27) 3885 { 3886 info->remainder = count - 24; 3887 3888 switch (shift_type) 3889 { 3890 case SHIFT_ASHIFT: 3891 info->special = "mov.b\t%s0,%t0\n\tsub.b\t%s0,%s0\n\tmov.w\t%f0,%e0\n\tsub.w\t%f0,%f0"; 3892 goto end; 3893 case SHIFT_LSHIFTRT: 3894 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\textu.w\t%f0\n\textu.l\t%S0"; 3895 info->cc_special = OLD_CC_SET_ZNV; 3896 goto end; 3897 case SHIFT_ASHIFTRT: 3898 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3899 info->cc_special = OLD_CC_SET_ZNV; 3900 goto end; 3901 } 3902 } 3903 else if (count == 28) 3904 { 3905 switch (shift_type) 3906 { 3907 case SHIFT_ASHIFT: 3908 if (TARGET_H8300H) 3909 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3910 else 3911 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 3912 goto end; 3913 case SHIFT_LSHIFTRT: 3914 if (TARGET_H8300H) 3915 { 3916 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3917 info->cc_special = OLD_CC_SET_ZNV; 3918 } 3919 else 3920 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 3921 goto end; 3922 case SHIFT_ASHIFTRT: 3923 info->remainder = count - 24; 3924 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3925 info->cc_special = OLD_CC_SET_ZNV; 3926 goto end; 3927 } 3928 } 3929 else if (count == 29) 3930 { 3931 switch (shift_type) 3932 { 3933 case SHIFT_ASHIFT: 3934 if (TARGET_H8300H) 3935 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3936 else 3937 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3938 goto end; 3939 case SHIFT_LSHIFTRT: 3940 if (TARGET_H8300H) 3941 { 3942 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3943 info->cc_special = OLD_CC_SET_ZNV; 3944 } 3945 else 3946 { 3947 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3948 info->cc_special = OLD_CC_SET_ZNV; 3949 } 3950 goto end; 3951 case SHIFT_ASHIFTRT: 3952 info->remainder = count - 24; 3953 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3954 info->cc_special = OLD_CC_SET_ZNV; 3955 goto end; 3956 } 3957 } 3958 else if (count == 30) 3959 { 3960 switch (shift_type) 3961 { 3962 case SHIFT_ASHIFT: 3963 if (TARGET_H8300H) 3964 info->special = "sub.w\t%e0,%e0\n\trotr.l\t%S0\n\trotr.l\t%S0\n\tsub.w\t%f0,%f0"; 3965 else 3966 info->special = "sub.w\t%e0,%e0\n\trotr.l\t#2,%S0\n\tsub.w\t%f0,%f0"; 3967 goto end; 3968 case SHIFT_LSHIFTRT: 3969 if (TARGET_H8300H) 3970 info->special = "sub.w\t%f0,%f0\n\trotl.l\t%S0\n\trotl.l\t%S0\n\textu.l\t%S0"; 3971 else 3972 info->special = "sub.w\t%f0,%f0\n\trotl.l\t#2,%S0\n\textu.l\t%S0"; 3973 goto end; 3974 case SHIFT_ASHIFTRT: 3975 info->remainder = count - 24; 3976 info->special = "mov.w\t%e0,%f0\n\tmov.b\t%t0,%s0\n\texts.w\t%f0\n\texts.l\t%S0"; 3977 info->cc_special = OLD_CC_SET_ZNV; 3978 goto end; 3979 } 3980 } 3981 else if (count == 31) 3982 { 3983 switch (shift_type) 3984 { 3985 case SHIFT_ASHIFT: 3986 info->special = "shlr.l\t%S0\n\txor.l\t%S0,%S0\n\trotxr.l\t%S0"; 3987 info->cc_special = OLD_CC_SET_ZNV; 3988 goto end; 3989 case SHIFT_LSHIFTRT: 3990 info->special = "shll.l\t%S0\n\txor.l\t%S0,%S0\n\trotxl.l\t%S0"; 3991 info->cc_special = OLD_CC_SET_ZNV; 3992 goto end; 3993 case SHIFT_ASHIFTRT: 3994 info->special = "shll\t%e0\n\tsubx\t%w0,%w0\n\texts.w\t%T0\n\texts.l\t%S0"; 3995 info->cc_special = OLD_CC_SET_ZNV; 3996 goto end; 3997 } 3998 } 3999 gcc_unreachable (); 4000 4001 default: 4002 gcc_unreachable (); 4003 } 4004 4005 end: 4006 if (!TARGET_H8300S) 4007 info->shift2 = NULL; 4008 } 4009 4010 /* Given COUNT and MODE of a shift, return 1 if a scratch reg may be 4011 needed for some shift with COUNT and MODE. Return 0 otherwise. */ 4012 4013 int 4014 h8300_shift_needs_scratch_p (int count, machine_mode mode, enum rtx_code type) 4015 { 4016 enum h8_cpu cpu; 4017 int a, lr, ar; 4018 4019 if (GET_MODE_BITSIZE (mode) <= count) 4020 return 1; 4021 4022 /* Find out the target CPU. */ 4023 if (TARGET_H8300S) 4024 cpu = H8_S; 4025 else 4026 cpu = H8_300H; 4027 4028 /* Find the shift algorithm. */ 4029 switch (mode) 4030 { 4031 case E_QImode: 4032 a = shift_alg_qi[cpu][SHIFT_ASHIFT][count]; 4033 lr = shift_alg_qi[cpu][SHIFT_LSHIFTRT][count]; 4034 ar = shift_alg_qi[cpu][SHIFT_ASHIFTRT][count]; 4035 break; 4036 4037 case E_HImode: 4038 a = shift_alg_hi[cpu][SHIFT_ASHIFT][count]; 4039 lr = shift_alg_hi[cpu][SHIFT_LSHIFTRT][count]; 4040 ar = shift_alg_hi[cpu][SHIFT_ASHIFTRT][count]; 4041 break; 4042 4043 case E_SImode: 4044 a = shift_alg_si[cpu][SHIFT_ASHIFT][count]; 4045 lr = shift_alg_si[cpu][SHIFT_LSHIFTRT][count]; 4046 ar = shift_alg_si[cpu][SHIFT_ASHIFTRT][count]; 4047 break; 4048 4049 default: 4050 gcc_unreachable (); 4051 } 4052 4053 /* On H8/300H, count == 8 uses a scratch register. */ 4054 if (type == CLOBBER) 4055 return (a == SHIFT_LOOP || lr == SHIFT_LOOP || ar == SHIFT_LOOP 4056 || (TARGET_H8300H && mode == SImode && count == 8)); 4057 else if (type == ASHIFT) 4058 return (a == SHIFT_LOOP 4059 || (TARGET_H8300H && mode == SImode && count == 8)); 4060 else if (type == LSHIFTRT) 4061 return (lr == SHIFT_LOOP 4062 || (TARGET_H8300H && mode == SImode && count == 8)); 4063 else if (type == ASHIFTRT) 4064 return (ar == SHIFT_LOOP 4065 || (TARGET_H8300H && mode == SImode && count == 8)); 4066 gcc_unreachable (); 4067 } 4068 4069 /* Output the assembler code for doing shifts. */ 4070 4071 const char * 4072 output_a_shift (rtx operands[4], rtx_code code) 4073 { 4074 static int loopend_lab; 4075 machine_mode mode = GET_MODE (operands[0]); 4076 enum shift_type shift_type; 4077 enum shift_mode shift_mode; 4078 struct shift_info info; 4079 int n; 4080 4081 loopend_lab++; 4082 4083 switch (mode) 4084 { 4085 case E_QImode: 4086 shift_mode = QIshift; 4087 break; 4088 case E_HImode: 4089 shift_mode = HIshift; 4090 break; 4091 case E_SImode: 4092 shift_mode = SIshift; 4093 break; 4094 default: 4095 gcc_unreachable (); 4096 } 4097 4098 switch (code) 4099 { 4100 case ASHIFTRT: 4101 shift_type = SHIFT_ASHIFTRT; 4102 break; 4103 case LSHIFTRT: 4104 shift_type = SHIFT_LSHIFTRT; 4105 break; 4106 case ASHIFT: 4107 shift_type = SHIFT_ASHIFT; 4108 break; 4109 default: 4110 gcc_unreachable (); 4111 } 4112 4113 /* This case must be taken care of by one of the two splitters 4114 that convert a variable shift into a loop. */ 4115 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4116 4117 n = INTVAL (operands[2]); 4118 4119 /* If the count is negative, make it 0. */ 4120 if (n < 0) 4121 n = 0; 4122 /* If the count is too big, truncate it. 4123 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4124 do the intuitive thing. */ 4125 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4126 n = GET_MODE_BITSIZE (mode); 4127 4128 get_shift_alg (shift_type, shift_mode, n, &info); 4129 4130 switch (info.alg) 4131 { 4132 case SHIFT_SPECIAL: 4133 output_asm_insn (info.special, operands); 4134 /* Fall through. */ 4135 4136 case SHIFT_INLINE: 4137 n = info.remainder; 4138 4139 /* Emit two bit shifts first. */ 4140 if (info.shift2 != NULL) 4141 { 4142 for (; n > 1; n -= 2) 4143 output_asm_insn (info.shift2, operands); 4144 } 4145 4146 /* Now emit one bit shifts for any residual. */ 4147 for (; n > 0; n--) 4148 output_asm_insn (info.shift1, operands); 4149 return ""; 4150 4151 case SHIFT_ROT_AND: 4152 { 4153 int m = GET_MODE_BITSIZE (mode) - n; 4154 const int mask = (shift_type == SHIFT_ASHIFT 4155 ? ((1 << m) - 1) << n 4156 : (1 << m) - 1); 4157 char insn_buf[200]; 4158 4159 /* Not all possibilities of rotate are supported. They shouldn't 4160 be generated, but let's watch for 'em. */ 4161 gcc_assert (info.shift1); 4162 4163 /* Emit two bit rotates first. */ 4164 if (info.shift2 != NULL) 4165 { 4166 for (; m > 1; m -= 2) 4167 output_asm_insn (info.shift2, operands); 4168 } 4169 4170 /* Now single bit rotates for any residual. */ 4171 for (; m > 0; m--) 4172 output_asm_insn (info.shift1, operands); 4173 4174 /* Now mask off the high bits. */ 4175 switch (mode) 4176 { 4177 case E_QImode: 4178 sprintf (insn_buf, "and\t#%d,%%X0", mask); 4179 break; 4180 4181 case E_HImode: 4182 sprintf (insn_buf, "and.w\t#%d,%%T0", mask); 4183 break; 4184 4185 default: 4186 gcc_unreachable (); 4187 } 4188 4189 output_asm_insn (insn_buf, operands); 4190 return ""; 4191 } 4192 4193 case SHIFT_LOOP: 4194 /* A loop to shift by a "large" constant value. 4195 If we have shift-by-2 insns, use them. */ 4196 if (info.shift2 != NULL) 4197 { 4198 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n / 2, 4199 names_big[REGNO (operands[3])]); 4200 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4201 output_asm_insn (info.shift2, operands); 4202 output_asm_insn ("add #0xff,%X3", operands); 4203 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4204 if (n % 2) 4205 output_asm_insn (info.shift1, operands); 4206 } 4207 else 4208 { 4209 fprintf (asm_out_file, "\tmov.b #%d,%sl\n", n, 4210 names_big[REGNO (operands[3])]); 4211 fprintf (asm_out_file, ".Llt%d:\n", loopend_lab); 4212 output_asm_insn (info.shift1, operands); 4213 output_asm_insn ("add #0xff,%X3", operands); 4214 fprintf (asm_out_file, "\tbne .Llt%d\n", loopend_lab); 4215 } 4216 return ""; 4217 4218 default: 4219 gcc_unreachable (); 4220 } 4221 } 4222 4223 /* Count the number of assembly instructions in a string TEMPL. */ 4224 4225 static unsigned int 4226 h8300_asm_insn_count (const char *templ) 4227 { 4228 unsigned int count = 1; 4229 4230 for (; *templ; templ++) 4231 if (*templ == '\n') 4232 count++; 4233 4234 return count; 4235 } 4236 4237 /* Compute the length of a shift insn. */ 4238 4239 unsigned int 4240 compute_a_shift_length (rtx operands[3], rtx_code code) 4241 { 4242 enum machine_mode mode = GET_MODE (operands[0]); 4243 enum shift_type shift_type; 4244 enum shift_mode shift_mode; 4245 struct shift_info info; 4246 unsigned int wlength = 0; 4247 4248 switch (mode) 4249 { 4250 case E_QImode: 4251 shift_mode = QIshift; 4252 break; 4253 case E_HImode: 4254 shift_mode = HIshift; 4255 break; 4256 case E_SImode: 4257 shift_mode = SIshift; 4258 break; 4259 default: 4260 gcc_unreachable (); 4261 } 4262 4263 switch (code) 4264 { 4265 case ASHIFTRT: 4266 shift_type = SHIFT_ASHIFTRT; 4267 break; 4268 case LSHIFTRT: 4269 shift_type = SHIFT_LSHIFTRT; 4270 break; 4271 case ASHIFT: 4272 shift_type = SHIFT_ASHIFT; 4273 break; 4274 default: 4275 gcc_unreachable (); 4276 } 4277 4278 if (GET_CODE (operands[2]) != CONST_INT) 4279 { 4280 /* Get the assembler code to do one shift. */ 4281 get_shift_alg (shift_type, shift_mode, 1, &info); 4282 4283 return (4 + h8300_asm_insn_count (info.shift1)) * 2; 4284 } 4285 else 4286 { 4287 int n = INTVAL (operands[2]); 4288 4289 /* If the count is negative, make it 0. */ 4290 if (n < 0) 4291 n = 0; 4292 /* If the count is too big, truncate it. 4293 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4294 do the intuitive thing. */ 4295 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4296 n = GET_MODE_BITSIZE (mode); 4297 4298 get_shift_alg (shift_type, shift_mode, n, &info); 4299 4300 switch (info.alg) 4301 { 4302 case SHIFT_SPECIAL: 4303 wlength += h8300_asm_insn_count (info.special); 4304 4305 /* Every assembly instruction used in SHIFT_SPECIAL case 4306 takes 2 bytes except xor.l, which takes 4 bytes, so if we 4307 see xor.l, we just pretend that xor.l counts as two insns 4308 so that the insn length will be computed correctly. */ 4309 if (strstr (info.special, "xor.l") != NULL) 4310 wlength++; 4311 4312 /* Fall through. */ 4313 4314 case SHIFT_INLINE: 4315 n = info.remainder; 4316 4317 if (info.shift2 != NULL) 4318 { 4319 wlength += h8300_asm_insn_count (info.shift2) * (n / 2); 4320 n = n % 2; 4321 } 4322 4323 wlength += h8300_asm_insn_count (info.shift1) * n; 4324 4325 return 2 * wlength; 4326 4327 case SHIFT_ROT_AND: 4328 { 4329 int m = GET_MODE_BITSIZE (mode) - n; 4330 4331 /* Not all possibilities of rotate are supported. They shouldn't 4332 be generated, but let's watch for 'em. */ 4333 gcc_assert (info.shift1); 4334 4335 if (info.shift2 != NULL) 4336 { 4337 wlength += h8300_asm_insn_count (info.shift2) * (m / 2); 4338 m = m % 2; 4339 } 4340 4341 wlength += h8300_asm_insn_count (info.shift1) * m; 4342 4343 /* Now mask off the high bits. */ 4344 switch (mode) 4345 { 4346 case E_QImode: 4347 wlength += 1; 4348 break; 4349 case E_HImode: 4350 wlength += 2; 4351 break; 4352 case E_SImode: 4353 wlength += 3; 4354 break; 4355 default: 4356 gcc_unreachable (); 4357 } 4358 return 2 * wlength; 4359 } 4360 4361 case SHIFT_LOOP: 4362 /* A loop to shift by a "large" constant value. 4363 If we have shift-by-2 insns, use them. */ 4364 if (info.shift2 != NULL) 4365 { 4366 wlength += 3 + h8300_asm_insn_count (info.shift2); 4367 if (n % 2) 4368 wlength += h8300_asm_insn_count (info.shift1); 4369 } 4370 else 4371 { 4372 wlength += 3 + h8300_asm_insn_count (info.shift1); 4373 } 4374 return 2 * wlength; 4375 4376 default: 4377 gcc_unreachable (); 4378 } 4379 } 4380 } 4381 4382 /* Compute which flag bits are valid after a shift insn. */ 4383 4384 int 4385 compute_a_shift_cc (rtx operands[3], rtx_code code) 4386 { 4387 machine_mode mode = GET_MODE (operands[0]); 4388 enum shift_type shift_type; 4389 enum shift_mode shift_mode; 4390 struct shift_info info; 4391 int n; 4392 4393 switch (mode) 4394 { 4395 case E_QImode: 4396 shift_mode = QIshift; 4397 break; 4398 case E_HImode: 4399 shift_mode = HIshift; 4400 break; 4401 case E_SImode: 4402 shift_mode = SIshift; 4403 break; 4404 default: 4405 gcc_unreachable (); 4406 } 4407 4408 switch (code) 4409 { 4410 case ASHIFTRT: 4411 shift_type = SHIFT_ASHIFTRT; 4412 break; 4413 case LSHIFTRT: 4414 shift_type = SHIFT_LSHIFTRT; 4415 break; 4416 case ASHIFT: 4417 shift_type = SHIFT_ASHIFT; 4418 break; 4419 default: 4420 gcc_unreachable (); 4421 } 4422 4423 /* This case must be taken care of by one of the two splitters 4424 that convert a variable shift into a loop. */ 4425 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 4426 4427 n = INTVAL (operands[2]); 4428 4429 /* If the count is negative, make it 0. */ 4430 if (n < 0) 4431 n = 0; 4432 /* If the count is too big, truncate it. 4433 ANSI says shifts of GET_MODE_BITSIZE are undefined - we choose to 4434 do the intuitive thing. */ 4435 else if ((unsigned int) n > GET_MODE_BITSIZE (mode)) 4436 n = GET_MODE_BITSIZE (mode); 4437 4438 get_shift_alg (shift_type, shift_mode, n, &info); 4439 4440 switch (info.alg) 4441 { 4442 case SHIFT_SPECIAL: 4443 if (info.remainder == 0) 4444 return (info.cc_special == OLD_CC_SET_ZN 4445 || info.cc_special == OLD_CC_SET_ZNV); 4446 4447 /* Fall through. */ 4448 4449 case SHIFT_INLINE: 4450 return (info.cc_inline == OLD_CC_SET_ZN 4451 || info.cc_inline == OLD_CC_SET_ZNV); 4452 4453 case SHIFT_ROT_AND: 4454 /* This case always ends with an and instruction. */ 4455 return true; 4456 4457 case SHIFT_LOOP: 4458 /* A loop to shift by a "large" constant value. 4459 If we have shift-by-2 insns, use them. */ 4460 if (info.shift2 != NULL) 4461 { 4462 if (n % 2) 4463 return (info.cc_inline == OLD_CC_SET_ZN 4464 || info.cc_inline == OLD_CC_SET_ZNV); 4465 4466 } 4467 return false; 4468 4469 default: 4470 gcc_unreachable (); 4471 } 4472 } 4473 4474 /* A rotation by a non-constant will cause a loop to be generated, in 4476 which a rotation by one bit is used. A rotation by a constant, 4477 including the one in the loop, will be taken care of by 4478 output_a_rotate () at the insn emit time. */ 4479 4480 int 4481 expand_a_rotate (rtx operands[]) 4482 { 4483 rtx dst = operands[0]; 4484 rtx src = operands[1]; 4485 rtx rotate_amount = operands[2]; 4486 machine_mode mode = GET_MODE (dst); 4487 4488 if (h8sx_classify_shift (mode, ROTATE, rotate_amount) == H8SX_SHIFT_UNARY) 4489 return false; 4490 4491 /* We rotate in place. */ 4492 emit_move_insn (dst, src); 4493 4494 if (GET_CODE (rotate_amount) != CONST_INT) 4495 { 4496 rtx counter = gen_reg_rtx (QImode); 4497 rtx_code_label *start_label = gen_label_rtx (); 4498 rtx_code_label *end_label = gen_label_rtx (); 4499 4500 /* If the rotate amount is less than or equal to 0, 4501 we go out of the loop. */ 4502 emit_cmp_and_jump_insns (rotate_amount, const0_rtx, LE, NULL_RTX, 4503 QImode, 0, end_label); 4504 4505 /* Initialize the loop counter. */ 4506 emit_move_insn (counter, rotate_amount); 4507 4508 emit_label (start_label); 4509 4510 /* Rotate by one bit. */ 4511 switch (mode) 4512 { 4513 case E_QImode: 4514 emit_insn (gen_rotlqi3_1 (dst, dst, const1_rtx)); 4515 break; 4516 case E_HImode: 4517 emit_insn (gen_rotlhi3_1 (dst, dst, const1_rtx)); 4518 break; 4519 case E_SImode: 4520 emit_insn (gen_rotlsi3_1 (dst, dst, const1_rtx)); 4521 break; 4522 default: 4523 gcc_unreachable (); 4524 } 4525 4526 /* Decrement the counter by 1. */ 4527 emit_insn (gen_addqi3 (counter, counter, constm1_rtx)); 4528 4529 /* If the loop counter is nonzero, we go back to the beginning 4530 of the loop. */ 4531 emit_cmp_and_jump_insns (counter, const0_rtx, NE, NULL_RTX, QImode, 1, 4532 start_label); 4533 4534 emit_label (end_label); 4535 } 4536 else 4537 { 4538 /* Rotate by AMOUNT bits. */ 4539 switch (mode) 4540 { 4541 case E_QImode: 4542 emit_insn (gen_rotlqi3_1 (dst, dst, rotate_amount)); 4543 break; 4544 case E_HImode: 4545 emit_insn (gen_rotlhi3_1 (dst, dst, rotate_amount)); 4546 break; 4547 case E_SImode: 4548 emit_insn (gen_rotlsi3_1 (dst, dst, rotate_amount)); 4549 break; 4550 default: 4551 gcc_unreachable (); 4552 } 4553 } 4554 4555 return 1; 4556 } 4557 4558 /* Output a rotate insn. */ 4559 4560 const char * 4561 output_a_rotate (enum rtx_code code, rtx *operands) 4562 { 4563 rtx dst = operands[0]; 4564 rtx rotate_amount = operands[2]; 4565 enum shift_mode rotate_mode; 4566 enum shift_type rotate_type; 4567 const char *insn_buf; 4568 int bits; 4569 int amount; 4570 machine_mode mode = GET_MODE (dst); 4571 4572 gcc_assert (GET_CODE (rotate_amount) == CONST_INT); 4573 4574 switch (mode) 4575 { 4576 case E_QImode: 4577 rotate_mode = QIshift; 4578 break; 4579 case E_HImode: 4580 rotate_mode = HIshift; 4581 break; 4582 case E_SImode: 4583 rotate_mode = SIshift; 4584 break; 4585 default: 4586 gcc_unreachable (); 4587 } 4588 4589 switch (code) 4590 { 4591 case ROTATERT: 4592 rotate_type = SHIFT_ASHIFT; 4593 break; 4594 case ROTATE: 4595 rotate_type = SHIFT_LSHIFTRT; 4596 break; 4597 default: 4598 gcc_unreachable (); 4599 } 4600 4601 amount = INTVAL (rotate_amount); 4602 4603 /* Clean up AMOUNT. */ 4604 if (amount < 0) 4605 amount = 0; 4606 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 4607 amount = GET_MODE_BITSIZE (mode); 4608 4609 /* Determine the faster direction. After this phase, amount will be 4610 at most a half of GET_MODE_BITSIZE (mode). */ 4611 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 4612 { 4613 /* Flip the direction. */ 4614 amount = GET_MODE_BITSIZE (mode) - amount; 4615 rotate_type = 4616 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 4617 } 4618 4619 /* See if a byte swap (in HImode) or a word swap (in SImode) can 4620 boost up the rotation. */ 4621 if ((mode == HImode && TARGET_H8300H && amount >= 6) 4622 || (mode == HImode && TARGET_H8300S && amount == 8) 4623 || (mode == SImode && TARGET_H8300H && amount >= 10) 4624 || (mode == SImode && TARGET_H8300S && amount >= 13)) 4625 { 4626 switch (mode) 4627 { 4628 case E_HImode: 4629 /* This code works on any family. */ 4630 insn_buf = "xor.b\t%s0,%t0\n\txor.b\t%t0,%s0\n\txor.b\t%s0,%t0"; 4631 output_asm_insn (insn_buf, operands); 4632 break; 4633 4634 case E_SImode: 4635 /* This code works on the H8/300H and H8S. */ 4636 insn_buf = "xor.w\t%e0,%f0\n\txor.w\t%f0,%e0\n\txor.w\t%e0,%f0"; 4637 output_asm_insn (insn_buf, operands); 4638 break; 4639 4640 default: 4641 gcc_unreachable (); 4642 } 4643 4644 /* Adjust AMOUNT and flip the direction. */ 4645 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 4646 rotate_type = 4647 (rotate_type == SHIFT_ASHIFT) ? SHIFT_LSHIFTRT : SHIFT_ASHIFT; 4648 } 4649 4650 /* Output rotate insns. */ 4651 for (bits = TARGET_H8300S ? 2 : 1; bits > 0; bits /= 2) 4652 { 4653 if (bits == 2) 4654 insn_buf = rotate_two[rotate_type][rotate_mode]; 4655 else 4656 insn_buf = rotate_one[cpu_type][rotate_type][rotate_mode]; 4657 4658 for (; amount >= bits; amount -= bits) 4659 output_asm_insn (insn_buf, operands); 4660 } 4661 4662 return ""; 4663 } 4664 4665 /* Compute the length of a rotate insn. */ 4666 4667 unsigned int 4668 compute_a_rotate_length (rtx *operands) 4669 { 4670 rtx src = operands[1]; 4671 rtx amount_rtx = operands[2]; 4672 machine_mode mode = GET_MODE (src); 4673 int amount; 4674 unsigned int length = 0; 4675 4676 gcc_assert (GET_CODE (amount_rtx) == CONST_INT); 4677 4678 amount = INTVAL (amount_rtx); 4679 4680 /* Clean up AMOUNT. */ 4681 if (amount < 0) 4682 amount = 0; 4683 if ((unsigned int) amount > GET_MODE_BITSIZE (mode)) 4684 amount = GET_MODE_BITSIZE (mode); 4685 4686 /* Determine the faster direction. After this phase, amount 4687 will be at most a half of GET_MODE_BITSIZE (mode). */ 4688 if ((unsigned int) amount > GET_MODE_BITSIZE (mode) / (unsigned) 2) 4689 /* Flip the direction. */ 4690 amount = GET_MODE_BITSIZE (mode) - amount; 4691 4692 /* See if a byte swap (in HImode) or a word swap (in SImode) can 4693 boost up the rotation. */ 4694 if ((mode == HImode && TARGET_H8300H && amount >= 6) 4695 || (mode == HImode && TARGET_H8300S && amount == 8) 4696 || (mode == SImode && TARGET_H8300H && amount >= 10) 4697 || (mode == SImode && TARGET_H8300S && amount >= 13)) 4698 { 4699 /* Adjust AMOUNT and flip the direction. */ 4700 amount = GET_MODE_BITSIZE (mode) / 2 - amount; 4701 length += 6; 4702 } 4703 4704 /* We use 2-bit rotations on the H8S. */ 4705 if (TARGET_H8300S) 4706 amount = amount / 2 + amount % 2; 4707 4708 /* The H8/300 uses three insns to rotate one bit, taking 6 4709 length. */ 4710 length += amount * 2; 4711 4712 return length; 4713 } 4714 4715 /* Fix the operands of a gen_xxx so that it could become a bit 4717 operating insn. */ 4718 4719 int 4720 fix_bit_operand (rtx *operands, enum rtx_code code) 4721 { 4722 /* The bit_operand predicate accepts any memory during RTL generation, but 4723 only 'U' memory afterwards, so if this is a MEM operand, we must force 4724 it to be valid for 'U' by reloading the address. */ 4725 4726 if (code == AND 4727 ? single_zero_operand (operands[2], QImode) 4728 : single_one_operand (operands[2], QImode)) 4729 { 4730 /* OK to have a memory dest. */ 4731 if (GET_CODE (operands[0]) == MEM 4732 && !satisfies_constraint_U (operands[0])) 4733 { 4734 rtx mem = gen_rtx_MEM (GET_MODE (operands[0]), 4735 copy_to_mode_reg (Pmode, 4736 XEXP (operands[0], 0))); 4737 MEM_COPY_ATTRIBUTES (mem, operands[0]); 4738 operands[0] = mem; 4739 } 4740 4741 if (GET_CODE (operands[1]) == MEM 4742 && !satisfies_constraint_U (operands[1])) 4743 { 4744 rtx mem = gen_rtx_MEM (GET_MODE (operands[1]), 4745 copy_to_mode_reg (Pmode, 4746 XEXP (operands[1], 0))); 4747 MEM_COPY_ATTRIBUTES (mem, operands[0]); 4748 operands[1] = mem; 4749 } 4750 return 0; 4751 } 4752 4753 /* Dest and src op must be register. */ 4754 4755 operands[1] = force_reg (QImode, operands[1]); 4756 { 4757 rtx res = gen_reg_rtx (QImode); 4758 switch (code) 4759 { 4760 case AND: 4761 emit_insn (gen_andqi3_1 (res, operands[1], operands[2])); 4762 break; 4763 case IOR: 4764 emit_insn (gen_iorqi3_1 (res, operands[1], operands[2])); 4765 break; 4766 case XOR: 4767 emit_insn (gen_xorqi3_1 (res, operands[1], operands[2])); 4768 break; 4769 default: 4770 gcc_unreachable (); 4771 } 4772 emit_insn (gen_movqi (operands[0], res)); 4773 } 4774 return 1; 4775 } 4776 4777 /* Return nonzero if FUNC is an interrupt function as specified 4778 by the "interrupt" attribute. */ 4779 4780 static int 4781 h8300_interrupt_function_p (tree func) 4782 { 4783 tree a; 4784 4785 if (TREE_CODE (func) != FUNCTION_DECL) 4786 return 0; 4787 4788 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); 4789 return a != NULL_TREE; 4790 } 4791 4792 /* Return nonzero if FUNC is a saveall function as specified by the 4793 "saveall" attribute. */ 4794 4795 static int 4796 h8300_saveall_function_p (tree func) 4797 { 4798 tree a; 4799 4800 if (TREE_CODE (func) != FUNCTION_DECL) 4801 return 0; 4802 4803 a = lookup_attribute ("saveall", DECL_ATTRIBUTES (func)); 4804 return a != NULL_TREE; 4805 } 4806 4807 /* Return nonzero if FUNC is an OS_Task function as specified 4808 by the "OS_Task" attribute. */ 4809 4810 static int 4811 h8300_os_task_function_p (tree func) 4812 { 4813 tree a; 4814 4815 if (TREE_CODE (func) != FUNCTION_DECL) 4816 return 0; 4817 4818 a = lookup_attribute ("OS_Task", DECL_ATTRIBUTES (func)); 4819 return a != NULL_TREE; 4820 } 4821 4822 /* Return nonzero if FUNC is a monitor function as specified 4823 by the "monitor" attribute. */ 4824 4825 static int 4826 h8300_monitor_function_p (tree func) 4827 { 4828 tree a; 4829 4830 if (TREE_CODE (func) != FUNCTION_DECL) 4831 return 0; 4832 4833 a = lookup_attribute ("monitor", DECL_ATTRIBUTES (func)); 4834 return a != NULL_TREE; 4835 } 4836 4837 /* Return nonzero if FUNC is a function that should be called 4838 through the function vector. */ 4839 4840 int 4841 h8300_funcvec_function_p (tree func) 4842 { 4843 tree a; 4844 4845 if (TREE_CODE (func) != FUNCTION_DECL) 4846 return 0; 4847 4848 a = lookup_attribute ("function_vector", DECL_ATTRIBUTES (func)); 4849 return a != NULL_TREE; 4850 } 4851 4852 /* Return nonzero if DECL is a variable that's in the eight bit 4853 data area. */ 4854 4855 int 4856 h8300_eightbit_data_p (tree decl) 4857 { 4858 tree a; 4859 4860 if (TREE_CODE (decl) != VAR_DECL) 4861 return 0; 4862 4863 a = lookup_attribute ("eightbit_data", DECL_ATTRIBUTES (decl)); 4864 return a != NULL_TREE; 4865 } 4866 4867 /* Return nonzero if DECL is a variable that's in the tiny 4868 data area. */ 4869 4870 int 4871 h8300_tiny_data_p (tree decl) 4872 { 4873 tree a; 4874 4875 if (TREE_CODE (decl) != VAR_DECL) 4876 return 0; 4877 4878 a = lookup_attribute ("tiny_data", DECL_ATTRIBUTES (decl)); 4879 return a != NULL_TREE; 4880 } 4881 4882 /* Generate an 'interrupt_handler' attribute for decls. We convert 4883 all the pragmas to corresponding attributes. */ 4884 4885 static void 4886 h8300_insert_attributes (tree node, tree *attributes) 4887 { 4888 if (TREE_CODE (node) == FUNCTION_DECL) 4889 { 4890 if (pragma_interrupt) 4891 { 4892 pragma_interrupt = 0; 4893 4894 /* Add an 'interrupt_handler' attribute. */ 4895 *attributes = tree_cons (get_identifier ("interrupt_handler"), 4896 NULL, *attributes); 4897 } 4898 4899 if (pragma_saveall) 4900 { 4901 pragma_saveall = 0; 4902 4903 /* Add an 'saveall' attribute. */ 4904 *attributes = tree_cons (get_identifier ("saveall"), 4905 NULL, *attributes); 4906 } 4907 } 4908 } 4909 4910 /* Supported attributes: 4911 4912 interrupt_handler: output a prologue and epilogue suitable for an 4913 interrupt handler. 4914 4915 saveall: output a prologue and epilogue that saves and restores 4916 all registers except the stack pointer. 4917 4918 function_vector: This function should be called through the 4919 function vector. 4920 4921 eightbit_data: This variable lives in the 8-bit data area and can 4922 be referenced with 8-bit absolute memory addresses. 4923 4924 tiny_data: This variable lives in the tiny data area and can be 4925 referenced with 16-bit absolute memory references. */ 4926 4927 static const struct attribute_spec h8300_attribute_table[] = 4928 { 4929 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, 4930 affects_type_identity, handler, exclude } */ 4931 { "interrupt_handler", 0, 0, true, false, false, false, 4932 h8300_handle_fndecl_attribute, NULL }, 4933 { "saveall", 0, 0, true, false, false, false, 4934 h8300_handle_fndecl_attribute, NULL }, 4935 { "OS_Task", 0, 0, true, false, false, false, 4936 h8300_handle_fndecl_attribute, NULL }, 4937 { "monitor", 0, 0, true, false, false, false, 4938 h8300_handle_fndecl_attribute, NULL }, 4939 { "function_vector", 0, 0, true, false, false, false, 4940 h8300_handle_fndecl_attribute, NULL }, 4941 { "eightbit_data", 0, 0, true, false, false, false, 4942 h8300_handle_eightbit_data_attribute, NULL }, 4943 { "tiny_data", 0, 0, true, false, false, false, 4944 h8300_handle_tiny_data_attribute, NULL }, 4945 { NULL, 0, 0, false, false, false, false, NULL, NULL } 4946 }; 4947 4948 4949 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in 4950 struct attribute_spec.handler. */ 4951 static tree 4952 h8300_handle_fndecl_attribute (tree *node, tree name, 4953 tree args ATTRIBUTE_UNUSED, 4954 int flags ATTRIBUTE_UNUSED, 4955 bool *no_add_attrs) 4956 { 4957 if (TREE_CODE (*node) != FUNCTION_DECL) 4958 { 4959 warning (OPT_Wattributes, "%qE attribute only applies to functions", 4960 name); 4961 *no_add_attrs = true; 4962 } 4963 4964 return NULL_TREE; 4965 } 4966 4967 /* Handle an "eightbit_data" attribute; arguments as in 4968 struct attribute_spec.handler. */ 4969 static tree 4970 h8300_handle_eightbit_data_attribute (tree *node, tree name, 4971 tree args ATTRIBUTE_UNUSED, 4972 int flags ATTRIBUTE_UNUSED, 4973 bool *no_add_attrs) 4974 { 4975 tree decl = *node; 4976 4977 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 4978 { 4979 set_decl_section_name (decl, ".eight"); 4980 } 4981 else 4982 { 4983 warning (OPT_Wattributes, "%qE attribute ignored", 4984 name); 4985 *no_add_attrs = true; 4986 } 4987 4988 return NULL_TREE; 4989 } 4990 4991 /* Handle an "tiny_data" attribute; arguments as in 4992 struct attribute_spec.handler. */ 4993 static tree 4994 h8300_handle_tiny_data_attribute (tree *node, tree name, 4995 tree args ATTRIBUTE_UNUSED, 4996 int flags ATTRIBUTE_UNUSED, 4997 bool *no_add_attrs) 4998 { 4999 tree decl = *node; 5000 5001 if (TREE_STATIC (decl) || DECL_EXTERNAL (decl)) 5002 { 5003 set_decl_section_name (decl, ".tiny"); 5004 } 5005 else 5006 { 5007 warning (OPT_Wattributes, "%qE attribute ignored", 5008 name); 5009 *no_add_attrs = true; 5010 } 5011 5012 return NULL_TREE; 5013 } 5014 5015 /* Mark function vectors, and various small data objects. */ 5016 5017 static void 5018 h8300_encode_section_info (tree decl, rtx rtl, int first) 5019 { 5020 int extra_flags = 0; 5021 5022 default_encode_section_info (decl, rtl, first); 5023 5024 if (TREE_CODE (decl) == FUNCTION_DECL 5025 && h8300_funcvec_function_p (decl)) 5026 extra_flags = SYMBOL_FLAG_FUNCVEC_FUNCTION; 5027 else if (TREE_CODE (decl) == VAR_DECL 5028 && (TREE_STATIC (decl) || DECL_EXTERNAL (decl))) 5029 { 5030 if (h8300_eightbit_data_p (decl)) 5031 extra_flags = SYMBOL_FLAG_EIGHTBIT_DATA; 5032 else if (first && h8300_tiny_data_p (decl)) 5033 extra_flags = SYMBOL_FLAG_TINY_DATA; 5034 } 5035 5036 if (extra_flags) 5037 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; 5038 } 5039 5040 /* Output a single-bit extraction. */ 5041 5042 const char * 5043 output_simode_bld (int bild, rtx operands[]) 5044 { 5045 /* Determine if we can clear the destination first. */ 5046 int clear_first = (REG_P (operands[0]) && REG_P (operands[1]) 5047 && REGNO (operands[0]) != REGNO (operands[1])); 5048 5049 if (clear_first) 5050 output_asm_insn ("sub.l\t%S0,%S0", operands); 5051 5052 /* Output the bit load or bit inverse load. */ 5053 if (bild) 5054 output_asm_insn ("bild\t%Z2,%Y1", operands); 5055 else 5056 output_asm_insn ("bld\t%Z2,%Y1", operands); 5057 5058 if (!clear_first) 5059 output_asm_insn ("xor.l\t%S0,%S0", operands); 5060 5061 /* Perform the bit store. */ 5062 output_asm_insn ("rotxl.l\t%S0", operands); 5063 5064 /* All done. */ 5065 return ""; 5066 } 5067 5068 /* Delayed-branch scheduling is more effective if we have some idea 5069 how long each instruction will be. Use a shorten_branches pass 5070 to get an initial estimate. */ 5071 5072 static void 5073 h8300_reorg (void) 5074 { 5075 if (flag_delayed_branch) 5076 shorten_branches (get_insns ()); 5077 } 5078 5079 /* Nonzero if X is a constant address suitable as an 8-bit absolute, 5080 which is a special case of the 'R' operand. */ 5081 5082 int 5083 h8300_eightbit_constant_address_p (rtx x) 5084 { 5085 /* The ranges of the 8-bit area. */ 5086 const unsigned HOST_WIDE_INT n1 = trunc_int_for_mode (0xff00, HImode); 5087 const unsigned HOST_WIDE_INT n2 = trunc_int_for_mode (0xffff, HImode); 5088 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00ffff00, SImode); 5089 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00ffffff, SImode); 5090 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0xffffff00, SImode); 5091 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0xffffffff, SImode); 5092 5093 unsigned HOST_WIDE_INT addr; 5094 5095 /* We accept symbols declared with eightbit_data. */ 5096 if (GET_CODE (x) == SYMBOL_REF) 5097 return (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0; 5098 5099 if (GET_CODE (x) == CONST 5100 && GET_CODE (XEXP (x, 0)) == PLUS 5101 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 5102 && (SYMBOL_REF_FLAGS (XEXP (XEXP (x, 0), 0)) & SYMBOL_FLAG_EIGHTBIT_DATA) != 0) 5103 return 1; 5104 5105 if (GET_CODE (x) != CONST_INT) 5106 return 0; 5107 5108 addr = INTVAL (x); 5109 5110 return (0 5111 || (TARGET_NORMAL_MODE && IN_RANGE (addr, n1, n2)) 5112 || (TARGET_H8300H && IN_RANGE (addr, h1, h2)) 5113 || (TARGET_H8300S && IN_RANGE (addr, s1, s2))); 5114 } 5115 5116 /* Nonzero if X is a constant address suitable as an 16-bit absolute 5117 on H8/300H and H8S. */ 5118 5119 int 5120 h8300_tiny_constant_address_p (rtx x) 5121 { 5122 /* The ranges of the 16-bit area. */ 5123 const unsigned HOST_WIDE_INT h1 = trunc_int_for_mode (0x00000000, SImode); 5124 const unsigned HOST_WIDE_INT h2 = trunc_int_for_mode (0x00007fff, SImode); 5125 const unsigned HOST_WIDE_INT h3 = trunc_int_for_mode (0x00ff8000, SImode); 5126 const unsigned HOST_WIDE_INT h4 = trunc_int_for_mode (0x00ffffff, SImode); 5127 const unsigned HOST_WIDE_INT s1 = trunc_int_for_mode (0x00000000, SImode); 5128 const unsigned HOST_WIDE_INT s2 = trunc_int_for_mode (0x00007fff, SImode); 5129 const unsigned HOST_WIDE_INT s3 = trunc_int_for_mode (0xffff8000, SImode); 5130 const unsigned HOST_WIDE_INT s4 = trunc_int_for_mode (0xffffffff, SImode); 5131 5132 unsigned HOST_WIDE_INT addr; 5133 5134 switch (GET_CODE (x)) 5135 { 5136 case SYMBOL_REF: 5137 /* In the normal mode, any symbol fits in the 16-bit absolute 5138 address range. We also accept symbols declared with 5139 tiny_data. */ 5140 return (TARGET_NORMAL_MODE 5141 || (SYMBOL_REF_FLAGS (x) & SYMBOL_FLAG_TINY_DATA) != 0); 5142 5143 case CONST_INT: 5144 addr = INTVAL (x); 5145 return (TARGET_NORMAL_MODE 5146 || (TARGET_H8300H 5147 && (IN_RANGE (addr, h1, h2) || IN_RANGE (addr, h3, h4))) 5148 || (TARGET_H8300S 5149 && (IN_RANGE (addr, s1, s2) || IN_RANGE (addr, s3, s4)))); 5150 5151 case CONST: 5152 return TARGET_NORMAL_MODE; 5153 5154 default: 5155 return 0; 5156 } 5157 5158 } 5159 5160 /* Return nonzero if ADDR1 and ADDR2 point to consecutive memory 5161 locations that can be accessed as a 16-bit word. */ 5162 5163 int 5164 byte_accesses_mergeable_p (rtx addr1, rtx addr2) 5165 { 5166 HOST_WIDE_INT offset1, offset2; 5167 rtx reg1, reg2; 5168 5169 if (REG_P (addr1)) 5170 { 5171 reg1 = addr1; 5172 offset1 = 0; 5173 } 5174 else if (GET_CODE (addr1) == PLUS 5175 && REG_P (XEXP (addr1, 0)) 5176 && GET_CODE (XEXP (addr1, 1)) == CONST_INT) 5177 { 5178 reg1 = XEXP (addr1, 0); 5179 offset1 = INTVAL (XEXP (addr1, 1)); 5180 } 5181 else 5182 return 0; 5183 5184 if (REG_P (addr2)) 5185 { 5186 reg2 = addr2; 5187 offset2 = 0; 5188 } 5189 else if (GET_CODE (addr2) == PLUS 5190 && REG_P (XEXP (addr2, 0)) 5191 && GET_CODE (XEXP (addr2, 1)) == CONST_INT) 5192 { 5193 reg2 = XEXP (addr2, 0); 5194 offset2 = INTVAL (XEXP (addr2, 1)); 5195 } 5196 else 5197 return 0; 5198 5199 if (((reg1 == stack_pointer_rtx && reg2 == stack_pointer_rtx) 5200 || (reg1 == frame_pointer_rtx && reg2 == frame_pointer_rtx)) 5201 && offset1 % 2 == 0 5202 && offset1 + 1 == offset2) 5203 return 1; 5204 5205 return 0; 5206 } 5207 5208 /* Return nonzero if we have the same comparison insn as I3 two insns 5209 before I3. I3 is assumed to be a comparison insn. */ 5210 5211 int 5212 same_cmp_preceding_p (rtx_insn *i3) 5213 { 5214 rtx_insn *i1, *i2; 5215 5216 /* Make sure we have a sequence of three insns. */ 5217 i2 = prev_nonnote_insn (i3); 5218 if (i2 == NULL) 5219 return 0; 5220 i1 = prev_nonnote_insn (i2); 5221 if (i1 == NULL) 5222 return 0; 5223 5224 return (INSN_P (i1) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5225 && any_condjump_p (i2) && onlyjump_p (i2)); 5226 } 5227 5228 /* Return nonzero if we have the same comparison insn as I1 two insns 5229 after I1. I1 is assumed to be a comparison insn. */ 5230 5231 int 5232 same_cmp_following_p (rtx_insn *i1) 5233 { 5234 rtx_insn *i2, *i3; 5235 5236 /* Make sure we have a sequence of three insns. */ 5237 i2 = next_nonnote_insn (i1); 5238 if (i2 == NULL) 5239 return 0; 5240 i3 = next_nonnote_insn (i2); 5241 if (i3 == NULL) 5242 return 0; 5243 5244 return (INSN_P (i3) && rtx_equal_p (PATTERN (i1), PATTERN (i3)) 5245 && any_condjump_p (i2) && onlyjump_p (i2)); 5246 } 5247 5248 /* Return nonzero if OPERANDS are valid for stm (or ldm) that pushes 5249 (or pops) N registers. OPERANDS are assumed to be an array of 5250 registers. */ 5251 5252 int 5253 h8300_regs_ok_for_stm (int n, rtx operands[]) 5254 { 5255 switch (n) 5256 { 5257 case 2: 5258 return ((REGNO (operands[0]) == 0 && REGNO (operands[1]) == 1) 5259 || (REGNO (operands[0]) == 2 && REGNO (operands[1]) == 3) 5260 || (REGNO (operands[0]) == 4 && REGNO (operands[1]) == 5)); 5261 case 3: 5262 return ((REGNO (operands[0]) == 0 5263 && REGNO (operands[1]) == 1 5264 && REGNO (operands[2]) == 2) 5265 || (REGNO (operands[0]) == 4 5266 && REGNO (operands[1]) == 5 5267 && REGNO (operands[2]) == 6)); 5268 5269 case 4: 5270 return (REGNO (operands[0]) == 0 5271 && REGNO (operands[1]) == 1 5272 && REGNO (operands[2]) == 2 5273 && REGNO (operands[3]) == 3); 5274 default: 5275 gcc_unreachable (); 5276 } 5277 } 5278 5279 /* Return nonzero if register OLD_REG can be renamed to register NEW_REG. */ 5280 5281 int 5282 h8300_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 5283 unsigned int new_reg) 5284 { 5285 /* Interrupt functions can only use registers that have already been 5286 saved by the prologue, even if they would normally be 5287 call-clobbered. */ 5288 5289 if (h8300_current_function_interrupt_function_p () 5290 && !df_regs_ever_live_p (new_reg)) 5291 return 0; 5292 5293 return 1; 5294 } 5295 5296 /* Returns true if register REGNO is safe to be allocated as a scratch 5297 register in the current function. */ 5298 5299 static bool 5300 h8300_hard_regno_scratch_ok (unsigned int regno) 5301 { 5302 if (h8300_current_function_interrupt_function_p () 5303 && ! WORD_REG_USED (regno)) 5304 return false; 5305 5306 return true; 5307 } 5308 5309 5310 /* Return nonzero if X is a REG or SUBREG suitable as a base register. */ 5311 5312 static int 5313 h8300_rtx_ok_for_base_p (rtx x, int strict) 5314 { 5315 /* Strip off SUBREG if any. */ 5316 if (GET_CODE (x) == SUBREG) 5317 x = SUBREG_REG (x); 5318 5319 return (REG_P (x) 5320 && (strict 5321 ? REG_OK_FOR_BASE_STRICT_P (x) 5322 : REG_OK_FOR_BASE_NONSTRICT_P (x))); 5323 } 5324 5325 /* Return nozero if X is a legitimate address. On the H8/300, a 5326 legitimate address has the form REG, REG+CONSTANT_ADDRESS or 5327 CONSTANT_ADDRESS. */ 5328 5329 static bool 5330 h8300_legitimate_address_p (machine_mode mode, rtx x, bool strict) 5331 { 5332 /* The register indirect addresses like @er0 is always valid. */ 5333 if (h8300_rtx_ok_for_base_p (x, strict)) 5334 return 1; 5335 5336 if (CONSTANT_ADDRESS_P (x)) 5337 return 1; 5338 5339 if (TARGET_H8300SX 5340 && ( GET_CODE (x) == PRE_INC 5341 || GET_CODE (x) == PRE_DEC 5342 || GET_CODE (x) == POST_INC 5343 || GET_CODE (x) == POST_DEC) 5344 && h8300_rtx_ok_for_base_p (XEXP (x, 0), strict)) 5345 return 1; 5346 5347 if (GET_CODE (x) == PLUS 5348 && CONSTANT_ADDRESS_P (XEXP (x, 1)) 5349 && h8300_rtx_ok_for_base_p (h8300_get_index (XEXP (x, 0), 5350 mode, 0), strict)) 5351 return 1; 5352 5353 return 0; 5354 } 5355 5356 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 5357 5358 static bool 5359 h8300_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 5360 { 5361 /* MAC register can only be of SImode. Otherwise, anything 5362 goes. */ 5363 return regno == MAC_REG ? mode == SImode : 1; 5364 } 5365 5366 /* Implement TARGET_MODES_TIEABLE_P. */ 5367 5368 static bool 5369 h8300_modes_tieable_p (machine_mode mode1, machine_mode mode2) 5370 { 5371 return (mode1 == mode2 5372 || ((mode1 == QImode 5373 || mode1 == HImode 5374 || mode1 == SImode) 5375 && (mode2 == QImode 5376 || mode2 == HImode 5377 || mode2 == SImode))); 5378 } 5379 5380 /* Helper function for the move patterns. Make sure a move is legitimate. */ 5381 5382 bool 5383 h8300_move_ok (rtx dest, rtx src) 5384 { 5385 rtx addr, other; 5386 5387 /* Validate that at least one operand is a register. */ 5388 if (MEM_P (dest)) 5389 { 5390 if (MEM_P (src) || CONSTANT_P (src)) 5391 return false; 5392 addr = XEXP (dest, 0); 5393 other = src; 5394 } 5395 else if (MEM_P (src)) 5396 { 5397 addr = XEXP (src, 0); 5398 other = dest; 5399 } 5400 else 5401 return true; 5402 5403 /* Validate that auto-inc doesn't affect OTHER. */ 5404 if (GET_RTX_CLASS (GET_CODE (addr)) != RTX_AUTOINC) 5405 return true; 5406 addr = XEXP (addr, 0); 5407 5408 if (addr == stack_pointer_rtx) 5409 return register_no_sp_elim_operand (other, VOIDmode); 5410 else 5411 return !reg_overlap_mentioned_p(other, addr); 5412 } 5413 5414 /* Perform target dependent optabs initialization. */ 5416 static void 5417 h8300_init_libfuncs (void) 5418 { 5419 set_optab_libfunc (smul_optab, HImode, "__mulhi3"); 5420 set_optab_libfunc (sdiv_optab, HImode, "__divhi3"); 5421 set_optab_libfunc (udiv_optab, HImode, "__udivhi3"); 5422 set_optab_libfunc (smod_optab, HImode, "__modhi3"); 5423 set_optab_libfunc (umod_optab, HImode, "__umodhi3"); 5424 } 5425 5426 /* Worker function for TARGET_FUNCTION_VALUE. 5428 5429 On the H8 the return value is in R0/R1. */ 5430 5431 static rtx 5432 h8300_function_value (const_tree ret_type, 5433 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 5434 bool outgoing ATTRIBUTE_UNUSED) 5435 { 5436 return gen_rtx_REG (TYPE_MODE (ret_type), R0_REG); 5437 } 5438 5439 /* Worker function for TARGET_LIBCALL_VALUE. 5440 5441 On the H8 the return value is in R0/R1. */ 5442 5443 static rtx 5444 h8300_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) 5445 { 5446 return gen_rtx_REG (mode, R0_REG); 5447 } 5448 5449 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 5450 5451 On the H8, R0 is the only register thus used. */ 5452 5453 static bool 5454 h8300_function_value_regno_p (const unsigned int regno) 5455 { 5456 return (regno == R0_REG); 5457 } 5458 5459 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 5460 5461 static bool 5462 h8300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 5463 { 5464 return (TYPE_MODE (type) == BLKmode 5465 || GET_MODE_SIZE (TYPE_MODE (type)) > 8); 5466 } 5467 5468 /* We emit the entire trampoline here. Depending on the pointer size, 5470 we use a different trampoline. 5471 5472 Pmode == HImode 5473 vvvv context 5474 1 0000 7903xxxx mov.w #0x1234,r3 5475 2 0004 5A00xxxx jmp @0x1234 5476 ^^^^ function 5477 5478 Pmode == SImode 5479 vvvvvvvv context 5480 2 0000 7A03xxxxxxxx mov.l #0x12345678,er3 5481 3 0006 5Axxxxxx jmp @0x123456 5482 ^^^^^^ function 5483 */ 5484 5485 static void 5486 h8300_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) 5487 { 5488 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 5489 rtx mem; 5490 5491 if (Pmode == HImode) 5492 { 5493 mem = adjust_address (m_tramp, HImode, 0); 5494 emit_move_insn (mem, GEN_INT (0x7903)); 5495 mem = adjust_address (m_tramp, Pmode, 2); 5496 emit_move_insn (mem, cxt); 5497 mem = adjust_address (m_tramp, HImode, 4); 5498 emit_move_insn (mem, GEN_INT (0x5a00)); 5499 mem = adjust_address (m_tramp, Pmode, 6); 5500 emit_move_insn (mem, fnaddr); 5501 } 5502 else 5503 { 5504 rtx tem; 5505 5506 mem = adjust_address (m_tramp, HImode, 0); 5507 emit_move_insn (mem, GEN_INT (0x7a03)); 5508 mem = adjust_address (m_tramp, Pmode, 2); 5509 emit_move_insn (mem, cxt); 5510 5511 tem = copy_to_reg (fnaddr); 5512 emit_insn (gen_andsi3 (tem, tem, GEN_INT (0x00ffffff))); 5513 emit_insn (gen_iorsi3 (tem, tem, GEN_INT (0x5a000000))); 5514 mem = adjust_address (m_tramp, SImode, 6); 5515 emit_move_insn (mem, tem); 5516 } 5517 } 5518 5519 /* Implement PUSH_ROUNDING. 5520 5521 On the H8/300, @-sp really pushes a byte if you ask it to - but that's 5522 dangerous, so we claim that it always pushes a word, then we catch 5523 the mov.b rx,@-sp and turn it into a mov.w rx,@-sp on output. 5524 5525 On the H8/300H, we simplify TARGET_QUICKCALL by setting this to 4 5526 and doing a similar thing. */ 5527 5528 poly_int64 5529 h8300_push_rounding (poly_int64 bytes) 5530 { 5531 return ((bytes + PARM_BOUNDARY / 8 - 1) & (-PARM_BOUNDARY / 8)); 5532 } 5533 5534 static bool 5535 h8300_ok_for_sibcall_p (tree fndecl, tree) 5536 { 5537 /* If either the caller or target are special, then assume sibling 5538 calls are not OK. */ 5539 if (!fndecl 5540 || h8300_os_task_function_p (fndecl) 5541 || h8300_monitor_function_p (fndecl) 5542 || h8300_interrupt_function_p (fndecl) 5543 || h8300_saveall_function_p (fndecl) 5544 || h8300_os_task_function_p (current_function_decl) 5545 || h8300_monitor_function_p (current_function_decl) 5546 || h8300_interrupt_function_p (current_function_decl) 5547 || h8300_saveall_function_p (current_function_decl)) 5548 return false; 5549 5550 return 1; 5551 } 5552 5553 /* Initialize the GCC target structure. */ 5555 #undef TARGET_ATTRIBUTE_TABLE 5556 #define TARGET_ATTRIBUTE_TABLE h8300_attribute_table 5557 5558 #undef TARGET_ASM_ALIGNED_HI_OP 5559 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 5560 5561 #undef TARGET_ASM_FILE_START 5562 #define TARGET_ASM_FILE_START h8300_file_start 5563 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 5564 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 5565 5566 #undef TARGET_ASM_FILE_END 5567 #define TARGET_ASM_FILE_END h8300_file_end 5568 5569 #undef TARGET_PRINT_OPERAND 5570 #define TARGET_PRINT_OPERAND h8300_print_operand 5571 #undef TARGET_PRINT_OPERAND_ADDRESS 5572 #define TARGET_PRINT_OPERAND_ADDRESS h8300_print_operand_address 5573 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 5574 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P h8300_print_operand_punct_valid_p 5575 5576 #undef TARGET_ENCODE_SECTION_INFO 5577 #define TARGET_ENCODE_SECTION_INFO h8300_encode_section_info 5578 5579 #undef TARGET_INSERT_ATTRIBUTES 5580 #define TARGET_INSERT_ATTRIBUTES h8300_insert_attributes 5581 5582 #undef TARGET_REGISTER_MOVE_COST 5583 #define TARGET_REGISTER_MOVE_COST h8300_register_move_cost 5584 5585 #undef TARGET_RTX_COSTS 5586 #define TARGET_RTX_COSTS h8300_rtx_costs 5587 5588 #undef TARGET_INIT_LIBFUNCS 5589 #define TARGET_INIT_LIBFUNCS h8300_init_libfuncs 5590 5591 #undef TARGET_FUNCTION_VALUE 5592 #define TARGET_FUNCTION_VALUE h8300_function_value 5593 5594 #undef TARGET_LIBCALL_VALUE 5595 #define TARGET_LIBCALL_VALUE h8300_libcall_value 5596 5597 #undef TARGET_FUNCTION_VALUE_REGNO_P 5598 #define TARGET_FUNCTION_VALUE_REGNO_P h8300_function_value_regno_p 5599 5600 #undef TARGET_RETURN_IN_MEMORY 5601 #define TARGET_RETURN_IN_MEMORY h8300_return_in_memory 5602 5603 #undef TARGET_FUNCTION_ARG 5604 #define TARGET_FUNCTION_ARG h8300_function_arg 5605 5606 #undef TARGET_FUNCTION_ARG_ADVANCE 5607 #define TARGET_FUNCTION_ARG_ADVANCE h8300_function_arg_advance 5608 5609 #undef TARGET_MACHINE_DEPENDENT_REORG 5610 #define TARGET_MACHINE_DEPENDENT_REORG h8300_reorg 5611 5612 #undef TARGET_HARD_REGNO_SCRATCH_OK 5613 #define TARGET_HARD_REGNO_SCRATCH_OK h8300_hard_regno_scratch_ok 5614 5615 #undef TARGET_HARD_REGNO_MODE_OK 5616 #define TARGET_HARD_REGNO_MODE_OK h8300_hard_regno_mode_ok 5617 5618 #undef TARGET_MODES_TIEABLE_P 5619 #define TARGET_MODES_TIEABLE_P h8300_modes_tieable_p 5620 5621 #undef TARGET_LRA_P 5622 #define TARGET_LRA_P hook_bool_void_false 5623 5624 #undef TARGET_LEGITIMATE_ADDRESS_P 5625 #define TARGET_LEGITIMATE_ADDRESS_P h8300_legitimate_address_p 5626 5627 #undef TARGET_CAN_ELIMINATE 5628 #define TARGET_CAN_ELIMINATE h8300_can_eliminate 5629 5630 #undef TARGET_CONDITIONAL_REGISTER_USAGE 5631 #define TARGET_CONDITIONAL_REGISTER_USAGE h8300_conditional_register_usage 5632 5633 #undef TARGET_TRAMPOLINE_INIT 5634 #define TARGET_TRAMPOLINE_INIT h8300_trampoline_init 5635 5636 #undef TARGET_OPTION_OVERRIDE 5637 #define TARGET_OPTION_OVERRIDE h8300_option_override 5638 5639 #undef TARGET_MODE_DEPENDENT_ADDRESS_P 5640 #define TARGET_MODE_DEPENDENT_ADDRESS_P h8300_mode_dependent_address_p 5641 5642 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE 5643 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 5644 5645 #undef TARGET_FLAGS_REGNUM 5646 #define TARGET_FLAGS_REGNUM 12 5647 5648 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 5649 #define TARGET_FUNCTION_OK_FOR_SIBCALL h8300_ok_for_sibcall_p 5650 5651 struct gcc_target targetm = TARGET_INITIALIZER; 5652
Indexes created Thu Mar 19 00:23:35 UTC 2026