avx5124vnniwintrin.h revision 1.1.1.5
1 1.1.1.5 mrg /* Copyright (C) 2015-2022 Free Software Foundation, Inc. 2 1.1 mrg 3 1.1 mrg This file is part of GCC. 4 1.1 mrg 5 1.1 mrg GCC is free software; you can redistribute it and/or modify 6 1.1 mrg it under the terms of the GNU General Public License as published by 7 1.1 mrg the Free Software Foundation; either version 3, or (at your option) 8 1.1 mrg any later version. 9 1.1 mrg 10 1.1 mrg GCC is distributed in the hope that it will be useful, 11 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of 12 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 1.1 mrg GNU General Public License for more details. 14 1.1 mrg 15 1.1 mrg Under Section 7 of GPL version 3, you are granted additional 16 1.1 mrg permissions described in the GCC Runtime Library Exception, version 17 1.1 mrg 3.1, as published by the Free Software Foundation. 18 1.1 mrg 19 1.1 mrg You should have received a copy of the GNU General Public License and 20 1.1 mrg a copy of the GCC Runtime Library Exception along with this program; 21 1.1 mrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 22 1.1 mrg <http://www.gnu.org/licenses/>. */ 23 1.1 mrg 24 1.1 mrg #if !defined _IMMINTRIN_H_INCLUDED 25 1.1 mrg # error "Never use <avx5124vnniwintrin.h> directly; include <x86intrin.h> instead." 26 1.1 mrg #endif 27 1.1 mrg 28 1.1 mrg #ifndef _AVX5124VNNIWINTRIN_H_INCLUDED 29 1.1 mrg #define _AVX5124VNNIWINTRIN_H_INCLUDED 30 1.1 mrg 31 1.1 mrg #ifndef __AVX5124VNNIW__ 32 1.1 mrg #pragma GCC push_options 33 1.1 mrg #pragma GCC target("avx5124vnniw") 34 1.1 mrg #define __DISABLE_AVX5124VNNIW__ 35 1.1 mrg #endif /* __AVX5124VNNIW__ */ 36 1.1 mrg 37 1.1 mrg extern __inline __m512i 38 1.1 mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 39 1.1 mrg _mm512_4dpwssd_epi32 (__m512i __A, __m512i __B, __m512i __C, 40 1.1 mrg __m512i __D, __m512i __E, __m128i *__F) 41 1.1 mrg { 42 1.1 mrg return (__m512i) __builtin_ia32_vp4dpwssd ((__v16si) __B, 43 1.1 mrg (__v16si) __C, 44 1.1 mrg (__v16si) __D, 45 1.1 mrg (__v16si) __E, 46 1.1 mrg (__v16si) __A, 47 1.1 mrg (const __v4si *) __F); 48 1.1 mrg } 49 1.1 mrg 50 1.1 mrg extern __inline __m512i 51 1.1 mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 52 1.1 mrg _mm512_mask_4dpwssd_epi32 (__m512i __A, __mmask16 __U, __m512i __B, 53 1.1 mrg __m512i __C, __m512i __D, __m512i __E, 54 1.1 mrg __m128i *__F) 55 1.1 mrg { 56 1.1 mrg return (__m512i) __builtin_ia32_vp4dpwssd_mask ((__v16si) __B, 57 1.1 mrg (__v16si) __C, 58 1.1 mrg (__v16si) __D, 59 1.1 mrg (__v16si) __E, 60 1.1 mrg (__v16si) __A, 61 1.1 mrg (const __v4si *) __F, 62 1.1 mrg (__v16si) __A, 63 1.1 mrg (__mmask16) __U); 64 1.1 mrg } 65 1.1 mrg 66 1.1 mrg extern __inline __m512i 67 1.1 mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 68 1.1 mrg _mm512_maskz_4dpwssd_epi32 (__mmask16 __U, __m512i __A, __m512i __B, 69 1.1 mrg __m512i __C, __m512i __D, __m512i __E, 70 1.1 mrg __m128i *__F) 71 1.1 mrg { 72 1.1 mrg return (__m512i) __builtin_ia32_vp4dpwssd_mask ((__v16si) __B, 73 1.1 mrg (__v16si) __C, 74 1.1 mrg (__v16si) __D, 75 1.1 mrg (__v16si) __E, 76 1.1 mrg (__v16si) __A, 77 1.1 mrg (const __v4si *) __F, 78 1.1 mrg (__v16si) _mm512_setzero_ps (), 79 1.1 mrg (__mmask16) __U); 80 1.1 mrg } 81 1.1 mrg 82 1.1 mrg extern __inline __m512i 83 1.1 mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 84 1.1 mrg _mm512_4dpwssds_epi32 (__m512i __A, __m512i __B, __m512i __C, 85 1.1 mrg __m512i __D, __m512i __E, __m128i *__F) 86 1.1 mrg { 87 1.1 mrg return (__m512i) __builtin_ia32_vp4dpwssds ((__v16si) __B, 88 1.1 mrg (__v16si) __C, 89 1.1 mrg (__v16si) __D, 90 1.1 mrg (__v16si) __E, 91 1.1 mrg (__v16si) __A, 92 1.1 mrg (const __v4si *) __F); 93 1.1 mrg } 94 1.1 mrg 95 1.1 mrg extern __inline __m512i 96 1.1 mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 97 1.1 mrg _mm512_mask_4dpwssds_epi32 (__m512i __A, __mmask16 __U, __m512i __B, 98 1.1 mrg __m512i __C, __m512i __D, __m512i __E, 99 1.1 mrg __m128i *__F) 100 1.1 mrg { 101 1.1 mrg return (__m512i) __builtin_ia32_vp4dpwssds_mask ((__v16si) __B, 102 1.1 mrg (__v16si) __C, 103 1.1 mrg (__v16si) __D, 104 1.1 mrg (__v16si) __E, 105 1.1 mrg (__v16si) __A, 106 1.1 mrg (const __v4si *) __F, 107 1.1 mrg (__v16si) __A, 108 1.1 mrg (__mmask16) __U); 109 1.1 mrg } 110 1.1 mrg 111 1.1 mrg extern __inline __m512i 112 1.1 mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 113 1.1 mrg _mm512_maskz_4dpwssds_epi32 (__mmask16 __U, __m512i __A, __m512i __B, 114 1.1 mrg __m512i __C, __m512i __D, __m512i __E, 115 1.1 mrg __m128i *__F) 116 1.1 mrg { 117 1.1 mrg return (__m512i) __builtin_ia32_vp4dpwssds_mask ((__v16si) __B, 118 1.1 mrg (__v16si) __C, 119 1.1 mrg (__v16si) __D, 120 1.1 mrg (__v16si) __E, 121 1.1 mrg (__v16si) __A, 122 1.1 mrg (const __v4si *) __F, 123 1.1 mrg (__v16si) _mm512_setzero_ps (), 124 1.1 mrg (__mmask16) __U); 125 1.1 mrg } 126 1.1 mrg 127 1.1 mrg #ifdef __DISABLE_AVX5124VNNIW__ 128 1.1 mrg #undef __DISABLE_AVX5124VNNIW__ 129 1.1 mrg #pragma GCC pop_options 130 1.1 mrg #endif /* __DISABLE_AVX5124VNNIW__ */ 131 1.1 mrg 132 1.1 mrg #endif /* _AVX5124VNNIWINTRIN_H_INCLUDED */ 133
Indexes created Sat Apr 11 00:22:22 UTC 2026