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avx512bitalgintrin.h revision 1.1
      1  1.1  mrg /* Copyright (C) 2017-2018 Free Software Foundation, Inc.
      2  1.1  mrg 
      3  1.1  mrg    This file is part of GCC.
      4  1.1  mrg 
      5  1.1  mrg    GCC is free software; you can redistribute it and/or modify
      6  1.1  mrg    it under the terms of the GNU General Public License as published by
      7  1.1  mrg    the Free Software Foundation; either version 3, or (at your option)
      8  1.1  mrg    any later version.
      9  1.1  mrg 
     10  1.1  mrg    GCC is distributed in the hope that it will be useful,
     11  1.1  mrg    but WITHOUT ANY WARRANTY; without even the implied warranty of
     12  1.1  mrg    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     13  1.1  mrg    GNU General Public License for more details.
     14  1.1  mrg 
     15  1.1  mrg    Under Section 7 of GPL version 3, you are granted additional
     16  1.1  mrg    permissions described in the GCC Runtime Library Exception, version
     17  1.1  mrg    3.1, as published by the Free Software Foundation.
     18  1.1  mrg 
     19  1.1  mrg    You should have received a copy of the GNU General Public License and
     20  1.1  mrg    a copy of the GCC Runtime Library Exception along with this program;
     21  1.1  mrg    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     22  1.1  mrg    <http://www.gnu.org/licenses/>.  */
     23  1.1  mrg 
     24  1.1  mrg #if !defined _IMMINTRIN_H_INCLUDED
     25  1.1  mrg # error "Never use <avx512bitalgintrin.h> directly; include <x86intrin.h> instead."
     26  1.1  mrg #endif
     27  1.1  mrg 
     28  1.1  mrg #ifndef _AVX512BITALGINTRIN_H_INCLUDED
     29  1.1  mrg #define _AVX512BITALGINTRIN_H_INCLUDED
     30  1.1  mrg 
     31  1.1  mrg #ifndef __AVX512BITALG__
     32  1.1  mrg #pragma GCC push_options
     33  1.1  mrg #pragma GCC target("avx512bitalg")
     34  1.1  mrg #define __DISABLE_AVX512BITALG__
     35  1.1  mrg #endif /* __AVX512BITALG__ */
     36  1.1  mrg 
     37  1.1  mrg extern __inline __m512i
     38  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     39  1.1  mrg _mm512_popcnt_epi8 (__m512i __A)
     40  1.1  mrg {
     41  1.1  mrg   return (__m512i) __builtin_ia32_vpopcountb_v64qi ((__v64qi) __A);
     42  1.1  mrg }
     43  1.1  mrg 
     44  1.1  mrg extern __inline __m512i
     45  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     46  1.1  mrg _mm512_popcnt_epi16 (__m512i __A)
     47  1.1  mrg {
     48  1.1  mrg   return (__m512i) __builtin_ia32_vpopcountw_v32hi ((__v32hi) __A);
     49  1.1  mrg }
     50  1.1  mrg 
     51  1.1  mrg #ifdef __DISABLE_AVX512BITALG__
     52  1.1  mrg #undef __DISABLE_AVX512BITALG__
     53  1.1  mrg #pragma GCC pop_options
     54  1.1  mrg #endif /* __DISABLE_AVX512BITALG__ */
     55  1.1  mrg 
     56  1.1  mrg #if !defined(__AVX512BITALG__) || !defined(__AVX512BW__)
     57  1.1  mrg #pragma GCC push_options
     58  1.1  mrg #pragma GCC target("avx512bitalg,avx512bw")
     59  1.1  mrg #define __DISABLE_AVX512BITALGBW__
     60  1.1  mrg #endif /* __AVX512VLBW__ */
     61  1.1  mrg 
     62  1.1  mrg extern __inline __m512i
     63  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     64  1.1  mrg _mm512_mask_popcnt_epi8 (__m512i __W, __mmask64 __U, __m512i __A)
     65  1.1  mrg {
     66  1.1  mrg   return (__m512i) __builtin_ia32_vpopcountb_v64qi_mask ((__v64qi) __A,
     67  1.1  mrg 							 (__v64qi) __W,
     68  1.1  mrg 							 (__mmask64) __U);
     69  1.1  mrg }
     70  1.1  mrg 
     71  1.1  mrg extern __inline __m512i
     72  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     73  1.1  mrg _mm512_maskz_popcnt_epi8 (__mmask64 __U, __m512i __A)
     74  1.1  mrg {
     75  1.1  mrg   return (__m512i) __builtin_ia32_vpopcountb_v64qi_mask ((__v64qi) __A,
     76  1.1  mrg 						(__v64qi)
     77  1.1  mrg 						_mm512_setzero_si512 (),
     78  1.1  mrg 						(__mmask64) __U);
     79  1.1  mrg }
     80  1.1  mrg extern __inline __m512i
     81  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     82  1.1  mrg _mm512_mask_popcnt_epi16 (__m512i __W, __mmask32 __U, __m512i __A)
     83  1.1  mrg {
     84  1.1  mrg   return (__m512i) __builtin_ia32_vpopcountw_v32hi_mask ((__v32hi) __A,
     85  1.1  mrg 							(__v32hi) __W,
     86  1.1  mrg 							(__mmask32) __U);
     87  1.1  mrg }
     88  1.1  mrg 
     89  1.1  mrg extern __inline __m512i
     90  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
     91  1.1  mrg _mm512_maskz_popcnt_epi16 (__mmask32 __U, __m512i __A)
     92  1.1  mrg {
     93  1.1  mrg   return (__m512i) __builtin_ia32_vpopcountw_v32hi_mask ((__v32hi) __A,
     94  1.1  mrg 						(__v32hi)
     95  1.1  mrg 						_mm512_setzero_si512 (),
     96  1.1  mrg 						(__mmask32) __U);
     97  1.1  mrg }
     98  1.1  mrg 
     99  1.1  mrg extern __inline __mmask64
    100  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    101  1.1  mrg _mm512_bitshuffle_epi64_mask (__m512i __A, __m512i __B)
    102  1.1  mrg {
    103  1.1  mrg   return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask ((__v64qi) __A,
    104  1.1  mrg 						 (__v64qi) __B,
    105  1.1  mrg 						 (__mmask64) -1);
    106  1.1  mrg }
    107  1.1  mrg 
    108  1.1  mrg extern __inline __mmask64
    109  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    110  1.1  mrg _mm512_mask_bitshuffle_epi64_mask (__mmask64 __M, __m512i __A, __m512i __B)
    111  1.1  mrg {
    112  1.1  mrg   return (__mmask64) __builtin_ia32_vpshufbitqmb512_mask ((__v64qi) __A,
    113  1.1  mrg 						 (__v64qi) __B,
    114  1.1  mrg 						 (__mmask64) __M);
    115  1.1  mrg }
    116  1.1  mrg 
    117  1.1  mrg #ifdef __DISABLE_AVX512BITALGBW__
    118  1.1  mrg #undef __DISABLE_AVX512BITALGBW__
    119  1.1  mrg #pragma GCC pop_options
    120  1.1  mrg #endif /* __DISABLE_AVX512BITALGBW__ */
    121  1.1  mrg 
    122  1.1  mrg #if !defined(__AVX512BITALG__) || !defined(__AVX512VL__) || !defined(__AVX512BW__)
    123  1.1  mrg #pragma GCC push_options
    124  1.1  mrg #pragma GCC target("avx512bitalg,avx512vl,avx512bw")
    125  1.1  mrg #define __DISABLE_AVX512BITALGVLBW__
    126  1.1  mrg #endif /* __AVX512VLBW__ */
    127  1.1  mrg 
    128  1.1  mrg extern __inline __m256i
    129  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    130  1.1  mrg _mm256_mask_popcnt_epi8 (__m256i __W, __mmask32 __U, __m256i __A)
    131  1.1  mrg {
    132  1.1  mrg   return (__m256i) __builtin_ia32_vpopcountb_v32qi_mask ((__v32qi) __A,
    133  1.1  mrg 							 (__v32qi) __W,
    134  1.1  mrg 							 (__mmask32) __U);
    135  1.1  mrg }
    136  1.1  mrg 
    137  1.1  mrg extern __inline __m256i
    138  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    139  1.1  mrg _mm256_maskz_popcnt_epi8 (__mmask32 __U, __m256i __A)
    140  1.1  mrg {
    141  1.1  mrg   return (__m256i) __builtin_ia32_vpopcountb_v32qi_mask ((__v32qi) __A,
    142  1.1  mrg 						(__v32qi)
    143  1.1  mrg 						 _mm256_setzero_si256 (),
    144  1.1  mrg 						(__mmask32) __U);
    145  1.1  mrg }
    146  1.1  mrg 
    147  1.1  mrg extern __inline __mmask32
    148  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    149  1.1  mrg _mm256_bitshuffle_epi64_mask (__m256i __A, __m256i __B)
    150  1.1  mrg {
    151  1.1  mrg   return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask ((__v32qi) __A,
    152  1.1  mrg 						 (__v32qi) __B,
    153  1.1  mrg 						 (__mmask32) -1);
    154  1.1  mrg }
    155  1.1  mrg 
    156  1.1  mrg extern __inline __mmask32
    157  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    158  1.1  mrg _mm256_mask_bitshuffle_epi64_mask (__mmask32 __M, __m256i __A, __m256i __B)
    159  1.1  mrg {
    160  1.1  mrg   return (__mmask32) __builtin_ia32_vpshufbitqmb256_mask ((__v32qi) __A,
    161  1.1  mrg 						 (__v32qi) __B,
    162  1.1  mrg 						 (__mmask32) __M);
    163  1.1  mrg }
    164  1.1  mrg 
    165  1.1  mrg #ifdef __DISABLE_AVX512BITALGVLBW__
    166  1.1  mrg #undef __DISABLE_AVX512BITALGVLBW__
    167  1.1  mrg #pragma GCC pop_options
    168  1.1  mrg #endif /* __DISABLE_AVX512BITALGVLBW__ */
    169  1.1  mrg 
    170  1.1  mrg 
    171  1.1  mrg #if !defined(__AVX512BITALG__) || !defined(__AVX512VL__)
    172  1.1  mrg #pragma GCC push_options
    173  1.1  mrg #pragma GCC target("avx512bitalg,avx512vl")
    174  1.1  mrg #define __DISABLE_AVX512BITALGVL__
    175  1.1  mrg #endif /* __AVX512VLBW__ */
    176  1.1  mrg 
    177  1.1  mrg extern __inline __mmask16
    178  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    179  1.1  mrg _mm_bitshuffle_epi64_mask (__m128i __A, __m128i __B)
    180  1.1  mrg {
    181  1.1  mrg   return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v16qi) __A,
    182  1.1  mrg 						 (__v16qi) __B,
    183  1.1  mrg 						 (__mmask16) -1);
    184  1.1  mrg }
    185  1.1  mrg 
    186  1.1  mrg extern __inline __mmask16
    187  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    188  1.1  mrg _mm_mask_bitshuffle_epi64_mask (__mmask16 __M, __m128i __A, __m128i __B)
    189  1.1  mrg {
    190  1.1  mrg   return (__mmask16) __builtin_ia32_vpshufbitqmb128_mask ((__v16qi) __A,
    191  1.1  mrg 						 (__v16qi) __B,
    192  1.1  mrg 						 (__mmask16) __M);
    193  1.1  mrg }
    194  1.1  mrg 
    195  1.1  mrg extern __inline __m256i
    196  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    197  1.1  mrg _mm256_popcnt_epi8 (__m256i __A)
    198  1.1  mrg {
    199  1.1  mrg   return (__m256i) __builtin_ia32_vpopcountb_v32qi ((__v32qi) __A);
    200  1.1  mrg }
    201  1.1  mrg 
    202  1.1  mrg extern __inline __m256i
    203  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    204  1.1  mrg _mm256_popcnt_epi16 (__m256i __A)
    205  1.1  mrg {
    206  1.1  mrg   return (__m256i) __builtin_ia32_vpopcountw_v16hi ((__v16hi) __A);
    207  1.1  mrg }
    208  1.1  mrg 
    209  1.1  mrg extern __inline __m128i
    210  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    211  1.1  mrg _mm_popcnt_epi8 (__m128i __A)
    212  1.1  mrg {
    213  1.1  mrg   return (__m128i) __builtin_ia32_vpopcountb_v16qi ((__v16qi) __A);
    214  1.1  mrg }
    215  1.1  mrg 
    216  1.1  mrg extern __inline __m128i
    217  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    218  1.1  mrg _mm_popcnt_epi16 (__m128i __A)
    219  1.1  mrg {
    220  1.1  mrg   return (__m128i) __builtin_ia32_vpopcountw_v8hi ((__v8hi) __A);
    221  1.1  mrg }
    222  1.1  mrg 
    223  1.1  mrg extern __inline __m256i
    224  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    225  1.1  mrg _mm256_mask_popcnt_epi16 (__m256i __W, __mmask16 __U, __m256i __A)
    226  1.1  mrg {
    227  1.1  mrg   return (__m256i) __builtin_ia32_vpopcountw_v16hi_mask ((__v16hi) __A,
    228  1.1  mrg 							(__v16hi) __W,
    229  1.1  mrg 							(__mmask16) __U);
    230  1.1  mrg }
    231  1.1  mrg 
    232  1.1  mrg extern __inline __m256i
    233  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    234  1.1  mrg _mm256_maskz_popcnt_epi16 (__mmask16 __U, __m256i __A)
    235  1.1  mrg {
    236  1.1  mrg   return (__m256i) __builtin_ia32_vpopcountw_v16hi_mask ((__v16hi) __A,
    237  1.1  mrg 						(__v16hi)
    238  1.1  mrg 						_mm256_setzero_si256 (),
    239  1.1  mrg 						(__mmask16) __U);
    240  1.1  mrg }
    241  1.1  mrg 
    242  1.1  mrg extern __inline __m128i
    243  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    244  1.1  mrg _mm_mask_popcnt_epi8 (__m128i __W, __mmask16 __U, __m128i __A)
    245  1.1  mrg {
    246  1.1  mrg   return (__m128i) __builtin_ia32_vpopcountb_v16qi_mask ((__v16qi) __A,
    247  1.1  mrg 							 (__v16qi) __W,
    248  1.1  mrg 							 (__mmask16) __U);
    249  1.1  mrg }
    250  1.1  mrg 
    251  1.1  mrg extern __inline __m128i
    252  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    253  1.1  mrg _mm_maskz_popcnt_epi8 (__mmask16 __U, __m128i __A)
    254  1.1  mrg {
    255  1.1  mrg   return (__m128i) __builtin_ia32_vpopcountb_v16qi_mask ((__v16qi) __A,
    256  1.1  mrg 							 (__v16qi)
    257  1.1  mrg 							 _mm_setzero_si128 (),
    258  1.1  mrg 							 (__mmask16) __U);
    259  1.1  mrg }
    260  1.1  mrg extern __inline __m128i
    261  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    262  1.1  mrg _mm_mask_popcnt_epi16 (__m128i __W, __mmask8 __U, __m128i __A)
    263  1.1  mrg {
    264  1.1  mrg   return (__m128i) __builtin_ia32_vpopcountw_v8hi_mask ((__v8hi) __A,
    265  1.1  mrg 							(__v8hi) __W,
    266  1.1  mrg 							(__mmask8) __U);
    267  1.1  mrg }
    268  1.1  mrg 
    269  1.1  mrg extern __inline __m128i
    270  1.1  mrg __attribute__((__gnu_inline__, __always_inline__, __artificial__))
    271  1.1  mrg _mm_maskz_popcnt_epi16 (__mmask8 __U, __m128i __A)
    272  1.1  mrg {
    273  1.1  mrg   return (__m128i) __builtin_ia32_vpopcountw_v8hi_mask ((__v8hi) __A,
    274  1.1  mrg 							(__v8hi)
    275  1.1  mrg 							_mm_setzero_si128 (),
    276  1.1  mrg 							(__mmask8) __U);
    277  1.1  mrg }
    278  1.1  mrg #ifdef __DISABLE_AVX512BITALGVL__
    279  1.1  mrg #undef __DISABLE_AVX512BITALGVL__
    280  1.1  mrg #pragma GCC pop_options
    281  1.1  mrg #endif /* __DISABLE_AVX512BITALGBW__ */
    282  1.1  mrg 
    283  1.1  mrg #endif /* _AVX512BITALGINTRIN_H_INCLUDED */
    284