i386.h revision 1.1.1.1.8.2
1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 4 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 Under Section 7 of GPL version 3, you are granted additional 19 permissions described in the GCC Runtime Library Exception, version 20 3.1, as published by the Free Software Foundation. 21 22 You should have received a copy of the GNU General Public License and 23 a copy of the GCC Runtime Library Exception along with this program; 24 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 25 <http://www.gnu.org/licenses/>. */ 26 27 /* The purpose of this file is to define the characteristics of the i386, 28 independent of assembler syntax or operating system. 29 30 Three other files build on this one to describe a specific assembler syntax: 31 bsd386.h, att386.h, and sun386.h. 32 33 The actual tm.h file for a particular system should include 34 this file, and then the file for the appropriate assembler syntax. 35 36 Many macros that specify assembler syntax are omitted entirely from 37 this file because they really belong in the files for particular 38 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 39 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 40 that start with ASM_ or end in ASM_OP. */ 41 42 /* Redefines for option macros. */ 43 44 #define TARGET_64BIT OPTION_ISA_64BIT 45 #define TARGET_MMX OPTION_ISA_MMX 46 #define TARGET_3DNOW OPTION_ISA_3DNOW 47 #define TARGET_3DNOW_A OPTION_ISA_3DNOW_A 48 #define TARGET_SSE OPTION_ISA_SSE 49 #define TARGET_SSE2 OPTION_ISA_SSE2 50 #define TARGET_SSE3 OPTION_ISA_SSE3 51 #define TARGET_SSSE3 OPTION_ISA_SSSE3 52 #define TARGET_SSE4_1 OPTION_ISA_SSE4_1 53 #define TARGET_SSE4_2 OPTION_ISA_SSE4_2 54 #define TARGET_AVX OPTION_ISA_AVX 55 #define TARGET_FMA OPTION_ISA_FMA 56 #define TARGET_SSE4A OPTION_ISA_SSE4A 57 #define TARGET_FMA4 OPTION_ISA_FMA4 58 #define TARGET_XOP OPTION_ISA_XOP 59 #define TARGET_LWP OPTION_ISA_LWP 60 #define TARGET_ROUND OPTION_ISA_ROUND 61 #define TARGET_ABM OPTION_ISA_ABM 62 #define TARGET_POPCNT OPTION_ISA_POPCNT 63 #define TARGET_SAHF OPTION_ISA_SAHF 64 #define TARGET_MOVBE OPTION_ISA_MOVBE 65 #define TARGET_CRC32 OPTION_ISA_CRC32 66 #define TARGET_AES OPTION_ISA_AES 67 #define TARGET_PCLMUL OPTION_ISA_PCLMUL 68 #define TARGET_CMPXCHG16B OPTION_ISA_CX16 69 70 71 /* SSE4.1 defines round instructions */ 72 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 73 #define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) 74 75 #include "config/vxworks-dummy.h" 76 77 /* Algorithm to expand string function with. */ 78 enum stringop_alg 79 { 80 no_stringop, 81 libcall, 82 rep_prefix_1_byte, 83 rep_prefix_4_byte, 84 rep_prefix_8_byte, 85 loop_1_byte, 86 loop, 87 unrolled_loop 88 }; 89 90 #define NAX_STRINGOP_ALGS 4 91 92 /* Specify what algorithm to use for stringops on known size. 93 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 94 known at compile time or estimated via feedback, the SIZE array 95 is walked in order until MAX is greater then the estimate (or -1 96 means infinity). Corresponding ALG is used then. 97 For example initializer: 98 {{256, loop}, {-1, rep_prefix_4_byte}} 99 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 100 be used otherwise. */ 101 struct stringop_algs 102 { 103 const enum stringop_alg unknown_size; 104 const struct stringop_strategy { 105 const int max; 106 const enum stringop_alg alg; 107 } size [NAX_STRINGOP_ALGS]; 108 }; 109 110 /* Define the specific costs for a given cpu */ 111 112 struct processor_costs { 113 const int add; /* cost of an add instruction */ 114 const int lea; /* cost of a lea instruction */ 115 const int shift_var; /* variable shift costs */ 116 const int shift_const; /* constant shift costs */ 117 const int mult_init[5]; /* cost of starting a multiply 118 in QImode, HImode, SImode, DImode, TImode*/ 119 const int mult_bit; /* cost of multiply per each bit set */ 120 const int divide[5]; /* cost of a divide/mod 121 in QImode, HImode, SImode, DImode, TImode*/ 122 int movsx; /* The cost of movsx operation. */ 123 int movzx; /* The cost of movzx operation. */ 124 const int large_insn; /* insns larger than this cost more */ 125 const int move_ratio; /* The threshold of number of scalar 126 memory-to-memory move insns. */ 127 const int movzbl_load; /* cost of loading using movzbl */ 128 const int int_load[3]; /* cost of loading integer registers 129 in QImode, HImode and SImode relative 130 to reg-reg move (2). */ 131 const int int_store[3]; /* cost of storing integer register 132 in QImode, HImode and SImode */ 133 const int fp_move; /* cost of reg,reg fld/fst */ 134 const int fp_load[3]; /* cost of loading FP register 135 in SFmode, DFmode and XFmode */ 136 const int fp_store[3]; /* cost of storing FP register 137 in SFmode, DFmode and XFmode */ 138 const int mmx_move; /* cost of moving MMX register. */ 139 const int mmx_load[2]; /* cost of loading MMX register 140 in SImode and DImode */ 141 const int mmx_store[2]; /* cost of storing MMX register 142 in SImode and DImode */ 143 const int sse_move; /* cost of moving SSE register. */ 144 const int sse_load[3]; /* cost of loading SSE register 145 in SImode, DImode and TImode*/ 146 const int sse_store[3]; /* cost of storing SSE register 147 in SImode, DImode and TImode*/ 148 const int mmxsse_to_integer; /* cost of moving mmxsse register to 149 integer and vice versa. */ 150 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 151 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 152 const int prefetch_block; /* bytes moved to cache for prefetch. */ 153 const int simultaneous_prefetches; /* number of parallel prefetch 154 operations. */ 155 const int branch_cost; /* Default value for BRANCH_COST. */ 156 const int fadd; /* cost of FADD and FSUB instructions. */ 157 const int fmul; /* cost of FMUL instruction. */ 158 const int fdiv; /* cost of FDIV instruction. */ 159 const int fabs; /* cost of FABS instruction. */ 160 const int fchs; /* cost of FCHS instruction. */ 161 const int fsqrt; /* cost of FSQRT instruction. */ 162 /* Specify what algorithm 163 to use for stringops on unknown size. */ 164 struct stringop_algs memcpy[2], memset[2]; 165 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding 166 load and store. */ 167 const int scalar_load_cost; /* Cost of scalar load. */ 168 const int scalar_store_cost; /* Cost of scalar store. */ 169 const int vec_stmt_cost; /* Cost of any vector operation, excluding 170 load, store, vector-to-scalar and 171 scalar-to-vector operation. */ 172 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ 173 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ 174 const int vec_align_load_cost; /* Cost of aligned vector load. */ 175 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 176 const int vec_store_cost; /* Cost of vector store. */ 177 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 178 cost model. */ 179 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 180 vectorizer cost model. */ 181 }; 182 183 extern const struct processor_costs *ix86_cost; 184 extern const struct processor_costs ix86_size_cost; 185 186 #define ix86_cur_cost() \ 187 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 188 189 /* Macros used in the machine description to test the flags. */ 190 191 /* configure can arrange to make this 2, to force a 486. */ 192 193 #ifndef TARGET_CPU_DEFAULT 194 #define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic 195 #endif 196 197 #ifndef TARGET_FPMATH_DEFAULT 198 #define TARGET_FPMATH_DEFAULT \ 199 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 200 #endif 201 202 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 203 204 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 205 compile-time constant. */ 206 #ifdef IN_LIBGCC2 207 #undef TARGET_64BIT 208 #ifdef __x86_64__ 209 #define TARGET_64BIT 1 210 #else 211 #define TARGET_64BIT 0 212 #endif 213 #else 214 #ifndef TARGET_BI_ARCH 215 #undef TARGET_64BIT 216 #if TARGET_64BIT_DEFAULT 217 #define TARGET_64BIT 1 218 #else 219 #define TARGET_64BIT 0 220 #endif 221 #endif 222 #endif 223 224 #define HAS_LONG_COND_BRANCH 1 225 #define HAS_LONG_UNCOND_BRANCH 1 226 227 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 228 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 229 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 230 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 231 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 232 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 233 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 234 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 235 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 236 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 237 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 238 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 239 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 240 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 241 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 242 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 243 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) 244 245 /* Feature tests against the various tunings. */ 246 enum ix86_tune_indices { 247 X86_TUNE_USE_LEAVE, 248 X86_TUNE_PUSH_MEMORY, 249 X86_TUNE_ZERO_EXTEND_WITH_AND, 250 X86_TUNE_UNROLL_STRLEN, 251 X86_TUNE_DEEP_BRANCH_PREDICTION, 252 X86_TUNE_BRANCH_PREDICTION_HINTS, 253 X86_TUNE_DOUBLE_WITH_ADD, 254 X86_TUNE_USE_SAHF, 255 X86_TUNE_MOVX, 256 X86_TUNE_PARTIAL_REG_STALL, 257 X86_TUNE_PARTIAL_FLAG_REG_STALL, 258 X86_TUNE_USE_HIMODE_FIOP, 259 X86_TUNE_USE_SIMODE_FIOP, 260 X86_TUNE_USE_MOV0, 261 X86_TUNE_USE_CLTD, 262 X86_TUNE_USE_XCHGB, 263 X86_TUNE_SPLIT_LONG_MOVES, 264 X86_TUNE_READ_MODIFY_WRITE, 265 X86_TUNE_READ_MODIFY, 266 X86_TUNE_PROMOTE_QIMODE, 267 X86_TUNE_FAST_PREFIX, 268 X86_TUNE_SINGLE_STRINGOP, 269 X86_TUNE_QIMODE_MATH, 270 X86_TUNE_HIMODE_MATH, 271 X86_TUNE_PROMOTE_QI_REGS, 272 X86_TUNE_PROMOTE_HI_REGS, 273 X86_TUNE_ADD_ESP_4, 274 X86_TUNE_ADD_ESP_8, 275 X86_TUNE_SUB_ESP_4, 276 X86_TUNE_SUB_ESP_8, 277 X86_TUNE_INTEGER_DFMODE_MOVES, 278 X86_TUNE_PARTIAL_REG_DEPENDENCY, 279 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, 280 X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL, 281 X86_TUNE_SSE_SPLIT_REGS, 282 X86_TUNE_SSE_TYPELESS_STORES, 283 X86_TUNE_SSE_LOAD0_BY_PXOR, 284 X86_TUNE_MEMORY_MISMATCH_STALL, 285 X86_TUNE_PROLOGUE_USING_MOVE, 286 X86_TUNE_EPILOGUE_USING_MOVE, 287 X86_TUNE_SHIFT1, 288 X86_TUNE_USE_FFREEP, 289 X86_TUNE_INTER_UNIT_MOVES, 290 X86_TUNE_INTER_UNIT_CONVERSIONS, 291 X86_TUNE_FOUR_JUMP_LIMIT, 292 X86_TUNE_SCHEDULE, 293 X86_TUNE_USE_BT, 294 X86_TUNE_USE_INCDEC, 295 X86_TUNE_PAD_RETURNS, 296 X86_TUNE_EXT_80387_CONSTANTS, 297 X86_TUNE_SHORTEN_X87_SSE, 298 X86_TUNE_AVOID_VECTOR_DECODE, 299 X86_TUNE_PROMOTE_HIMODE_IMUL, 300 X86_TUNE_SLOW_IMUL_IMM32_MEM, 301 X86_TUNE_SLOW_IMUL_IMM8, 302 X86_TUNE_MOVE_M1_VIA_OR, 303 X86_TUNE_NOT_UNPAIRABLE, 304 X86_TUNE_NOT_VECTORMODE, 305 X86_TUNE_USE_VECTOR_FP_CONVERTS, 306 X86_TUNE_USE_VECTOR_CONVERTS, 307 X86_TUNE_FUSE_CMP_AND_BRANCH, 308 X86_TUNE_OPT_AGU, 309 310 X86_TUNE_LAST 311 }; 312 313 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 314 315 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 316 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 317 #define TARGET_ZERO_EXTEND_WITH_AND \ 318 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 319 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 320 #define TARGET_DEEP_BRANCH_PREDICTION \ 321 ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION] 322 #define TARGET_BRANCH_PREDICTION_HINTS \ 323 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 324 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 325 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 326 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 327 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 328 #define TARGET_PARTIAL_FLAG_REG_STALL \ 329 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 330 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 331 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 332 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 333 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 334 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 335 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 336 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 337 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 338 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 339 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 340 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 341 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 342 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 343 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 344 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 345 #define TARGET_ADD_ESP_4 ix86_tune_features[X86_TUNE_ADD_ESP_4] 346 #define TARGET_ADD_ESP_8 ix86_tune_features[X86_TUNE_ADD_ESP_8] 347 #define TARGET_SUB_ESP_4 ix86_tune_features[X86_TUNE_SUB_ESP_4] 348 #define TARGET_SUB_ESP_8 ix86_tune_features[X86_TUNE_SUB_ESP_8] 349 #define TARGET_INTEGER_DFMODE_MOVES \ 350 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 351 #define TARGET_PARTIAL_REG_DEPENDENCY \ 352 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 353 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 354 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 355 #define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \ 356 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL] 357 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 358 #define TARGET_SSE_TYPELESS_STORES \ 359 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 360 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 361 #define TARGET_MEMORY_MISMATCH_STALL \ 362 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 363 #define TARGET_PROLOGUE_USING_MOVE \ 364 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 365 #define TARGET_EPILOGUE_USING_MOVE \ 366 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 367 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 368 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 369 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] 370 #define TARGET_INTER_UNIT_CONVERSIONS\ 371 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 372 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 373 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 374 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 375 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 376 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 377 #define TARGET_EXT_80387_CONSTANTS \ 378 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 379 #define TARGET_SHORTEN_X87_SSE ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE] 380 #define TARGET_AVOID_VECTOR_DECODE \ 381 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 382 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 383 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 384 #define TARGET_SLOW_IMUL_IMM32_MEM \ 385 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 386 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 387 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 388 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 389 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 390 #define TARGET_USE_VECTOR_FP_CONVERTS \ 391 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 392 #define TARGET_USE_VECTOR_CONVERTS \ 393 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 394 #define TARGET_FUSE_CMP_AND_BRANCH \ 395 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] 396 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 397 398 /* Feature tests against the various architecture variations. */ 399 enum ix86_arch_indices { 400 X86_ARCH_CMOV, 401 X86_ARCH_CMPXCHG, 402 X86_ARCH_CMPXCHG8B, 403 X86_ARCH_XADD, 404 X86_ARCH_BSWAP, 405 406 X86_ARCH_LAST 407 }; 408 409 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 410 411 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 412 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 413 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 414 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 415 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 416 417 /* For sane SSE instruction set generation we need fcomi instruction. 418 It is safe to enable all CMOVE instructions. */ 419 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE) 420 421 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 422 423 extern int x86_prefetch_sse; 424 425 #define TARGET_PREFETCH_SSE x86_prefetch_sse 426 427 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 428 429 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 430 #define TARGET_MIX_SSE_I387 \ 431 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 432 433 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 434 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 435 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 436 #define TARGET_SUN_TLS 0 437 438 extern int ix86_isa_flags; 439 440 #ifndef TARGET_64BIT_DEFAULT 441 #define TARGET_64BIT_DEFAULT 0 442 #endif 443 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 444 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 445 #endif 446 447 /* Fence to use after loop using storent. */ 448 449 extern tree x86_mfence; 450 #define FENCE_FOLLOWING_MOVNT x86_mfence 451 452 /* Once GDB has been enhanced to deal with functions without frame 453 pointers, we can change this to allow for elimination of 454 the frame pointer in leaf functions. */ 455 #define TARGET_DEFAULT 0 456 457 /* Extra bits to force. */ 458 #define TARGET_SUBTARGET_DEFAULT 0 459 #define TARGET_SUBTARGET_ISA_DEFAULT 0 460 461 /* Extra bits to force on w/ 32-bit mode. */ 462 #define TARGET_SUBTARGET32_DEFAULT 0 463 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 464 465 /* Extra bits to force on w/ 64-bit mode. */ 466 #define TARGET_SUBTARGET64_DEFAULT 0 467 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 468 469 /* This is not really a target flag, but is done this way so that 470 it's analogous to similar code for Mach-O on PowerPC. darwin.h 471 redefines this to 1. */ 472 #define TARGET_MACHO 0 473 474 /* Likewise, for the Windows 64-bit ABI. */ 475 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 476 477 /* Available call abi. */ 478 enum calling_abi 479 { 480 SYSV_ABI = 0, 481 MS_ABI = 1 482 }; 483 484 /* The abi used by target. */ 485 extern enum calling_abi ix86_abi; 486 487 /* The default abi used by target. */ 488 #define DEFAULT_ABI SYSV_ABI 489 490 /* Subtargets may reset this to 1 in order to enable 96-bit long double 491 with the rounding mode forced to 53 bits. */ 492 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 493 494 /* Sometimes certain combinations of command options do not make 495 sense on a particular target machine. You can define a macro 496 `OVERRIDE_OPTIONS' to take account of this. This macro, if 497 defined, is executed once just after all the command options have 498 been parsed. 499 500 Don't use this macro to turn on various extra optimizations for 501 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 502 503 #define OVERRIDE_OPTIONS override_options (true) 504 505 /* Define this to change the optimizations performed by default. */ 506 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 507 optimization_options ((LEVEL), (SIZE)) 508 509 /* -march=native handling only makes sense with compiler running on 510 an x86 or x86_64 chip. If changing this condition, also change 511 the condition in driver-i386.c. */ 512 #if defined(__i386__) || defined(__x86_64__) 513 /* In driver-i386.c. */ 514 extern const char *host_detect_local_cpu (int argc, const char **argv); 515 #define EXTRA_SPEC_FUNCTIONS \ 516 { "local_cpu_detect", host_detect_local_cpu }, 517 #define HAVE_LOCAL_CPU_DETECT 518 #endif 519 520 #if TARGET_64BIT_DEFAULT 521 #define OPT_ARCH64 "!m32" 522 #define OPT_ARCH32 "m32" 523 #else 524 #define OPT_ARCH64 "m64" 525 #define OPT_ARCH32 "!m64" 526 #endif 527 528 /* Support for configure-time defaults of some command line options. 529 The order here is important so that -march doesn't squash the 530 tune or cpu values. */ 531 #define OPTION_DEFAULT_SPECS \ 532 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 533 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 534 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 535 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 536 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 537 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 538 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 539 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 540 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 541 542 /* Specs for the compiler proper */ 543 544 #ifndef CC1_CPU_SPEC 545 #define CC1_CPU_SPEC_1 "\ 546 %{mcpu=*:-mtune=%* \ 547 %n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \ 548 %<mcpu=* \ 549 %{mintel-syntax:-masm=intel \ 550 %n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \ 551 %{msse5:-mavx \ 552 %n'-msse5' was removed.\n} \ 553 %{mno-intel-syntax:-masm=att \ 554 %n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}" 555 556 #ifndef HAVE_LOCAL_CPU_DETECT 557 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 558 #else 559 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 560 "%{march=native:%<march=native %:local_cpu_detect(arch) \ 561 %{!mtune=*:%<mtune=native %:local_cpu_detect(tune)}} \ 562 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 563 #endif 564 #endif 565 566 /* Target CPU builtins. */ 568 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 569 570 /* Target Pragmas. */ 571 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 572 573 enum target_cpu_default 574 { 575 TARGET_CPU_DEFAULT_generic = 0, 576 577 TARGET_CPU_DEFAULT_i386, 578 TARGET_CPU_DEFAULT_i486, 579 TARGET_CPU_DEFAULT_pentium, 580 TARGET_CPU_DEFAULT_pentium_mmx, 581 TARGET_CPU_DEFAULT_pentiumpro, 582 TARGET_CPU_DEFAULT_pentium2, 583 TARGET_CPU_DEFAULT_pentium3, 584 TARGET_CPU_DEFAULT_pentium4, 585 TARGET_CPU_DEFAULT_pentium_m, 586 TARGET_CPU_DEFAULT_prescott, 587 TARGET_CPU_DEFAULT_nocona, 588 TARGET_CPU_DEFAULT_core2, 589 TARGET_CPU_DEFAULT_atom, 590 591 TARGET_CPU_DEFAULT_geode, 592 TARGET_CPU_DEFAULT_k6, 593 TARGET_CPU_DEFAULT_k6_2, 594 TARGET_CPU_DEFAULT_k6_3, 595 TARGET_CPU_DEFAULT_athlon, 596 TARGET_CPU_DEFAULT_athlon_sse, 597 TARGET_CPU_DEFAULT_k8, 598 TARGET_CPU_DEFAULT_amdfam10, 599 600 TARGET_CPU_DEFAULT_max 601 }; 602 603 #ifndef CC1_SPEC 604 #define CC1_SPEC "%(cc1_cpu) " 605 #endif 606 607 /* This macro defines names of additional specifications to put in the 608 specs that can be used in various specifications like CC1_SPEC. Its 609 definition is an initializer with a subgrouping for each command option. 610 611 Each subgrouping contains a string constant, that defines the 612 specification name, and a string constant that used by the GCC driver 613 program. 614 615 Do not define this macro if it does not need to do anything. */ 616 617 #ifndef SUBTARGET_EXTRA_SPECS 618 #define SUBTARGET_EXTRA_SPECS 619 #endif 620 621 #define EXTRA_SPECS \ 622 { "cc1_cpu", CC1_CPU_SPEC }, \ 623 SUBTARGET_EXTRA_SPECS 624 625 627 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the 628 FPU, assume that the fpcw is set to extended precision; when using 629 only SSE, rounding is correct; when using both SSE and the FPU, 630 the rounding precision is indeterminate, since either may be chosen 631 apparently at random. */ 632 #define TARGET_FLT_EVAL_METHOD \ 633 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 634 635 /* Whether to allow x87 floating-point arithmetic on MODE (one of 636 SFmode, DFmode and XFmode) in the current excess precision 637 configuration. */ 638 #define X87_ENABLE_ARITH(MODE) \ 639 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) 640 641 /* Likewise, whether to allow direct conversions from integer mode 642 IMODE (HImode, SImode or DImode) to MODE. */ 643 #define X87_ENABLE_FLOAT(MODE, IMODE) \ 644 (flag_excess_precision == EXCESS_PRECISION_FAST \ 645 || (MODE) == XFmode \ 646 || ((MODE) == DFmode && (IMODE) == SImode) \ 647 || (IMODE) == HImode) 648 649 /* target machine storage layout */ 650 651 #define SHORT_TYPE_SIZE 16 652 #define INT_TYPE_SIZE 32 653 #define FLOAT_TYPE_SIZE 32 654 #define LONG_TYPE_SIZE BITS_PER_WORD 655 #define DOUBLE_TYPE_SIZE 64 656 #define LONG_LONG_TYPE_SIZE 64 657 #define LONG_DOUBLE_TYPE_SIZE 80 658 659 #define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE 660 661 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 662 #define MAX_BITS_PER_WORD 64 663 #else 664 #define MAX_BITS_PER_WORD 32 665 #endif 666 667 /* Define this if most significant byte of a word is the lowest numbered. */ 668 /* That is true on the 80386. */ 669 670 #define BITS_BIG_ENDIAN 0 671 672 /* Define this if most significant byte of a word is the lowest numbered. */ 673 /* That is not true on the 80386. */ 674 #define BYTES_BIG_ENDIAN 0 675 676 /* Define this if most significant word of a multiword number is the lowest 677 numbered. */ 678 /* Not true for 80386 */ 679 #define WORDS_BIG_ENDIAN 0 680 681 /* Width of a word, in units (bytes). */ 682 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 683 #ifdef IN_LIBGCC2 684 #define MIN_UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 685 #else 686 #define MIN_UNITS_PER_WORD 4 687 #endif 688 689 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 690 #define PARM_BOUNDARY BITS_PER_WORD 691 692 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 693 #define STACK_BOUNDARY \ 694 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 695 696 /* Stack boundary of the main function guaranteed by OS. */ 697 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 698 699 /* Minimum stack boundary. */ 700 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 701 702 /* Boundary (in *bits*) on which the stack pointer prefers to be 703 aligned; the compiler cannot rely on having this alignment. */ 704 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 705 706 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 707 both 32bit and 64bit, to support codes that need 128 bit stack 708 alignment for SSE instructions, but can't realign the stack. */ 709 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 710 711 /* 1 if -mstackrealign should be turned on by default. It will 712 generate an alternate prologue and epilogue that realigns the 713 runtime stack if nessary. This supports mixing codes that keep a 714 4-byte aligned stack, as specified by i386 psABI, with codes that 715 need a 16-byte aligned stack, as required by SSE instructions. */ 716 #define STACK_REALIGN_DEFAULT 0 717 718 /* Boundary (in *bits*) on which the incoming stack is aligned. */ 719 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 720 721 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 722 mandatory for the 64-bit ABI, and may or may not be true for other 723 operating systems. */ 724 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 725 726 /* Minimum allocation boundary for the code of a function. */ 727 #define FUNCTION_BOUNDARY 8 728 729 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 730 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 731 732 /* Alignment of field after `int : 0' in a structure. */ 733 734 #define EMPTY_FIELD_BOUNDARY BITS_PER_WORD 735 736 /* Minimum size in bits of the largest boundary to which any 737 and all fundamental data types supported by the hardware 738 might need to be aligned. No data type wants to be aligned 739 rounder than this. 740 741 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 742 and Pentium Pro XFmode values at 128 bit boundaries. */ 743 744 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128) 745 746 /* Maximum stack alignment. */ 747 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 748 749 /* Alignment value for attribute ((aligned)). It is a constant since 750 it is the part of the ABI. We shouldn't change it with -mavx. */ 751 #define ATTRIBUTE_ALIGNED_VALUE 128 752 753 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 754 #define ALIGN_MODE_128(MODE) \ 755 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 756 757 /* The published ABIs say that doubles should be aligned on word 758 boundaries, so lower the alignment for structure fields unless 759 -malign-double is set. */ 760 761 /* ??? Blah -- this macro is used directly by libobjc. Since it 762 supports no vector modes, cut out the complexity and fall back 763 on BIGGEST_FIELD_ALIGNMENT. */ 764 #ifdef IN_TARGET_LIBS 765 #ifdef __x86_64__ 766 #define BIGGEST_FIELD_ALIGNMENT 128 767 #else 768 #define BIGGEST_FIELD_ALIGNMENT 32 769 #endif 770 #else 771 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 772 x86_field_alignment (FIELD, COMPUTED) 773 #endif 774 775 /* If defined, a C expression to compute the alignment given to a 776 constant that is being placed in memory. EXP is the constant 777 and ALIGN is the alignment that the object would ordinarily have. 778 The value of this macro is used instead of that alignment to align 779 the object. 780 781 If this macro is not defined, then ALIGN is used. 782 783 The typical use of this macro is to increase alignment for string 784 constants to be word aligned so that `strcpy' calls that copy 785 constants can be done inline. */ 786 787 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 788 789 /* If defined, a C expression to compute the alignment for a static 790 variable. TYPE is the data type, and ALIGN is the alignment that 791 the object would ordinarily have. The value of this macro is used 792 instead of that alignment to align the object. 793 794 If this macro is not defined, then ALIGN is used. 795 796 One use of this macro is to increase alignment of medium-size 797 data to make it all fit in fewer cache lines. Another is to 798 cause character arrays to be word-aligned so that `strcpy' calls 799 that copy constants to character arrays can be done inline. */ 800 801 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 802 803 /* If defined, a C expression to compute the alignment for a local 804 variable. TYPE is the data type, and ALIGN is the alignment that 805 the object would ordinarily have. The value of this macro is used 806 instead of that alignment to align the object. 807 808 If this macro is not defined, then ALIGN is used. 809 810 One use of this macro is to increase alignment of medium-size 811 data to make it all fit in fewer cache lines. */ 812 813 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 814 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 815 816 /* If defined, a C expression to compute the alignment for stack slot. 817 TYPE is the data type, MODE is the widest mode available, and ALIGN 818 is the alignment that the slot would ordinarily have. The value of 819 this macro is used instead of that alignment to align the slot. 820 821 If this macro is not defined, then ALIGN is used when TYPE is NULL, 822 Otherwise, LOCAL_ALIGNMENT will be used. 823 824 One use of this macro is to set alignment of stack slot to the 825 maximum alignment of all possible modes which the slot may have. */ 826 827 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 828 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 829 830 /* If defined, a C expression to compute the alignment for a local 831 variable DECL. 832 833 If this macro is not defined, then 834 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 835 836 One use of this macro is to increase alignment of medium-size 837 data to make it all fit in fewer cache lines. */ 838 839 #define LOCAL_DECL_ALIGNMENT(DECL) \ 840 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 841 842 /* If defined, a C expression to compute the minimum required alignment 843 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 844 MODE, assuming normal alignment ALIGN. 845 846 If this macro is not defined, then (ALIGN) will be used. */ 847 848 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 849 ix86_minimum_alignment (EXP, MODE, ALIGN) 850 851 852 /* If defined, a C expression that gives the alignment boundary, in 853 bits, of an argument with the specified mode and type. If it is 854 not defined, `PARM_BOUNDARY' is used for all arguments. */ 855 856 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 857 ix86_function_arg_boundary ((MODE), (TYPE)) 858 859 /* Set this nonzero if move instructions will actually fail to work 860 when given unaligned data. */ 861 #define STRICT_ALIGNMENT 0 862 863 /* If bit field type is int, don't let it cross an int, 864 and give entire struct the alignment of an int. */ 865 /* Required on the 386 since it doesn't have bit-field insns. */ 866 #define PCC_BITFIELD_TYPE_MATTERS 1 867 868 /* Standard register usage. */ 870 871 /* This processor has special stack-like registers. See reg-stack.c 872 for details. */ 873 874 #define STACK_REGS 875 876 #define IS_STACK_MODE(MODE) \ 877 (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH)) \ 878 || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH)) \ 879 || (MODE) == XFmode) 880 881 /* Cover class containing the stack registers. */ 882 #define STACK_REG_COVER_CLASS FLOAT_REGS 883 884 /* Number of actual hardware registers. 885 The hardware registers are assigned numbers for the compiler 886 from 0 to just below FIRST_PSEUDO_REGISTER. 887 All registers that the compiler knows about must be given numbers, 888 even those that are not normally considered general registers. 889 890 In the 80386 we give the 8 general purpose registers the numbers 0-7. 891 We number the floating point registers 8-15. 892 Note that registers 0-7 can be accessed as a short or int, 893 while only 0-3 may be used with byte `mov' instructions. 894 895 Reg 16 does not correspond to any hardware register, but instead 896 appears in the RTL as an argument pointer prior to reload, and is 897 eliminated during reloading in favor of either the stack or frame 898 pointer. */ 899 900 #define FIRST_PSEUDO_REGISTER 53 901 902 /* Number of hardware registers that go into the DWARF-2 unwind info. 903 If not defined, equals FIRST_PSEUDO_REGISTER. */ 904 905 #define DWARF_FRAME_REGISTERS 17 906 907 /* 1 for registers that have pervasive standard uses 908 and are not available for the register allocator. 909 On the 80386, the stack pointer is such, as is the arg pointer. 910 911 The value is zero if the register is not fixed on either 32 or 912 64 bit targets, one if the register if fixed on both 32 and 64 913 bit targets, two if it is only fixed on 32bit targets and three 914 if its only fixed on 64bit targets. 915 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 916 */ 917 #define FIXED_REGISTERS \ 918 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 919 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 920 /*arg,flags,fpsr,fpcr,frame*/ \ 921 1, 1, 1, 1, 1, \ 922 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 923 0, 0, 0, 0, 0, 0, 0, 0, \ 924 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 925 0, 0, 0, 0, 0, 0, 0, 0, \ 926 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 927 2, 2, 2, 2, 2, 2, 2, 2, \ 928 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 929 2, 2, 2, 2, 2, 2, 2, 2 } 930 931 932 /* 1 for registers not available across function calls. 933 These must include the FIXED_REGISTERS and also any 934 registers that can be used without being saved. 935 The latter must include the registers where values are returned 936 and the register where structure-value addresses are passed. 937 Aside from that, you can include as many other registers as you like. 938 939 The value is zero if the register is not call used on either 32 or 940 64 bit targets, one if the register if call used on both 32 and 64 941 bit targets, two if it is only call used on 32bit targets and three 942 if its only call used on 64bit targets. 943 Proper values are computed in the CONDITIONAL_REGISTER_USAGE. 944 */ 945 #define CALL_USED_REGISTERS \ 946 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 947 { 1, 1, 1, 0, 3, 3, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 948 /*arg,flags,fpsr,fpcr,frame*/ \ 949 1, 1, 1, 1, 1, \ 950 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 951 1, 1, 1, 1, 1, 1, 1, 1, \ 952 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 953 1, 1, 1, 1, 1, 1, 1, 1, \ 954 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 955 1, 1, 1, 1, 2, 2, 2, 2, \ 956 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 957 1, 1, 1, 1, 1, 1, 1, 1 } 958 959 /* Order in which to allocate registers. Each register must be 960 listed once, even those in FIXED_REGISTERS. List frame pointer 961 late and fixed registers last. Note that, in general, we prefer 962 registers listed in CALL_USED_REGISTERS, keeping the others 963 available for storage of persistent values. 964 965 The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order, 966 so this is just empty initializer for array. */ 967 968 #define REG_ALLOC_ORDER \ 969 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 970 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 971 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 972 48, 49, 50, 51, 52 } 973 974 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order 975 to be rearranged based on a particular function. When using sse math, 976 we want to allocate SSE before x87 registers and vice versa. */ 977 978 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc () 979 980 981 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 982 983 /* Macro to conditionally modify fixed_regs/call_used_regs. */ 984 #define CONDITIONAL_REGISTER_USAGE ix86_conditional_register_usage () 985 986 /* Return number of consecutive hard regs needed starting at reg REGNO 987 to hold something of mode MODE. 988 This is ordinarily the length in words of a value of mode MODE 989 but can be less for certain modes in special long registers. 990 991 Actually there are no two word move instructions for consecutive 992 registers. And only registers 0-3 may have mov byte instructions 993 applied to them. 994 */ 995 996 #define HARD_REGNO_NREGS(REGNO, MODE) \ 997 (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 998 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 999 : ((MODE) == XFmode \ 1000 ? (TARGET_64BIT ? 2 : 3) \ 1001 : (MODE) == XCmode \ 1002 ? (TARGET_64BIT ? 4 : 6) \ 1003 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1004 1005 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 1006 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 1007 ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 1008 ? 0 \ 1009 : ((MODE) == XFmode || (MODE) == XCmode)) \ 1010 : 0) 1011 1012 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1013 1014 #define VALID_AVX256_REG_MODE(MODE) \ 1015 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1016 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) 1017 1018 #define VALID_SSE2_REG_MODE(MODE) \ 1019 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1020 || (MODE) == V2DImode || (MODE) == DFmode) 1021 1022 #define VALID_SSE_REG_MODE(MODE) \ 1023 ((MODE) == V1TImode || (MODE) == TImode \ 1024 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1025 || (MODE) == SFmode || (MODE) == TFmode) 1026 1027 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1028 ((MODE) == V2SFmode || (MODE) == SFmode) 1029 1030 #define VALID_MMX_REG_MODE(MODE) \ 1031 ((MODE == V1DImode) || (MODE) == DImode \ 1032 || (MODE) == V2SImode || (MODE) == SImode \ 1033 || (MODE) == V4HImode || (MODE) == V8QImode) 1034 1035 /* ??? No autovectorization into MMX or 3DNOW until we can reliably 1036 place emms and femms instructions. 1037 FIXME: AVX has 32byte floating point vector operations and 16byte 1038 integer vector operations. But vectorizer doesn't support 1039 different sizes for integer and floating point vectors. We limit 1040 vector size to 16byte. */ 1041 #define UNITS_PER_SIMD_WORD(MODE) \ 1042 (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16) \ 1043 : (TARGET_SSE ? 16 : UNITS_PER_WORD)) 1044 1045 #define VALID_DFP_MODE_P(MODE) \ 1046 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1047 1048 #define VALID_FP_MODE_P(MODE) \ 1049 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1050 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1051 1052 #define VALID_INT_MODE_P(MODE) \ 1053 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1054 || (MODE) == DImode \ 1055 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1056 || (MODE) == CDImode \ 1057 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1058 || (MODE) == TFmode || (MODE) == TCmode))) 1059 1060 /* Return true for modes passed in SSE registers. */ 1061 #define SSE_REG_MODE_P(MODE) \ 1062 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1063 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1064 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1065 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1066 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode) 1067 1068 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1069 1070 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1071 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1072 1073 /* Value is 1 if it is a good idea to tie two pseudo registers 1074 when one has mode MODE1 and one has mode MODE2. 1075 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1076 for any hard reg, then this must be 0 for correct output. */ 1077 1078 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 1079 1080 /* It is possible to write patterns to move flags; but until someone 1081 does it, */ 1082 #define AVOID_CCMODE_COPIES 1083 1084 /* Specify the modes required to caller save a given hard regno. 1085 We do this on i386 to prevent flags from being saved at all. 1086 1087 Kill any attempts to combine saving of modes. */ 1088 1089 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1090 (CC_REGNO_P (REGNO) ? VOIDmode \ 1091 : MMX_REGNO_P (REGNO) ? V8QImode \ 1092 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1093 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1094 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1095 : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode \ 1096 : (MODE)) 1097 1098 /* Specify the registers used for certain standard purposes. 1099 The values of these macros are register numbers. */ 1100 1101 /* on the 386 the pc register is %eip, and is not usable as a general 1102 register. The ordinary mov instructions won't work */ 1103 /* #define PC_REGNUM */ 1104 1105 /* Register to use for pushing function arguments. */ 1106 #define STACK_POINTER_REGNUM 7 1107 1108 /* Base register for access to local variables of the function. */ 1109 #define HARD_FRAME_POINTER_REGNUM 6 1110 1111 /* Base register for access to local variables of the function. */ 1112 #define FRAME_POINTER_REGNUM 20 1113 1114 /* First floating point reg */ 1115 #define FIRST_FLOAT_REG 8 1116 1117 /* First & last stack-like regs */ 1118 #define FIRST_STACK_REG FIRST_FLOAT_REG 1119 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1120 1121 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1122 #define LAST_SSE_REG (FIRST_SSE_REG + 7) 1123 1124 #define FIRST_MMX_REG (LAST_SSE_REG + 1) 1125 #define LAST_MMX_REG (FIRST_MMX_REG + 7) 1126 1127 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1128 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1129 1130 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1131 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1132 1133 /* Override this in other tm.h files to cope with various OS lossage 1134 requiring a frame pointer. */ 1135 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1136 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1137 #endif 1138 1139 /* Make sure we can access arbitrary call frames. */ 1140 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1141 1142 /* Base register for access to arguments of the function. */ 1143 #define ARG_POINTER_REGNUM 16 1144 1145 /* Register to hold the addressing base for position independent 1146 code access to data items. We don't use PIC pointer for 64bit 1147 mode. Define the regnum to dummy value to prevent gcc from 1148 pessimizing code dealing with EBX. 1149 1150 To avoid clobbering a call-saved register unnecessarily, we renumber 1151 the pic register when possible. The change is visible after the 1152 prologue has been emitted. */ 1153 1154 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG 1155 1156 #define PIC_OFFSET_TABLE_REGNUM \ 1157 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1158 || !flag_pic ? INVALID_REGNUM \ 1159 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1160 : REAL_PIC_OFFSET_TABLE_REGNUM) 1161 1162 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1163 1164 /* This is overridden by <cygwin.h>. */ 1165 #define MS_AGGREGATE_RETURN 0 1166 1167 /* This is overridden by <netware.h>. */ 1168 #define KEEP_AGGREGATE_RETURN_POINTER 0 1169 1170 /* Define the classes of registers for register constraints in the 1172 machine description. Also define ranges of constants. 1173 1174 One of the classes must always be named ALL_REGS and include all hard regs. 1175 If there is more than one class, another class must be named NO_REGS 1176 and contain no registers. 1177 1178 The name GENERAL_REGS must be the name of a class (or an alias for 1179 another name such as ALL_REGS). This is the class of registers 1180 that is allowed by "g" or "r" in a register constraint. 1181 Also, registers outside this class are allocated only when 1182 instructions express preferences for them. 1183 1184 The classes must be numbered in nondecreasing order; that is, 1185 a larger-numbered class must never be contained completely 1186 in a smaller-numbered class. 1187 1188 For any two classes, it is very desirable that there be another 1189 class that represents their union. 1190 1191 It might seem that class BREG is unnecessary, since no useful 386 1192 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1193 and the "b" register constraint is useful in asms for syscalls. 1194 1195 The flags, fpsr and fpcr registers are in no class. */ 1196 1197 enum reg_class 1198 { 1199 NO_REGS, 1200 AREG, DREG, CREG, BREG, SIREG, DIREG, 1201 AD_REGS, /* %eax/%edx for DImode */ 1202 CLOBBERED_REGS, /* call-clobbered integers */ 1203 Q_REGS, /* %eax %ebx %ecx %edx */ 1204 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1205 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1206 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1207 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp %r8 - %r15*/ 1208 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1209 FLOAT_REGS, 1210 SSE_FIRST_REG, 1211 SSE_REGS, 1212 MMX_REGS, 1213 FP_TOP_SSE_REGS, 1214 FP_SECOND_SSE_REGS, 1215 FLOAT_SSE_REGS, 1216 FLOAT_INT_REGS, 1217 INT_SSE_REGS, 1218 FLOAT_INT_SSE_REGS, 1219 ALL_REGS, LIM_REG_CLASSES 1220 }; 1221 1222 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1223 1224 #define INTEGER_CLASS_P(CLASS) \ 1225 reg_class_subset_p ((CLASS), GENERAL_REGS) 1226 #define FLOAT_CLASS_P(CLASS) \ 1227 reg_class_subset_p ((CLASS), FLOAT_REGS) 1228 #define SSE_CLASS_P(CLASS) \ 1229 reg_class_subset_p ((CLASS), SSE_REGS) 1230 #define MMX_CLASS_P(CLASS) \ 1231 ((CLASS) == MMX_REGS) 1232 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1233 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1234 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1235 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1236 #define MAYBE_SSE_CLASS_P(CLASS) \ 1237 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1238 #define MAYBE_MMX_CLASS_P(CLASS) \ 1239 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1240 1241 #define Q_CLASS_P(CLASS) \ 1242 reg_class_subset_p ((CLASS), Q_REGS) 1243 1244 /* Give names of register classes as strings for dump file. */ 1245 1246 #define REG_CLASS_NAMES \ 1247 { "NO_REGS", \ 1248 "AREG", "DREG", "CREG", "BREG", \ 1249 "SIREG", "DIREG", \ 1250 "AD_REGS", \ 1251 "CLOBBERED_REGS", \ 1252 "Q_REGS", "NON_Q_REGS", \ 1253 "INDEX_REGS", \ 1254 "LEGACY_REGS", \ 1255 "GENERAL_REGS", \ 1256 "FP_TOP_REG", "FP_SECOND_REG", \ 1257 "FLOAT_REGS", \ 1258 "SSE_FIRST_REG", \ 1259 "SSE_REGS", \ 1260 "MMX_REGS", \ 1261 "FP_TOP_SSE_REGS", \ 1262 "FP_SECOND_SSE_REGS", \ 1263 "FLOAT_SSE_REGS", \ 1264 "FLOAT_INT_REGS", \ 1265 "INT_SSE_REGS", \ 1266 "FLOAT_INT_SSE_REGS", \ 1267 "ALL_REGS" } 1268 1269 /* Define which registers fit in which classes. This is an initializer 1270 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1271 1272 Note that the default setting of CLOBBERED_REGS is for 32-bit; this 1273 is adjusted by CONDITIONAL_REGISTER_USAGE for the 64-bit ABI in effect. */ 1274 1275 #define REG_CLASS_CONTENTS \ 1276 { { 0x00, 0x0 }, \ 1277 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1278 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1279 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1280 { 0x03, 0x0 }, /* AD_REGS */ \ 1281 { 0x07, 0x0 }, /* CLOBBERED_REGS */ \ 1282 { 0x0f, 0x0 }, /* Q_REGS */ \ 1283 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1284 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1285 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1286 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1287 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1288 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1289 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ 1290 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1291 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1292 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1293 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1294 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1295 { 0x1ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1296 { 0x1fe100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1297 { 0x1fe1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1298 { 0xffffffff,0x1fffff } \ 1299 } 1300 1301 /* The same information, inverted: 1302 Return the class number of the smallest class containing 1303 reg number REGNO. This could be a conditional expression 1304 or could index an array. */ 1305 1306 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1307 1308 /* When defined, the compiler allows registers explicitly used in the 1309 rtl to be used as spill registers but prevents the compiler from 1310 extending the lifetime of these registers. */ 1311 1312 #define SMALL_REGISTER_CLASSES 1 1313 1314 #define QI_REG_P(X) (REG_P (X) && REGNO (X) <= BX_REG) 1315 1316 #define GENERAL_REGNO_P(N) \ 1317 ((N) <= STACK_POINTER_REGNUM || REX_INT_REGNO_P (N)) 1318 1319 #define GENERAL_REG_P(X) \ 1320 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1321 1322 #define ANY_QI_REG_P(X) (TARGET_64BIT ? GENERAL_REG_P(X) : QI_REG_P (X)) 1323 1324 #define REX_INT_REGNO_P(N) \ 1325 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1326 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1327 1328 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 1329 #define FP_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1330 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1331 #define ANY_FP_REGNO_P(N) (FP_REGNO_P (N) || SSE_REGNO_P (N)) 1332 1333 #define X87_FLOAT_MODE_P(MODE) \ 1334 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1335 1336 #define SSE_REG_P(N) (REG_P (N) && SSE_REGNO_P (REGNO (N))) 1337 #define SSE_REGNO_P(N) \ 1338 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1339 || REX_SSE_REGNO_P (N)) 1340 1341 #define REX_SSE_REGNO_P(N) \ 1342 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1343 1344 #define SSE_REGNO(N) \ 1345 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1346 1347 #define SSE_FLOAT_MODE_P(MODE) \ 1348 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1349 1350 #define SSE_VEC_FLOAT_MODE_P(MODE) \ 1351 ((TARGET_SSE && (MODE) == V4SFmode) || (TARGET_SSE2 && (MODE) == V2DFmode)) 1352 1353 #define AVX_FLOAT_MODE_P(MODE) \ 1354 (TARGET_AVX && ((MODE) == SFmode || (MODE) == DFmode)) 1355 1356 #define AVX128_VEC_FLOAT_MODE_P(MODE) \ 1357 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode)) 1358 1359 #define AVX256_VEC_FLOAT_MODE_P(MODE) \ 1360 (TARGET_AVX && ((MODE) == V8SFmode || (MODE) == V4DFmode)) 1361 1362 #define AVX_VEC_FLOAT_MODE_P(MODE) \ 1363 (TARGET_AVX && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1364 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1365 1366 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1367 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1368 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1369 1370 #define MMX_REG_P(XOP) (REG_P (XOP) && MMX_REGNO_P (REGNO (XOP))) 1371 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1372 1373 #define STACK_REG_P(XOP) (REG_P (XOP) && STACK_REGNO_P (REGNO (XOP))) 1374 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1375 1376 #define STACK_TOP_P(XOP) (REG_P (XOP) && REGNO (XOP) == FIRST_STACK_REG) 1377 1378 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1379 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1380 1381 /* The class value for index registers, and the one for base regs. */ 1382 1383 #define INDEX_REG_CLASS INDEX_REGS 1384 #define BASE_REG_CLASS GENERAL_REGS 1385 1386 /* Place additional restrictions on the register class to use when it 1387 is necessary to be able to hold a value of mode MODE in a reload 1388 register for which class CLASS would ordinarily be used. */ 1389 1390 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1391 ((MODE) == QImode && !TARGET_64BIT \ 1392 && ((CLASS) == ALL_REGS || (CLASS) == GENERAL_REGS \ 1393 || (CLASS) == LEGACY_REGS || (CLASS) == INDEX_REGS) \ 1394 ? Q_REGS : (CLASS)) 1395 1396 /* Given an rtx X being reloaded into a reg required to be 1397 in class CLASS, return the class of reg to actually use. 1398 In general this is just CLASS; but on some machines 1399 in some cases it is preferable to use a more restrictive class. 1400 On the 80386 series, we prevent floating constants from being 1401 reloaded into floating registers (since no move-insn can do that) 1402 and we ensure that QImodes aren't reloaded into the esi or edi reg. */ 1403 1404 /* Put float CONST_DOUBLE in the constant pool instead of fp regs. 1405 QImode must go into class Q_REGS. 1406 Narrow ALL_REGS to GENERAL_REGS. This supports allowing movsf and 1407 movdf to do mem-to-mem moves through integer regs. */ 1408 1409 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1410 ix86_preferred_reload_class ((X), (CLASS)) 1411 1412 /* Discourage putting floating-point values in SSE registers unless 1413 SSE math is being used, and likewise for the 387 registers. */ 1414 1415 #define PREFERRED_OUTPUT_RELOAD_CLASS(X, CLASS) \ 1416 ix86_preferred_output_reload_class ((X), (CLASS)) 1417 1418 /* If we are copying between general and FP registers, we need a memory 1419 location. The same is true for SSE and MMX registers. */ 1420 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1421 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1422 1423 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. 1424 There is no need to emit full 64 bit move on 64 bit targets 1425 for integral modes that can be moved using 32 bit move. */ 1426 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1427 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ 1428 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1429 : MODE) 1430 1431 /* Return the maximum number of consecutive registers 1432 needed to represent mode MODE in a register of class CLASS. */ 1433 /* On the 80386, this is the size of MODE in words, 1434 except in the FP regs, where a single reg is always enough. */ 1435 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1436 (!MAYBE_INTEGER_CLASS_P (CLASS) \ 1437 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 1438 : (((((MODE) == XFmode ? 12 : GET_MODE_SIZE (MODE))) \ 1439 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 1440 1441 /* A C expression whose value is nonzero if pseudos that have been 1442 assigned to registers of class CLASS would likely be spilled 1443 because registers of CLASS are needed for spill registers. 1444 1445 The default value of this macro returns 1 if CLASS has exactly one 1446 register and zero otherwise. On most machines, this default 1447 should be used. Only define this macro to some other expression 1448 if pseudo allocated by `local-alloc.c' end up in memory because 1449 their hard registers were needed for spill registers. If this 1450 macro returns nonzero for those classes, those pseudos will only 1451 be allocated by `global.c', which knows how to reallocate the 1452 pseudo to another register. If there would not be another 1453 register available for reallocation, you should not change the 1454 definition of this macro since the only effect of such a 1455 definition would be to slow down register allocation. */ 1456 1457 #define CLASS_LIKELY_SPILLED_P(CLASS) \ 1458 (((CLASS) == AREG) \ 1459 || ((CLASS) == DREG) \ 1460 || ((CLASS) == CREG) \ 1461 || ((CLASS) == BREG) \ 1462 || ((CLASS) == AD_REGS) \ 1463 || ((CLASS) == SIREG) \ 1464 || ((CLASS) == DIREG) \ 1465 || ((CLASS) == SSE_FIRST_REG) \ 1466 || ((CLASS) == FP_TOP_REG) \ 1467 || ((CLASS) == FP_SECOND_REG)) 1468 1469 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1470 1471 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1472 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1473 1474 /* Stack layout; function entry, exit and calling. */ 1476 1477 /* Define this if pushing a word on the stack 1478 makes the stack pointer a smaller address. */ 1479 #define STACK_GROWS_DOWNWARD 1480 1481 /* Define this to nonzero if the nominal address of the stack frame 1482 is at the high-address end of the local variables; 1483 that is, each additional local variable allocated 1484 goes at a more negative offset in the frame. */ 1485 #define FRAME_GROWS_DOWNWARD 1 1486 1487 /* Offset within stack frame to start allocating local variables at. 1488 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1489 first local allocated. Otherwise, it is the offset to the BEGINNING 1490 of the first local allocated. */ 1491 #define STARTING_FRAME_OFFSET 0 1492 1493 /* If we generate an insn to push BYTES bytes, 1494 this says how many the stack pointer really advances by. 1495 On 386, we have pushw instruction that decrements by exactly 2 no 1496 matter what the position was, there is no pushb. 1497 But as CIE data alignment factor on this arch is -4, we need to make 1498 sure all stack pointer adjustments are in multiple of 4. 1499 1500 For 64bit ABI we round up to 8 bytes. 1501 */ 1502 1503 #define PUSH_ROUNDING(BYTES) \ 1504 (TARGET_64BIT \ 1505 ? (((BYTES) + 7) & (-8)) \ 1506 : (((BYTES) + 3) & (-4))) 1507 1508 /* If defined, the maximum amount of space required for outgoing arguments will 1509 be computed and placed into the variable 1510 `crtl->outgoing_args_size'. No space will be pushed onto the 1511 stack for each call; instead, the function prologue should increase the stack 1512 frame size by this amount. 1513 1514 MS ABI seem to require 16 byte alignment everywhere except for function 1515 prologue and apilogue. This is not possible without 1516 ACCUMULATE_OUTGOING_ARGS. */ 1517 1518 #define ACCUMULATE_OUTGOING_ARGS \ 1519 (TARGET_ACCUMULATE_OUTGOING_ARGS || ix86_cfun_abi () == MS_ABI) 1520 1521 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1522 instructions to pass outgoing arguments. */ 1523 1524 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1525 1526 /* We want the stack and args grow in opposite directions, even if 1527 PUSH_ARGS is 0. */ 1528 #define PUSH_ARGS_REVERSED 1 1529 1530 /* Offset of first parameter from the argument pointer register value. */ 1531 #define FIRST_PARM_OFFSET(FNDECL) 0 1532 1533 /* Define this macro if functions should assume that stack space has been 1534 allocated for arguments even when their values are passed in registers. 1535 1536 The value of this macro is the size, in bytes, of the area reserved for 1537 arguments passed in registers for the function represented by FNDECL. 1538 1539 This space can be allocated by the caller, or be a part of the 1540 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1541 which. */ 1542 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1543 1544 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1545 (ix86_function_type_abi (FNTYPE) == MS_ABI) 1546 1547 /* Value is the number of bytes of arguments automatically 1548 popped when returning from a subroutine call. 1549 FUNDECL is the declaration node of the function (as a tree), 1550 FUNTYPE is the data type of the function (as a tree), 1551 or for a library call it is an identifier node for the subroutine name. 1552 SIZE is the number of bytes of arguments passed on the stack. 1553 1554 On the 80386, the RTD insn may be used to pop them if the number 1555 of args is fixed, but if the number is variable then the caller 1556 must pop them all. RTD can't be used for library calls now 1557 because the library is compiled with the Unix compiler. 1558 Use of RTD is a selectable option, since it is incompatible with 1559 standard Unix calling sequences. If the option is not selected, 1560 the caller must always pop the args. 1561 1562 The attribute stdcall is equivalent to RTD on a per module basis. */ 1563 1564 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) \ 1565 ix86_return_pops_args ((FUNDECL), (FUNTYPE), (SIZE)) 1566 1567 #define FUNCTION_VALUE_REGNO_P(N) ix86_function_value_regno_p (N) 1568 1569 /* Define how to find the value returned by a library function 1570 assuming the value has mode MODE. */ 1571 1572 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1573 1574 /* Define the size of the result block used for communication between 1575 untyped_call and untyped_return. The block contains a DImode value 1576 followed by the block used by fnsave and frstor. */ 1577 1578 #define APPLY_RESULT_SIZE (8+108) 1579 1580 /* 1 if N is a possible register number for function argument passing. */ 1581 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1582 1583 /* Define a data type for recording info about an argument list 1584 during the scan of that argument list. This data type should 1585 hold all necessary information about the function itself 1586 and about the args processed so far, enough to enable macros 1587 such as FUNCTION_ARG to determine where the next arg should go. */ 1588 1589 typedef struct ix86_args { 1590 int words; /* # words passed so far */ 1591 int nregs; /* # registers available for passing */ 1592 int regno; /* next available register number */ 1593 int fastcall; /* fastcall calling convention is used */ 1594 int sse_words; /* # sse words passed so far */ 1595 int sse_nregs; /* # sse registers available for passing */ 1596 int warn_avx; /* True when we want to warn about AVX ABI. */ 1597 int warn_sse; /* True when we want to warn about SSE ABI. */ 1598 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1599 int sse_regno; /* next available sse register number */ 1600 int mmx_words; /* # mmx words passed so far */ 1601 int mmx_nregs; /* # mmx registers available for passing */ 1602 int mmx_regno; /* next available mmx register number */ 1603 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1604 int float_in_sse; /* 1 if in 32-bit mode SFmode (2 for DFmode) should 1605 be passed in SSE registers. Otherwise 0. */ 1606 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1607 MS_ABI for ms abi. */ 1608 } CUMULATIVE_ARGS; 1609 1610 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1611 for a call to a function whose data type is FNTYPE. 1612 For a library call, FNTYPE is 0. */ 1613 1614 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1615 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1616 1617 /* Update the data in CUM to advance over an argument 1618 of mode MODE and data type TYPE. 1619 (TYPE is null for libcalls where that information may not be available.) */ 1620 1621 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1622 function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1623 1624 /* Define where to put the arguments to a function. 1625 Value is zero to push the argument on the stack, 1626 or a hard register in which to store the argument. 1627 1628 MODE is the argument's machine mode. 1629 TYPE is the data type of the argument (as a tree). 1630 This is null for libcalls where that information may 1631 not be available. 1632 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1633 the preceding args and about the function being called. 1634 NAMED is nonzero if this argument is a named parameter 1635 (otherwise it is an extra parameter matching an ellipsis). */ 1636 1637 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1638 function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1639 1640 /* Output assembler code to FILE to increment profiler label # LABELNO 1641 for profiling a function entry. */ 1642 1643 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1644 1645 #define MCOUNT_NAME "_mcount" 1646 1647 #define PROFILE_COUNT_REGISTER "edx" 1648 1649 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1650 the stack pointer does not matter. The value is tested only in 1651 functions that have frame pointers. 1652 No definition is equivalent to always zero. */ 1653 /* Note on the 386 it might be more efficient not to define this since 1654 we have to restore it ourselves from the frame pointer, in order to 1655 use pop */ 1656 1657 #define EXIT_IGNORE_STACK 1 1658 1659 /* Output assembler code for a block containing the constant parts 1660 of a trampoline, leaving space for the variable parts. */ 1661 1662 /* On the 386, the trampoline contains two instructions: 1663 mov #STATIC,ecx 1664 jmp FUNCTION 1665 The trampoline is generated entirely at runtime. The operand of JMP 1666 is the address of FUNCTION relative to the instruction following the 1667 JMP (which is 5 bytes long). */ 1668 1669 /* Length in units of the trampoline for entering a nested function. */ 1670 1671 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1672 1673 /* Definitions for register eliminations. 1675 1676 This is an array of structures. Each structure initializes one pair 1677 of eliminable registers. The "from" register number is given first, 1678 followed by "to". Eliminations of the same "from" register are listed 1679 in order of preference. 1680 1681 There are two registers that can always be eliminated on the i386. 1682 The frame pointer and the arg pointer can be replaced by either the 1683 hard frame pointer or to the stack pointer, depending upon the 1684 circumstances. The hard frame pointer is not used before reload and 1685 so it is not eligible for elimination. */ 1686 1687 #define ELIMINABLE_REGS \ 1688 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1689 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1690 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1691 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1692 1693 /* Define the offset between two registers, one to be eliminated, and the other 1694 its replacement, at the start of a routine. */ 1695 1696 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1697 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1698 1699 /* Addressing modes, and classification of registers for them. */ 1701 1702 /* Macros to check register numbers against specific register classes. */ 1703 1704 /* These assume that REGNO is a hard or pseudo reg number. 1705 They give nonzero only if REGNO is a hard reg of the suitable class 1706 or a pseudo reg currently allocated to a suitable hard reg. 1707 Since they use reg_renumber, they are safe only once reg_renumber 1708 has been allocated, which happens in local-alloc.c. */ 1709 1710 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1711 ((REGNO) < STACK_POINTER_REGNUM \ 1712 || REX_INT_REGNO_P (REGNO) \ 1713 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1714 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1715 1716 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1717 (GENERAL_REGNO_P (REGNO) \ 1718 || (REGNO) == ARG_POINTER_REGNUM \ 1719 || (REGNO) == FRAME_POINTER_REGNUM \ 1720 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1721 1722 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1723 and check its validity for a certain class. 1724 We have two alternate definitions for each of them. 1725 The usual definition accepts all pseudo regs; the other rejects 1726 them unless they have been allocated suitable hard regs. 1727 The symbol REG_OK_STRICT causes the latter definition to be used. 1728 1729 Most source files want to accept pseudo regs in the hope that 1730 they will get allocated to the class that the insn wants them to be in. 1731 Source files for reload pass need to be strict. 1732 After reload, it makes no difference, since pseudo regs have 1733 been eliminated by then. */ 1734 1735 1736 /* Non strict versions, pseudos are ok. */ 1737 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1738 (REGNO (X) < STACK_POINTER_REGNUM \ 1739 || REX_INT_REGNO_P (REGNO (X)) \ 1740 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1741 1742 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1743 (GENERAL_REGNO_P (REGNO (X)) \ 1744 || REGNO (X) == ARG_POINTER_REGNUM \ 1745 || REGNO (X) == FRAME_POINTER_REGNUM \ 1746 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1747 1748 /* Strict versions, hard registers only */ 1749 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1750 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1751 1752 #ifndef REG_OK_STRICT 1753 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1754 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1755 1756 #else 1757 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1758 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1759 #endif 1760 1761 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1762 that is a valid memory address for an instruction. 1763 The MODE argument is the machine mode for the MEM expression 1764 that wants to use this address. 1765 1766 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1767 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1768 1769 See legitimize_pic_address in i386.c for details as to what 1770 constitutes a legitimate address when -fpic is used. */ 1771 1772 #define MAX_REGS_PER_ADDRESS 2 1773 1774 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1775 1776 /* Nonzero if the constant value X is a legitimate general operand. 1777 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1778 1779 #define LEGITIMATE_CONSTANT_P(X) legitimate_constant_p (X) 1780 1781 /* Try a machine-dependent way of reloading an illegitimate address 1782 operand. If we find one, push the reload and jump to WIN. This 1783 macro is used in only one place: `find_reloads_address' in reload.c. */ 1784 1785 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ 1786 do { \ 1787 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1788 (int)(TYPE), (INDL))) \ 1789 goto WIN; \ 1790 } while (0) 1791 1792 /* If defined, a C expression to determine the base term of address X. 1793 This macro is used in only one place: `find_base_term' in alias.c. 1794 1795 It is always safe for this macro to not be defined. It exists so 1796 that alias analysis can understand machine-dependent addresses. 1797 1798 The typical use of this macro is to handle addresses containing 1799 a label_ref or symbol_ref within an UNSPEC. */ 1800 1801 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1802 1803 /* Nonzero if the constant value X is a legitimate general operand 1804 when generating PIC code. It is given that flag_pic is on and 1805 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1806 1807 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1808 1809 #define SYMBOLIC_CONST(X) \ 1810 (GET_CODE (X) == SYMBOL_REF \ 1811 || GET_CODE (X) == LABEL_REF \ 1812 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1813 1814 /* Max number of args passed in registers. If this is more than 3, we will 1816 have problems with ebx (register #4), since it is a caller save register and 1817 is also used as the pic register in ELF. So for now, don't allow more than 1818 3 registers to be passed in registers. */ 1819 1820 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1821 #define X86_64_REGPARM_MAX 6 1822 #define X86_64_MS_REGPARM_MAX 4 1823 1824 #define X86_32_REGPARM_MAX 3 1825 1826 #define REGPARM_MAX \ 1827 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_REGPARM_MAX \ 1828 : X86_64_REGPARM_MAX) \ 1829 : X86_32_REGPARM_MAX) 1830 1831 #define X86_64_SSE_REGPARM_MAX 8 1832 #define X86_64_MS_SSE_REGPARM_MAX 4 1833 1834 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1835 1836 #define SSE_REGPARM_MAX \ 1837 (TARGET_64BIT ? (TARGET_64BIT_MS_ABI ? X86_64_MS_SSE_REGPARM_MAX \ 1838 : X86_64_SSE_REGPARM_MAX) \ 1839 : X86_32_SSE_REGPARM_MAX) 1840 1841 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1842 1843 1844 /* Specify the machine mode that this machine uses 1846 for the index in the tablejump instruction. */ 1847 #define CASE_VECTOR_MODE \ 1848 (!TARGET_64BIT || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1849 1850 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1851 #define DEFAULT_SIGNED_CHAR 1 1852 1853 /* Max number of bytes we can move from memory to memory 1854 in one reasonably fast instruction. */ 1855 #define MOVE_MAX 16 1856 1857 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1858 move efficiently, as opposed to MOVE_MAX which is the maximum 1859 number of bytes we can move with a single instruction. */ 1860 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 1861 1862 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1863 move-instruction pairs, we will do a movmem or libcall instead. 1864 Increasing the value will always make code faster, but eventually 1865 incurs high cost in increased code size. 1866 1867 If you don't define this, a reasonable default is used. */ 1868 1869 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1870 1871 /* If a clear memory operation would take CLEAR_RATIO or more simple 1872 move-instruction sequences, we will do a clrmem or libcall instead. */ 1873 1874 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1875 1876 /* Define if shifts truncate the shift count 1877 which implies one can omit a sign-extension or zero-extension 1878 of a shift count. */ 1879 /* On i386, shifts do truncate the count. But bit opcodes don't. */ 1880 1881 /* #define SHIFT_COUNT_TRUNCATED */ 1882 1883 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1884 is done just by pretending it is already truncated. */ 1885 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1886 1887 /* A macro to update M and UNSIGNEDP when an object whose type is 1888 TYPE and which has the specified mode and signedness is to be 1889 stored in a register. This macro is only called when TYPE is a 1890 scalar type. 1891 1892 On i386 it is sometimes useful to promote HImode and QImode 1893 quantities to SImode. The choice depends on target type. */ 1894 1895 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1896 do { \ 1897 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1898 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1899 (MODE) = SImode; \ 1900 } while (0) 1901 1902 /* Specify the machine mode that pointers have. 1903 After generation of rtl, the compiler makes no further distinction 1904 between pointers and any other objects of this machine mode. */ 1905 #define Pmode (TARGET_64BIT ? DImode : SImode) 1906 1907 /* A function address in a call instruction 1908 is a byte address (for indexing purposes) 1909 so give the MEM rtx a byte's mode. */ 1910 #define FUNCTION_MODE QImode 1911 1912 /* A C expression for the cost of moving data from a register in class FROM to 1914 one in class TO. The classes are expressed using the enumeration values 1915 such as `GENERAL_REGS'. A value of 2 is the default; other values are 1916 interpreted relative to that. 1917 1918 It is not required that the cost always equal 2 when FROM is the same as TO; 1919 on some machines it is expensive to move between registers if they are not 1920 general registers. */ 1921 1922 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 1923 ix86_register_move_cost ((MODE), (CLASS1), (CLASS2)) 1924 1925 /* A C expression for the cost of moving data of mode M between a 1926 register and memory. A value of 2 is the default; this cost is 1927 relative to those in `REGISTER_MOVE_COST'. 1928 1929 If moving between registers and memory is more expensive than 1930 between two registers, you should define this macro to express the 1931 relative cost. */ 1932 1933 #define MEMORY_MOVE_COST(MODE, CLASS, IN) \ 1934 ix86_memory_move_cost ((MODE), (CLASS), (IN)) 1935 1936 /* A C expression for the cost of a branch instruction. A value of 1 1937 is the default; other values are interpreted relative to that. */ 1938 1939 #define BRANCH_COST(speed_p, predictable_p) \ 1940 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1941 1942 /* Define this macro as a C expression which is nonzero if accessing 1943 less than a word of memory (i.e. a `char' or a `short') is no 1944 faster than accessing a word of memory, i.e., if such access 1945 require more than one instruction or if there is no difference in 1946 cost between byte and (aligned) word loads. 1947 1948 When this macro is not defined, the compiler will access a field by 1949 finding the smallest containing object; when it is defined, a 1950 fullword load will be used if alignment permits. Unless bytes 1951 accesses are faster than word accesses, using word accesses is 1952 preferable since it may eliminate subsequent memory access if 1953 subsequent accesses occur to other fields in the same word of the 1954 structure, but to different bytes. */ 1955 1956 #define SLOW_BYTE_ACCESS 0 1957 1958 /* Nonzero if access to memory by shorts is slow and undesirable. */ 1959 #define SLOW_SHORT_ACCESS 0 1960 1961 /* Define this macro to be the value 1 if unaligned accesses have a 1962 cost many times greater than aligned accesses, for example if they 1963 are emulated in a trap handler. 1964 1965 When this macro is nonzero, the compiler will act as if 1966 `STRICT_ALIGNMENT' were nonzero when generating code for block 1967 moves. This can cause significantly more instructions to be 1968 produced. Therefore, do not set this macro nonzero if unaligned 1969 accesses only add a cycle or two to the time for a memory access. 1970 1971 If the value of this macro is always zero, it need not be defined. */ 1972 1973 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1974 1975 /* Define this macro if it is as good or better to call a constant 1976 function address than to call an address kept in a register. 1977 1978 Desirable on the 386 because a CALL with a constant address is 1979 faster than one with a register address. */ 1980 1981 #define NO_FUNCTION_CSE 1982 1983 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1985 return the mode to be used for the comparison. 1986 1987 For floating-point equality comparisons, CCFPEQmode should be used. 1988 VOIDmode should be used in all other cases. 1989 1990 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1991 possible, to allow for more combinations. */ 1992 1993 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1994 1995 /* Return nonzero if MODE implies a floating point inequality can be 1996 reversed. */ 1997 1998 #define REVERSIBLE_CC_MODE(MODE) 1 1999 2000 /* A C expression whose value is reversed condition code of the CODE for 2001 comparison done in CC_MODE mode. */ 2002 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 2003 2004 2005 /* Control the assembler format that we output, to the extent 2007 this does not vary between assemblers. */ 2008 2009 /* How to refer to registers in assembler output. 2010 This sequence is indexed by compiler's hard-register-number (see above). */ 2011 2012 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 2013 For non floating point regs, the following are the HImode names. 2014 2015 For float regs, the stack top is sometimes referred to as "%st(0)" 2016 instead of just "%st". PRINT_OPERAND handles this with the "y" code. */ 2017 2018 #define HI_REGISTER_NAMES \ 2019 {"ax","dx","cx","bx","si","di","bp","sp", \ 2020 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 2021 "argp", "flags", "fpsr", "fpcr", "frame", \ 2022 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 2023 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 2024 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 2025 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 2026 2027 #define REGISTER_NAMES HI_REGISTER_NAMES 2028 2029 /* Table of additional register names to use in user input. */ 2030 2031 #define ADDITIONAL_REGISTER_NAMES \ 2032 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 2033 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 2034 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 2035 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 2036 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 2037 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 2038 2039 /* Note we are omitting these since currently I don't know how 2040 to get gcc to use these, since they want the same but different 2041 number as al, and ax. 2042 */ 2043 2044 #define QI_REGISTER_NAMES \ 2045 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 2046 2047 /* These parallel the array above, and can be used to access bits 8:15 2048 of regs 0 through 3. */ 2049 2050 #define QI_HIGH_REGISTER_NAMES \ 2051 {"ah", "dh", "ch", "bh", } 2052 2053 /* How to renumber registers for dbx and gdb. */ 2054 2055 #define DBX_REGISTER_NUMBER(N) \ 2056 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 2057 2058 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 2059 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 2060 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 2061 2062 /* Before the prologue, RA is at 0(%esp). */ 2063 #define INCOMING_RETURN_ADDR_RTX \ 2064 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 2065 2066 /* After the prologue, RA is at -4(AP) in the current frame. */ 2067 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 2068 ((COUNT) == 0 \ 2069 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, -UNITS_PER_WORD)) \ 2070 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 2071 2072 /* PC is dbx register 8; let's use that column for RA. */ 2073 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 2074 2075 /* Before the prologue, the top of the frame is at 4(%esp). */ 2076 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 2077 2078 /* Describe how we implement __builtin_eh_return. */ 2079 #define EH_RETURN_DATA_REGNO(N) ((N) < 2 ? (N) : INVALID_REGNUM) 2080 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 2081 2082 2083 /* Select a format to encode pointers in exception handling data. CODE 2084 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2085 true if the symbol may be affected by dynamic relocations. 2086 2087 ??? All x86 object file formats are capable of representing this. 2088 After all, the relocation needed is the same as for the call insn. 2089 Whether or not a particular assembler allows us to enter such, I 2090 guess we'll have to see. */ 2091 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 2092 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 2093 2094 /* This is how to output an insn to push a register on the stack. 2095 It need not be very fast code. */ 2096 2097 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 2098 do { \ 2099 if (TARGET_64BIT) \ 2100 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 2101 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2102 else \ 2103 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2104 } while (0) 2105 2106 /* This is how to output an insn to pop a register from the stack. 2107 It need not be very fast code. */ 2108 2109 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 2110 do { \ 2111 if (TARGET_64BIT) \ 2112 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 2113 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 2114 else \ 2115 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 2116 } while (0) 2117 2118 /* This is how to output an element of a case-vector that is absolute. */ 2119 2120 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 2121 ix86_output_addr_vec_elt ((FILE), (VALUE)) 2122 2123 /* This is how to output an element of a case-vector that is relative. */ 2124 2125 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2126 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2127 2128 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is 2129 true. */ 2130 2131 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2132 { \ 2133 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2134 { \ 2135 if (TARGET_AVX) \ 2136 (PTR) += 1; \ 2137 else \ 2138 (PTR) += 2; \ 2139 } \ 2140 } 2141 2142 /* A C statement or statements which output an assembler instruction 2143 opcode to the stdio stream STREAM. The macro-operand PTR is a 2144 variable of type `char *' which points to the opcode name in 2145 its "internal" form--the form that is written in the machine 2146 description. */ 2147 2148 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2149 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2150 2151 /* A C statement to output to the stdio stream FILE an assembler 2152 command to pad the location counter to a multiple of 1<<LOG 2153 bytes if it is within MAX_SKIP bytes. */ 2154 2155 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2156 #undef ASM_OUTPUT_MAX_SKIP_PAD 2157 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2158 if ((LOG) != 0) \ 2159 { \ 2160 if ((MAX_SKIP) == 0) \ 2161 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2162 else \ 2163 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2164 } 2165 #endif 2166 2167 /* Under some conditions we need jump tables in the text section, 2168 because the assembler cannot handle label differences between 2169 sections. This is the case for x86_64 on Mach-O for example. */ 2170 2171 #define JUMP_TABLES_IN_TEXT_SECTION \ 2172 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2173 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2174 2175 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2176 and switch back. For x86 we do this only to save a few bytes that 2177 would otherwise be unused in the text section. */ 2178 #define CRT_MKSTR2(VAL) #VAL 2179 #define CRT_MKSTR(x) CRT_MKSTR2(x) 2180 2181 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2182 asm (SECTION_OP "\n\t" \ 2183 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2184 TEXT_SECTION_ASM_OP); 2185 2186 /* Print operand X (an rtx) in assembler syntax to file FILE. 2188 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2189 Effect of various CODE letters is described in i386.c near 2190 print_operand function. */ 2191 2192 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2193 ((CODE) == '*' || (CODE) == '+' || (CODE) == '&' || (CODE) == ';') 2194 2195 #define PRINT_OPERAND(FILE, X, CODE) \ 2196 print_operand ((FILE), (X), (CODE)) 2197 2198 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 2199 print_operand_address ((FILE), (ADDR)) 2200 2201 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 2202 do { \ 2203 if (! output_addr_const_extra (FILE, (X))) \ 2204 goto FAIL; \ 2205 } while (0); 2206 2207 /* Which processor to schedule for. The cpu attribute defines a list that 2209 mirrors this list, so changes to i386.md must be made at the same time. */ 2210 2211 enum processor_type 2212 { 2213 PROCESSOR_I386 = 0, /* 80386 */ 2214 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2215 PROCESSOR_PENTIUM, 2216 PROCESSOR_PENTIUMPRO, 2217 PROCESSOR_GEODE, 2218 PROCESSOR_K6, 2219 PROCESSOR_ATHLON, 2220 PROCESSOR_PENTIUM4, 2221 PROCESSOR_K8, 2222 PROCESSOR_NOCONA, 2223 PROCESSOR_CORE2, 2224 PROCESSOR_GENERIC32, 2225 PROCESSOR_GENERIC64, 2226 PROCESSOR_AMDFAM10, 2227 PROCESSOR_ATOM, 2228 PROCESSOR_max 2229 }; 2230 2231 extern enum processor_type ix86_tune; 2232 extern enum processor_type ix86_arch; 2233 2234 enum fpmath_unit 2235 { 2236 FPMATH_387 = 1, 2237 FPMATH_SSE = 2 2238 }; 2239 2240 extern enum fpmath_unit ix86_fpmath; 2241 2242 enum tls_dialect 2243 { 2244 TLS_DIALECT_GNU, 2245 TLS_DIALECT_GNU2, 2246 TLS_DIALECT_SUN 2247 }; 2248 2249 extern enum tls_dialect ix86_tls_dialect; 2250 2251 enum cmodel { 2252 CM_32, /* The traditional 32-bit ABI. */ 2253 CM_SMALL, /* Assumes all code and data fits in the low 31 bits. */ 2254 CM_KERNEL, /* Assumes all code and data fits in the high 31 bits. */ 2255 CM_MEDIUM, /* Assumes code fits in the low 31 bits; data unlimited. */ 2256 CM_LARGE, /* No assumptions. */ 2257 CM_SMALL_PIC, /* Assumes code+data+got/plt fits in a 31 bit region. */ 2258 CM_MEDIUM_PIC,/* Assumes code+got/plt fits in a 31 bit region. */ 2259 CM_LARGE_PIC /* No assumptions. */ 2260 }; 2261 2262 extern enum cmodel ix86_cmodel; 2263 2264 /* Size of the RED_ZONE area. */ 2265 #define RED_ZONE_SIZE 128 2266 /* Reserved area of the red zone for temporaries. */ 2267 #define RED_ZONE_RESERVE 8 2268 2269 enum asm_dialect { 2270 ASM_ATT, 2271 ASM_INTEL 2272 }; 2273 2274 extern enum asm_dialect ix86_asm_dialect; 2275 extern unsigned int ix86_preferred_stack_boundary; 2276 extern unsigned int ix86_incoming_stack_boundary; 2277 extern int ix86_branch_cost, ix86_section_threshold; 2278 2279 /* Smallest class containing REGNO. */ 2280 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2281 2282 extern rtx ix86_compare_op0; /* operand 0 for comparisons */ 2283 extern rtx ix86_compare_op1; /* operand 1 for comparisons */ 2284 2285 enum ix86_fpcmp_strategy { 2286 IX86_FPCMP_SAHF, 2287 IX86_FPCMP_COMI, 2288 IX86_FPCMP_ARITH 2289 }; 2290 2291 /* To properly truncate FP values into integers, we need to set i387 control 2293 word. We can't emit proper mode switching code before reload, as spills 2294 generated by reload may truncate values incorrectly, but we still can avoid 2295 redundant computation of new control word by the mode switching pass. 2296 The fldcw instructions are still emitted redundantly, but this is probably 2297 not going to be noticeable problem, as most CPUs do have fast path for 2298 the sequence. 2299 2300 The machinery is to emit simple truncation instructions and split them 2301 before reload to instructions having USEs of two memory locations that 2302 are filled by this code to old and new control word. 2303 2304 Post-reload pass may be later used to eliminate the redundant fildcw if 2305 needed. */ 2306 2307 enum ix86_entity 2308 { 2309 I387_TRUNC = 0, 2310 I387_FLOOR, 2311 I387_CEIL, 2312 I387_MASK_PM, 2313 MAX_386_ENTITIES 2314 }; 2315 2316 enum ix86_stack_slot 2317 { 2318 SLOT_VIRTUAL = 0, 2319 SLOT_TEMP, 2320 SLOT_CW_STORED, 2321 SLOT_CW_TRUNC, 2322 SLOT_CW_FLOOR, 2323 SLOT_CW_CEIL, 2324 SLOT_CW_MASK_PM, 2325 MAX_386_STACK_LOCALS 2326 }; 2327 2328 /* Define this macro if the port needs extra instructions inserted 2329 for mode switching in an optimizing compilation. */ 2330 2331 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2332 ix86_optimize_mode_switching[(ENTITY)] 2333 2334 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2335 initializer for an array of integers. Each initializer element N 2336 refers to an entity that needs mode switching, and specifies the 2337 number of different modes that might need to be set for this 2338 entity. The position of the initializer in the initializer - 2339 starting counting at zero - determines the integer that is used to 2340 refer to the mode-switched entity in question. */ 2341 2342 #define NUM_MODES_FOR_MODE_SWITCHING \ 2343 { I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2344 2345 /* ENTITY is an integer specifying a mode-switched entity. If 2346 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2347 return an integer value not larger than the corresponding element 2348 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2349 must be switched into prior to the execution of INSN. */ 2350 2351 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2352 2353 /* This macro specifies the order in which modes for ENTITY are 2354 processed. 0 is the highest priority. */ 2355 2356 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2357 2358 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2359 is the set of hard registers live at the point where the insn(s) 2360 are to be inserted. */ 2361 2362 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2363 ((MODE) != I387_CW_ANY && (MODE) != I387_CW_UNINITIALIZED \ 2364 ? emit_i387_cw_initialization (MODE), 0 \ 2365 : 0) 2366 2367 2368 /* Avoid renaming of stack registers, as doing so in combination with 2370 scheduling just increases amount of live registers at time and in 2371 the turn amount of fxch instructions needed. 2372 2373 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2374 2375 #define HARD_REGNO_RENAME_OK(SRC, TARGET) \ 2376 (! IN_RANGE ((SRC), FIRST_STACK_REG, LAST_STACK_REG)) 2377 2378 2379 #define FASTCALL_PREFIX '@' 2381 2382 /* Machine specific CFA tracking during prologue/epilogue generation. */ 2384 2385 #ifndef USED_FOR_TARGET 2386 struct GTY(()) machine_cfa_state 2387 { 2388 rtx reg; 2389 HOST_WIDE_INT offset; 2390 }; 2391 2392 struct GTY(()) machine_function { 2393 struct stack_local_entry *stack_locals; 2394 const char *some_ld_name; 2395 int varargs_gpr_size; 2396 int varargs_fpr_size; 2397 int optimize_mode_switching[MAX_386_ENTITIES]; 2398 2399 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE 2400 has been computed for. */ 2401 int use_fast_prologue_epilogue_nregs; 2402 2403 /* The CFA state at the end of the prologue. */ 2404 struct machine_cfa_state cfa; 2405 2406 /* This value is used for amd64 targets and specifies the current abi 2407 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2408 enum calling_abi call_abi; 2409 2410 /* Nonzero if the function accesses a previous frame. */ 2411 BOOL_BITFIELD accesses_prev_frame : 1; 2412 2413 /* Nonzero if the function requires a CLD in the prologue. */ 2414 BOOL_BITFIELD needs_cld : 1; 2415 2416 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2417 expander to determine the style used. */ 2418 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2419 2420 /* If true, the current function needs the default PIC register, not 2421 an alternate register (on x86) and must not use the red zone (on 2422 x86_64), even if it's a leaf function. We don't want the 2423 function to be regarded as non-leaf because TLS calls need not 2424 affect register allocation. This flag is set when a TLS call 2425 instruction is expanded within a function, and never reset, even 2426 if all such instructions are optimized away. Use the 2427 ix86_current_function_calls_tls_descriptor macro for a better 2428 approximation. */ 2429 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2430 2431 /* If true, the current function has a STATIC_CHAIN is placed on the 2432 stack below the return address. */ 2433 BOOL_BITFIELD static_chain_on_stack : 1; 2434 }; 2435 #endif 2436 2437 #define ix86_stack_locals (cfun->machine->stack_locals) 2438 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2439 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2440 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2441 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) 2442 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2443 (cfun->machine->tls_descriptor_call_expanded_p) 2444 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2445 calls are optimized away, we try to detect cases in which it was 2446 optimized away. Since such instructions (use (reg REG_SP)), we can 2447 verify whether there's any such instruction live by testing that 2448 REG_SP is live. */ 2449 #define ix86_current_function_calls_tls_descriptor \ 2450 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2451 #define ix86_cfa_state (&cfun->machine->cfa) 2452 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2453 2454 /* Control behavior of x86_file_start. */ 2455 #define X86_FILE_START_VERSION_DIRECTIVE false 2456 #define X86_FILE_START_FLTUSED false 2457 2458 /* Flag to mark data that is in the large address area. */ 2459 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2460 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2461 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2462 2463 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2464 have defined always, to avoid ifdefing. */ 2465 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2466 #define SYMBOL_REF_DLLIMPORT_P(X) \ 2467 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2468 2469 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2470 #define SYMBOL_REF_DLLEXPORT_P(X) \ 2471 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2472 2473 /* Model costs for vectorizer. */ 2474 2475 /* Cost of conditional branch. */ 2476 #undef TARG_COND_BRANCH_COST 2477 #define TARG_COND_BRANCH_COST ix86_cost->branch_cost 2478 2479 /* Enum through the target specific extra va_list types. 2480 Please, do not iterate the base va_list type name. */ 2481 #define TARGET_ENUM_VA_LIST(IDX, PNAME, PTYPE) \ 2482 (TARGET_64BIT ? ix86_enum_va_list (IDX, PNAME, PTYPE) : 0) 2483 2484 /* Cost of any scalar operation, excluding load and store. */ 2485 #undef TARG_SCALAR_STMT_COST 2486 #define TARG_SCALAR_STMT_COST ix86_cost->scalar_stmt_cost 2487 2488 /* Cost of scalar load. */ 2489 #undef TARG_SCALAR_LOAD_COST 2490 #define TARG_SCALAR_LOAD_COST ix86_cost->scalar_load_cost 2491 2492 /* Cost of scalar store. */ 2493 #undef TARG_SCALAR_STORE_COST 2494 #define TARG_SCALAR_STORE_COST ix86_cost->scalar_store_cost 2495 2496 /* Cost of any vector operation, excluding load, store or vector to scalar 2497 operation. */ 2498 #undef TARG_VEC_STMT_COST 2499 #define TARG_VEC_STMT_COST ix86_cost->vec_stmt_cost 2500 2501 /* Cost of vector to scalar operation. */ 2502 #undef TARG_VEC_TO_SCALAR_COST 2503 #define TARG_VEC_TO_SCALAR_COST ix86_cost->vec_to_scalar_cost 2504 2505 /* Cost of scalar to vector operation. */ 2506 #undef TARG_SCALAR_TO_VEC_COST 2507 #define TARG_SCALAR_TO_VEC_COST ix86_cost->scalar_to_vec_cost 2508 2509 /* Cost of aligned vector load. */ 2510 #undef TARG_VEC_LOAD_COST 2511 #define TARG_VEC_LOAD_COST ix86_cost->vec_align_load_cost 2512 2513 /* Cost of misaligned vector load. */ 2514 #undef TARG_VEC_UNALIGNED_LOAD_COST 2515 #define TARG_VEC_UNALIGNED_LOAD_COST ix86_cost->vec_unalign_load_cost 2516 2517 /* Cost of vector store. */ 2518 #undef TARG_VEC_STORE_COST 2519 #define TARG_VEC_STORE_COST ix86_cost->vec_store_cost 2520 2521 /* Cost of conditional taken branch for vectorizer cost model. */ 2522 #undef TARG_COND_TAKEN_BRANCH_COST 2523 #define TARG_COND_TAKEN_BRANCH_COST ix86_cost->cond_taken_branch_cost 2524 2525 /* Cost of conditional not taken branch for vectorizer cost model. */ 2526 #undef TARG_COND_NOT_TAKEN_BRANCH_COST 2527 #define TARG_COND_NOT_TAKEN_BRANCH_COST ix86_cost->cond_not_taken_branch_cost 2528 2529 /* 2530 Local variables: 2531 version-control: t 2532 End: 2533 */ 2534
Indexes created Tue Jul 21 00:24:56 UTC 2026