i386.h revision 1.1.1.2
1 /* Definitions of target machine for GCC for IA-32. 2 Copyright (C) 1988-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 Under Section 7 of GPL version 3, you are granted additional 17 permissions described in the GCC Runtime Library Exception, version 18 3.1, as published by the Free Software Foundation. 19 20 You should have received a copy of the GNU General Public License and 21 a copy of the GCC Runtime Library Exception along with this program; 22 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23 <http://www.gnu.org/licenses/>. */ 24 25 /* The purpose of this file is to define the characteristics of the i386, 26 independent of assembler syntax or operating system. 27 28 Three other files build on this one to describe a specific assembler syntax: 29 bsd386.h, att386.h, and sun386.h. 30 31 The actual tm.h file for a particular system should include 32 this file, and then the file for the appropriate assembler syntax. 33 34 Many macros that specify assembler syntax are omitted entirely from 35 this file because they really belong in the files for particular 36 assemblers. These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR, 37 ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many 38 that start with ASM_ or end in ASM_OP. */ 39 40 /* Redefines for option macros. */ 41 42 #define TARGET_64BIT TARGET_ISA_64BIT 43 #define TARGET_MMX TARGET_ISA_MMX 44 #define TARGET_3DNOW TARGET_ISA_3DNOW 45 #define TARGET_3DNOW_A TARGET_ISA_3DNOW_A 46 #define TARGET_SSE TARGET_ISA_SSE 47 #define TARGET_SSE2 TARGET_ISA_SSE2 48 #define TARGET_SSE3 TARGET_ISA_SSE3 49 #define TARGET_SSSE3 TARGET_ISA_SSSE3 50 #define TARGET_SSE4_1 TARGET_ISA_SSE4_1 51 #define TARGET_SSE4_2 TARGET_ISA_SSE4_2 52 #define TARGET_AVX TARGET_ISA_AVX 53 #define TARGET_AVX2 TARGET_ISA_AVX2 54 #define TARGET_FMA TARGET_ISA_FMA 55 #define TARGET_SSE4A TARGET_ISA_SSE4A 56 #define TARGET_FMA4 TARGET_ISA_FMA4 57 #define TARGET_XOP TARGET_ISA_XOP 58 #define TARGET_LWP TARGET_ISA_LWP 59 #define TARGET_ROUND TARGET_ISA_ROUND 60 #define TARGET_ABM TARGET_ISA_ABM 61 #define TARGET_BMI TARGET_ISA_BMI 62 #define TARGET_BMI2 TARGET_ISA_BMI2 63 #define TARGET_LZCNT TARGET_ISA_LZCNT 64 #define TARGET_TBM TARGET_ISA_TBM 65 #define TARGET_POPCNT TARGET_ISA_POPCNT 66 #define TARGET_SAHF TARGET_ISA_SAHF 67 #define TARGET_MOVBE TARGET_ISA_MOVBE 68 #define TARGET_CRC32 TARGET_ISA_CRC32 69 #define TARGET_AES TARGET_ISA_AES 70 #define TARGET_PCLMUL TARGET_ISA_PCLMUL 71 #define TARGET_CMPXCHG16B TARGET_ISA_CX16 72 #define TARGET_FSGSBASE TARGET_ISA_FSGSBASE 73 #define TARGET_RDRND TARGET_ISA_RDRND 74 #define TARGET_F16C TARGET_ISA_F16C 75 #define TARGET_RTM TARGET_ISA_RTM 76 #define TARGET_HLE TARGET_ISA_HLE 77 #define TARGET_RDSEED TARGET_ISA_RDSEED 78 #define TARGET_PRFCHW TARGET_ISA_PRFCHW 79 #define TARGET_ADX TARGET_ISA_ADX 80 #define TARGET_FXSR TARGET_ISA_FXSR 81 #define TARGET_XSAVE TARGET_ISA_XSAVE 82 #define TARGET_XSAVEOPT TARGET_ISA_XSAVEOPT 83 84 #define TARGET_LP64 TARGET_ABI_64 85 #define TARGET_X32 TARGET_ABI_X32 86 87 /* SSE4.1 defines round instructions */ 88 #define OPTION_MASK_ISA_ROUND OPTION_MASK_ISA_SSE4_1 89 #define TARGET_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0) 90 91 #include "config/vxworks-dummy.h" 92 93 #include "config/i386/i386-opts.h" 94 95 #define MAX_STRINGOP_ALGS 4 96 97 /* Specify what algorithm to use for stringops on known size. 98 When size is unknown, the UNKNOWN_SIZE alg is used. When size is 99 known at compile time or estimated via feedback, the SIZE array 100 is walked in order until MAX is greater then the estimate (or -1 101 means infinity). Corresponding ALG is used then. 102 When NOALIGN is true the code guaranting the alignment of the memory 103 block is skipped. 104 105 For example initializer: 106 {{256, loop}, {-1, rep_prefix_4_byte}} 107 will use loop for blocks smaller or equal to 256 bytes, rep prefix will 108 be used otherwise. */ 109 struct stringop_algs 110 { 111 const enum stringop_alg unknown_size; 112 const struct stringop_strategy { 113 const int max; 114 const enum stringop_alg alg; 115 int noalign; 116 } size [MAX_STRINGOP_ALGS]; 117 }; 118 119 /* Define the specific costs for a given cpu */ 120 121 struct processor_costs { 122 const int add; /* cost of an add instruction */ 123 const int lea; /* cost of a lea instruction */ 124 const int shift_var; /* variable shift costs */ 125 const int shift_const; /* constant shift costs */ 126 const int mult_init[5]; /* cost of starting a multiply 127 in QImode, HImode, SImode, DImode, TImode*/ 128 const int mult_bit; /* cost of multiply per each bit set */ 129 const int divide[5]; /* cost of a divide/mod 130 in QImode, HImode, SImode, DImode, TImode*/ 131 int movsx; /* The cost of movsx operation. */ 132 int movzx; /* The cost of movzx operation. */ 133 const int large_insn; /* insns larger than this cost more */ 134 const int move_ratio; /* The threshold of number of scalar 135 memory-to-memory move insns. */ 136 const int movzbl_load; /* cost of loading using movzbl */ 137 const int int_load[3]; /* cost of loading integer registers 138 in QImode, HImode and SImode relative 139 to reg-reg move (2). */ 140 const int int_store[3]; /* cost of storing integer register 141 in QImode, HImode and SImode */ 142 const int fp_move; /* cost of reg,reg fld/fst */ 143 const int fp_load[3]; /* cost of loading FP register 144 in SFmode, DFmode and XFmode */ 145 const int fp_store[3]; /* cost of storing FP register 146 in SFmode, DFmode and XFmode */ 147 const int mmx_move; /* cost of moving MMX register. */ 148 const int mmx_load[2]; /* cost of loading MMX register 149 in SImode and DImode */ 150 const int mmx_store[2]; /* cost of storing MMX register 151 in SImode and DImode */ 152 const int sse_move; /* cost of moving SSE register. */ 153 const int sse_load[3]; /* cost of loading SSE register 154 in SImode, DImode and TImode*/ 155 const int sse_store[3]; /* cost of storing SSE register 156 in SImode, DImode and TImode*/ 157 const int mmxsse_to_integer; /* cost of moving mmxsse register to 158 integer and vice versa. */ 159 const int l1_cache_size; /* size of l1 cache, in kilobytes. */ 160 const int l2_cache_size; /* size of l2 cache, in kilobytes. */ 161 const int prefetch_block; /* bytes moved to cache for prefetch. */ 162 const int simultaneous_prefetches; /* number of parallel prefetch 163 operations. */ 164 const int branch_cost; /* Default value for BRANCH_COST. */ 165 const int fadd; /* cost of FADD and FSUB instructions. */ 166 const int fmul; /* cost of FMUL instruction. */ 167 const int fdiv; /* cost of FDIV instruction. */ 168 const int fabs; /* cost of FABS instruction. */ 169 const int fchs; /* cost of FCHS instruction. */ 170 const int fsqrt; /* cost of FSQRT instruction. */ 171 /* Specify what algorithm 172 to use for stringops on unknown size. */ 173 struct stringop_algs memcpy[2], memset[2]; 174 const int scalar_stmt_cost; /* Cost of any scalar operation, excluding 175 load and store. */ 176 const int scalar_load_cost; /* Cost of scalar load. */ 177 const int scalar_store_cost; /* Cost of scalar store. */ 178 const int vec_stmt_cost; /* Cost of any vector operation, excluding 179 load, store, vector-to-scalar and 180 scalar-to-vector operation. */ 181 const int vec_to_scalar_cost; /* Cost of vect-to-scalar operation. */ 182 const int scalar_to_vec_cost; /* Cost of scalar-to-vector operation. */ 183 const int vec_align_load_cost; /* Cost of aligned vector load. */ 184 const int vec_unalign_load_cost; /* Cost of unaligned vector load. */ 185 const int vec_store_cost; /* Cost of vector store. */ 186 const int cond_taken_branch_cost; /* Cost of taken branch for vectorizer 187 cost model. */ 188 const int cond_not_taken_branch_cost;/* Cost of not taken branch for 189 vectorizer cost model. */ 190 }; 191 192 extern const struct processor_costs *ix86_cost; 193 extern const struct processor_costs ix86_size_cost; 194 195 #define ix86_cur_cost() \ 196 (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost) 197 198 /* Macros used in the machine description to test the flags. */ 199 200 /* configure can arrange to change it. */ 201 202 #ifndef TARGET_CPU_DEFAULT 203 #define TARGET_CPU_DEFAULT PROCESSOR_GENERIC32 204 #endif 205 206 #ifndef TARGET_FPMATH_DEFAULT 207 #define TARGET_FPMATH_DEFAULT \ 208 (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387) 209 #endif 210 211 #define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS 212 213 /* 64bit Sledgehammer mode. For libgcc2 we make sure this is a 214 compile-time constant. */ 215 #ifdef IN_LIBGCC2 216 #undef TARGET_64BIT 217 #ifdef __x86_64__ 218 #define TARGET_64BIT 1 219 #else 220 #define TARGET_64BIT 0 221 #endif 222 #else 223 #ifndef TARGET_BI_ARCH 224 #undef TARGET_64BIT 225 #if TARGET_64BIT_DEFAULT 226 #define TARGET_64BIT 1 227 #else 228 #define TARGET_64BIT 0 229 #endif 230 #endif 231 #endif 232 233 #define HAS_LONG_COND_BRANCH 1 234 #define HAS_LONG_UNCOND_BRANCH 1 235 236 #define TARGET_386 (ix86_tune == PROCESSOR_I386) 237 #define TARGET_486 (ix86_tune == PROCESSOR_I486) 238 #define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM) 239 #define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO) 240 #define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE) 241 #define TARGET_K6 (ix86_tune == PROCESSOR_K6) 242 #define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON) 243 #define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4) 244 #define TARGET_K8 (ix86_tune == PROCESSOR_K8) 245 #define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON) 246 #define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA) 247 #define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2) 248 #define TARGET_COREI7 (ix86_tune == PROCESSOR_COREI7) 249 #define TARGET_HASWELL (ix86_tune == PROCESSOR_HASWELL) 250 #define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32) 251 #define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64) 252 #define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64) 253 #define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10) 254 #define TARGET_BDVER1 (ix86_tune == PROCESSOR_BDVER1) 255 #define TARGET_BDVER2 (ix86_tune == PROCESSOR_BDVER2) 256 #define TARGET_BDVER3 (ix86_tune == PROCESSOR_BDVER3) 257 #define TARGET_BTVER1 (ix86_tune == PROCESSOR_BTVER1) 258 #define TARGET_BTVER2 (ix86_tune == PROCESSOR_BTVER2) 259 #define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM) 260 261 /* Feature tests against the various tunings. */ 262 enum ix86_tune_indices { 263 X86_TUNE_USE_LEAVE, 264 X86_TUNE_PUSH_MEMORY, 265 X86_TUNE_ZERO_EXTEND_WITH_AND, 266 X86_TUNE_UNROLL_STRLEN, 267 X86_TUNE_BRANCH_PREDICTION_HINTS, 268 X86_TUNE_DOUBLE_WITH_ADD, 269 X86_TUNE_USE_SAHF, 270 X86_TUNE_MOVX, 271 X86_TUNE_PARTIAL_REG_STALL, 272 X86_TUNE_PARTIAL_FLAG_REG_STALL, 273 X86_TUNE_LCP_STALL, 274 X86_TUNE_USE_HIMODE_FIOP, 275 X86_TUNE_USE_SIMODE_FIOP, 276 X86_TUNE_USE_MOV0, 277 X86_TUNE_USE_CLTD, 278 X86_TUNE_USE_XCHGB, 279 X86_TUNE_SPLIT_LONG_MOVES, 280 X86_TUNE_READ_MODIFY_WRITE, 281 X86_TUNE_READ_MODIFY, 282 X86_TUNE_PROMOTE_QIMODE, 283 X86_TUNE_FAST_PREFIX, 284 X86_TUNE_SINGLE_STRINGOP, 285 X86_TUNE_QIMODE_MATH, 286 X86_TUNE_HIMODE_MATH, 287 X86_TUNE_PROMOTE_QI_REGS, 288 X86_TUNE_PROMOTE_HI_REGS, 289 X86_TUNE_SINGLE_POP, 290 X86_TUNE_DOUBLE_POP, 291 X86_TUNE_SINGLE_PUSH, 292 X86_TUNE_DOUBLE_PUSH, 293 X86_TUNE_INTEGER_DFMODE_MOVES, 294 X86_TUNE_PARTIAL_REG_DEPENDENCY, 295 X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY, 296 X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL, 297 X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL, 298 X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL, 299 X86_TUNE_SSE_SPLIT_REGS, 300 X86_TUNE_SSE_TYPELESS_STORES, 301 X86_TUNE_SSE_LOAD0_BY_PXOR, 302 X86_TUNE_MEMORY_MISMATCH_STALL, 303 X86_TUNE_PROLOGUE_USING_MOVE, 304 X86_TUNE_EPILOGUE_USING_MOVE, 305 X86_TUNE_SHIFT1, 306 X86_TUNE_USE_FFREEP, 307 X86_TUNE_INTER_UNIT_MOVES, 308 X86_TUNE_INTER_UNIT_CONVERSIONS, 309 X86_TUNE_FOUR_JUMP_LIMIT, 310 X86_TUNE_SCHEDULE, 311 X86_TUNE_USE_BT, 312 X86_TUNE_USE_INCDEC, 313 X86_TUNE_PAD_RETURNS, 314 X86_TUNE_PAD_SHORT_FUNCTION, 315 X86_TUNE_EXT_80387_CONSTANTS, 316 X86_TUNE_AVOID_VECTOR_DECODE, 317 X86_TUNE_PROMOTE_HIMODE_IMUL, 318 X86_TUNE_SLOW_IMUL_IMM32_MEM, 319 X86_TUNE_SLOW_IMUL_IMM8, 320 X86_TUNE_MOVE_M1_VIA_OR, 321 X86_TUNE_NOT_UNPAIRABLE, 322 X86_TUNE_NOT_VECTORMODE, 323 X86_TUNE_USE_VECTOR_FP_CONVERTS, 324 X86_TUNE_USE_VECTOR_CONVERTS, 325 X86_TUNE_FUSE_CMP_AND_BRANCH, 326 X86_TUNE_OPT_AGU, 327 X86_TUNE_VECTORIZE_DOUBLE, 328 X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL, 329 X86_TUNE_AVX128_OPTIMAL, 330 X86_TUNE_REASSOC_INT_TO_PARALLEL, 331 X86_TUNE_REASSOC_FP_TO_PARALLEL, 332 X86_TUNE_GENERAL_REGS_SSE_SPILL, 333 X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE, 334 335 X86_TUNE_LAST 336 }; 337 338 extern unsigned char ix86_tune_features[X86_TUNE_LAST]; 339 340 #define TARGET_USE_LEAVE ix86_tune_features[X86_TUNE_USE_LEAVE] 341 #define TARGET_PUSH_MEMORY ix86_tune_features[X86_TUNE_PUSH_MEMORY] 342 #define TARGET_ZERO_EXTEND_WITH_AND \ 343 ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND] 344 #define TARGET_UNROLL_STRLEN ix86_tune_features[X86_TUNE_UNROLL_STRLEN] 345 #define TARGET_BRANCH_PREDICTION_HINTS \ 346 ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS] 347 #define TARGET_DOUBLE_WITH_ADD ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD] 348 #define TARGET_USE_SAHF ix86_tune_features[X86_TUNE_USE_SAHF] 349 #define TARGET_MOVX ix86_tune_features[X86_TUNE_MOVX] 350 #define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL] 351 #define TARGET_PARTIAL_FLAG_REG_STALL \ 352 ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL] 353 #define TARGET_LCP_STALL \ 354 ix86_tune_features[X86_TUNE_LCP_STALL] 355 #define TARGET_USE_HIMODE_FIOP ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP] 356 #define TARGET_USE_SIMODE_FIOP ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP] 357 #define TARGET_USE_MOV0 ix86_tune_features[X86_TUNE_USE_MOV0] 358 #define TARGET_USE_CLTD ix86_tune_features[X86_TUNE_USE_CLTD] 359 #define TARGET_USE_XCHGB ix86_tune_features[X86_TUNE_USE_XCHGB] 360 #define TARGET_SPLIT_LONG_MOVES ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES] 361 #define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE] 362 #define TARGET_READ_MODIFY ix86_tune_features[X86_TUNE_READ_MODIFY] 363 #define TARGET_PROMOTE_QImode ix86_tune_features[X86_TUNE_PROMOTE_QIMODE] 364 #define TARGET_FAST_PREFIX ix86_tune_features[X86_TUNE_FAST_PREFIX] 365 #define TARGET_SINGLE_STRINGOP ix86_tune_features[X86_TUNE_SINGLE_STRINGOP] 366 #define TARGET_QIMODE_MATH ix86_tune_features[X86_TUNE_QIMODE_MATH] 367 #define TARGET_HIMODE_MATH ix86_tune_features[X86_TUNE_HIMODE_MATH] 368 #define TARGET_PROMOTE_QI_REGS ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS] 369 #define TARGET_PROMOTE_HI_REGS ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS] 370 #define TARGET_SINGLE_POP ix86_tune_features[X86_TUNE_SINGLE_POP] 371 #define TARGET_DOUBLE_POP ix86_tune_features[X86_TUNE_DOUBLE_POP] 372 #define TARGET_SINGLE_PUSH ix86_tune_features[X86_TUNE_SINGLE_PUSH] 373 #define TARGET_DOUBLE_PUSH ix86_tune_features[X86_TUNE_DOUBLE_PUSH] 374 #define TARGET_INTEGER_DFMODE_MOVES \ 375 ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES] 376 #define TARGET_PARTIAL_REG_DEPENDENCY \ 377 ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY] 378 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \ 379 ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY] 380 #define TARGET_SSE_UNALIGNED_LOAD_OPTIMAL \ 381 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_LOAD_OPTIMAL] 382 #define TARGET_SSE_UNALIGNED_STORE_OPTIMAL \ 383 ix86_tune_features[X86_TUNE_SSE_UNALIGNED_STORE_OPTIMAL] 384 #define TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL \ 385 ix86_tune_features[X86_TUNE_SSE_PACKED_SINGLE_INSN_OPTIMAL] 386 #define TARGET_SSE_SPLIT_REGS ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS] 387 #define TARGET_SSE_TYPELESS_STORES \ 388 ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES] 389 #define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR] 390 #define TARGET_MEMORY_MISMATCH_STALL \ 391 ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL] 392 #define TARGET_PROLOGUE_USING_MOVE \ 393 ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE] 394 #define TARGET_EPILOGUE_USING_MOVE \ 395 ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE] 396 #define TARGET_SHIFT1 ix86_tune_features[X86_TUNE_SHIFT1] 397 #define TARGET_USE_FFREEP ix86_tune_features[X86_TUNE_USE_FFREEP] 398 #define TARGET_INTER_UNIT_MOVES ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES] 399 #define TARGET_INTER_UNIT_CONVERSIONS\ 400 ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS] 401 #define TARGET_FOUR_JUMP_LIMIT ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT] 402 #define TARGET_SCHEDULE ix86_tune_features[X86_TUNE_SCHEDULE] 403 #define TARGET_USE_BT ix86_tune_features[X86_TUNE_USE_BT] 404 #define TARGET_USE_INCDEC ix86_tune_features[X86_TUNE_USE_INCDEC] 405 #define TARGET_PAD_RETURNS ix86_tune_features[X86_TUNE_PAD_RETURNS] 406 #define TARGET_PAD_SHORT_FUNCTION \ 407 ix86_tune_features[X86_TUNE_PAD_SHORT_FUNCTION] 408 #define TARGET_EXT_80387_CONSTANTS \ 409 ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS] 410 #define TARGET_AVOID_VECTOR_DECODE \ 411 ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE] 412 #define TARGET_TUNE_PROMOTE_HIMODE_IMUL \ 413 ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL] 414 #define TARGET_SLOW_IMUL_IMM32_MEM \ 415 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM] 416 #define TARGET_SLOW_IMUL_IMM8 ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8] 417 #define TARGET_MOVE_M1_VIA_OR ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR] 418 #define TARGET_NOT_UNPAIRABLE ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE] 419 #define TARGET_NOT_VECTORMODE ix86_tune_features[X86_TUNE_NOT_VECTORMODE] 420 #define TARGET_USE_VECTOR_FP_CONVERTS \ 421 ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS] 422 #define TARGET_USE_VECTOR_CONVERTS \ 423 ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS] 424 #define TARGET_FUSE_CMP_AND_BRANCH \ 425 ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH] 426 #define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU] 427 #define TARGET_VECTORIZE_DOUBLE \ 428 ix86_tune_features[X86_TUNE_VECTORIZE_DOUBLE] 429 #define TARGET_SOFTWARE_PREFETCHING_BENEFICIAL \ 430 ix86_tune_features[X86_TUNE_SOFTWARE_PREFETCHING_BENEFICIAL] 431 #define TARGET_AVX128_OPTIMAL \ 432 ix86_tune_features[X86_TUNE_AVX128_OPTIMAL] 433 #define TARGET_REASSOC_INT_TO_PARALLEL \ 434 ix86_tune_features[X86_TUNE_REASSOC_INT_TO_PARALLEL] 435 #define TARGET_REASSOC_FP_TO_PARALLEL \ 436 ix86_tune_features[X86_TUNE_REASSOC_FP_TO_PARALLEL] 437 #define TARGET_GENERAL_REGS_SSE_SPILL \ 438 ix86_tune_features[X86_TUNE_GENERAL_REGS_SSE_SPILL] 439 #define TARGET_AVOID_MEM_OPND_FOR_CMOVE \ 440 ix86_tune_features[X86_TUNE_AVOID_MEM_OPND_FOR_CMOVE] 441 442 /* Feature tests against the various architecture variations. */ 443 enum ix86_arch_indices { 444 X86_ARCH_CMOV, 445 X86_ARCH_CMPXCHG, 446 X86_ARCH_CMPXCHG8B, 447 X86_ARCH_XADD, 448 X86_ARCH_BSWAP, 449 450 X86_ARCH_LAST 451 }; 452 453 extern unsigned char ix86_arch_features[X86_ARCH_LAST]; 454 455 #define TARGET_CMOV ix86_arch_features[X86_ARCH_CMOV] 456 #define TARGET_CMPXCHG ix86_arch_features[X86_ARCH_CMPXCHG] 457 #define TARGET_CMPXCHG8B ix86_arch_features[X86_ARCH_CMPXCHG8B] 458 #define TARGET_XADD ix86_arch_features[X86_ARCH_XADD] 459 #define TARGET_BSWAP ix86_arch_features[X86_ARCH_BSWAP] 460 461 /* For sane SSE instruction set generation we need fcomi instruction. 462 It is safe to enable all CMOVE instructions. Also, RDRAND intrinsic 463 expands to a sequence that includes conditional move. */ 464 #define TARGET_CMOVE (TARGET_CMOV || TARGET_SSE || TARGET_RDRND) 465 466 #define TARGET_FISTTP (TARGET_SSE3 && TARGET_80387) 467 468 extern unsigned char x86_prefetch_sse; 469 #define TARGET_PREFETCH_SSE x86_prefetch_sse 470 471 #define ASSEMBLER_DIALECT (ix86_asm_dialect) 472 473 #define TARGET_SSE_MATH ((ix86_fpmath & FPMATH_SSE) != 0) 474 #define TARGET_MIX_SSE_I387 \ 475 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387)) 476 477 #define TARGET_GNU_TLS (ix86_tls_dialect == TLS_DIALECT_GNU) 478 #define TARGET_GNU2_TLS (ix86_tls_dialect == TLS_DIALECT_GNU2) 479 #define TARGET_ANY_GNU_TLS (TARGET_GNU_TLS || TARGET_GNU2_TLS) 480 #define TARGET_SUN_TLS 0 481 482 #ifndef TARGET_64BIT_DEFAULT 483 #define TARGET_64BIT_DEFAULT 0 484 #endif 485 #ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 486 #define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0 487 #endif 488 489 /* Fence to use after loop using storent. */ 490 491 extern tree x86_mfence; 492 #define FENCE_FOLLOWING_MOVNT x86_mfence 493 494 /* Once GDB has been enhanced to deal with functions without frame 495 pointers, we can change this to allow for elimination of 496 the frame pointer in leaf functions. */ 497 #define TARGET_DEFAULT 0 498 499 /* Extra bits to force. */ 500 #define TARGET_SUBTARGET_DEFAULT 0 501 #define TARGET_SUBTARGET_ISA_DEFAULT 0 502 503 /* Extra bits to force on w/ 32-bit mode. */ 504 #define TARGET_SUBTARGET32_DEFAULT 0 505 #define TARGET_SUBTARGET32_ISA_DEFAULT 0 506 507 /* Extra bits to force on w/ 64-bit mode. */ 508 #define TARGET_SUBTARGET64_DEFAULT 0 509 #define TARGET_SUBTARGET64_ISA_DEFAULT 0 510 511 /* Replace MACH-O, ifdefs by in-line tests, where possible. 512 (a) Macros defined in config/i386/darwin.h */ 513 #define TARGET_MACHO 0 514 #define TARGET_MACHO_BRANCH_ISLANDS 0 515 #define MACHOPIC_ATT_STUB 0 516 /* (b) Macros defined in config/darwin.h */ 517 #define MACHO_DYNAMIC_NO_PIC_P 0 518 #define MACHOPIC_INDIRECT 0 519 #define MACHOPIC_PURE 0 520 521 /* For the RDOS */ 522 #define TARGET_RDOS 0 523 524 /* For the Windows 64-bit ABI. */ 525 #define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 526 527 /* For the Windows 32-bit ABI. */ 528 #define TARGET_32BIT_MS_ABI (!TARGET_64BIT && ix86_cfun_abi () == MS_ABI) 529 530 /* This is re-defined by cygming.h. */ 531 #define TARGET_SEH 0 532 533 /* The default abi used by target. */ 534 #define DEFAULT_ABI SYSV_ABI 535 536 /* Subtargets may reset this to 1 in order to enable 96-bit long double 537 with the rounding mode forced to 53 bits. */ 538 #define TARGET_96_ROUND_53_LONG_DOUBLE 0 539 540 /* -march=native handling only makes sense with compiler running on 541 an x86 or x86_64 chip. If changing this condition, also change 542 the condition in driver-i386.c. */ 543 #if defined(__i386__) || defined(__x86_64__) 544 /* In driver-i386.c. */ 545 extern const char *host_detect_local_cpu (int argc, const char **argv); 546 #define EXTRA_SPEC_FUNCTIONS \ 547 { "local_cpu_detect", host_detect_local_cpu }, 548 #define HAVE_LOCAL_CPU_DETECT 549 #endif 550 551 #if TARGET_64BIT_DEFAULT 552 #define OPT_ARCH64 "!m32" 553 #define OPT_ARCH32 "m32" 554 #else 555 #define OPT_ARCH64 "m64|mx32" 556 #define OPT_ARCH32 "m64|mx32:;" 557 #endif 558 559 /* Support for configure-time defaults of some command line options. 560 The order here is important so that -march doesn't squash the 561 tune or cpu values. */ 562 #define OPTION_DEFAULT_SPECS \ 563 {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 564 {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 565 {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 566 {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \ 567 {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 568 {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \ 569 {"arch", "%{!march=*:-march=%(VALUE)}"}, \ 570 {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"}, \ 571 {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"}, 572 573 /* Specs for the compiler proper */ 574 575 #ifndef CC1_CPU_SPEC 576 #define CC1_CPU_SPEC_1 "" 577 578 #ifndef HAVE_LOCAL_CPU_DETECT 579 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 580 #else 581 #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ 582 "%{march=native:%>march=native %:local_cpu_detect(arch) \ 583 %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ 584 %{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" 585 #endif 586 #endif 587 588 /* Target CPU builtins. */ 590 #define TARGET_CPU_CPP_BUILTINS() ix86_target_macros () 591 592 /* Target Pragmas. */ 593 #define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas () 594 595 #ifndef CC1_SPEC 596 #define CC1_SPEC "%(cc1_cpu) " 597 #endif 598 599 /* This macro defines names of additional specifications to put in the 600 specs that can be used in various specifications like CC1_SPEC. Its 601 definition is an initializer with a subgrouping for each command option. 602 603 Each subgrouping contains a string constant, that defines the 604 specification name, and a string constant that used by the GCC driver 605 program. 606 607 Do not define this macro if it does not need to do anything. */ 608 609 #ifndef SUBTARGET_EXTRA_SPECS 610 #define SUBTARGET_EXTRA_SPECS 611 #endif 612 613 #define EXTRA_SPECS \ 614 { "cc1_cpu", CC1_CPU_SPEC }, \ 615 SUBTARGET_EXTRA_SPECS 616 617 619 /* Set the value of FLT_EVAL_METHOD in float.h. When using only the 620 FPU, assume that the fpcw is set to extended precision; when using 621 only SSE, rounding is correct; when using both SSE and the FPU, 622 the rounding precision is indeterminate, since either may be chosen 623 apparently at random. */ 624 #define TARGET_FLT_EVAL_METHOD \ 625 (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2) 626 627 /* Whether to allow x87 floating-point arithmetic on MODE (one of 628 SFmode, DFmode and XFmode) in the current excess precision 629 configuration. */ 630 #define X87_ENABLE_ARITH(MODE) \ 631 (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode) 632 633 /* Likewise, whether to allow direct conversions from integer mode 634 IMODE (HImode, SImode or DImode) to MODE. */ 635 #define X87_ENABLE_FLOAT(MODE, IMODE) \ 636 (flag_excess_precision == EXCESS_PRECISION_FAST \ 637 || (MODE) == XFmode \ 638 || ((MODE) == DFmode && (IMODE) == SImode) \ 639 || (IMODE) == HImode) 640 641 /* target machine storage layout */ 642 643 #define SHORT_TYPE_SIZE 16 644 #define INT_TYPE_SIZE 32 645 #define LONG_TYPE_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 646 #define POINTER_SIZE (TARGET_X32 ? 32 : BITS_PER_WORD) 647 #define LONG_LONG_TYPE_SIZE 64 648 #define FLOAT_TYPE_SIZE 32 649 #define DOUBLE_TYPE_SIZE 64 650 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_64 ? 64 : 80) 651 652 /* Define this to set long double type size to use in libgcc2.c, which can 653 not depend on target_flags. */ 654 #ifdef __LONG_DOUBLE_64__ 655 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 656 #else 657 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 658 #endif 659 660 #define WIDEST_HARDWARE_FP_SIZE 80 661 662 #if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT 663 #define MAX_BITS_PER_WORD 64 664 #else 665 #define MAX_BITS_PER_WORD 32 666 #endif 667 668 /* Define this if most significant byte of a word is the lowest numbered. */ 669 /* That is true on the 80386. */ 670 671 #define BITS_BIG_ENDIAN 0 672 673 /* Define this if most significant byte of a word is the lowest numbered. */ 674 /* That is not true on the 80386. */ 675 #define BYTES_BIG_ENDIAN 0 676 677 /* Define this if most significant word of a multiword number is the lowest 678 numbered. */ 679 /* Not true for 80386 */ 680 #define WORDS_BIG_ENDIAN 0 681 682 /* Width of a word, in units (bytes). */ 683 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 684 685 #ifndef IN_LIBGCC2 686 #define MIN_UNITS_PER_WORD 4 687 #endif 688 689 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 690 #define PARM_BOUNDARY BITS_PER_WORD 691 692 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 693 #define STACK_BOUNDARY \ 694 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD) 695 696 /* Stack boundary of the main function guaranteed by OS. */ 697 #define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32) 698 699 /* Minimum stack boundary. */ 700 #define MIN_STACK_BOUNDARY (TARGET_64BIT ? (TARGET_SSE ? 128 : 64) : 32) 701 702 /* Boundary (in *bits*) on which the stack pointer prefers to be 703 aligned; the compiler cannot rely on having this alignment. */ 704 #define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary 705 706 /* It should be MIN_STACK_BOUNDARY. But we set it to 128 bits for 707 both 32bit and 64bit, to support codes that need 128 bit stack 708 alignment for SSE instructions, but can't realign the stack. */ 709 #define PREFERRED_STACK_BOUNDARY_DEFAULT 128 710 711 /* 1 if -mstackrealign should be turned on by default. It will 712 generate an alternate prologue and epilogue that realigns the 713 runtime stack if nessary. This supports mixing codes that keep a 714 4-byte aligned stack, as specified by i386 psABI, with codes that 715 need a 16-byte aligned stack, as required by SSE instructions. */ 716 #define STACK_REALIGN_DEFAULT 0 717 718 /* Boundary (in *bits*) on which the incoming stack is aligned. */ 719 #define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary 720 721 /* According to Windows x64 software convention, the maximum stack allocatable 722 in the prologue is 4G - 8 bytes. Furthermore, there is a limited set of 723 instructions allowed to adjust the stack pointer in the epilog, forcing the 724 use of frame pointer for frames larger than 2 GB. This theorical limit 725 is reduced by 256, an over-estimated upper bound for the stack use by the 726 prologue. 727 We define only one threshold for both the prolog and the epilog. When the 728 frame size is larger than this threshold, we allocate the area to save SSE 729 regs, then save them, and then allocate the remaining. There is no SEH 730 unwind info for this later allocation. */ 731 #define SEH_MAX_FRAME_SIZE ((2U << 30) - 256) 732 733 /* Target OS keeps a vector-aligned (128-bit, 16-byte) stack. This is 734 mandatory for the 64-bit ABI, and may or may not be true for other 735 operating systems. */ 736 #define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT 737 738 /* Minimum allocation boundary for the code of a function. */ 739 #define FUNCTION_BOUNDARY 8 740 741 /* C++ stores the virtual bit in the lowest bit of function pointers. */ 742 #define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn 743 744 /* Minimum size in bits of the largest boundary to which any 745 and all fundamental data types supported by the hardware 746 might need to be aligned. No data type wants to be aligned 747 rounder than this. 748 749 Pentium+ prefers DFmode values to be aligned to 64 bit boundary 750 and Pentium Pro XFmode values at 128 bit boundaries. */ 751 752 #define BIGGEST_ALIGNMENT (TARGET_AVX ? 256 : 128) 753 754 /* Maximum stack alignment. */ 755 #define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT 756 757 /* Alignment value for attribute ((aligned)). It is a constant since 758 it is the part of the ABI. We shouldn't change it with -mavx. */ 759 #define ATTRIBUTE_ALIGNED_VALUE 128 760 761 /* Decide whether a variable of mode MODE should be 128 bit aligned. */ 762 #define ALIGN_MODE_128(MODE) \ 763 ((MODE) == XFmode || SSE_REG_MODE_P (MODE)) 764 765 /* The published ABIs say that doubles should be aligned on word 766 boundaries, so lower the alignment for structure fields unless 767 -malign-double is set. */ 768 769 /* ??? Blah -- this macro is used directly by libobjc. Since it 770 supports no vector modes, cut out the complexity and fall back 771 on BIGGEST_FIELD_ALIGNMENT. */ 772 #ifdef IN_TARGET_LIBS 773 #ifdef __x86_64__ 774 #define BIGGEST_FIELD_ALIGNMENT 128 775 #else 776 #define BIGGEST_FIELD_ALIGNMENT 32 777 #endif 778 #else 779 #define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \ 780 x86_field_alignment (FIELD, COMPUTED) 781 #endif 782 783 /* If defined, a C expression to compute the alignment given to a 784 constant that is being placed in memory. EXP is the constant 785 and ALIGN is the alignment that the object would ordinarily have. 786 The value of this macro is used instead of that alignment to align 787 the object. 788 789 If this macro is not defined, then ALIGN is used. 790 791 The typical use of this macro is to increase alignment for string 792 constants to be word aligned so that `strcpy' calls that copy 793 constants can be done inline. */ 794 795 #define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN)) 796 797 /* If defined, a C expression to compute the alignment for a static 798 variable. TYPE is the data type, and ALIGN is the alignment that 799 the object would ordinarily have. The value of this macro is used 800 instead of that alignment to align the object. 801 802 If this macro is not defined, then ALIGN is used. 803 804 One use of this macro is to increase alignment of medium-size 805 data to make it all fit in fewer cache lines. Another is to 806 cause character arrays to be word-aligned so that `strcpy' calls 807 that copy constants to character arrays can be done inline. */ 808 809 #define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN)) 810 811 /* If defined, a C expression to compute the alignment for a local 812 variable. TYPE is the data type, and ALIGN is the alignment that 813 the object would ordinarily have. The value of this macro is used 814 instead of that alignment to align the object. 815 816 If this macro is not defined, then ALIGN is used. 817 818 One use of this macro is to increase alignment of medium-size 819 data to make it all fit in fewer cache lines. */ 820 821 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 822 ix86_local_alignment ((TYPE), VOIDmode, (ALIGN)) 823 824 /* If defined, a C expression to compute the alignment for stack slot. 825 TYPE is the data type, MODE is the widest mode available, and ALIGN 826 is the alignment that the slot would ordinarily have. The value of 827 this macro is used instead of that alignment to align the slot. 828 829 If this macro is not defined, then ALIGN is used when TYPE is NULL, 830 Otherwise, LOCAL_ALIGNMENT will be used. 831 832 One use of this macro is to set alignment of stack slot to the 833 maximum alignment of all possible modes which the slot may have. */ 834 835 #define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \ 836 ix86_local_alignment ((TYPE), (MODE), (ALIGN)) 837 838 /* If defined, a C expression to compute the alignment for a local 839 variable DECL. 840 841 If this macro is not defined, then 842 LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used. 843 844 One use of this macro is to increase alignment of medium-size 845 data to make it all fit in fewer cache lines. */ 846 847 #define LOCAL_DECL_ALIGNMENT(DECL) \ 848 ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL)) 849 850 /* If defined, a C expression to compute the minimum required alignment 851 for dynamic stack realignment purposes for EXP (a TYPE or DECL), 852 MODE, assuming normal alignment ALIGN. 853 854 If this macro is not defined, then (ALIGN) will be used. */ 855 856 #define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \ 857 ix86_minimum_alignment (EXP, MODE, ALIGN) 858 859 860 /* Set this nonzero if move instructions will actually fail to work 861 when given unaligned data. */ 862 #define STRICT_ALIGNMENT 0 863 864 /* If bit field type is int, don't let it cross an int, 865 and give entire struct the alignment of an int. */ 866 /* Required on the 386 since it doesn't have bit-field insns. */ 867 #define PCC_BITFIELD_TYPE_MATTERS 1 868 869 /* Standard register usage. */ 871 872 /* This processor has special stack-like registers. See reg-stack.c 873 for details. */ 874 875 #define STACK_REGS 876 877 #define IS_STACK_MODE(MODE) \ 878 (((MODE) == SFmode && !(TARGET_SSE && TARGET_SSE_MATH)) \ 879 || ((MODE) == DFmode && !(TARGET_SSE2 && TARGET_SSE_MATH)) \ 880 || (MODE) == XFmode) 881 882 /* Number of actual hardware registers. 883 The hardware registers are assigned numbers for the compiler 884 from 0 to just below FIRST_PSEUDO_REGISTER. 885 All registers that the compiler knows about must be given numbers, 886 even those that are not normally considered general registers. 887 888 In the 80386 we give the 8 general purpose registers the numbers 0-7. 889 We number the floating point registers 8-15. 890 Note that registers 0-7 can be accessed as a short or int, 891 while only 0-3 may be used with byte `mov' instructions. 892 893 Reg 16 does not correspond to any hardware register, but instead 894 appears in the RTL as an argument pointer prior to reload, and is 895 eliminated during reloading in favor of either the stack or frame 896 pointer. */ 897 898 #define FIRST_PSEUDO_REGISTER 53 899 900 /* Number of hardware registers that go into the DWARF-2 unwind info. 901 If not defined, equals FIRST_PSEUDO_REGISTER. */ 902 903 #define DWARF_FRAME_REGISTERS 17 904 905 /* 1 for registers that have pervasive standard uses 906 and are not available for the register allocator. 907 On the 80386, the stack pointer is such, as is the arg pointer. 908 909 REX registers are disabled for 32bit targets in 910 TARGET_CONDITIONAL_REGISTER_USAGE. */ 911 912 #define FIXED_REGISTERS \ 913 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 914 { 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, \ 915 /*arg,flags,fpsr,fpcr,frame*/ \ 916 1, 1, 1, 1, 1, \ 917 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 918 0, 0, 0, 0, 0, 0, 0, 0, \ 919 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 920 0, 0, 0, 0, 0, 0, 0, 0, \ 921 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 922 0, 0, 0, 0, 0, 0, 0, 0, \ 923 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 924 0, 0, 0, 0, 0, 0, 0, 0 } 925 926 /* 1 for registers not available across function calls. 927 These must include the FIXED_REGISTERS and also any 928 registers that can be used without being saved. 929 The latter must include the registers where values are returned 930 and the register where structure-value addresses are passed. 931 Aside from that, you can include as many other registers as you like. 932 933 Value is set to 1 if the register is call used unconditionally. 934 Bit one is set if the register is call used on TARGET_32BIT ABI. 935 Bit two is set if the register is call used on TARGET_64BIT ABI. 936 Bit three is set if the register is call used on TARGET_64BIT_MS_ABI. 937 938 Proper values are computed in TARGET_CONDITIONAL_REGISTER_USAGE. */ 939 940 #define CALL_USED_REGISTERS \ 941 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/ \ 942 { 1, 1, 1, 0, 4, 4, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 943 /*arg,flags,fpsr,fpcr,frame*/ \ 944 1, 1, 1, 1, 1, \ 945 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/ \ 946 1, 1, 1, 1, 1, 1, 6, 6, \ 947 /* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/ \ 948 1, 1, 1, 1, 1, 1, 1, 1, \ 949 /* r8, r9, r10, r11, r12, r13, r14, r15*/ \ 950 1, 1, 1, 1, 2, 2, 2, 2, \ 951 /*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/ \ 952 6, 6, 6, 6, 6, 6, 6, 6 } 953 954 /* Order in which to allocate registers. Each register must be 955 listed once, even those in FIXED_REGISTERS. List frame pointer 956 late and fixed registers last. Note that, in general, we prefer 957 registers listed in CALL_USED_REGISTERS, keeping the others 958 available for storage of persistent values. 959 960 The ADJUST_REG_ALLOC_ORDER actually overwrite the order, 961 so this is just empty initializer for array. */ 962 963 #define REG_ALLOC_ORDER \ 964 { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\ 965 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \ 966 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ 967 48, 49, 50, 51, 52 } 968 969 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 970 to be rearranged based on a particular function. When using sse math, 971 we want to allocate SSE before x87 registers and vice versa. */ 972 973 #define ADJUST_REG_ALLOC_ORDER x86_order_regs_for_local_alloc () 974 975 976 #define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL) 977 978 /* Return number of consecutive hard regs needed starting at reg REGNO 979 to hold something of mode MODE. 980 This is ordinarily the length in words of a value of mode MODE 981 but can be less for certain modes in special long registers. 982 983 Actually there are no two word move instructions for consecutive 984 registers. And only registers 0-3 may have mov byte instructions 985 applied to them. */ 986 987 #define HARD_REGNO_NREGS(REGNO, MODE) \ 988 (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 989 ? (COMPLEX_MODE_P (MODE) ? 2 : 1) \ 990 : ((MODE) == XFmode \ 991 ? (TARGET_64BIT ? 2 : 3) \ 992 : (MODE) == XCmode \ 993 ? (TARGET_64BIT ? 4 : 6) \ 994 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 995 996 #define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE) \ 997 ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT) \ 998 ? (STACK_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO) \ 999 ? 0 \ 1000 : ((MODE) == XFmode || (MODE) == XCmode)) \ 1001 : 0) 1002 1003 #define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8) 1004 1005 #define VALID_AVX256_REG_MODE(MODE) \ 1006 ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1007 || (MODE) == V4DImode || (MODE) == V2TImode || (MODE) == V8SFmode \ 1008 || (MODE) == V4DFmode) 1009 1010 #define VALID_AVX256_REG_OR_OI_MODE(MODE) \ 1011 (VALID_AVX256_REG_MODE (MODE) || (MODE) == OImode) 1012 1013 #define VALID_SSE2_REG_MODE(MODE) \ 1014 ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1015 || (MODE) == V2DImode || (MODE) == DFmode) 1016 1017 #define VALID_SSE_REG_MODE(MODE) \ 1018 ((MODE) == V1TImode || (MODE) == TImode \ 1019 || (MODE) == V4SFmode || (MODE) == V4SImode \ 1020 || (MODE) == SFmode || (MODE) == TFmode) 1021 1022 #define VALID_MMX_REG_MODE_3DNOW(MODE) \ 1023 ((MODE) == V2SFmode || (MODE) == SFmode) 1024 1025 #define VALID_MMX_REG_MODE(MODE) \ 1026 ((MODE == V1DImode) || (MODE) == DImode \ 1027 || (MODE) == V2SImode || (MODE) == SImode \ 1028 || (MODE) == V4HImode || (MODE) == V8QImode) 1029 1030 #define VALID_DFP_MODE_P(MODE) \ 1031 ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode) 1032 1033 #define VALID_FP_MODE_P(MODE) \ 1034 ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode \ 1035 || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode) \ 1036 1037 #define VALID_INT_MODE_P(MODE) \ 1038 ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode \ 1039 || (MODE) == DImode \ 1040 || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode \ 1041 || (MODE) == CDImode \ 1042 || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode \ 1043 || (MODE) == TFmode || (MODE) == TCmode))) 1044 1045 /* Return true for modes passed in SSE registers. */ 1046 #define SSE_REG_MODE_P(MODE) \ 1047 ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode \ 1048 || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode \ 1049 || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode \ 1050 || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode \ 1051 || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode \ 1052 || (MODE) == V2TImode) 1053 1054 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 1055 1056 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1057 ix86_hard_regno_mode_ok ((REGNO), (MODE)) 1058 1059 /* Value is 1 if it is a good idea to tie two pseudo registers 1060 when one has mode MODE1 and one has mode MODE2. 1061 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1062 for any hard reg, then this must be 0 for correct output. */ 1063 1064 #define MODES_TIEABLE_P(MODE1, MODE2) ix86_modes_tieable_p (MODE1, MODE2) 1065 1066 /* It is possible to write patterns to move flags; but until someone 1067 does it, */ 1068 #define AVOID_CCMODE_COPIES 1069 1070 /* Specify the modes required to caller save a given hard regno. 1071 We do this on i386 to prevent flags from being saved at all. 1072 1073 Kill any attempts to combine saving of modes. */ 1074 1075 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1076 (CC_REGNO_P (REGNO) ? VOIDmode \ 1077 : MMX_REGNO_P (REGNO) ? V8QImode \ 1078 : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode \ 1079 : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \ 1080 : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode \ 1081 : (MODE) == QImode && !(TARGET_64BIT || QI_REGNO_P (REGNO)) ? SImode \ 1082 : (MODE)) 1083 1084 /* The only ABI that saves SSE registers across calls is Win64 (thus no 1085 need to check the current ABI here), and with AVX enabled Win64 only 1086 guarantees that the low 16 bytes are saved. */ 1087 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1088 (SSE_REGNO_P (REGNO) && GET_MODE_SIZE (MODE) > 16) 1089 1090 /* Specify the registers used for certain standard purposes. 1091 The values of these macros are register numbers. */ 1092 1093 /* on the 386 the pc register is %eip, and is not usable as a general 1094 register. The ordinary mov instructions won't work */ 1095 /* #define PC_REGNUM */ 1096 1097 /* Register to use for pushing function arguments. */ 1098 #define STACK_POINTER_REGNUM 7 1099 1100 /* Base register for access to local variables of the function. */ 1101 #define HARD_FRAME_POINTER_REGNUM 6 1102 1103 /* Base register for access to local variables of the function. */ 1104 #define FRAME_POINTER_REGNUM 20 1105 1106 /* First floating point reg */ 1107 #define FIRST_FLOAT_REG 8 1108 1109 /* First & last stack-like regs */ 1110 #define FIRST_STACK_REG FIRST_FLOAT_REG 1111 #define LAST_STACK_REG (FIRST_FLOAT_REG + 7) 1112 1113 #define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1) 1114 #define LAST_SSE_REG (FIRST_SSE_REG + 7) 1115 1116 #define FIRST_MMX_REG (LAST_SSE_REG + 1) 1117 #define LAST_MMX_REG (FIRST_MMX_REG + 7) 1118 1119 #define FIRST_REX_INT_REG (LAST_MMX_REG + 1) 1120 #define LAST_REX_INT_REG (FIRST_REX_INT_REG + 7) 1121 1122 #define FIRST_REX_SSE_REG (LAST_REX_INT_REG + 1) 1123 #define LAST_REX_SSE_REG (FIRST_REX_SSE_REG + 7) 1124 1125 /* Override this in other tm.h files to cope with various OS lossage 1126 requiring a frame pointer. */ 1127 #ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1128 #define SUBTARGET_FRAME_POINTER_REQUIRED 0 1129 #endif 1130 1131 /* Make sure we can access arbitrary call frames. */ 1132 #define SETUP_FRAME_ADDRESSES() ix86_setup_frame_addresses () 1133 1134 /* Base register for access to arguments of the function. */ 1135 #define ARG_POINTER_REGNUM 16 1136 1137 /* Register to hold the addressing base for position independent 1138 code access to data items. We don't use PIC pointer for 64bit 1139 mode. Define the regnum to dummy value to prevent gcc from 1140 pessimizing code dealing with EBX. 1141 1142 To avoid clobbering a call-saved register unnecessarily, we renumber 1143 the pic register when possible. The change is visible after the 1144 prologue has been emitted. */ 1145 1146 #define REAL_PIC_OFFSET_TABLE_REGNUM BX_REG 1147 1148 #define PIC_OFFSET_TABLE_REGNUM \ 1149 ((TARGET_64BIT && ix86_cmodel == CM_SMALL_PIC) \ 1150 || !flag_pic ? INVALID_REGNUM \ 1151 : reload_completed ? REGNO (pic_offset_table_rtx) \ 1152 : REAL_PIC_OFFSET_TABLE_REGNUM) 1153 1154 #define GOT_SYMBOL_NAME "_GLOBAL_OFFSET_TABLE_" 1155 1156 /* This is overridden by <cygwin.h>. */ 1157 #define MS_AGGREGATE_RETURN 0 1158 1159 #define KEEP_AGGREGATE_RETURN_POINTER 0 1160 1161 /* Define the classes of registers for register constraints in the 1163 machine description. Also define ranges of constants. 1164 1165 One of the classes must always be named ALL_REGS and include all hard regs. 1166 If there is more than one class, another class must be named NO_REGS 1167 and contain no registers. 1168 1169 The name GENERAL_REGS must be the name of a class (or an alias for 1170 another name such as ALL_REGS). This is the class of registers 1171 that is allowed by "g" or "r" in a register constraint. 1172 Also, registers outside this class are allocated only when 1173 instructions express preferences for them. 1174 1175 The classes must be numbered in nondecreasing order; that is, 1176 a larger-numbered class must never be contained completely 1177 in a smaller-numbered class. 1178 1179 For any two classes, it is very desirable that there be another 1180 class that represents their union. 1181 1182 It might seem that class BREG is unnecessary, since no useful 386 1183 opcode needs reg %ebx. But some systems pass args to the OS in ebx, 1184 and the "b" register constraint is useful in asms for syscalls. 1185 1186 The flags, fpsr and fpcr registers are in no class. */ 1187 1188 enum reg_class 1189 { 1190 NO_REGS, 1191 AREG, DREG, CREG, BREG, SIREG, DIREG, 1192 AD_REGS, /* %eax/%edx for DImode */ 1193 Q_REGS, /* %eax %ebx %ecx %edx */ 1194 NON_Q_REGS, /* %esi %edi %ebp %esp */ 1195 INDEX_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp */ 1196 LEGACY_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp */ 1197 CLOBBERED_REGS, /* call-clobbered integer registers */ 1198 GENERAL_REGS, /* %eax %ebx %ecx %edx %esi %edi %ebp %esp 1199 %r8 %r9 %r10 %r11 %r12 %r13 %r14 %r15 */ 1200 FP_TOP_REG, FP_SECOND_REG, /* %st(0) %st(1) */ 1201 FLOAT_REGS, 1202 SSE_FIRST_REG, 1203 SSE_REGS, 1204 MMX_REGS, 1205 FP_TOP_SSE_REGS, 1206 FP_SECOND_SSE_REGS, 1207 FLOAT_SSE_REGS, 1208 FLOAT_INT_REGS, 1209 INT_SSE_REGS, 1210 FLOAT_INT_SSE_REGS, 1211 ALL_REGS, LIM_REG_CLASSES 1212 }; 1213 1214 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 1215 1216 #define INTEGER_CLASS_P(CLASS) \ 1217 reg_class_subset_p ((CLASS), GENERAL_REGS) 1218 #define FLOAT_CLASS_P(CLASS) \ 1219 reg_class_subset_p ((CLASS), FLOAT_REGS) 1220 #define SSE_CLASS_P(CLASS) \ 1221 reg_class_subset_p ((CLASS), SSE_REGS) 1222 #define MMX_CLASS_P(CLASS) \ 1223 ((CLASS) == MMX_REGS) 1224 #define MAYBE_INTEGER_CLASS_P(CLASS) \ 1225 reg_classes_intersect_p ((CLASS), GENERAL_REGS) 1226 #define MAYBE_FLOAT_CLASS_P(CLASS) \ 1227 reg_classes_intersect_p ((CLASS), FLOAT_REGS) 1228 #define MAYBE_SSE_CLASS_P(CLASS) \ 1229 reg_classes_intersect_p (SSE_REGS, (CLASS)) 1230 #define MAYBE_MMX_CLASS_P(CLASS) \ 1231 reg_classes_intersect_p (MMX_REGS, (CLASS)) 1232 1233 #define Q_CLASS_P(CLASS) \ 1234 reg_class_subset_p ((CLASS), Q_REGS) 1235 1236 /* Give names of register classes as strings for dump file. */ 1237 1238 #define REG_CLASS_NAMES \ 1239 { "NO_REGS", \ 1240 "AREG", "DREG", "CREG", "BREG", \ 1241 "SIREG", "DIREG", \ 1242 "AD_REGS", \ 1243 "Q_REGS", "NON_Q_REGS", \ 1244 "INDEX_REGS", \ 1245 "LEGACY_REGS", \ 1246 "CLOBBERED_REGS", \ 1247 "GENERAL_REGS", \ 1248 "FP_TOP_REG", "FP_SECOND_REG", \ 1249 "FLOAT_REGS", \ 1250 "SSE_FIRST_REG", \ 1251 "SSE_REGS", \ 1252 "MMX_REGS", \ 1253 "FP_TOP_SSE_REGS", \ 1254 "FP_SECOND_SSE_REGS", \ 1255 "FLOAT_SSE_REGS", \ 1256 "FLOAT_INT_REGS", \ 1257 "INT_SSE_REGS", \ 1258 "FLOAT_INT_SSE_REGS", \ 1259 "ALL_REGS" } 1260 1261 /* Define which registers fit in which classes. This is an initializer 1262 for a vector of HARD_REG_SET of length N_REG_CLASSES. 1263 1264 Note that CLOBBERED_REGS are calculated by 1265 TARGET_CONDITIONAL_REGISTER_USAGE. */ 1266 1267 #define REG_CLASS_CONTENTS \ 1268 { { 0x00, 0x0 }, \ 1269 { 0x01, 0x0 }, { 0x02, 0x0 }, /* AREG, DREG */ \ 1270 { 0x04, 0x0 }, { 0x08, 0x0 }, /* CREG, BREG */ \ 1271 { 0x10, 0x0 }, { 0x20, 0x0 }, /* SIREG, DIREG */ \ 1272 { 0x03, 0x0 }, /* AD_REGS */ \ 1273 { 0x0f, 0x0 }, /* Q_REGS */ \ 1274 { 0x1100f0, 0x1fe0 }, /* NON_Q_REGS */ \ 1275 { 0x7f, 0x1fe0 }, /* INDEX_REGS */ \ 1276 { 0x1100ff, 0x0 }, /* LEGACY_REGS */ \ 1277 { 0x00, 0x0 }, /* CLOBBERED_REGS */ \ 1278 { 0x1100ff, 0x1fe0 }, /* GENERAL_REGS */ \ 1279 { 0x100, 0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\ 1280 { 0xff00, 0x0 }, /* FLOAT_REGS */ \ 1281 { 0x200000, 0x0 }, /* SSE_FIRST_REG */ \ 1282 { 0x1fe00000,0x1fe000 }, /* SSE_REGS */ \ 1283 { 0xe0000000, 0x1f }, /* MMX_REGS */ \ 1284 { 0x1fe00100,0x1fe000 }, /* FP_TOP_SSE_REG */ \ 1285 { 0x1fe00200,0x1fe000 }, /* FP_SECOND_SSE_REG */ \ 1286 { 0x1fe0ff00,0x1fe000 }, /* FLOAT_SSE_REGS */ \ 1287 { 0x11ffff, 0x1fe0 }, /* FLOAT_INT_REGS */ \ 1288 { 0x1ff100ff,0x1fffe0 }, /* INT_SSE_REGS */ \ 1289 { 0x1ff1ffff,0x1fffe0 }, /* FLOAT_INT_SSE_REGS */ \ 1290 { 0xffffffff,0x1fffff } \ 1291 } 1292 1293 /* The same information, inverted: 1294 Return the class number of the smallest class containing 1295 reg number REGNO. This could be a conditional expression 1296 or could index an array. */ 1297 1298 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 1299 1300 /* When this hook returns true for MODE, the compiler allows 1301 registers explicitly used in the rtl to be used as spill registers 1302 but prevents the compiler from extending the lifetime of these 1303 registers. */ 1304 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 1305 1306 #define QI_REG_P(X) (REG_P (X) && QI_REGNO_P (REGNO (X))) 1307 #define QI_REGNO_P(N) IN_RANGE ((N), AX_REG, BX_REG) 1308 1309 #define GENERAL_REG_P(X) \ 1310 (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 1311 #define GENERAL_REGNO_P(N) \ 1312 (IN_RANGE ((N), AX_REG, SP_REG) || REX_INT_REGNO_P (N)) 1313 1314 #define ANY_QI_REG_P(X) (REG_P (X) && ANY_QI_REGNO_P (REGNO (X))) 1315 #define ANY_QI_REGNO_P(N) \ 1316 (TARGET_64BIT ? GENERAL_REGNO_P (N) : QI_REGNO_P (N)) 1317 1318 #define REX_INT_REG_P(X) (REG_P (X) && REX_INT_REGNO_P (REGNO (X))) 1319 #define REX_INT_REGNO_P(N) \ 1320 IN_RANGE ((N), FIRST_REX_INT_REG, LAST_REX_INT_REG) 1321 1322 #define STACK_REG_P(X) (REG_P (X) && STACK_REGNO_P (REGNO (X))) 1323 #define STACK_REGNO_P(N) IN_RANGE ((N), FIRST_STACK_REG, LAST_STACK_REG) 1324 1325 #define ANY_FP_REG_P(X) (REG_P (X) && ANY_FP_REGNO_P (REGNO (X))) 1326 #define ANY_FP_REGNO_P(N) (STACK_REGNO_P (N) || SSE_REGNO_P (N)) 1327 1328 #define X87_FLOAT_MODE_P(MODE) \ 1329 (TARGET_80387 && ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode)) 1330 1331 #define SSE_REG_P(X) (REG_P (X) && SSE_REGNO_P (REGNO (X))) 1332 #define SSE_REGNO_P(N) \ 1333 (IN_RANGE ((N), FIRST_SSE_REG, LAST_SSE_REG) \ 1334 || REX_SSE_REGNO_P (N)) 1335 1336 #define REX_SSE_REGNO_P(N) \ 1337 IN_RANGE ((N), FIRST_REX_SSE_REG, LAST_REX_SSE_REG) 1338 1339 #define SSE_REGNO(N) \ 1340 ((N) < 8 ? FIRST_SSE_REG + (N) : FIRST_REX_SSE_REG + (N) - 8) 1341 1342 #define SSE_FLOAT_MODE_P(MODE) \ 1343 ((TARGET_SSE && (MODE) == SFmode) || (TARGET_SSE2 && (MODE) == DFmode)) 1344 1345 #define FMA4_VEC_FLOAT_MODE_P(MODE) \ 1346 (TARGET_FMA4 && ((MODE) == V4SFmode || (MODE) == V2DFmode \ 1347 || (MODE) == V8SFmode || (MODE) == V4DFmode)) 1348 1349 #define MMX_REG_P(X) (REG_P (X) && MMX_REGNO_P (REGNO (X))) 1350 #define MMX_REGNO_P(N) IN_RANGE ((N), FIRST_MMX_REG, LAST_MMX_REG) 1351 1352 #define STACK_TOP_P(X) (REG_P (X) && REGNO (X) == FIRST_STACK_REG) 1353 1354 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 1355 #define CC_REGNO_P(X) ((X) == FLAGS_REG || (X) == FPSR_REG) 1356 1357 /* The class value for index registers, and the one for base regs. */ 1358 1359 #define INDEX_REG_CLASS INDEX_REGS 1360 #define BASE_REG_CLASS GENERAL_REGS 1361 1362 /* Place additional restrictions on the register class to use when it 1363 is necessary to be able to hold a value of mode MODE in a reload 1364 register for which class CLASS would ordinarily be used. 1365 1366 We avoid classes containing registers from multiple units due to 1367 the limitation in ix86_secondary_memory_needed. We limit these 1368 classes to their "natural mode" single unit register class, depending 1369 on the unit availability. 1370 1371 Please note that reg_class_subset_p is not commutative, so these 1372 conditions mean "... if (CLASS) includes ALL registers from the 1373 register set." */ 1374 1375 #define LIMIT_RELOAD_CLASS(MODE, CLASS) \ 1376 (((MODE) == QImode && !TARGET_64BIT \ 1377 && reg_class_subset_p (Q_REGS, (CLASS))) ? Q_REGS \ 1378 : (((MODE) == SImode || (MODE) == DImode) \ 1379 && reg_class_subset_p (GENERAL_REGS, (CLASS))) ? GENERAL_REGS \ 1380 : (SSE_FLOAT_MODE_P (MODE) && TARGET_SSE_MATH \ 1381 && reg_class_subset_p (SSE_REGS, (CLASS))) ? SSE_REGS \ 1382 : (X87_FLOAT_MODE_P (MODE) \ 1383 && reg_class_subset_p (FLOAT_REGS, (CLASS))) ? FLOAT_REGS \ 1384 : (CLASS)) 1385 1386 /* If we are copying between general and FP registers, we need a memory 1387 location. The same is true for SSE and MMX registers. */ 1388 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1389 ix86_secondary_memory_needed ((CLASS1), (CLASS2), (MODE), 1) 1390 1391 /* Get_secondary_mem widens integral modes to BITS_PER_WORD. 1392 There is no need to emit full 64 bit move on 64 bit targets 1393 for integral modes that can be moved using 32 bit move. */ 1394 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 1395 (GET_MODE_BITSIZE (MODE) < 32 && INTEGRAL_MODE_P (MODE) \ 1396 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 1397 : MODE) 1398 1399 /* Return a class of registers that cannot change FROM mode to TO mode. */ 1400 1401 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1402 ix86_cannot_change_mode_class (FROM, TO, CLASS) 1403 1404 /* Stack layout; function entry, exit and calling. */ 1406 1407 /* Define this if pushing a word on the stack 1408 makes the stack pointer a smaller address. */ 1409 #define STACK_GROWS_DOWNWARD 1410 1411 /* Define this to nonzero if the nominal address of the stack frame 1412 is at the high-address end of the local variables; 1413 that is, each additional local variable allocated 1414 goes at a more negative offset in the frame. */ 1415 #define FRAME_GROWS_DOWNWARD 1 1416 1417 /* Offset within stack frame to start allocating local variables at. 1418 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1419 first local allocated. Otherwise, it is the offset to the BEGINNING 1420 of the first local allocated. */ 1421 #define STARTING_FRAME_OFFSET 0 1422 1423 /* If we generate an insn to push BYTES bytes, this says how many the stack 1424 pointer really advances by. On 386, we have pushw instruction that 1425 decrements by exactly 2 no matter what the position was, there is no pushb. 1426 1427 But as CIE data alignment factor on this arch is -4 for 32bit targets 1428 and -8 for 64bit targets, we need to make sure all stack pointer adjustments 1429 are in multiple of 4 for 32bit targets and 8 for 64bit targets. */ 1430 1431 #define PUSH_ROUNDING(BYTES) \ 1432 (((BYTES) + UNITS_PER_WORD - 1) & -UNITS_PER_WORD) 1433 1434 /* If defined, the maximum amount of space required for outgoing arguments 1435 will be computed and placed into the variable `crtl->outgoing_args_size'. 1436 No space will be pushed onto the stack for each call; instead, the 1437 function prologue should increase the stack frame size by this amount. 1438 1439 64-bit MS ABI seem to require 16 byte alignment everywhere except for 1440 function prologue and apilogue. This is not possible without 1441 ACCUMULATE_OUTGOING_ARGS. */ 1442 1443 #define ACCUMULATE_OUTGOING_ARGS \ 1444 (TARGET_ACCUMULATE_OUTGOING_ARGS || TARGET_64BIT_MS_ABI) 1445 1446 /* If defined, a C expression whose value is nonzero when we want to use PUSH 1447 instructions to pass outgoing arguments. */ 1448 1449 #define PUSH_ARGS (TARGET_PUSH_ARGS && !ACCUMULATE_OUTGOING_ARGS) 1450 1451 /* We want the stack and args grow in opposite directions, even if 1452 PUSH_ARGS is 0. */ 1453 #define PUSH_ARGS_REVERSED 1 1454 1455 /* Offset of first parameter from the argument pointer register value. */ 1456 #define FIRST_PARM_OFFSET(FNDECL) 0 1457 1458 /* Define this macro if functions should assume that stack space has been 1459 allocated for arguments even when their values are passed in registers. 1460 1461 The value of this macro is the size, in bytes, of the area reserved for 1462 arguments passed in registers for the function represented by FNDECL. 1463 1464 This space can be allocated by the caller, or be a part of the 1465 machine-dependent stack frame: `OUTGOING_REG_PARM_STACK_SPACE' says 1466 which. */ 1467 #define REG_PARM_STACK_SPACE(FNDECL) ix86_reg_parm_stack_space (FNDECL) 1468 1469 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) \ 1470 (TARGET_64BIT && ix86_function_type_abi (FNTYPE) == MS_ABI) 1471 1472 /* Define how to find the value returned by a library function 1473 assuming the value has mode MODE. */ 1474 1475 #define LIBCALL_VALUE(MODE) ix86_libcall_value (MODE) 1476 1477 /* Define the size of the result block used for communication between 1478 untyped_call and untyped_return. The block contains a DImode value 1479 followed by the block used by fnsave and frstor. */ 1480 1481 #define APPLY_RESULT_SIZE (8+108) 1482 1483 /* 1 if N is a possible register number for function argument passing. */ 1484 #define FUNCTION_ARG_REGNO_P(N) ix86_function_arg_regno_p (N) 1485 1486 /* Define a data type for recording info about an argument list 1487 during the scan of that argument list. This data type should 1488 hold all necessary information about the function itself 1489 and about the args processed so far, enough to enable macros 1490 such as FUNCTION_ARG to determine where the next arg should go. */ 1491 1492 typedef struct ix86_args { 1493 int words; /* # words passed so far */ 1494 int nregs; /* # registers available for passing */ 1495 int regno; /* next available register number */ 1496 int fastcall; /* fastcall or thiscall calling convention 1497 is used */ 1498 int sse_words; /* # sse words passed so far */ 1499 int sse_nregs; /* # sse registers available for passing */ 1500 int warn_avx; /* True when we want to warn about AVX ABI. */ 1501 int warn_sse; /* True when we want to warn about SSE ABI. */ 1502 int warn_mmx; /* True when we want to warn about MMX ABI. */ 1503 int sse_regno; /* next available sse register number */ 1504 int mmx_words; /* # mmx words passed so far */ 1505 int mmx_nregs; /* # mmx registers available for passing */ 1506 int mmx_regno; /* next available mmx register number */ 1507 int maybe_vaarg; /* true for calls to possibly vardic fncts. */ 1508 int caller; /* true if it is caller. */ 1509 int float_in_sse; /* Set to 1 or 2 for 32bit targets if 1510 SFmode/DFmode arguments should be passed 1511 in SSE registers. Otherwise 0. */ 1512 enum calling_abi call_abi; /* Set to SYSV_ABI for sysv abi. Otherwise 1513 MS_ABI for ms abi. */ 1514 } CUMULATIVE_ARGS; 1515 1516 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1517 for a call to a function whose data type is FNTYPE. 1518 For a library call, FNTYPE is 0. */ 1519 1520 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1521 init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL), \ 1522 (N_NAMED_ARGS) != -1) 1523 1524 /* Output assembler code to FILE to increment profiler label # LABELNO 1525 for profiling a function entry. */ 1526 1527 #define FUNCTION_PROFILER(FILE, LABELNO) x86_function_profiler (FILE, LABELNO) 1528 1529 #define MCOUNT_NAME "_mcount" 1530 1531 #define MCOUNT_NAME_BEFORE_PROLOGUE "__fentry__" 1532 1533 #define PROFILE_COUNT_REGISTER "edx" 1534 1535 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1536 the stack pointer does not matter. The value is tested only in 1537 functions that have frame pointers. 1538 No definition is equivalent to always zero. */ 1539 /* Note on the 386 it might be more efficient not to define this since 1540 we have to restore it ourselves from the frame pointer, in order to 1541 use pop */ 1542 1543 #define EXIT_IGNORE_STACK 1 1544 1545 /* Output assembler code for a block containing the constant parts 1546 of a trampoline, leaving space for the variable parts. */ 1547 1548 /* On the 386, the trampoline contains two instructions: 1549 mov #STATIC,ecx 1550 jmp FUNCTION 1551 The trampoline is generated entirely at runtime. The operand of JMP 1552 is the address of FUNCTION relative to the instruction following the 1553 JMP (which is 5 bytes long). */ 1554 1555 /* Length in units of the trampoline for entering a nested function. */ 1556 1557 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 24 : 10) 1558 1559 /* Definitions for register eliminations. 1561 1562 This is an array of structures. Each structure initializes one pair 1563 of eliminable registers. The "from" register number is given first, 1564 followed by "to". Eliminations of the same "from" register are listed 1565 in order of preference. 1566 1567 There are two registers that can always be eliminated on the i386. 1568 The frame pointer and the arg pointer can be replaced by either the 1569 hard frame pointer or to the stack pointer, depending upon the 1570 circumstances. The hard frame pointer is not used before reload and 1571 so it is not eligible for elimination. */ 1572 1573 #define ELIMINABLE_REGS \ 1574 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1575 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1576 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1577 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}} \ 1578 1579 /* Define the offset between two registers, one to be eliminated, and the other 1580 its replacement, at the start of a routine. */ 1581 1582 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1583 ((OFFSET) = ix86_initial_elimination_offset ((FROM), (TO))) 1584 1585 /* Addressing modes, and classification of registers for them. */ 1587 1588 /* Macros to check register numbers against specific register classes. */ 1589 1590 /* These assume that REGNO is a hard or pseudo reg number. 1591 They give nonzero only if REGNO is a hard reg of the suitable class 1592 or a pseudo reg currently allocated to a suitable hard reg. 1593 Since they use reg_renumber, they are safe only once reg_renumber 1594 has been allocated, which happens in reginfo.c during register 1595 allocation. */ 1596 1597 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1598 ((REGNO) < STACK_POINTER_REGNUM \ 1599 || REX_INT_REGNO_P (REGNO) \ 1600 || (unsigned) reg_renumber[(REGNO)] < STACK_POINTER_REGNUM \ 1601 || REX_INT_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1602 1603 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1604 (GENERAL_REGNO_P (REGNO) \ 1605 || (REGNO) == ARG_POINTER_REGNUM \ 1606 || (REGNO) == FRAME_POINTER_REGNUM \ 1607 || GENERAL_REGNO_P ((unsigned) reg_renumber[(REGNO)])) 1608 1609 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1610 and check its validity for a certain class. 1611 We have two alternate definitions for each of them. 1612 The usual definition accepts all pseudo regs; the other rejects 1613 them unless they have been allocated suitable hard regs. 1614 The symbol REG_OK_STRICT causes the latter definition to be used. 1615 1616 Most source files want to accept pseudo regs in the hope that 1617 they will get allocated to the class that the insn wants them to be in. 1618 Source files for reload pass need to be strict. 1619 After reload, it makes no difference, since pseudo regs have 1620 been eliminated by then. */ 1621 1622 1623 /* Non strict versions, pseudos are ok. */ 1624 #define REG_OK_FOR_INDEX_NONSTRICT_P(X) \ 1625 (REGNO (X) < STACK_POINTER_REGNUM \ 1626 || REX_INT_REGNO_P (REGNO (X)) \ 1627 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1628 1629 #define REG_OK_FOR_BASE_NONSTRICT_P(X) \ 1630 (GENERAL_REGNO_P (REGNO (X)) \ 1631 || REGNO (X) == ARG_POINTER_REGNUM \ 1632 || REGNO (X) == FRAME_POINTER_REGNUM \ 1633 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1634 1635 /* Strict versions, hard registers only */ 1636 #define REG_OK_FOR_INDEX_STRICT_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1637 #define REG_OK_FOR_BASE_STRICT_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1638 1639 #ifndef REG_OK_STRICT 1640 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_NONSTRICT_P (X) 1641 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_NONSTRICT_P (X) 1642 1643 #else 1644 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_INDEX_STRICT_P (X) 1645 #define REG_OK_FOR_BASE_P(X) REG_OK_FOR_BASE_STRICT_P (X) 1646 #endif 1647 1648 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1649 that is a valid memory address for an instruction. 1650 The MODE argument is the machine mode for the MEM expression 1651 that wants to use this address. 1652 1653 The other macros defined here are used only in TARGET_LEGITIMATE_ADDRESS_P, 1654 except for CONSTANT_ADDRESS_P which is usually machine-independent. 1655 1656 See legitimize_pic_address in i386.c for details as to what 1657 constitutes a legitimate address when -fpic is used. */ 1658 1659 #define MAX_REGS_PER_ADDRESS 2 1660 1661 #define CONSTANT_ADDRESS_P(X) constant_address_p (X) 1662 1663 /* Try a machine-dependent way of reloading an illegitimate address 1664 operand. If we find one, push the reload and jump to WIN. This 1665 macro is used in only one place: `find_reloads_address' in reload.c. */ 1666 1667 #define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, INDL, WIN) \ 1668 do { \ 1669 if (ix86_legitimize_reload_address ((X), (MODE), (OPNUM), \ 1670 (int)(TYPE), (INDL))) \ 1671 goto WIN; \ 1672 } while (0) 1673 1674 /* If defined, a C expression to determine the base term of address X. 1675 This macro is used in only one place: `find_base_term' in alias.c. 1676 1677 It is always safe for this macro to not be defined. It exists so 1678 that alias analysis can understand machine-dependent addresses. 1679 1680 The typical use of this macro is to handle addresses containing 1681 a label_ref or symbol_ref within an UNSPEC. */ 1682 1683 #define FIND_BASE_TERM(X) ix86_find_base_term (X) 1684 1685 /* Nonzero if the constant value X is a legitimate general operand 1686 when generating PIC code. It is given that flag_pic is on and 1687 that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1688 1689 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 1690 1691 #define SYMBOLIC_CONST(X) \ 1692 (GET_CODE (X) == SYMBOL_REF \ 1693 || GET_CODE (X) == LABEL_REF \ 1694 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 1695 1696 /* Max number of args passed in registers. If this is more than 3, we will 1698 have problems with ebx (register #4), since it is a caller save register and 1699 is also used as the pic register in ELF. So for now, don't allow more than 1700 3 registers to be passed in registers. */ 1701 1702 /* Abi specific values for REGPARM_MAX and SSE_REGPARM_MAX */ 1703 #define X86_64_REGPARM_MAX 6 1704 #define X86_64_MS_REGPARM_MAX 4 1705 1706 #define X86_32_REGPARM_MAX 3 1707 1708 #define REGPARM_MAX \ 1709 (TARGET_64BIT \ 1710 ? (TARGET_64BIT_MS_ABI \ 1711 ? X86_64_MS_REGPARM_MAX \ 1712 : X86_64_REGPARM_MAX) \ 1713 : X86_32_REGPARM_MAX) 1714 1715 #define X86_64_SSE_REGPARM_MAX 8 1716 #define X86_64_MS_SSE_REGPARM_MAX 4 1717 1718 #define X86_32_SSE_REGPARM_MAX (TARGET_SSE ? (TARGET_MACHO ? 4 : 3) : 0) 1719 1720 #define SSE_REGPARM_MAX \ 1721 (TARGET_64BIT \ 1722 ? (TARGET_64BIT_MS_ABI \ 1723 ? X86_64_MS_SSE_REGPARM_MAX \ 1724 : X86_64_SSE_REGPARM_MAX) \ 1725 : X86_32_SSE_REGPARM_MAX) 1726 1727 #define MMX_REGPARM_MAX (TARGET_64BIT ? 0 : (TARGET_MMX ? 3 : 0)) 1728 1729 /* Specify the machine mode that this machine uses 1731 for the index in the tablejump instruction. */ 1732 #define CASE_VECTOR_MODE \ 1733 (!TARGET_LP64 || (flag_pic && ix86_cmodel != CM_LARGE_PIC) ? SImode : DImode) 1734 1735 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1736 #define DEFAULT_SIGNED_CHAR 1 1737 1738 /* Max number of bytes we can move from memory to memory 1739 in one reasonably fast instruction. */ 1740 #define MOVE_MAX 16 1741 1742 /* MOVE_MAX_PIECES is the number of bytes at a time which we can 1743 move efficiently, as opposed to MOVE_MAX which is the maximum 1744 number of bytes we can move with a single instruction. */ 1745 #define MOVE_MAX_PIECES UNITS_PER_WORD 1746 1747 /* If a memory-to-memory move would take MOVE_RATIO or more simple 1748 move-instruction pairs, we will do a movmem or libcall instead. 1749 Increasing the value will always make code faster, but eventually 1750 incurs high cost in increased code size. 1751 1752 If you don't define this, a reasonable default is used. */ 1753 1754 #define MOVE_RATIO(speed) ((speed) ? ix86_cost->move_ratio : 3) 1755 1756 /* If a clear memory operation would take CLEAR_RATIO or more simple 1757 move-instruction sequences, we will do a clrmem or libcall instead. */ 1758 1759 #define CLEAR_RATIO(speed) ((speed) ? MIN (6, ix86_cost->move_ratio) : 2) 1760 1761 /* Define if shifts truncate the shift count which implies one can 1762 omit a sign-extension or zero-extension of a shift count. 1763 1764 On i386, shifts do truncate the count. But bit test instructions 1765 take the modulo of the bit offset operand. */ 1766 1767 /* #define SHIFT_COUNT_TRUNCATED */ 1768 1769 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1770 is done just by pretending it is already truncated. */ 1771 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1772 1773 /* A macro to update M and UNSIGNEDP when an object whose type is 1774 TYPE and which has the specified mode and signedness is to be 1775 stored in a register. This macro is only called when TYPE is a 1776 scalar type. 1777 1778 On i386 it is sometimes useful to promote HImode and QImode 1779 quantities to SImode. The choice depends on target type. */ 1780 1781 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 1782 do { \ 1783 if (((MODE) == HImode && TARGET_PROMOTE_HI_REGS) \ 1784 || ((MODE) == QImode && TARGET_PROMOTE_QI_REGS)) \ 1785 (MODE) = SImode; \ 1786 } while (0) 1787 1788 /* Specify the machine mode that pointers have. 1789 After generation of rtl, the compiler makes no further distinction 1790 between pointers and any other objects of this machine mode. */ 1791 #define Pmode (ix86_pmode == PMODE_DI ? DImode : SImode) 1792 1793 /* A C expression whose value is zero if pointers that need to be extended 1794 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and 1795 greater then zero if they are zero-extended and less then zero if the 1796 ptr_extend instruction should be used. */ 1797 1798 #define POINTERS_EXTEND_UNSIGNED 1 1799 1800 /* A function address in a call instruction 1801 is a byte address (for indexing purposes) 1802 so give the MEM rtx a byte's mode. */ 1803 #define FUNCTION_MODE QImode 1804 1805 1807 /* A C expression for the cost of a branch instruction. A value of 1 1808 is the default; other values are interpreted relative to that. */ 1809 1810 #define BRANCH_COST(speed_p, predictable_p) \ 1811 (!(speed_p) ? 2 : (predictable_p) ? 0 : ix86_branch_cost) 1812 1813 /* An integer expression for the size in bits of the largest integer machine 1814 mode that should actually be used. We allow pairs of registers. */ 1815 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 1816 1817 /* Define this macro as a C expression which is nonzero if accessing 1818 less than a word of memory (i.e. a `char' or a `short') is no 1819 faster than accessing a word of memory, i.e., if such access 1820 require more than one instruction or if there is no difference in 1821 cost between byte and (aligned) word loads. 1822 1823 When this macro is not defined, the compiler will access a field by 1824 finding the smallest containing object; when it is defined, a 1825 fullword load will be used if alignment permits. Unless bytes 1826 accesses are faster than word accesses, using word accesses is 1827 preferable since it may eliminate subsequent memory access if 1828 subsequent accesses occur to other fields in the same word of the 1829 structure, but to different bytes. */ 1830 1831 #define SLOW_BYTE_ACCESS 0 1832 1833 /* Nonzero if access to memory by shorts is slow and undesirable. */ 1834 #define SLOW_SHORT_ACCESS 0 1835 1836 /* Define this macro to be the value 1 if unaligned accesses have a 1837 cost many times greater than aligned accesses, for example if they 1838 are emulated in a trap handler. 1839 1840 When this macro is nonzero, the compiler will act as if 1841 `STRICT_ALIGNMENT' were nonzero when generating code for block 1842 moves. This can cause significantly more instructions to be 1843 produced. Therefore, do not set this macro nonzero if unaligned 1844 accesses only add a cycle or two to the time for a memory access. 1845 1846 If the value of this macro is always zero, it need not be defined. */ 1847 1848 /* #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 0 */ 1849 1850 /* Define this macro if it is as good or better to call a constant 1851 function address than to call an address kept in a register. 1852 1853 Desirable on the 386 because a CALL with a constant address is 1854 faster than one with a register address. */ 1855 1856 #define NO_FUNCTION_CSE 1857 1858 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 1860 return the mode to be used for the comparison. 1861 1862 For floating-point equality comparisons, CCFPEQmode should be used. 1863 VOIDmode should be used in all other cases. 1864 1865 For integer comparisons against zero, reduce to CCNOmode or CCZmode if 1866 possible, to allow for more combinations. */ 1867 1868 #define SELECT_CC_MODE(OP, X, Y) ix86_cc_mode ((OP), (X), (Y)) 1869 1870 /* Return nonzero if MODE implies a floating point inequality can be 1871 reversed. */ 1872 1873 #define REVERSIBLE_CC_MODE(MODE) 1 1874 1875 /* A C expression whose value is reversed condition code of the CODE for 1876 comparison done in CC_MODE mode. */ 1877 #define REVERSE_CONDITION(CODE, MODE) ix86_reverse_condition ((CODE), (MODE)) 1878 1879 1880 /* Control the assembler format that we output, to the extent 1882 this does not vary between assemblers. */ 1883 1884 /* How to refer to registers in assembler output. 1885 This sequence is indexed by compiler's hard-register-number (see above). */ 1886 1887 /* In order to refer to the first 8 regs as 32-bit regs, prefix an "e". 1888 For non floating point regs, the following are the HImode names. 1889 1890 For float regs, the stack top is sometimes referred to as "%st(0)" 1891 instead of just "%st". TARGET_PRINT_OPERAND handles this with the 1892 "y" code. */ 1893 1894 #define HI_REGISTER_NAMES \ 1895 {"ax","dx","cx","bx","si","di","bp","sp", \ 1896 "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)", \ 1897 "argp", "flags", "fpsr", "fpcr", "frame", \ 1898 "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7", \ 1899 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", \ 1900 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ 1901 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"} 1902 1903 #define REGISTER_NAMES HI_REGISTER_NAMES 1904 1905 /* Table of additional register names to use in user input. */ 1906 1907 #define ADDITIONAL_REGISTER_NAMES \ 1908 { { "eax", 0 }, { "edx", 1 }, { "ecx", 2 }, { "ebx", 3 }, \ 1909 { "esi", 4 }, { "edi", 5 }, { "ebp", 6 }, { "esp", 7 }, \ 1910 { "rax", 0 }, { "rdx", 1 }, { "rcx", 2 }, { "rbx", 3 }, \ 1911 { "rsi", 4 }, { "rdi", 5 }, { "rbp", 6 }, { "rsp", 7 }, \ 1912 { "al", 0 }, { "dl", 1 }, { "cl", 2 }, { "bl", 3 }, \ 1913 { "ah", 0 }, { "dh", 1 }, { "ch", 2 }, { "bh", 3 } } 1914 1915 /* Note we are omitting these since currently I don't know how 1916 to get gcc to use these, since they want the same but different 1917 number as al, and ax. 1918 */ 1919 1920 #define QI_REGISTER_NAMES \ 1921 {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} 1922 1923 /* These parallel the array above, and can be used to access bits 8:15 1924 of regs 0 through 3. */ 1925 1926 #define QI_HIGH_REGISTER_NAMES \ 1927 {"ah", "dh", "ch", "bh", } 1928 1929 /* How to renumber registers for dbx and gdb. */ 1930 1931 #define DBX_REGISTER_NUMBER(N) \ 1932 (TARGET_64BIT ? dbx64_register_map[(N)] : dbx_register_map[(N)]) 1933 1934 extern int const dbx_register_map[FIRST_PSEUDO_REGISTER]; 1935 extern int const dbx64_register_map[FIRST_PSEUDO_REGISTER]; 1936 extern int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER]; 1937 1938 /* Before the prologue, RA is at 0(%esp). */ 1939 #define INCOMING_RETURN_ADDR_RTX \ 1940 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 1941 1942 /* After the prologue, RA is at -4(AP) in the current frame. */ 1943 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1944 ((COUNT) == 0 \ 1945 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 1946 -UNITS_PER_WORD)) \ 1947 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) 1948 1949 /* PC is dbx register 8; let's use that column for RA. */ 1950 #define DWARF_FRAME_RETURN_COLUMN (TARGET_64BIT ? 16 : 8) 1951 1952 /* Before the prologue, the top of the frame is at 4(%esp). */ 1953 #define INCOMING_FRAME_SP_OFFSET UNITS_PER_WORD 1954 1955 /* Describe how we implement __builtin_eh_return. */ 1956 #define EH_RETURN_DATA_REGNO(N) ((N) <= DX_REG ? (N) : INVALID_REGNUM) 1957 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, CX_REG) 1958 1959 1960 /* Select a format to encode pointers in exception handling data. CODE 1961 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 1962 true if the symbol may be affected by dynamic relocations. 1963 1964 ??? All x86 object file formats are capable of representing this. 1965 After all, the relocation needed is the same as for the call insn. 1966 Whether or not a particular assembler allows us to enter such, I 1967 guess we'll have to see. */ 1968 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 1969 asm_preferred_eh_data_format ((CODE), (GLOBAL)) 1970 1971 /* This is how to output an insn to push a register on the stack. 1972 It need not be very fast code. */ 1973 1974 #define ASM_OUTPUT_REG_PUSH(FILE, REGNO) \ 1975 do { \ 1976 if (TARGET_64BIT) \ 1977 asm_fprintf ((FILE), "\tpush{q}\t%%r%s\n", \ 1978 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 1979 else \ 1980 asm_fprintf ((FILE), "\tpush{l}\t%%e%s\n", reg_names[(REGNO)]); \ 1981 } while (0) 1982 1983 /* This is how to output an insn to pop a register from the stack. 1984 It need not be very fast code. */ 1985 1986 #define ASM_OUTPUT_REG_POP(FILE, REGNO) \ 1987 do { \ 1988 if (TARGET_64BIT) \ 1989 asm_fprintf ((FILE), "\tpop{q}\t%%r%s\n", \ 1990 reg_names[(REGNO)] + (REX_INT_REGNO_P (REGNO) != 0)); \ 1991 else \ 1992 asm_fprintf ((FILE), "\tpop{l}\t%%e%s\n", reg_names[(REGNO)]); \ 1993 } while (0) 1994 1995 /* This is how to output an element of a case-vector that is absolute. */ 1996 1997 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1998 ix86_output_addr_vec_elt ((FILE), (VALUE)) 1999 2000 /* This is how to output an element of a case-vector that is relative. */ 2001 2002 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2003 ix86_output_addr_diff_elt ((FILE), (VALUE), (REL)) 2004 2005 /* When we see %v, we will print the 'v' prefix if TARGET_AVX is true. */ 2006 2007 #define ASM_OUTPUT_AVX_PREFIX(STREAM, PTR) \ 2008 { \ 2009 if ((PTR)[0] == '%' && (PTR)[1] == 'v') \ 2010 (PTR) += TARGET_AVX ? 1 : 2; \ 2011 } 2012 2013 /* A C statement or statements which output an assembler instruction 2014 opcode to the stdio stream STREAM. The macro-operand PTR is a 2015 variable of type `char *' which points to the opcode name in 2016 its "internal" form--the form that is written in the machine 2017 description. */ 2018 2019 #define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 2020 ASM_OUTPUT_AVX_PREFIX ((STREAM), (PTR)) 2021 2022 /* A C statement to output to the stdio stream FILE an assembler 2023 command to pad the location counter to a multiple of 1<<LOG 2024 bytes if it is within MAX_SKIP bytes. */ 2025 2026 #ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2027 #undef ASM_OUTPUT_MAX_SKIP_PAD 2028 #define ASM_OUTPUT_MAX_SKIP_PAD(FILE, LOG, MAX_SKIP) \ 2029 if ((LOG) != 0) \ 2030 { \ 2031 if ((MAX_SKIP) == 0) \ 2032 fprintf ((FILE), "\t.p2align %d\n", (LOG)); \ 2033 else \ 2034 fprintf ((FILE), "\t.p2align %d,,%d\n", (LOG), (MAX_SKIP)); \ 2035 } 2036 #endif 2037 2038 /* Write the extra assembler code needed to declare a function 2039 properly. */ 2040 2041 #undef ASM_OUTPUT_FUNCTION_LABEL 2042 #define ASM_OUTPUT_FUNCTION_LABEL(FILE, NAME, DECL) \ 2043 ix86_asm_output_function_label (FILE, NAME, DECL) 2044 2045 /* Under some conditions we need jump tables in the text section, 2046 because the assembler cannot handle label differences between 2047 sections. This is the case for x86_64 on Mach-O for example. */ 2048 2049 #define JUMP_TABLES_IN_TEXT_SECTION \ 2050 (flag_pic && ((TARGET_MACHO && TARGET_64BIT) \ 2051 || (!TARGET_64BIT && !HAVE_AS_GOTOFF_IN_DATA))) 2052 2053 /* Switch to init or fini section via SECTION_OP, emit a call to FUNC, 2054 and switch back. For x86 we do this only to save a few bytes that 2055 would otherwise be unused in the text section. */ 2056 #define CRT_MKSTR2(VAL) #VAL 2057 #define CRT_MKSTR(x) CRT_MKSTR2(x) 2058 2059 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 2060 asm (SECTION_OP "\n\t" \ 2061 "call " CRT_MKSTR(__USER_LABEL_PREFIX__) #FUNC "\n" \ 2062 TEXT_SECTION_ASM_OP); 2063 2064 /* Default threshold for putting data in large sections 2065 with x86-64 medium memory model */ 2066 #define DEFAULT_LARGE_SECTION_THRESHOLD 65536 2067 2068 /* Which processor to tune code generation for. These must be in sync 2070 with processor_target_table in i386.c. */ 2071 2072 enum processor_type 2073 { 2074 PROCESSOR_GENERIC32 = 0, 2075 PROCESSOR_GENERIC64, 2076 PROCESSOR_I386, /* 80386 */ 2077 PROCESSOR_I486, /* 80486DX, 80486SX, 80486DX[24] */ 2078 PROCESSOR_PENTIUM, 2079 PROCESSOR_PENTIUMPRO, 2080 PROCESSOR_PENTIUM4, 2081 PROCESSOR_NOCONA, 2082 PROCESSOR_CORE2, 2083 PROCESSOR_COREI7, 2084 PROCESSOR_HASWELL, 2085 PROCESSOR_ATOM, 2086 PROCESSOR_GEODE, 2087 PROCESSOR_K6, 2088 PROCESSOR_ATHLON, 2089 PROCESSOR_K8, 2090 PROCESSOR_AMDFAM10, 2091 PROCESSOR_BDVER1, 2092 PROCESSOR_BDVER2, 2093 PROCESSOR_BDVER3, 2094 PROCESSOR_BTVER1, 2095 PROCESSOR_BTVER2, 2096 PROCESSOR_max 2097 }; 2098 2099 extern enum processor_type ix86_tune; 2100 extern enum processor_type ix86_arch; 2101 2102 /* Size of the RED_ZONE area. */ 2103 #define RED_ZONE_SIZE 128 2104 /* Reserved area of the red zone for temporaries. */ 2105 #define RED_ZONE_RESERVE 8 2106 2107 extern unsigned int ix86_preferred_stack_boundary; 2108 extern unsigned int ix86_incoming_stack_boundary; 2109 2110 /* Smallest class containing REGNO. */ 2111 extern enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER]; 2112 2113 enum ix86_fpcmp_strategy { 2114 IX86_FPCMP_SAHF, 2115 IX86_FPCMP_COMI, 2116 IX86_FPCMP_ARITH 2117 }; 2118 2119 /* To properly truncate FP values into integers, we need to set i387 control 2121 word. We can't emit proper mode switching code before reload, as spills 2122 generated by reload may truncate values incorrectly, but we still can avoid 2123 redundant computation of new control word by the mode switching pass. 2124 The fldcw instructions are still emitted redundantly, but this is probably 2125 not going to be noticeable problem, as most CPUs do have fast path for 2126 the sequence. 2127 2128 The machinery is to emit simple truncation instructions and split them 2129 before reload to instructions having USEs of two memory locations that 2130 are filled by this code to old and new control word. 2131 2132 Post-reload pass may be later used to eliminate the redundant fildcw if 2133 needed. */ 2134 2135 enum ix86_entity 2136 { 2137 AVX_U128 = 0, 2138 I387_TRUNC, 2139 I387_FLOOR, 2140 I387_CEIL, 2141 I387_MASK_PM, 2142 MAX_386_ENTITIES 2143 }; 2144 2145 enum ix86_stack_slot 2146 { 2147 SLOT_TEMP = 0, 2148 SLOT_CW_STORED, 2149 SLOT_CW_TRUNC, 2150 SLOT_CW_FLOOR, 2151 SLOT_CW_CEIL, 2152 SLOT_CW_MASK_PM, 2153 MAX_386_STACK_LOCALS 2154 }; 2155 2156 enum avx_u128_state 2157 { 2158 AVX_U128_CLEAN, 2159 AVX_U128_DIRTY, 2160 AVX_U128_ANY 2161 }; 2162 2163 /* Define this macro if the port needs extra instructions inserted 2164 for mode switching in an optimizing compilation. */ 2165 2166 #define OPTIMIZE_MODE_SWITCHING(ENTITY) \ 2167 ix86_optimize_mode_switching[(ENTITY)] 2168 2169 /* If you define `OPTIMIZE_MODE_SWITCHING', you have to define this as 2170 initializer for an array of integers. Each initializer element N 2171 refers to an entity that needs mode switching, and specifies the 2172 number of different modes that might need to be set for this 2173 entity. The position of the initializer in the initializer - 2174 starting counting at zero - determines the integer that is used to 2175 refer to the mode-switched entity in question. */ 2176 2177 #define NUM_MODES_FOR_MODE_SWITCHING \ 2178 { AVX_U128_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY, I387_CW_ANY } 2179 2180 /* ENTITY is an integer specifying a mode-switched entity. If 2181 `OPTIMIZE_MODE_SWITCHING' is defined, you must define this macro to 2182 return an integer value not larger than the corresponding element 2183 in `NUM_MODES_FOR_MODE_SWITCHING', to denote the mode that ENTITY 2184 must be switched into prior to the execution of INSN. */ 2185 2186 #define MODE_NEEDED(ENTITY, I) ix86_mode_needed ((ENTITY), (I)) 2187 2188 /* If this macro is defined, it is evaluated for every INSN during 2189 mode switching. It determines the mode that an insn results in (if 2190 different from the incoming mode). */ 2191 2192 #define MODE_AFTER(ENTITY, MODE, I) ix86_mode_after ((ENTITY), (MODE), (I)) 2193 2194 /* If this macro is defined, it is evaluated for every ENTITY that 2195 needs mode switching. It should evaluate to an integer, which is 2196 a mode that ENTITY is assumed to be switched to at function entry. */ 2197 2198 #define MODE_ENTRY(ENTITY) ix86_mode_entry (ENTITY) 2199 2200 /* If this macro is defined, it is evaluated for every ENTITY that 2201 needs mode switching. It should evaluate to an integer, which is 2202 a mode that ENTITY is assumed to be switched to at function exit. */ 2203 2204 #define MODE_EXIT(ENTITY) ix86_mode_exit (ENTITY) 2205 2206 /* This macro specifies the order in which modes for ENTITY are 2207 processed. 0 is the highest priority. */ 2208 2209 #define MODE_PRIORITY_TO_MODE(ENTITY, N) (N) 2210 2211 /* Generate one or more insns to set ENTITY to MODE. HARD_REG_LIVE 2212 is the set of hard registers live at the point where the insn(s) 2213 are to be inserted. */ 2214 2215 #define EMIT_MODE_SET(ENTITY, MODE, HARD_REGS_LIVE) \ 2216 ix86_emit_mode_set ((ENTITY), (MODE), (HARD_REGS_LIVE)) 2217 2218 /* Avoid renaming of stack registers, as doing so in combination with 2220 scheduling just increases amount of live registers at time and in 2221 the turn amount of fxch instructions needed. 2222 2223 ??? Maybe Pentium chips benefits from renaming, someone can try.... */ 2224 2225 #define HARD_REGNO_RENAME_OK(SRC, TARGET) !STACK_REGNO_P (SRC) 2226 2227 2228 #define FASTCALL_PREFIX '@' 2230 2231 /* Machine specific frame tracking during prologue/epilogue generation. */ 2233 2234 #ifndef USED_FOR_TARGET 2235 struct GTY(()) machine_frame_state 2236 { 2237 /* This pair tracks the currently active CFA as reg+offset. When reg 2238 is drap_reg, we don't bother trying to record here the real CFA when 2239 it might really be a DW_CFA_def_cfa_expression. */ 2240 rtx cfa_reg; 2241 HOST_WIDE_INT cfa_offset; 2242 2243 /* The current offset (canonically from the CFA) of ESP and EBP. 2244 When stack frame re-alignment is active, these may not be relative 2245 to the CFA. However, in all cases they are relative to the offsets 2246 of the saved registers stored in ix86_frame. */ 2247 HOST_WIDE_INT sp_offset; 2248 HOST_WIDE_INT fp_offset; 2249 2250 /* The size of the red-zone that may be assumed for the purposes of 2251 eliding register restore notes in the epilogue. This may be zero 2252 if no red-zone is in effect, or may be reduced from the real 2253 red-zone value by a maximum runtime stack re-alignment value. */ 2254 int red_zone_offset; 2255 2256 /* Indicate whether each of ESP, EBP or DRAP currently holds a valid 2257 value within the frame. If false then the offset above should be 2258 ignored. Note that DRAP, if valid, *always* points to the CFA and 2259 thus has an offset of zero. */ 2260 BOOL_BITFIELD sp_valid : 1; 2261 BOOL_BITFIELD fp_valid : 1; 2262 BOOL_BITFIELD drap_valid : 1; 2263 2264 /* Indicate whether the local stack frame has been re-aligned. When 2265 set, the SP/FP offsets above are relative to the aligned frame 2266 and not the CFA. */ 2267 BOOL_BITFIELD realigned : 1; 2268 }; 2269 2270 /* Private to winnt.c. */ 2271 struct seh_frame_state; 2272 2273 struct GTY(()) machine_function { 2274 struct stack_local_entry *stack_locals; 2275 const char *some_ld_name; 2276 int varargs_gpr_size; 2277 int varargs_fpr_size; 2278 int optimize_mode_switching[MAX_386_ENTITIES]; 2279 2280 /* Number of saved registers USE_FAST_PROLOGUE_EPILOGUE 2281 has been computed for. */ 2282 int use_fast_prologue_epilogue_nregs; 2283 2284 /* For -fsplit-stack support: A stack local which holds a pointer to 2285 the stack arguments for a function with a variable number of 2286 arguments. This is set at the start of the function and is used 2287 to initialize the overflow_arg_area field of the va_list 2288 structure. */ 2289 rtx split_stack_varargs_pointer; 2290 2291 /* This value is used for amd64 targets and specifies the current abi 2292 to be used. MS_ABI means ms abi. Otherwise SYSV_ABI means sysv abi. */ 2293 ENUM_BITFIELD(calling_abi) call_abi : 8; 2294 2295 /* Nonzero if the function accesses a previous frame. */ 2296 BOOL_BITFIELD accesses_prev_frame : 1; 2297 2298 /* Nonzero if the function requires a CLD in the prologue. */ 2299 BOOL_BITFIELD needs_cld : 1; 2300 2301 /* Set by ix86_compute_frame_layout and used by prologue/epilogue 2302 expander to determine the style used. */ 2303 BOOL_BITFIELD use_fast_prologue_epilogue : 1; 2304 2305 /* If true, the current function needs the default PIC register, not 2306 an alternate register (on x86) and must not use the red zone (on 2307 x86_64), even if it's a leaf function. We don't want the 2308 function to be regarded as non-leaf because TLS calls need not 2309 affect register allocation. This flag is set when a TLS call 2310 instruction is expanded within a function, and never reset, even 2311 if all such instructions are optimized away. Use the 2312 ix86_current_function_calls_tls_descriptor macro for a better 2313 approximation. */ 2314 BOOL_BITFIELD tls_descriptor_call_expanded_p : 1; 2315 2316 /* If true, the current function has a STATIC_CHAIN is placed on the 2317 stack below the return address. */ 2318 BOOL_BITFIELD static_chain_on_stack : 1; 2319 2320 /* During prologue/epilogue generation, the current frame state. 2321 Otherwise, the frame state at the end of the prologue. */ 2322 struct machine_frame_state fs; 2323 2324 /* During SEH output, this is non-null. */ 2325 struct seh_frame_state * GTY((skip(""))) seh; 2326 }; 2327 #endif 2328 2329 #define ix86_stack_locals (cfun->machine->stack_locals) 2330 #define ix86_varargs_gpr_size (cfun->machine->varargs_gpr_size) 2331 #define ix86_varargs_fpr_size (cfun->machine->varargs_fpr_size) 2332 #define ix86_optimize_mode_switching (cfun->machine->optimize_mode_switching) 2333 #define ix86_current_function_needs_cld (cfun->machine->needs_cld) 2334 #define ix86_tls_descriptor_calls_expanded_in_cfun \ 2335 (cfun->machine->tls_descriptor_call_expanded_p) 2336 /* Since tls_descriptor_call_expanded is not cleared, even if all TLS 2337 calls are optimized away, we try to detect cases in which it was 2338 optimized away. Since such instructions (use (reg REG_SP)), we can 2339 verify whether there's any such instruction live by testing that 2340 REG_SP is live. */ 2341 #define ix86_current_function_calls_tls_descriptor \ 2342 (ix86_tls_descriptor_calls_expanded_in_cfun && df_regs_ever_live_p (SP_REG)) 2343 #define ix86_static_chain_on_stack (cfun->machine->static_chain_on_stack) 2344 2345 /* Control behavior of x86_file_start. */ 2346 #define X86_FILE_START_VERSION_DIRECTIVE false 2347 #define X86_FILE_START_FLTUSED false 2348 2349 /* Flag to mark data that is in the large address area. */ 2350 #define SYMBOL_FLAG_FAR_ADDR (SYMBOL_FLAG_MACH_DEP << 0) 2351 #define SYMBOL_REF_FAR_ADDR_P(X) \ 2352 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_FAR_ADDR) != 0) 2353 2354 /* Flags to mark dllimport/dllexport. Used by PE ports, but handy to 2355 have defined always, to avoid ifdefing. */ 2356 #define SYMBOL_FLAG_DLLIMPORT (SYMBOL_FLAG_MACH_DEP << 1) 2357 #define SYMBOL_REF_DLLIMPORT_P(X) \ 2358 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLIMPORT) != 0) 2359 2360 #define SYMBOL_FLAG_DLLEXPORT (SYMBOL_FLAG_MACH_DEP << 2) 2361 #define SYMBOL_REF_DLLEXPORT_P(X) \ 2362 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_DLLEXPORT) != 0) 2363 2364 extern void debug_ready_dispatch (void); 2365 extern void debug_dispatch_window (int); 2366 2367 /* The value at zero is only defined for the BMI instructions 2368 LZCNT and TZCNT, not the BSR/BSF insns in the original isa. */ 2369 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2370 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_BMI) 2371 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 2372 ((VALUE) = GET_MODE_BITSIZE (MODE), TARGET_LZCNT) 2373 2374 2375 /* Flags returned by ix86_get_callcvt (). */ 2376 #define IX86_CALLCVT_CDECL 0x1 2377 #define IX86_CALLCVT_STDCALL 0x2 2378 #define IX86_CALLCVT_FASTCALL 0x4 2379 #define IX86_CALLCVT_THISCALL 0x8 2380 #define IX86_CALLCVT_REGPARM 0x10 2381 #define IX86_CALLCVT_SSEREGPARM 0x20 2382 2383 #define IX86_BASE_CALLCVT(FLAGS) \ 2384 ((FLAGS) & (IX86_CALLCVT_CDECL | IX86_CALLCVT_STDCALL \ 2385 | IX86_CALLCVT_FASTCALL | IX86_CALLCVT_THISCALL)) 2386 2387 #define RECIP_MASK_NONE 0x00 2388 #define RECIP_MASK_DIV 0x01 2389 #define RECIP_MASK_SQRT 0x02 2390 #define RECIP_MASK_VEC_DIV 0x04 2391 #define RECIP_MASK_VEC_SQRT 0x08 2392 #define RECIP_MASK_ALL (RECIP_MASK_DIV | RECIP_MASK_SQRT \ 2393 | RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2394 #define RECIP_MASK_DEFAULT (RECIP_MASK_VEC_DIV | RECIP_MASK_VEC_SQRT) 2395 2396 #define TARGET_RECIP_DIV ((recip_mask & RECIP_MASK_DIV) != 0) 2397 #define TARGET_RECIP_SQRT ((recip_mask & RECIP_MASK_SQRT) != 0) 2398 #define TARGET_RECIP_VEC_DIV ((recip_mask & RECIP_MASK_VEC_DIV) != 0) 2399 #define TARGET_RECIP_VEC_SQRT ((recip_mask & RECIP_MASK_VEC_SQRT) != 0) 2400 2401 #define IX86_HLE_ACQUIRE (1 << 16) 2402 #define IX86_HLE_RELEASE (1 << 17) 2403 2404 /* 2405 Local variables: 2406 version-control: t 2407 End: 2408 */ 2409
Indexes created Wed Jul 22 00:25:13 UTC 2026