1 1.12 mrg /* Copyright (C) 2003-2022 Free Software Foundation, Inc. 2 1.1 mrg 3 1.1 mrg This file is part of GCC. 4 1.1 mrg 5 1.1 mrg GCC is free software; you can redistribute it and/or modify 6 1.1 mrg it under the terms of the GNU General Public License as published by 7 1.1 mrg the Free Software Foundation; either version 3, or (at your option) 8 1.1 mrg any later version. 9 1.1 mrg 10 1.1 mrg GCC is distributed in the hope that it will be useful, 11 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of 12 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 1.1 mrg GNU General Public License for more details. 14 1.1 mrg 15 1.1 mrg Under Section 7 of GPL version 3, you are granted additional 16 1.1 mrg permissions described in the GCC Runtime Library Exception, version 17 1.1 mrg 3.1, as published by the Free Software Foundation. 18 1.1 mrg 19 1.1 mrg You should have received a copy of the GNU General Public License and 20 1.1 mrg a copy of the GCC Runtime Library Exception along with this program; 21 1.1 mrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 22 1.1 mrg <http://www.gnu.org/licenses/>. */ 23 1.1 mrg 24 1.1 mrg /* Implemented from the specification included in the Intel C++ Compiler 25 1.1 mrg User Guide and Reference, version 9.0. */ 26 1.1 mrg 27 1.1 mrg #ifndef _PMMINTRIN_H_INCLUDED 28 1.1 mrg #define _PMMINTRIN_H_INCLUDED 29 1.1 mrg 30 1.1 mrg /* We need definitions from the SSE2 and SSE header files*/ 31 1.1 mrg #include <emmintrin.h> 32 1.12 mrg #include <mwaitintrin.h> 33 1.1 mrg 34 1.5 mrg #ifndef __SSE3__ 35 1.5 mrg #pragma GCC push_options 36 1.5 mrg #pragma GCC target("sse3") 37 1.5 mrg #define __DISABLE_SSE3__ 38 1.5 mrg #endif /* __SSE3__ */ 39 1.5 mrg 40 1.1 mrg /* Additional bits in the MXCSR. */ 41 1.1 mrg #define _MM_DENORMALS_ZERO_MASK 0x0040 42 1.1 mrg #define _MM_DENORMALS_ZERO_ON 0x0040 43 1.1 mrg #define _MM_DENORMALS_ZERO_OFF 0x0000 44 1.1 mrg 45 1.1 mrg #define _MM_SET_DENORMALS_ZERO_MODE(mode) \ 46 1.1 mrg _mm_setcsr ((_mm_getcsr () & ~_MM_DENORMALS_ZERO_MASK) | (mode)) 47 1.1 mrg #define _MM_GET_DENORMALS_ZERO_MODE() \ 48 1.1 mrg (_mm_getcsr() & _MM_DENORMALS_ZERO_MASK) 49 1.1 mrg 50 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 51 1.1 mrg _mm_addsub_ps (__m128 __X, __m128 __Y) 52 1.1 mrg { 53 1.1 mrg return (__m128) __builtin_ia32_addsubps ((__v4sf)__X, (__v4sf)__Y); 54 1.1 mrg } 55 1.1 mrg 56 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 57 1.1 mrg _mm_hadd_ps (__m128 __X, __m128 __Y) 58 1.1 mrg { 59 1.1 mrg return (__m128) __builtin_ia32_haddps ((__v4sf)__X, (__v4sf)__Y); 60 1.1 mrg } 61 1.1 mrg 62 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 63 1.1 mrg _mm_hsub_ps (__m128 __X, __m128 __Y) 64 1.1 mrg { 65 1.1 mrg return (__m128) __builtin_ia32_hsubps ((__v4sf)__X, (__v4sf)__Y); 66 1.1 mrg } 67 1.1 mrg 68 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 69 1.1 mrg _mm_movehdup_ps (__m128 __X) 70 1.1 mrg { 71 1.1 mrg return (__m128) __builtin_ia32_movshdup ((__v4sf)__X); 72 1.1 mrg } 73 1.1 mrg 74 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 75 1.1 mrg _mm_moveldup_ps (__m128 __X) 76 1.1 mrg { 77 1.1 mrg return (__m128) __builtin_ia32_movsldup ((__v4sf)__X); 78 1.1 mrg } 79 1.1 mrg 80 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 81 1.1 mrg _mm_addsub_pd (__m128d __X, __m128d __Y) 82 1.1 mrg { 83 1.1 mrg return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y); 84 1.1 mrg } 85 1.1 mrg 86 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 87 1.1 mrg _mm_hadd_pd (__m128d __X, __m128d __Y) 88 1.1 mrg { 89 1.1 mrg return (__m128d) __builtin_ia32_haddpd ((__v2df)__X, (__v2df)__Y); 90 1.1 mrg } 91 1.1 mrg 92 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 93 1.1 mrg _mm_hsub_pd (__m128d __X, __m128d __Y) 94 1.1 mrg { 95 1.1 mrg return (__m128d) __builtin_ia32_hsubpd ((__v2df)__X, (__v2df)__Y); 96 1.1 mrg } 97 1.1 mrg 98 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 99 1.1 mrg _mm_loaddup_pd (double const *__P) 100 1.1 mrg { 101 1.1 mrg return _mm_load1_pd (__P); 102 1.1 mrg } 103 1.1 mrg 104 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 105 1.1 mrg _mm_movedup_pd (__m128d __X) 106 1.1 mrg { 107 1.1 mrg return _mm_shuffle_pd (__X, __X, _MM_SHUFFLE2 (0,0)); 108 1.1 mrg } 109 1.1 mrg 110 1.1 mrg extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 111 1.1 mrg _mm_lddqu_si128 (__m128i const *__P) 112 1.1 mrg { 113 1.1 mrg return (__m128i) __builtin_ia32_lddqu ((char const *)__P); 114 1.1 mrg } 115 1.1 mrg 116 1.5 mrg #ifdef __DISABLE_SSE3__ 117 1.5 mrg #undef __DISABLE_SSE3__ 118 1.5 mrg #pragma GCC pop_options 119 1.5 mrg #endif /* __DISABLE_SSE3__ */ 120 1.1 mrg 121 1.1 mrg #endif /* _PMMINTRIN_H_INCLUDED */ 122
Indexes created Tue Apr 14 00:22:26 UTC 2026