pmmintrin.h revision 1.1
1 1.1 mrg /* Copyright (C) 2003, 2004, 2005, 2006, 2007, 2008, 2009 2 1.1 mrg Free Software Foundation, Inc. 3 1.1 mrg 4 1.1 mrg This file is part of GCC. 5 1.1 mrg 6 1.1 mrg GCC is free software; you can redistribute it and/or modify 7 1.1 mrg it under the terms of the GNU General Public License as published by 8 1.1 mrg the Free Software Foundation; either version 3, or (at your option) 9 1.1 mrg any later version. 10 1.1 mrg 11 1.1 mrg GCC is distributed in the hope that it will be useful, 12 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of 13 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 1.1 mrg GNU General Public License for more details. 15 1.1 mrg 16 1.1 mrg Under Section 7 of GPL version 3, you are granted additional 17 1.1 mrg permissions described in the GCC Runtime Library Exception, version 18 1.1 mrg 3.1, as published by the Free Software Foundation. 19 1.1 mrg 20 1.1 mrg You should have received a copy of the GNU General Public License and 21 1.1 mrg a copy of the GCC Runtime Library Exception along with this program; 22 1.1 mrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 23 1.1 mrg <http://www.gnu.org/licenses/>. */ 24 1.1 mrg 25 1.1 mrg /* Implemented from the specification included in the Intel C++ Compiler 26 1.1 mrg User Guide and Reference, version 9.0. */ 27 1.1 mrg 28 1.1 mrg #ifndef _PMMINTRIN_H_INCLUDED 29 1.1 mrg #define _PMMINTRIN_H_INCLUDED 30 1.1 mrg 31 1.1 mrg #ifndef __SSE3__ 32 1.1 mrg # error "SSE3 instruction set not enabled" 33 1.1 mrg #else 34 1.1 mrg 35 1.1 mrg /* We need definitions from the SSE2 and SSE header files*/ 36 1.1 mrg #include <emmintrin.h> 37 1.1 mrg 38 1.1 mrg /* Additional bits in the MXCSR. */ 39 1.1 mrg #define _MM_DENORMALS_ZERO_MASK 0x0040 40 1.1 mrg #define _MM_DENORMALS_ZERO_ON 0x0040 41 1.1 mrg #define _MM_DENORMALS_ZERO_OFF 0x0000 42 1.1 mrg 43 1.1 mrg #define _MM_SET_DENORMALS_ZERO_MODE(mode) \ 44 1.1 mrg _mm_setcsr ((_mm_getcsr () & ~_MM_DENORMALS_ZERO_MASK) | (mode)) 45 1.1 mrg #define _MM_GET_DENORMALS_ZERO_MODE() \ 46 1.1 mrg (_mm_getcsr() & _MM_DENORMALS_ZERO_MASK) 47 1.1 mrg 48 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 49 1.1 mrg _mm_addsub_ps (__m128 __X, __m128 __Y) 50 1.1 mrg { 51 1.1 mrg return (__m128) __builtin_ia32_addsubps ((__v4sf)__X, (__v4sf)__Y); 52 1.1 mrg } 53 1.1 mrg 54 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 55 1.1 mrg _mm_hadd_ps (__m128 __X, __m128 __Y) 56 1.1 mrg { 57 1.1 mrg return (__m128) __builtin_ia32_haddps ((__v4sf)__X, (__v4sf)__Y); 58 1.1 mrg } 59 1.1 mrg 60 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 61 1.1 mrg _mm_hsub_ps (__m128 __X, __m128 __Y) 62 1.1 mrg { 63 1.1 mrg return (__m128) __builtin_ia32_hsubps ((__v4sf)__X, (__v4sf)__Y); 64 1.1 mrg } 65 1.1 mrg 66 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 67 1.1 mrg _mm_movehdup_ps (__m128 __X) 68 1.1 mrg { 69 1.1 mrg return (__m128) __builtin_ia32_movshdup ((__v4sf)__X); 70 1.1 mrg } 71 1.1 mrg 72 1.1 mrg extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 73 1.1 mrg _mm_moveldup_ps (__m128 __X) 74 1.1 mrg { 75 1.1 mrg return (__m128) __builtin_ia32_movsldup ((__v4sf)__X); 76 1.1 mrg } 77 1.1 mrg 78 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 79 1.1 mrg _mm_addsub_pd (__m128d __X, __m128d __Y) 80 1.1 mrg { 81 1.1 mrg return (__m128d) __builtin_ia32_addsubpd ((__v2df)__X, (__v2df)__Y); 82 1.1 mrg } 83 1.1 mrg 84 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 85 1.1 mrg _mm_hadd_pd (__m128d __X, __m128d __Y) 86 1.1 mrg { 87 1.1 mrg return (__m128d) __builtin_ia32_haddpd ((__v2df)__X, (__v2df)__Y); 88 1.1 mrg } 89 1.1 mrg 90 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 91 1.1 mrg _mm_hsub_pd (__m128d __X, __m128d __Y) 92 1.1 mrg { 93 1.1 mrg return (__m128d) __builtin_ia32_hsubpd ((__v2df)__X, (__v2df)__Y); 94 1.1 mrg } 95 1.1 mrg 96 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 97 1.1 mrg _mm_loaddup_pd (double const *__P) 98 1.1 mrg { 99 1.1 mrg return _mm_load1_pd (__P); 100 1.1 mrg } 101 1.1 mrg 102 1.1 mrg extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 103 1.1 mrg _mm_movedup_pd (__m128d __X) 104 1.1 mrg { 105 1.1 mrg return _mm_shuffle_pd (__X, __X, _MM_SHUFFLE2 (0,0)); 106 1.1 mrg } 107 1.1 mrg 108 1.1 mrg extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 109 1.1 mrg _mm_lddqu_si128 (__m128i const *__P) 110 1.1 mrg { 111 1.1 mrg return (__m128i) __builtin_ia32_lddqu ((char const *)__P); 112 1.1 mrg } 113 1.1 mrg 114 1.1 mrg extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 115 1.1 mrg _mm_monitor (void const * __P, unsigned int __E, unsigned int __H) 116 1.1 mrg { 117 1.1 mrg __builtin_ia32_monitor (__P, __E, __H); 118 1.1 mrg } 119 1.1 mrg 120 1.1 mrg extern __inline void __attribute__((__gnu_inline__, __always_inline__, __artificial__)) 121 1.1 mrg _mm_mwait (unsigned int __E, unsigned int __H) 122 1.1 mrg { 123 1.1 mrg __builtin_ia32_mwait (__E, __H); 124 1.1 mrg } 125 1.1 mrg 126 1.1 mrg #endif /* __SSE3__ */ 127 1.1 mrg 128 1.1 mrg #endif /* _PMMINTRIN_H_INCLUDED */ 129
Indexes created Tue Apr 14 00:22:26 UTC 2026