1 1.1 mrg ;; Generic DFA-based pipeline description for LoongArch targets 2 1.1 mrg ;; Copyright (C) 2021-2022 Free Software Foundation, Inc. 3 1.1 mrg ;; Contributed by Loongson Ltd. 4 1.1 mrg ;; Based on MIPS target for GNU compiler. 5 1.1 mrg 6 1.1 mrg ;; This file is part of GCC. 7 1.1 mrg 8 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify it 9 1.1 mrg ;; under the terms of the GNU General Public License as published 10 1.1 mrg ;; by the Free Software Foundation; either version 3, or (at your 11 1.1 mrg ;; option) any later version. 12 1.1 mrg 13 1.1 mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT 14 1.1 mrg ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15 1.1 mrg ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16 1.1 mrg ;; License for more details. 17 1.1 mrg 18 1.1 mrg ;; You should have received a copy of the GNU General Public License 19 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 20 1.1 mrg ;; <http://www.gnu.org/licenses/>. 21 1.1 mrg 22 1.1 mrg (define_automaton "alu,imuldiv") 23 1.1 mrg 24 1.1 mrg (define_cpu_unit "alu" "alu") 25 1.1 mrg (define_cpu_unit "imuldiv" "imuldiv") 26 1.1 mrg 27 1.1 mrg ;; Ghost instructions produce no real code. 28 1.1 mrg ;; They exist purely to express an effect on dataflow. 29 1.1 mrg (define_insn_reservation "ghost" 0 30 1.1 mrg (eq_attr "type" "ghost") 31 1.1 mrg "nothing") 32 1.1 mrg 33 1.1 mrg (define_insn_reservation "generic_alu" 1 34 1.1 mrg (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith, 35 1.1 mrg shift,slt,clz,trap,multi,nop,logical,signext,move") 36 1.1 mrg "alu") 37 1.1 mrg 38 1.1 mrg (define_insn_reservation "generic_load" 3 39 1.1 mrg (eq_attr "type" "load,fpload,fpidxload") 40 1.1 mrg "alu") 41 1.1 mrg 42 1.1 mrg (define_insn_reservation "generic_store" 1 43 1.1 mrg (eq_attr "type" "store,fpstore,fpidxstore") 44 1.1 mrg "alu") 45 1.1 mrg 46 1.1 mrg (define_insn_reservation "generic_xfer" 2 47 1.1 mrg (eq_attr "type" "mftg,mgtf") 48 1.1 mrg "alu") 49 1.1 mrg 50 1.1 mrg (define_insn_reservation "generic_branch" 1 51 1.1 mrg (eq_attr "type" "branch,jump,call") 52 1.1 mrg "alu") 53 1.1 mrg 54 1.1 mrg (define_insn_reservation "generic_imul" 17 55 1.1 mrg (eq_attr "type" "imul") 56 1.1 mrg "imuldiv*17") 57 1.1 mrg 58 1.1 mrg (define_insn_reservation "generic_fcvt" 1 59 1.1 mrg (eq_attr "type" "fcvt") 60 1.1 mrg "alu") 61 1.1 mrg 62 1.1 mrg (define_insn_reservation "generic_fmove" 2 63 1.1 mrg (eq_attr "type" "fabs,fneg,fmove") 64 1.1 mrg "alu") 65 1.1 mrg 66 1.1 mrg (define_insn_reservation "generic_fcmp" 3 67 1.1 mrg (eq_attr "type" "fcmp") 68 1.1 mrg "alu") 69 1.1 mrg 70 1.1 mrg (define_insn_reservation "generic_fadd" 4 71 1.1 mrg (eq_attr "type" "fadd") 72 1.1 mrg "alu") 73 1.1 mrg 74 1.1 mrg (define_insn_reservation "generic_fmul_single" 7 75 1.1 mrg (and (eq_attr "type" "fmul,fmadd") 76 1.1 mrg (eq_attr "mode" "SF")) 77 1.1 mrg "alu") 78 1.1 mrg 79 1.1 mrg (define_insn_reservation "generic_fmul_double" 8 80 1.1 mrg (and (eq_attr "type" "fmul,fmadd") 81 1.1 mrg (eq_attr "mode" "DF")) 82 1.1 mrg "alu") 83 1.1 mrg 84 1.1 mrg (define_insn_reservation "generic_fdiv_single" 23 85 1.1 mrg (and (eq_attr "type" "fdiv,frdiv") 86 1.1 mrg (eq_attr "mode" "SF")) 87 1.1 mrg "alu") 88 1.1 mrg 89 1.1 mrg (define_insn_reservation "generic_fdiv_double" 36 90 1.1 mrg (and (eq_attr "type" "fdiv,frdiv") 91 1.1 mrg (eq_attr "mode" "DF")) 92 1.1 mrg "alu") 93 1.1 mrg 94 1.1 mrg (define_insn_reservation "generic_fsqrt_single" 54 95 1.1 mrg (and (eq_attr "type" "fsqrt,frsqrt") 96 1.1 mrg (eq_attr "mode" "SF")) 97 1.1 mrg "alu") 98 1.1 mrg 99 1.1 mrg (define_insn_reservation "generic_fsqrt_double" 112 100 1.1 mrg (and (eq_attr "type" "fsqrt,frsqrt") 101 1.1 mrg (eq_attr "mode" "DF")) 102 1.1 mrg "alu") 103 1.1 mrg 104 1.1 mrg (define_insn_reservation "generic_atomic" 10 105 1.1 mrg (eq_attr "type" "atomic") 106 1.1 mrg "alu") 107 1.1 mrg 108 1.1 mrg ;; Sync loop consists of (in order) 109 1.1 mrg ;; (1) optional sync, 110 1.1 mrg ;; (2) LL instruction, 111 1.1 mrg ;; (3) branch and 1-2 ALU instructions, 112 1.1 mrg ;; (4) SC instruction, 113 1.1 mrg ;; (5) branch and ALU instruction. 114 1.1 mrg ;; The net result of this reservation is a big delay with a flush of 115 1.1 mrg ;; ALU pipeline. 116 1.1 mrg (define_insn_reservation "generic_sync_loop" 40 117 1.1 mrg (eq_attr "type" "syncloop") 118 1.1 mrg "alu*39") 119
Indexes created Wed Sep 09 00:24:13 UTC 2026