m68k.h revision 1.5
1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. 2 Copyright (C) 1987-2015 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* We need to have MOTOROLA always defined (either 0 or 1) because we use 21 if-statements and ?: on it. This way we have compile-time error checking 22 for both the MOTOROLA and MIT code paths. We do rely on the host compiler 23 to optimize away all constant tests. */ 24 #if MOTOROLA /* Use the Motorola assembly syntax. */ 25 #else 26 # define MOTOROLA 0 /* Use the MIT assembly syntax. */ 27 #endif 28 29 /* Handle --with-cpu default option from configure script. */ 30 #define OPTION_DEFAULT_SPECS \ 31 { "cpu", "%{!m68020-40:%{!m68020-60:\ 32 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}" }, 33 34 /* Pass flags to gas indicating which type of processor we have. This 35 can be simplified when we can rely on the assembler supporting .cpu 36 and .arch directives. */ 37 38 #define ASM_CPU_SPEC "\ 39 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \ 40 %{m68020-40:-m68040}%{m68020-60:-m68040}\ 41 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ 42 " 43 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \ 44 %{msep-data|mid-shared-library:--pcrel} \ 45 " 46 47 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)" 48 49 #define EXTRA_SPECS \ 50 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 51 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \ 52 SUBTARGET_EXTRA_SPECS 53 54 #define SUBTARGET_EXTRA_SPECS 55 56 /* Note that some other tm.h files include this one and then override 57 many of the definitions that relate to assembler syntax. */ 58 59 #define TARGET_CPU_CPP_BUILTINS() \ 60 do \ 61 { \ 62 builtin_define ("__m68k__"); \ 63 builtin_define_std ("mc68000"); \ 64 /* The other mc680x0 macros have traditionally been derived \ 65 from the tuning setting. For example, -m68020-60 defines \ 66 m68060, even though it generates pure 68020 code. */ \ 67 switch (m68k_tune) \ 68 { \ 69 case u68010: \ 70 builtin_define_std ("mc68010"); \ 71 break; \ 72 \ 73 case u68020: \ 74 builtin_define_std ("mc68020"); \ 75 break; \ 76 \ 77 case u68030: \ 78 builtin_define_std ("mc68030"); \ 79 break; \ 80 \ 81 case u68040: \ 82 builtin_define_std ("mc68040"); \ 83 break; \ 84 \ 85 case u68060: \ 86 builtin_define_std ("mc68060"); \ 87 break; \ 88 \ 89 case u68020_60: \ 90 builtin_define_std ("mc68060"); \ 91 /* Fall through. */ \ 92 case u68020_40: \ 93 builtin_define_std ("mc68040"); \ 94 builtin_define_std ("mc68030"); \ 95 builtin_define_std ("mc68020"); \ 96 break; \ 97 \ 98 case ucpu32: \ 99 builtin_define_std ("mc68332"); \ 100 builtin_define_std ("mcpu32"); \ 101 builtin_define_std ("mc68020"); \ 102 break; \ 103 \ 104 case ucfv1: \ 105 builtin_define ("__mcfv1__"); \ 106 break; \ 107 \ 108 case ucfv2: \ 109 builtin_define ("__mcfv2__"); \ 110 break; \ 111 \ 112 case ucfv3: \ 113 builtin_define ("__mcfv3__"); \ 114 break; \ 115 \ 116 case ucfv4: \ 117 builtin_define ("__mcfv4__"); \ 118 break; \ 119 \ 120 case ucfv4e: \ 121 builtin_define ("__mcfv4e__"); \ 122 break; \ 123 \ 124 case ucfv5: \ 125 builtin_define ("__mcfv5__"); \ 126 break; \ 127 \ 128 default: \ 129 break; \ 130 } \ 131 \ 132 if (TARGET_68881) \ 133 builtin_define ("__HAVE_68881__"); \ 134 \ 135 if (TARGET_COLDFIRE) \ 136 { \ 137 const char *tmp; \ 138 \ 139 tmp = m68k_cpp_cpu_ident ("cf"); \ 140 if (tmp) \ 141 builtin_define (tmp); \ 142 tmp = m68k_cpp_cpu_family ("cf"); \ 143 if (tmp) \ 144 builtin_define (tmp); \ 145 builtin_define ("__mcoldfire__"); \ 146 \ 147 if (TARGET_ISAC) \ 148 builtin_define ("__mcfisac__"); \ 149 else if (TARGET_ISAB) \ 150 { \ 151 builtin_define ("__mcfisab__"); \ 152 /* ISA_B: Legacy 5407 defines. */ \ 153 builtin_define ("__mcf5400__"); \ 154 builtin_define ("__mcf5407__"); \ 155 } \ 156 else if (TARGET_ISAAPLUS) \ 157 { \ 158 builtin_define ("__mcfisaaplus__"); \ 159 /* ISA_A+: legacy defines. */ \ 160 builtin_define ("__mcf528x__"); \ 161 builtin_define ("__mcf5200__"); \ 162 } \ 163 else \ 164 { \ 165 builtin_define ("__mcfisaa__"); \ 166 /* ISA_A: legacy defines. */ \ 167 switch (m68k_tune) \ 168 { \ 169 case ucfv2: \ 170 builtin_define ("__mcf5200__"); \ 171 break; \ 172 \ 173 case ucfv3: \ 174 builtin_define ("__mcf5307__"); \ 175 builtin_define ("__mcf5300__"); \ 176 break; \ 177 \ 178 default: \ 179 break; \ 180 } \ 181 } \ 182 } \ 183 \ 184 if (TARGET_COLDFIRE_FPU) \ 185 builtin_define ("__mcffpu__"); \ 186 \ 187 if (TARGET_CF_HWDIV) \ 188 builtin_define ("__mcfhwdiv__"); \ 189 \ 190 if (TARGET_FIDOA) \ 191 builtin_define ("__mfido__"); \ 192 \ 193 builtin_assert ("cpu=m68k"); \ 194 builtin_assert ("machine=m68k"); \ 195 } \ 196 while (0) 197 198 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI 199 quantities. */ 200 #define INT_OP_STANDARD 0 /* .byte, .short, .long */ 201 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ 202 #define INT_OP_NO_DOT 2 /* byte, short, long */ 203 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ 204 205 /* Set the default. */ 206 #define INT_OP_GROUP INT_OP_DOT_WORD 207 208 /* Bit values used by m68k-devices.def to identify processor capabilities. */ 209 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ 210 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ 211 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ 212 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ 213 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ 214 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ 215 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ 216 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ 217 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ 218 #define FL_ISA_68000 (1 << 9) 219 #define FL_ISA_68010 (1 << 10) 220 #define FL_ISA_68020 (1 << 11) 221 #define FL_ISA_68040 (1 << 12) 222 #define FL_ISA_A (1 << 13) 223 #define FL_ISA_APLUS (1 << 14) 224 #define FL_ISA_B (1 << 15) 225 #define FL_ISA_C (1 << 16) 226 #define FL_FIDOA (1 << 17) 227 #define FL_CAS (1 << 18) /* Support cas insn. */ 228 #define FL_MMU 0 /* Used by multilib machinery. */ 229 #define FL_UCLINUX 0 /* Used by multilib machinery. */ 230 231 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) 232 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) 233 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) 234 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) 235 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) 236 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881) 237 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0) 238 #define TARGET_CAS ((m68k_cpu_flags & FL_CAS) != 0) 239 240 /* Size (in bytes) of FPU registers. */ 241 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) 242 243 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) 244 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) 245 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) 246 247 /* Some instructions are common to more than one ISA. */ 248 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC) 249 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC) 250 #define ISA_HAS_TAS (!TARGET_COLDFIRE || TARGET_ISAB || TARGET_ISAC) 251 252 #define TUNE_68000 (m68k_tune == u68000) 253 #define TUNE_68010 (m68k_tune == u68010) 254 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010) 255 #define TUNE_68030 (m68k_tune == u68030 \ 256 || m68k_tune == u68020_40 \ 257 || m68k_tune == u68020_60) 258 #define TUNE_68040 (m68k_tune == u68040 \ 259 || m68k_tune == u68020_40 \ 260 || m68k_tune == u68020_60) 261 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) 262 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060) 263 #define TUNE_CPU32 (m68k_tune == ucpu32) 264 #define TUNE_CFV1 (m68k_tune == ucfv1) 265 #define TUNE_CFV2 (m68k_tune == ucfv2) 266 #define TUNE_CFV3 (m68k_tune == ucfv3) 267 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e) 268 269 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0) 270 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0) 271 272 /* These are meant to be redefined in the host dependent files */ 273 #define SUBTARGET_OVERRIDE_OPTIONS 274 275 /* target machine storage layout */ 277 278 /* "long double" is the same as "double" on ColdFire and fido 279 targets. */ 280 281 #define LONG_DOUBLE_TYPE_SIZE \ 282 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80) 283 284 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp 285 instructions, we get proper intermediate rounding, otherwise we 286 get extended precision results. */ 287 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) 288 289 #define BITS_BIG_ENDIAN 1 290 #define BYTES_BIG_ENDIAN 1 291 #define WORDS_BIG_ENDIAN 1 292 293 #define UNITS_PER_WORD 4 294 295 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 296 #define STACK_BOUNDARY 16 297 #define FUNCTION_BOUNDARY 16 298 #define EMPTY_FIELD_BOUNDARY 16 299 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */ 300 #define PREFERRED_STACK_BOUNDARY \ 301 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16) 302 303 /* No data type wants to be aligned rounder than this. 304 Most published ABIs say that ints should be aligned on 16-bit 305 boundaries, but CPUs with 32-bit busses get better performance 306 aligned on 32-bit boundaries. */ 307 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) 308 309 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) 310 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1 311 312 #define DWARF_CIE_DATA_ALIGNMENT -2 313 314 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 315 316 /* Define these to avoid dependence on meaning of `int'. */ 317 #define WCHAR_TYPE "long int" 318 #define WCHAR_TYPE_SIZE 32 319 320 /* Maximum number of library IDs we permit with -mid-shared-library. */ 321 #define MAX_LIBRARY_ID 255 322 323 324 /* Standard register usage. */ 326 327 /* For the m68k, we give the data registers numbers 0-7, 328 the address registers numbers 010-017 (8-15), 329 and the 68881 floating point registers numbers 020-027 (16-23). 330 We also have a fake `arg-pointer' register 030 (24) used for 331 register elimination. */ 332 #define FIRST_PSEUDO_REGISTER 25 333 334 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ 335 #define PIC_OFFSET_TABLE_REGNUM \ 336 (!flag_pic ? INVALID_REGNUM \ 337 : reload_completed ? REGNO (pic_offset_table_rtx) \ 338 : PIC_REG) 339 340 /* 1 for registers that have pervasive standard uses 341 and are not available for the register allocator. 342 On the m68k, only the stack pointer is such. 343 Our fake arg-pointer is obviously fixed as well. */ 344 #define FIXED_REGISTERS \ 345 {/* Data registers. */ \ 346 0, 0, 0, 0, 0, 0, 0, 0, \ 347 \ 348 /* Address registers. */ \ 349 0, 0, 0, 0, 0, 0, 0, 1, \ 350 \ 351 /* Floating point registers \ 352 (if available). */ \ 353 0, 0, 0, 0, 0, 0, 0, 0, \ 354 \ 355 /* Arg pointer. */ \ 356 1 } 357 358 /* 1 for registers not available across function calls. 359 These must include the FIXED_REGISTERS and also any 360 registers that can be used without being saved. 361 The latter must include the registers where values are returned 362 and the register where structure-value addresses are passed. 363 Aside from that, you can include as many other registers as you like. */ 364 #define CALL_USED_REGISTERS \ 365 {/* Data registers. */ \ 366 1, 1, 0, 0, 0, 0, 0, 0, \ 367 \ 368 /* Address registers. */ \ 369 1, 1, 0, 0, 0, 0, 0, 1, \ 370 \ 371 /* Floating point registers \ 372 (if available). */ \ 373 1, 1, 0, 0, 0, 0, 0, 0, \ 374 \ 375 /* Arg pointer. */ \ 376 1 } 377 378 #define REG_ALLOC_ORDER \ 379 { /* d0/d1/a0/a1 */ \ 380 0, 1, 8, 9, \ 381 /* d2-d7 */ \ 382 2, 3, 4, 5, 6, 7, \ 383 /* a2-a7/arg */ \ 384 10, 11, 12, 13, 14, 15, 24, \ 385 /* fp0-fp7 */ \ 386 16, 17, 18, 19, 20, 21, 22, 23\ 387 } 388 389 390 /* On the m68k, ordinary registers hold 32 bits worth; 391 for the 68881 registers, a single register is always enough for 392 anything that can be stored in them at all. */ 393 #define HARD_REGNO_NREGS(REGNO, MODE) \ 394 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 395 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 396 397 /* A C expression that is nonzero if hard register NEW_REG can be 398 considered for use as a rename register for OLD_REG register. */ 399 400 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 401 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) 402 403 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 404 m68k_regno_mode_ok ((REGNO), (MODE)) 405 406 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 407 m68k_secondary_reload_class (CLASS, MODE, X) 408 409 #define MODES_TIEABLE_P(MODE1, MODE2) \ 410 (! TARGET_HARD_FLOAT \ 411 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 412 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 413 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 414 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 415 416 /* Specify the registers used for certain standard purposes. 417 The values of these macros are register numbers. */ 418 419 #define STACK_POINTER_REGNUM SP_REG 420 421 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS 422 ABI uses %a6 for shared library calls, therefore the frame 423 pointer is shifted to %a5 on this target. */ 424 #define FRAME_POINTER_REGNUM A6_REG 425 426 /* Base register for access to arguments of the function. 427 * This isn't a hardware register. It will be eliminated to the 428 * stack pointer or frame pointer. 429 */ 430 #define ARG_POINTER_REGNUM 24 431 432 #define STATIC_CHAIN_REGNUM A0_REG 433 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0" 434 435 /* Register in which address to store a structure value 436 is passed to a function. */ 437 #define M68K_STRUCT_VALUE_REGNUM A1_REG 438 439 440 442 /* The m68k has three kinds of registers, so eight classes would be 443 a complete set. One of them is not needed. */ 444 enum reg_class { 445 NO_REGS, DATA_REGS, 446 ADDR_REGS, FP_REGS, 447 GENERAL_REGS, DATA_OR_FP_REGS, 448 ADDR_OR_FP_REGS, ALL_REGS, 449 LIM_REG_CLASSES }; 450 451 #define N_REG_CLASSES (int) LIM_REG_CLASSES 452 453 #define REG_CLASS_NAMES \ 454 { "NO_REGS", "DATA_REGS", \ 455 "ADDR_REGS", "FP_REGS", \ 456 "GENERAL_REGS", "DATA_OR_FP_REGS", \ 457 "ADDR_OR_FP_REGS", "ALL_REGS" } 458 459 #define REG_CLASS_CONTENTS \ 460 { \ 461 {0x00000000}, /* NO_REGS */ \ 462 {0x000000ff}, /* DATA_REGS */ \ 463 {0x0100ff00}, /* ADDR_REGS */ \ 464 {0x00ff0000}, /* FP_REGS */ \ 465 {0x0100ffff}, /* GENERAL_REGS */ \ 466 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ 467 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ 468 {0x01ffffff}, /* ALL_REGS */ \ 469 } 470 471 extern enum reg_class regno_reg_class[]; 472 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) 473 #define INDEX_REG_CLASS GENERAL_REGS 474 #define BASE_REG_CLASS ADDR_REGS 475 476 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 477 m68k_preferred_reload_class (X, CLASS) 478 479 /* On the m68k, this is the size of MODE in words, 480 except in the FP regs, where a single reg is always enough. */ 481 #define CLASS_MAX_NREGS(CLASS, MODE) \ 482 ((CLASS) == FP_REGS ? 1 \ 483 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 484 485 /* Moves between fp regs and other regs are two insns. */ 486 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 487 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) 488 489 490 /* Stack layout; function entry, exit and calling. */ 492 493 #define STACK_GROWS_DOWNWARD 1 494 #define FRAME_GROWS_DOWNWARD 1 495 #define STARTING_FRAME_OFFSET 0 496 497 /* On the 680x0, sp@- in a byte insn really pushes a word. 498 On the ColdFire, sp@- in a byte insn pushes just a byte. */ 499 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) 500 501 #define FIRST_PARM_OFFSET(FNDECL) 8 502 503 /* On the m68k the return value defaults to D0. */ 504 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 505 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG) 506 507 /* On the m68k the return value defaults to D0. */ 508 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG) 509 510 /* On the m68k, D0 is usually the only register used. */ 511 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG) 512 513 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 514 more than one register. 515 XXX This macro is m68k specific and used only for m68kemb.h. */ 516 #define NEEDS_UNTYPED_CALL 0 517 518 /* On the m68k, all arguments are usually pushed on the stack. */ 519 #define FUNCTION_ARG_REGNO_P(N) 0 520 521 /* On the m68k, this is a single integer, which is a number of bytes 523 of arguments scanned so far. */ 524 #define CUMULATIVE_ARGS int 525 526 /* On the m68k, the offset starts at 0. */ 527 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 528 ((CUM) = 0) 529 530 #define FUNCTION_PROFILER(FILE, LABELNO) \ 531 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 532 533 #define EXIT_IGNORE_STACK 1 534 535 /* Output assembler code for a block containing the constant parts 536 of a trampoline, leaving space for the variable parts. 537 538 On the m68k, the trampoline looks like this: 539 movl #STATIC,a0 540 jmp FUNCTION 541 542 WARNING: Targets that may run on 68040+ cpus must arrange for 543 the instruction cache to be flushed. Previous incarnations of 544 the m68k trampoline code attempted to get around this by either 545 using an out-of-line transfer function or pc-relative data, but 546 the fact remains that the code to jump to the transfer function 547 or the code to load the pc-relative data needs to be flushed 548 just as much as the "variable" portion of the trampoline. 549 Recognizing that a cache flush is going to be required anyway, 550 dispense with such notions and build a smaller trampoline. 551 552 Since more instructions are required to move a template into 553 place than to create it on the spot, don't use a template. */ 554 555 #define TRAMPOLINE_SIZE 12 556 #define TRAMPOLINE_ALIGNMENT 16 557 558 /* Targets redefine this to invoke code to either flush the cache, 559 or enable stack execution (or both). */ 560 #ifndef FINALIZE_TRAMPOLINE 561 #define FINALIZE_TRAMPOLINE(TRAMP) 562 #endif 563 564 /* This is the library routine that is used to transfer control from the 565 trampoline to the actual nested function. It is defined for backward 566 compatibility, for linking with object code that used the old trampoline 567 definition. 568 569 A colon is used with no explicit operands to cause the template string 570 to be scanned for %-constructs. 571 572 The function name __transfer_from_trampoline is not actually used. 573 The function definition just permits use of "asm with operands" 574 (though the operand list is empty). */ 575 #define TRANSFER_FROM_TRAMPOLINE \ 576 void \ 577 __transfer_from_trampoline () \ 578 { \ 579 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \ 580 asm (GLOBAL_ASM_OP "___trampoline"); \ 581 asm ("___trampoline:"); \ 582 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 583 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 584 asm ("rts":); \ 585 } 586 587 /* There are two registers that can always be eliminated on the m68k. 589 The frame pointer and the arg pointer can be replaced by either the 590 hard frame pointer or to the stack pointer, depending upon the 591 circumstances. The hard frame pointer is not used before reload and 592 so it is not eligible for elimination. */ 593 #define ELIMINABLE_REGS \ 594 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 595 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 596 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 597 598 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 599 (OFFSET) = m68k_initial_elimination_offset(FROM, TO) 600 601 /* Addressing modes, and classification of registers for them. */ 603 604 #define HAVE_POST_INCREMENT 1 605 #define HAVE_PRE_DECREMENT 1 606 607 /* Macros to check register numbers against specific register classes. */ 608 609 /* True for data registers, D0 through D7. */ 610 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7) 611 612 /* True for address registers, A0 through A7. */ 613 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15) 614 615 /* True for integer registers, D0 through D7 and A0 through A7. */ 616 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15) 617 618 /* True for floating point registers, FP0 through FP7. */ 619 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23) 620 621 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 622 (INT_REGNO_P (REGNO) \ 623 || INT_REGNO_P (reg_renumber[REGNO])) 624 625 #define REGNO_OK_FOR_BASE_P(REGNO) \ 626 (ADDRESS_REGNO_P (REGNO) \ 627 || ADDRESS_REGNO_P (reg_renumber[REGNO])) 628 629 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ 630 (INT_REGNO_P (REGNO) \ 631 || REGNO == ARG_POINTER_REGNUM \ 632 || REGNO >= FIRST_PSEUDO_REGISTER) 633 634 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ 635 (ADDRESS_REGNO_P (REGNO) \ 636 || REGNO == ARG_POINTER_REGNUM \ 637 || REGNO >= FIRST_PSEUDO_REGISTER) 638 639 /* Now macros that check whether X is a register and also, 640 strictly, whether it is in a specified class. 641 642 These macros are specific to the m68k, and may be used only 643 in code for printing assembler insns and in conditions for 644 define_optimization. */ 645 646 /* 1 if X is a data register. */ 647 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X))) 648 649 /* 1 if X is an fp register. */ 650 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 651 652 /* 1 if X is an address register */ 653 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X))) 654 655 /* True if SYMBOL + OFFSET constants must refer to something within 657 SYMBOL's section. */ 658 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 659 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 660 #endif 661 662 #define MAX_REGS_PER_ADDRESS 2 663 664 #define CONSTANT_ADDRESS_P(X) \ 665 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 666 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 667 || GET_CODE (X) == HIGH) \ 668 && m68k_legitimate_constant_p (Pmode, X)) 669 670 #ifndef REG_OK_STRICT 671 #define REG_STRICT_P 0 672 #else 673 #define REG_STRICT_P 1 674 #endif 675 676 #define LEGITIMATE_PIC_OPERAND_P(X) \ 677 (!symbolic_operand (X, VOIDmode) \ 678 || (TARGET_PCREL && REG_STRICT_P) \ 679 || m68k_tls_reference_p (X, true)) 680 681 #define REG_OK_FOR_BASE_P(X) \ 682 m68k_legitimate_base_reg_p (X, REG_STRICT_P) 683 684 #define REG_OK_FOR_INDEX_P(X) \ 685 m68k_legitimate_index_reg_p (X, REG_STRICT_P) 686 687 688 /* This address is OK as it stands. */ 690 #define PIC_CASE_VECTOR_ADDRESS(index) index 691 #define CASE_VECTOR_MODE HImode 692 #define CASE_VECTOR_PC_RELATIVE 1 693 694 #define DEFAULT_SIGNED_CHAR 1 695 #define MOVE_MAX 4 696 #define SLOW_BYTE_ACCESS 0 697 698 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 699 700 /* The 68020 BFFFO and ColdFire FF1 instructions return 32 for zero. */ 701 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 702 703 #define STORE_FLAG_VALUE (-1) 704 705 #define Pmode SImode 706 #define FUNCTION_MODE QImode 707 708 709 /* Tell final.c how to eliminate redundant test instructions. */ 711 712 /* Here we define machine-dependent flags and fields in cc_status 713 (see `conditions.h'). */ 714 715 /* Set if the cc value is actually in the 68881, so a floating point 716 conditional branch must be output. */ 717 #define CC_IN_68881 04000 718 719 /* On the 68000, all the insns to store in an address register fail to 720 set the cc's. However, in some cases these instructions can make it 721 possibly invalid to use the saved cc's. In those cases we clear out 722 some or all of the saved cc's so they won't be used. */ 723 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 724 725 /* The shift instructions always clear the overflow bit. */ 726 #define CC_OVERFLOW_UNUSABLE 01000 727 728 /* The shift instructions use the carry bit in a way not compatible with 729 conditional branches. conditions.h uses CC_NO_OVERFLOW for this purpose. 730 Rename it to something more understandable. */ 731 #define CC_NO_CARRY CC_NO_OVERFLOW 732 733 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 734 do { if (cc_prev_status.flags & CC_IN_68881) \ 735 return FLOAT; \ 736 if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 737 return NO_OV; \ 738 return NORMAL; } while (0) 739 740 /* Control the assembler format that we output. */ 742 743 #define ASM_APP_ON "#APP\n" 744 #define ASM_APP_OFF "#NO_APP\n" 745 #define TEXT_SECTION_ASM_OP "\t.text" 746 #define DATA_SECTION_ASM_OP "\t.data" 747 #define GLOBAL_ASM_OP "\t.globl\t" 748 #define REGISTER_PREFIX "" 749 #define LOCAL_LABEL_PREFIX "" 750 #define USER_LABEL_PREFIX "_" 751 #define IMMEDIATE_PREFIX "#" 752 753 #define REGISTER_NAMES \ 754 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \ 755 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \ 756 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \ 757 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \ 758 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \ 759 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \ 760 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \ 761 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \ 762 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" } 763 764 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp" 765 766 /* Return a register name by index, handling %fp nicely. 767 We don't replace %fp for targets that don't map it to %a6 768 since it may confuse GAS. */ 769 #define M68K_REGNAME(r) ( \ 770 ((FRAME_POINTER_REGNUM == A6_REG) \ 771 && ((r) == FRAME_POINTER_REGNUM) \ 772 && frame_pointer_needed) ? \ 773 M68K_FP_REG_NAME : reg_names[(r)]) 774 775 /* On the Sun-3, the floating point registers have numbers 776 18 to 25, not 16 to 23 as they do in the compiler. */ 777 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 778 779 /* Before the prologue, RA is at 0(%sp). */ 780 #define INCOMING_RETURN_ADDR_RTX \ 781 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 782 783 /* After the prologue, RA is at 4(AP) in the current frame. */ 784 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 785 ((COUNT) == 0 \ 786 ? gen_rtx_MEM (Pmode, plus_constant (Pmode, arg_pointer_rtx, \ 787 UNITS_PER_WORD)) \ 788 : gen_rtx_MEM (Pmode, plus_constant (Pmode, FRAME, UNITS_PER_WORD))) 789 790 /* We must not use the DBX register numbers for the DWARF 2 CFA column 791 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 792 Instead use the identity mapping. */ 793 #define DWARF_FRAME_REGNUM(REG) \ 794 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM) 795 796 /* The return column was originally 24, but gcc used 25 for a while too. 797 Define both registers 24 and 25 as Pmode ones and use 24 in our own 798 unwind information. */ 799 #define DWARF_FRAME_REGISTERS 25 800 #define DWARF_FRAME_RETURN_COLUMN 24 801 #define DWARF_ALT_FRAME_RETURN_COLUMN 25 802 803 /* Before the prologue, the top of the frame is at 4(%sp). */ 804 #define INCOMING_FRAME_SP_OFFSET 4 805 806 #define EPILOGUE_USES(REGNO) m68k_epilogue_uses (REGNO) 807 808 /* Describe how we implement __builtin_eh_return. */ 809 #define EH_RETURN_DATA_REGNO(N) \ 810 ((N) < 2 ? (N) : INVALID_REGNUM) 811 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) 812 #define EH_RETURN_HANDLER_RTX \ 813 gen_rtx_MEM (Pmode, \ 814 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ 815 plus_constant (Pmode, EH_RETURN_STACKADJ_RTX, \ 816 UNITS_PER_WORD))) 817 818 /* Select a format to encode pointers in exception handling data. CODE 819 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 820 true if the symbol may be affected by dynamic relocations. 821 822 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support 823 a read-only text segment without imposing a fixed gap between the 824 text and data segments. As a result, the text segment cannot refer 825 to anything in the data segment, even in PC-relative form. Because 826 .eh_frame refers to both code and data, it follows that .eh_frame 827 must be in the data segment itself, and that the offset between 828 .eh_frame and code will not be a link-time constant. 829 830 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel 831 | DW_EH_PE_indirect for all code references. However, gcc currently 832 handles indirect references using a per-TU constant pool. This means 833 that if a function and its eh_frame are removed by the linker, the 834 eh_frame's indirect references to the removed function will not be 835 removed, leading to an unresolved symbol error. 836 837 It isn't clear that any -msep-data or -mid-shared-library target 838 would benefit from a read-only .eh_frame anyway. In particular, 839 no known target that supports these options has a feature like 840 PT_GNU_RELRO. Without any such feature to motivate them, indirect 841 references would be unnecessary bloat, so we simply use an absolute 842 pointer for code and global references. We still use pc-relative 843 references to data, as this avoids a relocation. */ 844 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 845 (flag_pic \ 846 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ 847 && ((GLOBAL) || (CODE))) \ 848 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 849 : DW_EH_PE_absptr) 850 851 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 852 asm_fprintf (FILE, "%U%s", NAME) 853 854 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 855 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) 856 857 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 858 asm_fprintf (FILE, (MOTOROLA \ 859 ? "\tmove.l %s,-(%Rsp)\n" \ 860 : "\tmovel %s,%Rsp@-\n"), \ 861 reg_names[REGNO]) 862 863 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 864 asm_fprintf (FILE, (MOTOROLA \ 865 ? "\tmove.l (%Rsp)+,%s\n" \ 866 : "\tmovel %Rsp@+,%s\n"), \ 867 reg_names[REGNO]) 868 869 /* The m68k does not use absolute case-vectors, but we must define this macro 870 anyway. */ 871 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 872 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 873 874 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 875 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 876 877 /* We don't have a way to align to more than a two-byte boundary, so do the 878 best we can and don't complain. */ 879 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 880 if ((LOG) >= 1) \ 881 fprintf (FILE, "\t.even\n"); 882 883 #ifdef HAVE_GAS_BALIGN_AND_P2ALIGN 884 /* Use "move.l %a4,%a4" to advance within code. */ 885 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 886 if ((LOG) > 0) \ 887 fprintf ((FILE), "\t.balignw %u,0x284c\n", 1 << (LOG)); 888 #endif 889 890 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 891 fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) 892 893 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 894 ( fputs (".comm ", (FILE)), \ 895 assemble_name ((FILE), (NAME)), \ 896 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 897 898 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 899 ( fputs (".lcomm ", (FILE)), \ 900 assemble_name ((FILE), (NAME)), \ 901 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 902 903 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 904 m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS) 905 906 /* On the 68000, we use several CODE characters: 907 '.' for dot needed in Motorola-style opcode names. 908 '-' for an operand pushing on the stack: 909 sp@-, -(sp) or -(%sp) depending on the style of syntax. 910 '+' for an operand pushing on the stack: 911 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 912 '@' for a reference to the top word on the stack: 913 sp@, (sp) or (%sp) depending on the style of syntax. 914 '#' for an immediate operand prefix (# in MIT and Motorola syntax 915 but & in SGS syntax). 916 '!' for the fpcr register (used in some float-to-fixed conversions). 917 '$' for the letter `s' in an op code, but only on the 68040. 918 '&' for the letter `d' in an op code, but only on the 68040. 919 '/' for register prefix needed by longlong.h. 920 '?' for m68k_library_id_string 921 922 'b' for byte insn (no effect, on the Sun; this is for the ISI). 923 'd' to force memory addressing to be absolute, not relative. 924 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 925 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 926 or print pair of registers as rx:ry. */ 927 928 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 929 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 930 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 931 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?') 932 933 934 /* See m68k.c for the m68k specific codes. */ 935 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 936 937 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 938 939 #include "config/m68k/m68k-opts.h" 940 941 enum fpu_type 942 { 943 FPUTYPE_NONE, 944 FPUTYPE_68881, 945 FPUTYPE_COLDFIRE 946 }; 947 948 enum m68k_function_kind 949 { 950 m68k_fk_normal_function, 951 m68k_fk_interrupt_handler, 952 m68k_fk_interrupt_thread 953 }; 954 955 /* Variables in m68k.c; see there for details. */ 956 extern enum target_device m68k_cpu; 957 extern enum uarch_type m68k_tune; 958 extern enum fpu_type m68k_fpu; 959 extern unsigned int m68k_cpu_flags; 960 extern unsigned int m68k_tune_flags; 961 extern const char *m68k_symbolic_call; 962 extern const char *m68k_symbolic_jump; 963 964 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR, 965 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P }; 966 967 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; 968 969 /* ??? HOST_WIDE_INT is not being defined for auto-generated files. 970 Workaround that. */ 971 #ifdef HOST_WIDE_INT 972 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } 973 M68K_CONST_METHOD; 974 975 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT); 976 #endif 977 978 extern void m68k_emit_move_double (rtx [2]); 979 980 extern int m68k_sched_address_bypass_p (rtx_insn *, rtx_insn *); 981 extern int m68k_sched_indexed_address_bypass_p (rtx_insn *, rtx_insn *); 982 983 #define CPU_UNITS_QUERY 1 984
Indexes created Fri Jul 03 00:25:33 UTC 2026