1 1.12 mrg ;; Copyright (C) 2005-2022 Free Software Foundation, Inc. 2 1.1 mrg ;; 3 1.1 mrg ;; This file is part of GCC. 4 1.1 mrg ;; 5 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify 6 1.1 mrg ;; it under the terms of the GNU General Public License as published by 7 1.1 mrg ;; the Free Software Foundation; either version 3, or (at your option) 8 1.1 mrg ;; any later version. 9 1.1 mrg ;; 10 1.1 mrg ;; GCC is distributed in the hope that it will be useful, 11 1.1 mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12 1.1 mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 1.1 mrg ;; GNU General Public License for more details. 14 1.1 mrg ;; 15 1.1 mrg ;; You should have received a copy of the GNU General Public License 16 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 17 1.1 mrg ;; <http://www.gnu.org/licenses/>. 18 1.1 mrg 19 1.3 mrg ;; MIPS DSP ASE Revision 0.98 3/24/2005 20 1.3 mrg (define_c_enum "unspec" [ 21 1.3 mrg UNSPEC_ADDQ 22 1.3 mrg UNSPEC_ADDQ_S 23 1.3 mrg UNSPEC_SUBQ 24 1.3 mrg UNSPEC_SUBQ_S 25 1.3 mrg UNSPEC_ADDSC 26 1.3 mrg UNSPEC_ADDWC 27 1.3 mrg UNSPEC_MODSUB 28 1.3 mrg UNSPEC_RADDU_W_QB 29 1.3 mrg UNSPEC_ABSQ_S 30 1.3 mrg UNSPEC_PRECRQ_QB_PH 31 1.3 mrg UNSPEC_PRECRQ_PH_W 32 1.3 mrg UNSPEC_PRECRQ_RS_PH_W 33 1.3 mrg UNSPEC_PRECRQU_S_QB_PH 34 1.3 mrg UNSPEC_PRECEQ_W_PHL 35 1.3 mrg UNSPEC_PRECEQ_W_PHR 36 1.3 mrg UNSPEC_PRECEQU_PH_QBL 37 1.3 mrg UNSPEC_PRECEQU_PH_QBR 38 1.3 mrg UNSPEC_PRECEQU_PH_QBLA 39 1.3 mrg UNSPEC_PRECEQU_PH_QBRA 40 1.3 mrg UNSPEC_PRECEU_PH_QBL 41 1.3 mrg UNSPEC_PRECEU_PH_QBR 42 1.3 mrg UNSPEC_PRECEU_PH_QBLA 43 1.3 mrg UNSPEC_PRECEU_PH_QBRA 44 1.3 mrg UNSPEC_SHLL 45 1.3 mrg UNSPEC_SHLL_S 46 1.3 mrg UNSPEC_SHRL_QB 47 1.3 mrg UNSPEC_SHRA_PH 48 1.3 mrg UNSPEC_SHRA_R 49 1.3 mrg UNSPEC_MULEU_S_PH_QBL 50 1.3 mrg UNSPEC_MULEU_S_PH_QBR 51 1.3 mrg UNSPEC_MULQ_RS_PH 52 1.3 mrg UNSPEC_MULEQ_S_W_PHL 53 1.3 mrg UNSPEC_MULEQ_S_W_PHR 54 1.3 mrg UNSPEC_DPAU_H_QBL 55 1.3 mrg UNSPEC_DPAU_H_QBR 56 1.3 mrg UNSPEC_DPSU_H_QBL 57 1.3 mrg UNSPEC_DPSU_H_QBR 58 1.3 mrg UNSPEC_DPAQ_S_W_PH 59 1.3 mrg UNSPEC_DPSQ_S_W_PH 60 1.3 mrg UNSPEC_MULSAQ_S_W_PH 61 1.3 mrg UNSPEC_DPAQ_SA_L_W 62 1.3 mrg UNSPEC_DPSQ_SA_L_W 63 1.3 mrg UNSPEC_MAQ_S_W_PHL 64 1.3 mrg UNSPEC_MAQ_S_W_PHR 65 1.3 mrg UNSPEC_MAQ_SA_W_PHL 66 1.3 mrg UNSPEC_MAQ_SA_W_PHR 67 1.3 mrg UNSPEC_BITREV 68 1.3 mrg UNSPEC_INSV 69 1.3 mrg UNSPEC_REPL_QB 70 1.3 mrg UNSPEC_REPL_PH 71 1.3 mrg UNSPEC_CMP_EQ 72 1.3 mrg UNSPEC_CMP_LT 73 1.3 mrg UNSPEC_CMP_LE 74 1.3 mrg UNSPEC_CMPGU_EQ_QB 75 1.3 mrg UNSPEC_CMPGU_LT_QB 76 1.3 mrg UNSPEC_CMPGU_LE_QB 77 1.3 mrg UNSPEC_PICK 78 1.3 mrg UNSPEC_PACKRL_PH 79 1.3 mrg UNSPEC_EXTR_W 80 1.3 mrg UNSPEC_EXTR_R_W 81 1.3 mrg UNSPEC_EXTR_RS_W 82 1.3 mrg UNSPEC_EXTR_S_H 83 1.3 mrg UNSPEC_EXTP 84 1.3 mrg UNSPEC_EXTPDP 85 1.3 mrg UNSPEC_SHILO 86 1.3 mrg UNSPEC_MTHLIP 87 1.3 mrg UNSPEC_WRDSP 88 1.3 mrg UNSPEC_RDDSP 89 1.3 mrg ]) 90 1.3 mrg 91 1.1 mrg (define_constants 92 1.1 mrg [(CCDSP_PO_REGNUM 182) 93 1.1 mrg (CCDSP_SC_REGNUM 183) 94 1.1 mrg (CCDSP_CA_REGNUM 184) 95 1.1 mrg (CCDSP_OU_REGNUM 185) 96 1.1 mrg (CCDSP_CC_REGNUM 186) 97 1.1 mrg (CCDSP_EF_REGNUM 187)]) 98 1.1 mrg 99 1.1 mrg ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE. 100 1.1 mrg (define_mode_iterator DSP [(SI "ISA_HAS_DSP") 101 1.1 mrg (V2HI "ISA_HAS_DSP") 102 1.1 mrg (V4QI "ISA_HAS_DSP")]) 103 1.1 mrg 104 1.1 mrg ;; This mode iterator allows v2hi, v4qi for vector/SIMD data. 105 1.1 mrg (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP") 106 1.1 mrg (V4QI "ISA_HAS_DSP")]) 107 1.1 mrg 108 1.1 mrg ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data. 109 1.1 mrg (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP") 110 1.1 mrg (V2HI "ISA_HAS_DSP")]) 111 1.1 mrg 112 1.1 mrg ;; DSP instructions use q for fixed-point data, and u for integer in the infix. 113 1.1 mrg (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) 114 1.1 mrg 115 1.1 mrg ;; DSP instructions use nothing for fixed-point data, and u for integer in 116 1.1 mrg ;; the infix. 117 1.1 mrg (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")]) 118 1.1 mrg 119 1.1 mrg ;; DSP instructions use w, ph, qb in the postfix. 120 1.1 mrg (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")]) 121 1.1 mrg 122 1.1 mrg ;; DSP shift masks for SI, V2HI, V4QI. 123 1.1 mrg (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")]) 124 1.1 mrg 125 1.1 mrg ;; MIPS DSP ASE Revision 0.98 3/24/2005 126 1.1 mrg ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic 127 1.1 mrg ;; ADDQ* 128 1.1 mrg (define_insn "add<DSPV:mode>3" 129 1.5 mrg [(set (match_operand:DSPV 0 "register_operand" "=d") 130 1.5 mrg (plus:DSPV (match_operand:DSPV 1 "register_operand" "d") 131 1.5 mrg (match_operand:DSPV 2 "register_operand" "d"))) 132 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 133 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))] 134 1.3 mrg "ISA_HAS_DSP" 135 1.1 mrg "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 136 1.3 mrg [(set_attr "type" "dspalu") 137 1.1 mrg (set_attr "mode" "SI")]) 138 1.1 mrg 139 1.1 mrg (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" 140 1.5 mrg [(set (match_operand:DSP 0 "register_operand" "=d") 141 1.5 mrg (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 142 1.5 mrg (match_operand:DSP 2 "register_operand" "d")] 143 1.5 mrg UNSPEC_ADDQ_S)) 144 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 145 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))] 146 1.3 mrg "ISA_HAS_DSP" 147 1.1 mrg "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 148 1.3 mrg [(set_attr "type" "dspalusat") 149 1.1 mrg (set_attr "mode" "SI")]) 150 1.1 mrg 151 1.1 mrg ;; SUBQ* 152 1.1 mrg (define_insn "sub<DSPV:mode>3" 153 1.5 mrg [(set (match_operand:DSPV 0 "register_operand" "=d") 154 1.5 mrg (minus:DSPV (match_operand:DSPV 1 "register_operand" "d") 155 1.5 mrg (match_operand:DSPV 2 "register_operand" "d"))) 156 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 157 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))] 158 1.1 mrg "ISA_HAS_DSP" 159 1.1 mrg "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 160 1.3 mrg [(set_attr "type" "dspalu") 161 1.1 mrg (set_attr "mode" "SI")]) 162 1.1 mrg 163 1.1 mrg (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" 164 1.5 mrg [(set (match_operand:DSP 0 "register_operand" "=d") 165 1.5 mrg (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 166 1.5 mrg (match_operand:DSP 2 "register_operand" "d")] 167 1.5 mrg UNSPEC_SUBQ_S)) 168 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 169 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))] 170 1.1 mrg "ISA_HAS_DSP" 171 1.1 mrg "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 172 1.3 mrg [(set_attr "type" "dspalusat") 173 1.1 mrg (set_attr "mode" "SI")]) 174 1.1 mrg 175 1.1 mrg ;; ADDSC 176 1.1 mrg (define_insn "mips_addsc" 177 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d") 178 1.5 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d") 179 1.5 mrg (match_operand:SI 2 "register_operand" "d")] 180 1.5 mrg UNSPEC_ADDSC)) 181 1.5 mrg (set (reg:CCDSP CCDSP_CA_REGNUM) 182 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))] 183 1.1 mrg "ISA_HAS_DSP" 184 1.1 mrg "addsc\t%0,%1,%2" 185 1.3 mrg [(set_attr "type" "dspalu") 186 1.1 mrg (set_attr "mode" "SI")]) 187 1.1 mrg 188 1.1 mrg ;; ADDWC 189 1.1 mrg (define_insn "mips_addwc" 190 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d") 191 1.5 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d") 192 1.5 mrg (match_operand:SI 2 "register_operand" "d") 193 1.5 mrg (reg:CCDSP CCDSP_CA_REGNUM)] 194 1.5 mrg UNSPEC_ADDWC)) 195 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 196 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))] 197 1.1 mrg "ISA_HAS_DSP" 198 1.1 mrg "addwc\t%0,%1,%2" 199 1.3 mrg [(set_attr "type" "dspalu") 200 1.1 mrg (set_attr "mode" "SI")]) 201 1.1 mrg 202 1.1 mrg ;; MODSUB 203 1.1 mrg (define_insn "mips_modsub" 204 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 205 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d") 206 1.1 mrg (match_operand:SI 2 "register_operand" "d")] 207 1.1 mrg UNSPEC_MODSUB))] 208 1.1 mrg "ISA_HAS_DSP" 209 1.1 mrg "modsub\t%0,%1,%2" 210 1.3 mrg [(set_attr "type" "dspalu") 211 1.1 mrg (set_attr "mode" "SI")]) 212 1.1 mrg 213 1.1 mrg ;; RADDU* 214 1.1 mrg (define_insn "mips_raddu_w_qb" 215 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 216 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] 217 1.1 mrg UNSPEC_RADDU_W_QB))] 218 1.1 mrg "ISA_HAS_DSP" 219 1.1 mrg "raddu.w.qb\t%0,%1" 220 1.3 mrg [(set_attr "type" "dspalu") 221 1.1 mrg (set_attr "mode" "SI")]) 222 1.1 mrg 223 1.1 mrg ;; ABSQ* 224 1.1 mrg (define_insn "mips_absq_s_<DSPQ:dspfmt2>" 225 1.5 mrg [(set (match_operand:DSPQ 0 "register_operand" "=d") 226 1.5 mrg (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] 227 1.5 mrg UNSPEC_ABSQ_S)) 228 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 229 1.5 mrg (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))] 230 1.1 mrg "ISA_HAS_DSP" 231 1.1 mrg "absq_s.<DSPQ:dspfmt2>\t%0,%1" 232 1.3 mrg [(set_attr "type" "dspalusat") 233 1.1 mrg (set_attr "mode" "SI")]) 234 1.1 mrg 235 1.1 mrg ;; PRECRQ* 236 1.1 mrg (define_insn "mips_precrq_qb_ph" 237 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d") 238 1.1 mrg (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 239 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 240 1.1 mrg UNSPEC_PRECRQ_QB_PH))] 241 1.1 mrg "ISA_HAS_DSP" 242 1.1 mrg "precrq.qb.ph\t%0,%1,%2" 243 1.3 mrg [(set_attr "type" "dspalu") 244 1.1 mrg (set_attr "mode" "SI")]) 245 1.1 mrg 246 1.1 mrg (define_insn "mips_precrq_ph_w" 247 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 248 1.1 mrg (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 249 1.1 mrg (match_operand:SI 2 "register_operand" "d")] 250 1.1 mrg UNSPEC_PRECRQ_PH_W))] 251 1.1 mrg "ISA_HAS_DSP" 252 1.1 mrg "precrq.ph.w\t%0,%1,%2" 253 1.3 mrg [(set_attr "type" "dspalu") 254 1.1 mrg (set_attr "mode" "SI")]) 255 1.1 mrg 256 1.1 mrg (define_insn "mips_precrq_rs_ph_w" 257 1.5 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 258 1.5 mrg (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 259 1.5 mrg (match_operand:SI 2 "register_operand" "d")] 260 1.5 mrg UNSPEC_PRECRQ_RS_PH_W)) 261 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 262 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] 263 1.5 mrg UNSPEC_PRECRQ_RS_PH_W))] 264 1.1 mrg "ISA_HAS_DSP" 265 1.1 mrg "precrq_rs.ph.w\t%0,%1,%2" 266 1.3 mrg [(set_attr "type" "dspalu") 267 1.1 mrg (set_attr "mode" "SI")]) 268 1.1 mrg 269 1.1 mrg ;; PRECRQU* 270 1.1 mrg (define_insn "mips_precrqu_s_qb_ph" 271 1.5 mrg [(set (match_operand:V4QI 0 "register_operand" "=d") 272 1.5 mrg (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 273 1.5 mrg (match_operand:V2HI 2 "register_operand" "d")] 274 1.5 mrg UNSPEC_PRECRQU_S_QB_PH)) 275 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 276 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] 277 1.5 mrg UNSPEC_PRECRQU_S_QB_PH))] 278 1.1 mrg "ISA_HAS_DSP" 279 1.1 mrg "precrqu_s.qb.ph\t%0,%1,%2" 280 1.3 mrg [(set_attr "type" "dspalusat") 281 1.1 mrg (set_attr "mode" "SI")]) 282 1.1 mrg 283 1.1 mrg ;; PRECEQ* 284 1.1 mrg (define_insn "mips_preceq_w_phl" 285 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 286 1.1 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 287 1.1 mrg UNSPEC_PRECEQ_W_PHL))] 288 1.1 mrg "ISA_HAS_DSP" 289 1.1 mrg "preceq.w.phl\t%0,%1" 290 1.3 mrg [(set_attr "type" "dspalu") 291 1.1 mrg (set_attr "mode" "SI")]) 292 1.1 mrg 293 1.1 mrg (define_insn "mips_preceq_w_phr" 294 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 295 1.1 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 296 1.1 mrg UNSPEC_PRECEQ_W_PHR))] 297 1.1 mrg "ISA_HAS_DSP" 298 1.1 mrg "preceq.w.phr\t%0,%1" 299 1.3 mrg [(set_attr "type" "dspalu") 300 1.1 mrg (set_attr "mode" "SI")]) 301 1.1 mrg 302 1.1 mrg ;; PRECEQU* 303 1.1 mrg (define_insn "mips_precequ_ph_qbl" 304 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 305 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 306 1.1 mrg UNSPEC_PRECEQU_PH_QBL))] 307 1.1 mrg "ISA_HAS_DSP" 308 1.1 mrg "precequ.ph.qbl\t%0,%1" 309 1.3 mrg [(set_attr "type" "dspalu") 310 1.1 mrg (set_attr "mode" "SI")]) 311 1.1 mrg 312 1.1 mrg (define_insn "mips_precequ_ph_qbr" 313 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 314 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 315 1.1 mrg UNSPEC_PRECEQU_PH_QBR))] 316 1.1 mrg "ISA_HAS_DSP" 317 1.1 mrg "precequ.ph.qbr\t%0,%1" 318 1.3 mrg [(set_attr "type" "dspalu") 319 1.1 mrg (set_attr "mode" "SI")]) 320 1.1 mrg 321 1.1 mrg (define_insn "mips_precequ_ph_qbla" 322 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 323 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 324 1.1 mrg UNSPEC_PRECEQU_PH_QBLA))] 325 1.1 mrg "ISA_HAS_DSP" 326 1.1 mrg "precequ.ph.qbla\t%0,%1" 327 1.3 mrg [(set_attr "type" "dspalu") 328 1.1 mrg (set_attr "mode" "SI")]) 329 1.1 mrg 330 1.1 mrg (define_insn "mips_precequ_ph_qbra" 331 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 332 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 333 1.1 mrg UNSPEC_PRECEQU_PH_QBRA))] 334 1.1 mrg "ISA_HAS_DSP" 335 1.1 mrg "precequ.ph.qbra\t%0,%1" 336 1.3 mrg [(set_attr "type" "dspalu") 337 1.1 mrg (set_attr "mode" "SI")]) 338 1.1 mrg 339 1.1 mrg ;; PRECEU* 340 1.1 mrg (define_insn "mips_preceu_ph_qbl" 341 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 342 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 343 1.1 mrg UNSPEC_PRECEU_PH_QBL))] 344 1.1 mrg "ISA_HAS_DSP" 345 1.1 mrg "preceu.ph.qbl\t%0,%1" 346 1.3 mrg [(set_attr "type" "dspalu") 347 1.1 mrg (set_attr "mode" "SI")]) 348 1.1 mrg 349 1.1 mrg (define_insn "mips_preceu_ph_qbr" 350 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 351 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 352 1.1 mrg UNSPEC_PRECEU_PH_QBR))] 353 1.1 mrg "ISA_HAS_DSP" 354 1.1 mrg "preceu.ph.qbr\t%0,%1" 355 1.3 mrg [(set_attr "type" "dspalu") 356 1.1 mrg (set_attr "mode" "SI")]) 357 1.1 mrg 358 1.1 mrg (define_insn "mips_preceu_ph_qbla" 359 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 360 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 361 1.1 mrg UNSPEC_PRECEU_PH_QBLA))] 362 1.1 mrg "ISA_HAS_DSP" 363 1.1 mrg "preceu.ph.qbla\t%0,%1" 364 1.3 mrg [(set_attr "type" "dspalu") 365 1.1 mrg (set_attr "mode" "SI")]) 366 1.1 mrg 367 1.1 mrg (define_insn "mips_preceu_ph_qbra" 368 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 369 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 370 1.1 mrg UNSPEC_PRECEU_PH_QBRA))] 371 1.1 mrg "ISA_HAS_DSP" 372 1.1 mrg "preceu.ph.qbra\t%0,%1" 373 1.3 mrg [(set_attr "type" "dspalu") 374 1.1 mrg (set_attr "mode" "SI")]) 375 1.1 mrg 376 1.1 mrg ;; Table 2-2. MIPS DSP ASE Instructions: Shift 377 1.1 mrg ;; SHLL* 378 1.1 mrg (define_insn "mips_shll_<DSPV:dspfmt2>" 379 1.5 mrg [(set (match_operand:DSPV 0 "register_operand" "=d,d") 380 1.5 mrg (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") 381 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d")] 382 1.5 mrg UNSPEC_SHLL)) 383 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 384 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))] 385 1.1 mrg "ISA_HAS_DSP" 386 1.1 mrg { 387 1.1 mrg if (which_alternative == 0) 388 1.1 mrg { 389 1.1 mrg if (INTVAL (operands[2]) 390 1.1 mrg & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>) 391 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>); 392 1.1 mrg return "shll.<DSPV:dspfmt2>\t%0,%1,%2"; 393 1.1 mrg } 394 1.1 mrg return "shllv.<DSPV:dspfmt2>\t%0,%1,%2"; 395 1.1 mrg } 396 1.3 mrg [(set_attr "type" "dspalu") 397 1.1 mrg (set_attr "mode" "SI")]) 398 1.1 mrg 399 1.1 mrg (define_insn "mips_shll_s_<DSPQ:dspfmt2>" 400 1.5 mrg [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 401 1.5 mrg (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 402 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d")] 403 1.5 mrg UNSPEC_SHLL_S)) 404 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 405 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))] 406 1.1 mrg "ISA_HAS_DSP" 407 1.1 mrg { 408 1.1 mrg if (which_alternative == 0) 409 1.1 mrg { 410 1.1 mrg if (INTVAL (operands[2]) 411 1.1 mrg & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 412 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 413 1.1 mrg return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 414 1.1 mrg } 415 1.1 mrg return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 416 1.1 mrg } 417 1.3 mrg [(set_attr "type" "dspalusat") 418 1.1 mrg (set_attr "mode" "SI")]) 419 1.1 mrg 420 1.1 mrg ;; SHRL* 421 1.1 mrg (define_insn "mips_shrl_qb" 422 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d,d") 423 1.1 mrg (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") 424 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 425 1.1 mrg UNSPEC_SHRL_QB))] 426 1.1 mrg "ISA_HAS_DSP" 427 1.1 mrg { 428 1.1 mrg if (which_alternative == 0) 429 1.1 mrg { 430 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7) 431 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7); 432 1.1 mrg return "shrl.qb\t%0,%1,%2"; 433 1.1 mrg } 434 1.1 mrg return "shrlv.qb\t%0,%1,%2"; 435 1.1 mrg } 436 1.3 mrg [(set_attr "type" "dspalu") 437 1.1 mrg (set_attr "mode" "SI")]) 438 1.1 mrg 439 1.1 mrg ;; SHRA* 440 1.1 mrg (define_insn "mips_shra_ph" 441 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d,d") 442 1.1 mrg (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") 443 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 444 1.1 mrg UNSPEC_SHRA_PH))] 445 1.1 mrg "ISA_HAS_DSP" 446 1.1 mrg { 447 1.1 mrg if (which_alternative == 0) 448 1.1 mrg { 449 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf) 450 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf); 451 1.1 mrg return "shra.ph\t%0,%1,%2"; 452 1.1 mrg } 453 1.1 mrg return "shrav.ph\t%0,%1,%2"; 454 1.1 mrg } 455 1.3 mrg [(set_attr "type" "dspalu") 456 1.1 mrg (set_attr "mode" "SI")]) 457 1.1 mrg 458 1.1 mrg (define_insn "mips_shra_r_<DSPQ:dspfmt2>" 459 1.1 mrg [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 460 1.1 mrg (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 461 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 462 1.1 mrg UNSPEC_SHRA_R))] 463 1.1 mrg "ISA_HAS_DSP" 464 1.1 mrg { 465 1.1 mrg if (which_alternative == 0) 466 1.1 mrg { 467 1.1 mrg if (INTVAL (operands[2]) 468 1.1 mrg & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 469 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 470 1.1 mrg return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 471 1.1 mrg } 472 1.1 mrg return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 473 1.1 mrg } 474 1.3 mrg [(set_attr "type" "dspalu") 475 1.1 mrg (set_attr "mode" "SI")]) 476 1.1 mrg 477 1.1 mrg ;; Table 2-3. MIPS DSP ASE Instructions: Multiply 478 1.1 mrg ;; MULEU* 479 1.1 mrg (define_insn "mips_muleu_s_ph_qbl" 480 1.5 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 481 1.5 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 482 1.5 mrg (match_operand:V2HI 2 "register_operand" "d")] 483 1.5 mrg UNSPEC_MULEU_S_PH_QBL)) 484 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 485 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) 486 1.5 mrg (clobber (match_scratch:DI 3 "=x"))] 487 1.1 mrg "ISA_HAS_DSP" 488 1.1 mrg "muleu_s.ph.qbl\t%0,%1,%2" 489 1.1 mrg [(set_attr "type" "imul3") 490 1.1 mrg (set_attr "mode" "SI")]) 491 1.1 mrg 492 1.1 mrg (define_insn "mips_muleu_s_ph_qbr" 493 1.5 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 494 1.5 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 495 1.5 mrg (match_operand:V2HI 2 "register_operand" "d")] 496 1.5 mrg UNSPEC_MULEU_S_PH_QBR)) 497 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 498 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) 499 1.5 mrg (clobber (match_scratch:DI 3 "=x"))] 500 1.1 mrg "ISA_HAS_DSP" 501 1.1 mrg "muleu_s.ph.qbr\t%0,%1,%2" 502 1.1 mrg [(set_attr "type" "imul3") 503 1.1 mrg (set_attr "mode" "SI")]) 504 1.1 mrg 505 1.1 mrg ;; MULQ* 506 1.1 mrg (define_insn "mips_mulq_rs_ph" 507 1.5 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 508 1.5 mrg (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 509 1.5 mrg (match_operand:V2HI 2 "register_operand" "d")] 510 1.5 mrg UNSPEC_MULQ_RS_PH)) 511 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 512 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) 513 1.5 mrg (clobber (match_scratch:DI 3 "=x"))] 514 1.1 mrg "ISA_HAS_DSP" 515 1.1 mrg "mulq_rs.ph\t%0,%1,%2" 516 1.1 mrg [(set_attr "type" "imul3") 517 1.1 mrg (set_attr "mode" "SI")]) 518 1.1 mrg 519 1.1 mrg ;; MULEQ* 520 1.1 mrg (define_insn "mips_muleq_s_w_phl" 521 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d") 522 1.5 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 523 1.5 mrg (match_operand:V2HI 2 "register_operand" "d")] 524 1.5 mrg UNSPEC_MULEQ_S_W_PHL)) 525 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 526 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) 527 1.5 mrg (clobber (match_scratch:DI 3 "=x"))] 528 1.1 mrg "ISA_HAS_DSP" 529 1.1 mrg "muleq_s.w.phl\t%0,%1,%2" 530 1.1 mrg [(set_attr "type" "imul3") 531 1.1 mrg (set_attr "mode" "SI")]) 532 1.1 mrg 533 1.1 mrg (define_insn "mips_muleq_s_w_phr" 534 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d") 535 1.5 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 536 1.5 mrg (match_operand:V2HI 2 "register_operand" "d")] 537 1.5 mrg UNSPEC_MULEQ_S_W_PHR)) 538 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 539 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) 540 1.5 mrg (clobber (match_scratch:DI 3 "=x"))] 541 1.1 mrg "ISA_HAS_DSP" 542 1.1 mrg "muleq_s.w.phr\t%0,%1,%2" 543 1.1 mrg [(set_attr "type" "imul3") 544 1.1 mrg (set_attr "mode" "SI")]) 545 1.1 mrg 546 1.1 mrg ;; DPAU* 547 1.1 mrg (define_insn "mips_dpau_h_qbl" 548 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 549 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 550 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 551 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 552 1.1 mrg UNSPEC_DPAU_H_QBL))] 553 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 554 1.1 mrg "dpau.h.qbl\t%q0,%2,%3" 555 1.3 mrg [(set_attr "type" "dspmac") 556 1.3 mrg (set_attr "accum_in" "1") 557 1.1 mrg (set_attr "mode" "SI")]) 558 1.1 mrg 559 1.1 mrg (define_insn "mips_dpau_h_qbr" 560 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 561 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 562 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 563 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 564 1.1 mrg UNSPEC_DPAU_H_QBR))] 565 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 566 1.1 mrg "dpau.h.qbr\t%q0,%2,%3" 567 1.3 mrg [(set_attr "type" "dspmac") 568 1.3 mrg (set_attr "accum_in" "1") 569 1.1 mrg (set_attr "mode" "SI")]) 570 1.1 mrg 571 1.1 mrg ;; DPSU* 572 1.1 mrg (define_insn "mips_dpsu_h_qbl" 573 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 574 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 575 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 576 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 577 1.1 mrg UNSPEC_DPSU_H_QBL))] 578 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 579 1.1 mrg "dpsu.h.qbl\t%q0,%2,%3" 580 1.3 mrg [(set_attr "type" "dspmac") 581 1.3 mrg (set_attr "accum_in" "1") 582 1.1 mrg (set_attr "mode" "SI")]) 583 1.1 mrg 584 1.1 mrg (define_insn "mips_dpsu_h_qbr" 585 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 586 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 587 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 588 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 589 1.1 mrg UNSPEC_DPSU_H_QBR))] 590 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 591 1.1 mrg "dpsu.h.qbr\t%q0,%2,%3" 592 1.3 mrg [(set_attr "type" "dspmac") 593 1.3 mrg (set_attr "accum_in" "1") 594 1.1 mrg (set_attr "mode" "SI")]) 595 1.1 mrg 596 1.1 mrg ;; DPAQ* 597 1.1 mrg (define_insn "mips_dpaq_s_w_ph" 598 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 599 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 600 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 601 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 602 1.5 mrg UNSPEC_DPAQ_S_W_PH)) 603 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 604 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 605 1.5 mrg UNSPEC_DPAQ_S_W_PH))] 606 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 607 1.1 mrg "dpaq_s.w.ph\t%q0,%2,%3" 608 1.3 mrg [(set_attr "type" "dspmac") 609 1.3 mrg (set_attr "accum_in" "1") 610 1.1 mrg (set_attr "mode" "SI")]) 611 1.1 mrg 612 1.1 mrg ;; DPSQ* 613 1.1 mrg (define_insn "mips_dpsq_s_w_ph" 614 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 615 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 616 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 617 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 618 1.5 mrg UNSPEC_DPSQ_S_W_PH)) 619 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 620 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 621 1.5 mrg UNSPEC_DPSQ_S_W_PH))] 622 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 623 1.1 mrg "dpsq_s.w.ph\t%q0,%2,%3" 624 1.3 mrg [(set_attr "type" "dspmac") 625 1.3 mrg (set_attr "accum_in" "1") 626 1.1 mrg (set_attr "mode" "SI")]) 627 1.1 mrg 628 1.1 mrg ;; MULSAQ* 629 1.1 mrg (define_insn "mips_mulsaq_s_w_ph" 630 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 631 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 632 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 633 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 634 1.5 mrg UNSPEC_MULSAQ_S_W_PH)) 635 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 636 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 637 1.5 mrg UNSPEC_MULSAQ_S_W_PH))] 638 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 639 1.1 mrg "mulsaq_s.w.ph\t%q0,%2,%3" 640 1.3 mrg [(set_attr "type" "dspmac") 641 1.3 mrg (set_attr "accum_in" "1") 642 1.1 mrg (set_attr "mode" "SI")]) 643 1.1 mrg 644 1.1 mrg ;; DPAQ* 645 1.1 mrg (define_insn "mips_dpaq_sa_l_w" 646 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 647 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 648 1.5 mrg (match_operand:SI 2 "register_operand" "d") 649 1.5 mrg (match_operand:SI 3 "register_operand" "d")] 650 1.5 mrg UNSPEC_DPAQ_SA_L_W)) 651 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 652 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 653 1.5 mrg UNSPEC_DPAQ_SA_L_W))] 654 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 655 1.1 mrg "dpaq_sa.l.w\t%q0,%2,%3" 656 1.3 mrg [(set_attr "type" "dspmacsat") 657 1.3 mrg (set_attr "accum_in" "1") 658 1.1 mrg (set_attr "mode" "SI")]) 659 1.1 mrg 660 1.1 mrg ;; DPSQ* 661 1.1 mrg (define_insn "mips_dpsq_sa_l_w" 662 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 663 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 664 1.5 mrg (match_operand:SI 2 "register_operand" "d") 665 1.5 mrg (match_operand:SI 3 "register_operand" "d")] 666 1.5 mrg UNSPEC_DPSQ_SA_L_W)) 667 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 668 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 669 1.5 mrg UNSPEC_DPSQ_SA_L_W))] 670 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 671 1.1 mrg "dpsq_sa.l.w\t%q0,%2,%3" 672 1.3 mrg [(set_attr "type" "dspmacsat") 673 1.3 mrg (set_attr "accum_in" "1") 674 1.1 mrg (set_attr "mode" "SI")]) 675 1.1 mrg 676 1.1 mrg ;; MAQ* 677 1.1 mrg (define_insn "mips_maq_s_w_phl" 678 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 679 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 680 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 681 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 682 1.5 mrg UNSPEC_MAQ_S_W_PHL)) 683 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 684 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 685 1.5 mrg UNSPEC_MAQ_S_W_PHL))] 686 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 687 1.1 mrg "maq_s.w.phl\t%q0,%2,%3" 688 1.3 mrg [(set_attr "type" "dspmac") 689 1.3 mrg (set_attr "accum_in" "1") 690 1.1 mrg (set_attr "mode" "SI")]) 691 1.1 mrg 692 1.1 mrg (define_insn "mips_maq_s_w_phr" 693 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 694 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 695 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 696 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 697 1.5 mrg UNSPEC_MAQ_S_W_PHR)) 698 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 699 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 700 1.5 mrg UNSPEC_MAQ_S_W_PHR))] 701 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 702 1.1 mrg "maq_s.w.phr\t%q0,%2,%3" 703 1.3 mrg [(set_attr "type" "dspmac") 704 1.3 mrg (set_attr "accum_in" "1") 705 1.1 mrg (set_attr "mode" "SI")]) 706 1.1 mrg 707 1.1 mrg ;; MAQ_SA* 708 1.1 mrg (define_insn "mips_maq_sa_w_phl" 709 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 710 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 711 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 712 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 713 1.5 mrg UNSPEC_MAQ_SA_W_PHL)) 714 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 715 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 716 1.5 mrg UNSPEC_MAQ_SA_W_PHL))] 717 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 718 1.1 mrg "maq_sa.w.phl\t%q0,%2,%3" 719 1.3 mrg [(set_attr "type" "dspmacsat") 720 1.3 mrg (set_attr "accum_in" "1") 721 1.1 mrg (set_attr "mode" "SI")]) 722 1.1 mrg 723 1.1 mrg (define_insn "mips_maq_sa_w_phr" 724 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 725 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 726 1.5 mrg (match_operand:V2HI 2 "register_operand" "d") 727 1.5 mrg (match_operand:V2HI 3 "register_operand" "d")] 728 1.5 mrg UNSPEC_MAQ_SA_W_PHR)) 729 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 730 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 731 1.5 mrg UNSPEC_MAQ_SA_W_PHR))] 732 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 733 1.1 mrg "maq_sa.w.phr\t%q0,%2,%3" 734 1.3 mrg [(set_attr "type" "dspmacsat") 735 1.3 mrg (set_attr "accum_in" "1") 736 1.1 mrg (set_attr "mode" "SI")]) 737 1.1 mrg 738 1.1 mrg ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation 739 1.1 mrg ;; BITREV 740 1.1 mrg (define_insn "mips_bitrev" 741 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 742 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d")] 743 1.1 mrg UNSPEC_BITREV))] 744 1.1 mrg "ISA_HAS_DSP" 745 1.1 mrg "bitrev\t%0,%1" 746 1.3 mrg [(set_attr "type" "dspalu") 747 1.1 mrg (set_attr "mode" "SI")]) 748 1.1 mrg 749 1.1 mrg ;; INSV 750 1.1 mrg (define_insn "mips_insv" 751 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 752 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "0") 753 1.1 mrg (match_operand:SI 2 "register_operand" "d") 754 1.1 mrg (reg:CCDSP CCDSP_SC_REGNUM) 755 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 756 1.1 mrg UNSPEC_INSV))] 757 1.1 mrg "ISA_HAS_DSP" 758 1.1 mrg "insv\t%0,%2" 759 1.3 mrg [(set_attr "type" "dspalu") 760 1.1 mrg (set_attr "mode" "SI")]) 761 1.1 mrg 762 1.1 mrg ;; REPL* 763 1.1 mrg (define_insn "mips_repl_qb" 764 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d,d") 765 1.1 mrg (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] 766 1.1 mrg UNSPEC_REPL_QB))] 767 1.1 mrg "ISA_HAS_DSP" 768 1.1 mrg { 769 1.1 mrg if (which_alternative == 0) 770 1.1 mrg { 771 1.1 mrg if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff) 772 1.1 mrg operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); 773 1.1 mrg return "repl.qb\t%0,%1"; 774 1.1 mrg } 775 1.1 mrg return "replv.qb\t%0,%1"; 776 1.1 mrg } 777 1.3 mrg [(set_attr "type" "dspalu") 778 1.1 mrg (set_attr "mode" "SI")]) 779 1.1 mrg 780 1.1 mrg (define_insn "mips_repl_ph" 781 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d,d") 782 1.1 mrg (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] 783 1.1 mrg UNSPEC_REPL_PH))] 784 1.1 mrg "ISA_HAS_DSP" 785 1.1 mrg "@ 786 1.1 mrg repl.ph\t%0,%1 787 1.1 mrg replv.ph\t%0,%1" 788 1.3 mrg [(set_attr "type" "dspalu") 789 1.1 mrg (set_attr "mode" "SI")]) 790 1.1 mrg 791 1.1 mrg ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick 792 1.1 mrg ;; CMPU.* CMP.* 793 1.1 mrg (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>" 794 1.1 mrg [(set (reg:CCDSP CCDSP_CC_REGNUM) 795 1.1 mrg (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 796 1.1 mrg (match_operand:DSPV 1 "register_operand" "d") 797 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 798 1.1 mrg UNSPEC_CMP_EQ))] 799 1.1 mrg "ISA_HAS_DSP" 800 1.1 mrg "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1" 801 1.3 mrg [(set_attr "type" "dspalu") 802 1.1 mrg (set_attr "mode" "SI")]) 803 1.1 mrg 804 1.1 mrg (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>" 805 1.1 mrg [(set (reg:CCDSP CCDSP_CC_REGNUM) 806 1.1 mrg (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 807 1.1 mrg (match_operand:DSPV 1 "register_operand" "d") 808 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 809 1.1 mrg UNSPEC_CMP_LT))] 810 1.1 mrg "ISA_HAS_DSP" 811 1.1 mrg "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1" 812 1.3 mrg [(set_attr "type" "dspalu") 813 1.1 mrg (set_attr "mode" "SI")]) 814 1.1 mrg 815 1.1 mrg (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>" 816 1.1 mrg [(set (reg:CCDSP CCDSP_CC_REGNUM) 817 1.1 mrg (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 818 1.1 mrg (match_operand:DSPV 1 "register_operand" "d") 819 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 820 1.1 mrg UNSPEC_CMP_LE))] 821 1.1 mrg "ISA_HAS_DSP" 822 1.1 mrg "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1" 823 1.3 mrg [(set_attr "type" "dspalu") 824 1.1 mrg (set_attr "mode" "SI")]) 825 1.1 mrg 826 1.1 mrg (define_insn "mips_cmpgu_eq_qb" 827 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 828 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 829 1.1 mrg (match_operand:V4QI 2 "register_operand" "d")] 830 1.1 mrg UNSPEC_CMPGU_EQ_QB))] 831 1.1 mrg "ISA_HAS_DSP" 832 1.1 mrg "cmpgu.eq.qb\t%0,%1,%2" 833 1.3 mrg [(set_attr "type" "dspalu") 834 1.1 mrg (set_attr "mode" "SI")]) 835 1.1 mrg 836 1.1 mrg (define_insn "mips_cmpgu_lt_qb" 837 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 838 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 839 1.1 mrg (match_operand:V4QI 2 "register_operand" "d")] 840 1.1 mrg UNSPEC_CMPGU_LT_QB))] 841 1.1 mrg "ISA_HAS_DSP" 842 1.1 mrg "cmpgu.lt.qb\t%0,%1,%2" 843 1.3 mrg [(set_attr "type" "dspalu") 844 1.1 mrg (set_attr "mode" "SI")]) 845 1.1 mrg 846 1.1 mrg (define_insn "mips_cmpgu_le_qb" 847 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 848 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 849 1.1 mrg (match_operand:V4QI 2 "register_operand" "d")] 850 1.1 mrg UNSPEC_CMPGU_LE_QB))] 851 1.1 mrg "ISA_HAS_DSP" 852 1.1 mrg "cmpgu.le.qb\t%0,%1,%2" 853 1.3 mrg [(set_attr "type" "dspalu") 854 1.1 mrg (set_attr "mode" "SI")]) 855 1.1 mrg 856 1.1 mrg ;; PICK* 857 1.1 mrg (define_insn "mips_pick_<DSPV:dspfmt2>" 858 1.1 mrg [(set (match_operand:DSPV 0 "register_operand" "=d") 859 1.1 mrg (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d") 860 1.1 mrg (match_operand:DSPV 2 "register_operand" "d") 861 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 862 1.1 mrg UNSPEC_PICK))] 863 1.1 mrg "ISA_HAS_DSP" 864 1.1 mrg "pick.<DSPV:dspfmt2>\t%0,%1,%2" 865 1.3 mrg [(set_attr "type" "dspalu") 866 1.1 mrg (set_attr "mode" "SI")]) 867 1.1 mrg 868 1.1 mrg ;; PACKRL* 869 1.1 mrg (define_insn "mips_packrl_ph" 870 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 871 1.1 mrg (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 872 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 873 1.1 mrg UNSPEC_PACKRL_PH))] 874 1.1 mrg "ISA_HAS_DSP" 875 1.1 mrg "packrl.ph\t%0,%1,%2" 876 1.3 mrg [(set_attr "type" "dspalu") 877 1.1 mrg (set_attr "mode" "SI")]) 878 1.1 mrg 879 1.1 mrg ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access 880 1.1 mrg ;; EXTR* 881 1.1 mrg (define_insn "mips_extr_w" 882 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 883 1.5 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 884 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d")] 885 1.5 mrg UNSPEC_EXTR_W)) 886 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 887 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))] 888 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 889 1.1 mrg { 890 1.1 mrg if (which_alternative == 0) 891 1.1 mrg { 892 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 893 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 894 1.1 mrg return "extr.w\t%0,%q1,%2"; 895 1.1 mrg } 896 1.1 mrg return "extrv.w\t%0,%q1,%2"; 897 1.1 mrg } 898 1.3 mrg [(set_attr "type" "accext") 899 1.1 mrg (set_attr "mode" "SI")]) 900 1.1 mrg 901 1.1 mrg (define_insn "mips_extr_r_w" 902 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 903 1.5 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 904 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d")] 905 1.5 mrg UNSPEC_EXTR_R_W)) 906 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 907 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))] 908 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 909 1.1 mrg { 910 1.1 mrg if (which_alternative == 0) 911 1.1 mrg { 912 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 913 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 914 1.1 mrg return "extr_r.w\t%0,%q1,%2"; 915 1.1 mrg } 916 1.1 mrg return "extrv_r.w\t%0,%q1,%2"; 917 1.1 mrg } 918 1.3 mrg [(set_attr "type" "accext") 919 1.1 mrg (set_attr "mode" "SI")]) 920 1.1 mrg 921 1.1 mrg (define_insn "mips_extr_rs_w" 922 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 923 1.5 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 924 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d")] 925 1.5 mrg UNSPEC_EXTR_RS_W)) 926 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 927 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))] 928 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 929 1.1 mrg { 930 1.1 mrg if (which_alternative == 0) 931 1.1 mrg { 932 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 933 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 934 1.1 mrg return "extr_rs.w\t%0,%q1,%2"; 935 1.1 mrg } 936 1.1 mrg return "extrv_rs.w\t%0,%q1,%2"; 937 1.1 mrg } 938 1.3 mrg [(set_attr "type" "accext") 939 1.1 mrg (set_attr "mode" "SI")]) 940 1.1 mrg 941 1.1 mrg ;; EXTR*_S.H 942 1.1 mrg (define_insn "mips_extr_s_h" 943 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 944 1.5 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 945 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d")] 946 1.5 mrg UNSPEC_EXTR_S_H)) 947 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 948 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))] 949 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 950 1.1 mrg { 951 1.1 mrg if (which_alternative == 0) 952 1.1 mrg { 953 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 954 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 955 1.1 mrg return "extr_s.h\t%0,%q1,%2"; 956 1.1 mrg } 957 1.1 mrg return "extrv_s.h\t%0,%q1,%2"; 958 1.1 mrg } 959 1.3 mrg [(set_attr "type" "accext") 960 1.1 mrg (set_attr "mode" "SI")]) 961 1.1 mrg 962 1.1 mrg ;; EXTP* 963 1.1 mrg (define_insn "mips_extp" 964 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 965 1.5 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 966 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d") 967 1.5 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 968 1.5 mrg UNSPEC_EXTP)) 969 1.5 mrg (set (reg:CCDSP CCDSP_EF_REGNUM) 970 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))] 971 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 972 1.1 mrg { 973 1.1 mrg if (which_alternative == 0) 974 1.1 mrg { 975 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 976 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 977 1.1 mrg return "extp\t%0,%q1,%2"; 978 1.1 mrg } 979 1.1 mrg return "extpv\t%0,%q1,%2"; 980 1.1 mrg } 981 1.3 mrg [(set_attr "type" "accext") 982 1.1 mrg (set_attr "mode" "SI")]) 983 1.1 mrg 984 1.1 mrg (define_insn "mips_extpdp" 985 1.5 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 986 1.5 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 987 1.5 mrg (match_operand:SI 2 "arith_operand" "I,d") 988 1.5 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 989 1.5 mrg UNSPEC_EXTPDP)) 990 1.5 mrg (set (reg:CCDSP CCDSP_PO_REGNUM) 991 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) 992 1.5 mrg (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) 993 1.5 mrg (set (reg:CCDSP CCDSP_EF_REGNUM) 994 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))] 995 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 996 1.1 mrg { 997 1.1 mrg if (which_alternative == 0) 998 1.1 mrg { 999 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 1000 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 1001 1.1 mrg return "extpdp\t%0,%q1,%2"; 1002 1.1 mrg } 1003 1.1 mrg return "extpdpv\t%0,%q1,%2"; 1004 1.1 mrg } 1005 1.3 mrg [(set_attr "type" "accext") 1006 1.1 mrg (set_attr "mode" "SI")]) 1007 1.1 mrg 1008 1.1 mrg ;; SHILO* 1009 1.1 mrg (define_insn "mips_shilo" 1010 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a,a") 1011 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") 1012 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 1013 1.1 mrg UNSPEC_SHILO))] 1014 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 1015 1.1 mrg { 1016 1.1 mrg if (which_alternative == 0) 1017 1.1 mrg { 1018 1.1 mrg if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31) 1019 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 1020 1.1 mrg return "shilo\t%q0,%2"; 1021 1.1 mrg } 1022 1.1 mrg return "shilov\t%q0,%2"; 1023 1.1 mrg } 1024 1.3 mrg [(set_attr "type" "accmod") 1025 1.1 mrg (set_attr "mode" "SI")]) 1026 1.1 mrg 1027 1.1 mrg ;; MTHLIP* 1028 1.1 mrg (define_insn "mips_mthlip" 1029 1.5 mrg [(set (match_operand:DI 0 "register_operand" "=a") 1030 1.5 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 1031 1.5 mrg (match_operand:SI 2 "register_operand" "d") 1032 1.5 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 1033 1.5 mrg UNSPEC_MTHLIP)) 1034 1.5 mrg (set (reg:CCDSP CCDSP_PO_REGNUM) 1035 1.5 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) 1036 1.5 mrg (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))] 1037 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 1038 1.1 mrg "mthlip\t%2,%q0" 1039 1.3 mrg [(set_attr "type" "accmod") 1040 1.1 mrg (set_attr "mode" "SI")]) 1041 1.1 mrg 1042 1.1 mrg ;; WRDSP 1043 1.1 mrg (define_insn "mips_wrdsp" 1044 1.5 mrg [(set (reg:CCDSP CCDSP_PO_REGNUM) 1045 1.5 mrg (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") 1046 1.5 mrg (match_operand:SI 1 "const_uimm6_operand" "YA")] 1047 1.5 mrg UNSPEC_WRDSP)) 1048 1.5 mrg (set (reg:CCDSP CCDSP_SC_REGNUM) 1049 1.5 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1050 1.5 mrg (set (reg:CCDSP CCDSP_CA_REGNUM) 1051 1.5 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1052 1.5 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 1053 1.5 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1054 1.5 mrg (set (reg:CCDSP CCDSP_CC_REGNUM) 1055 1.5 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1056 1.5 mrg (set (reg:CCDSP CCDSP_EF_REGNUM) 1057 1.5 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))] 1058 1.1 mrg "ISA_HAS_DSP" 1059 1.1 mrg "wrdsp\t%0,%1" 1060 1.3 mrg [(set_attr "type" "dspalu") 1061 1.1 mrg (set_attr "mode" "SI")]) 1062 1.1 mrg 1063 1.1 mrg ;; RDDSP 1064 1.1 mrg (define_insn "mips_rddsp" 1065 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 1066 1.1 mrg (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA") 1067 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM) 1068 1.1 mrg (reg:CCDSP CCDSP_SC_REGNUM) 1069 1.1 mrg (reg:CCDSP CCDSP_CA_REGNUM) 1070 1.1 mrg (reg:CCDSP CCDSP_OU_REGNUM) 1071 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM) 1072 1.1 mrg (reg:CCDSP CCDSP_EF_REGNUM)] 1073 1.1 mrg UNSPEC_RDDSP))] 1074 1.1 mrg "ISA_HAS_DSP" 1075 1.1 mrg "rddsp\t%0,%1" 1076 1.3 mrg [(set_attr "type" "dspalu") 1077 1.1 mrg (set_attr "mode" "SI")]) 1078 1.1 mrg 1079 1.1 mrg ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load 1080 1.1 mrg ;; L*X 1081 1.1 mrg (define_expand "mips_lbux" 1082 1.1 mrg [(match_operand:SI 0 "register_operand") 1083 1.1 mrg (match_operand 1 "pmode_register_operand") 1084 1.1 mrg (match_operand:SI 2 "register_operand")] 1085 1.1 mrg "ISA_HAS_DSP" 1086 1.1 mrg { 1087 1.1 mrg operands[2] = convert_to_mode (Pmode, operands[2], false); 1088 1.3 mrg emit_insn (PMODE_INSN (gen_mips_lbux_extsi, 1089 1.3 mrg (operands[0], operands[1], operands[2]))); 1090 1.1 mrg DONE; 1091 1.1 mrg }) 1092 1.1 mrg 1093 1.3 mrg (define_insn "mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>" 1094 1.3 mrg [(set (match_operand:GPR 0 "register_operand" "=d") 1095 1.3 mrg (any_extend:GPR 1096 1.3 mrg (mem:SHORT (plus:P (match_operand:P 1 "register_operand" "d") 1097 1.3 mrg (match_operand:P 2 "register_operand" "d")))))] 1098 1.3 mrg "ISA_HAS_L<SHORT:SIZE><U>X" 1099 1.3 mrg "l<SHORT:size><u>x\t%0,%2(%1)" 1100 1.1 mrg [(set_attr "type" "load") 1101 1.5 mrg (set_attr "mode" "<GPR:MODE>")]) 1102 1.1 mrg 1103 1.1 mrg (define_expand "mips_lhx" 1104 1.1 mrg [(match_operand:SI 0 "register_operand") 1105 1.1 mrg (match_operand 1 "pmode_register_operand") 1106 1.1 mrg (match_operand:SI 2 "register_operand")] 1107 1.1 mrg "ISA_HAS_DSP" 1108 1.1 mrg { 1109 1.1 mrg operands[2] = convert_to_mode (Pmode, operands[2], false); 1110 1.3 mrg emit_insn (PMODE_INSN (gen_mips_lhx_extsi, 1111 1.3 mrg (operands[0], operands[1], operands[2]))); 1112 1.1 mrg DONE; 1113 1.1 mrg }) 1114 1.1 mrg 1115 1.3 mrg (define_expand "mips_l<size>x" 1116 1.3 mrg [(match_operand:GPR 0 "register_operand") 1117 1.1 mrg (match_operand 1 "pmode_register_operand") 1118 1.1 mrg (match_operand:SI 2 "register_operand")] 1119 1.1 mrg "ISA_HAS_DSP" 1120 1.1 mrg { 1121 1.1 mrg operands[2] = convert_to_mode (Pmode, operands[2], false); 1122 1.3 mrg emit_insn (PMODE_INSN (gen_mips_l<size>x, 1123 1.3 mrg (operands[0], operands[1], operands[2]))); 1124 1.1 mrg DONE; 1125 1.1 mrg }) 1126 1.1 mrg 1127 1.3 mrg (define_insn "mips_l<GPR:size>x_<P:mode>" 1128 1.3 mrg [(set (match_operand:GPR 0 "register_operand" "=d") 1129 1.3 mrg (mem:GPR (plus:P (match_operand:P 1 "register_operand" "d") 1130 1.3 mrg (match_operand:P 2 "register_operand" "d"))))] 1131 1.3 mrg "ISA_HAS_L<GPR:SIZE>X" 1132 1.3 mrg "l<GPR:size>x\t%0,%2(%1)" 1133 1.3 mrg [(set_attr "type" "load") 1134 1.5 mrg (set_attr "mode" "<GPR:MODE>")]) 1135 1.3 mrg 1136 1.3 mrg (define_insn "*mips_lw<u>x_<P:mode>_ext" 1137 1.3 mrg [(set (match_operand:DI 0 "register_operand" "=d") 1138 1.3 mrg (any_extend:DI 1139 1.3 mrg (mem:SI (plus:P (match_operand:P 1 "register_operand" "d") 1140 1.3 mrg (match_operand:P 2 "register_operand" "d")))))] 1141 1.3 mrg "ISA_HAS_LW<U>X && TARGET_64BIT" 1142 1.3 mrg "lw<u>x\t%0,%2(%1)" 1143 1.1 mrg [(set_attr "type" "load") 1144 1.5 mrg (set_attr "mode" "DI")]) 1145 1.1 mrg 1146 1.1 mrg ;; Table 2-8. MIPS DSP ASE Instructions: Branch 1147 1.1 mrg ;; BPOSGE32 1148 1.1 mrg (define_insn "mips_bposge" 1149 1.1 mrg [(set (pc) 1150 1.1 mrg (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM) 1151 1.1 mrg (match_operand:SI 1 "immediate_operand" "I")) 1152 1.1 mrg (label_ref (match_operand 0 "" "")) 1153 1.1 mrg (pc)))] 1154 1.1 mrg "ISA_HAS_DSP" 1155 1.1 mrg "%*bposge%1\t%0%/" 1156 1.1 mrg [(set_attr "type" "branch")]) 1157 1.1 mrg 1158 1.3 mrg (define_expand "mips_madd<u>" 1159 1.3 mrg [(set (match_operand:DI 0 "register_operand") 1160 1.3 mrg (plus:DI 1161 1.3 mrg (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) 1162 1.3 mrg (any_extend:DI (match_operand:SI 3 "register_operand"))) 1163 1.3 mrg (match_operand:DI 1 "register_operand")))] 1164 1.3 mrg "ISA_HAS_DSP && !TARGET_64BIT") 1165 1.3 mrg 1166 1.3 mrg (define_expand "mips_msub<u>" 1167 1.3 mrg [(set (match_operand:DI 0 "register_operand") 1168 1.3 mrg (minus:DI 1169 1.3 mrg (match_operand:DI 1 "register_operand") 1170 1.3 mrg (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) 1171 1.3 mrg (any_extend:DI (match_operand:SI 3 "register_operand")))))] 1172 1.3 mrg "ISA_HAS_DSP && !TARGET_64BIT") 1173
Indexes created Sat Jun 27 00:24:51 UTC 2026