mips-dsp.md revision 1.3
1 1.3 mrg ;; Copyright (C) 2005-2013 Free Software Foundation, Inc. 2 1.1 mrg ;; 3 1.1 mrg ;; This file is part of GCC. 4 1.1 mrg ;; 5 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify 6 1.1 mrg ;; it under the terms of the GNU General Public License as published by 7 1.1 mrg ;; the Free Software Foundation; either version 3, or (at your option) 8 1.1 mrg ;; any later version. 9 1.1 mrg ;; 10 1.1 mrg ;; GCC is distributed in the hope that it will be useful, 11 1.1 mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12 1.1 mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 1.1 mrg ;; GNU General Public License for more details. 14 1.1 mrg ;; 15 1.1 mrg ;; You should have received a copy of the GNU General Public License 16 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 17 1.1 mrg ;; <http://www.gnu.org/licenses/>. 18 1.1 mrg 19 1.3 mrg ;; MIPS DSP ASE Revision 0.98 3/24/2005 20 1.3 mrg (define_c_enum "unspec" [ 21 1.3 mrg UNSPEC_ADDQ 22 1.3 mrg UNSPEC_ADDQ_S 23 1.3 mrg UNSPEC_SUBQ 24 1.3 mrg UNSPEC_SUBQ_S 25 1.3 mrg UNSPEC_ADDSC 26 1.3 mrg UNSPEC_ADDWC 27 1.3 mrg UNSPEC_MODSUB 28 1.3 mrg UNSPEC_RADDU_W_QB 29 1.3 mrg UNSPEC_ABSQ_S 30 1.3 mrg UNSPEC_PRECRQ_QB_PH 31 1.3 mrg UNSPEC_PRECRQ_PH_W 32 1.3 mrg UNSPEC_PRECRQ_RS_PH_W 33 1.3 mrg UNSPEC_PRECRQU_S_QB_PH 34 1.3 mrg UNSPEC_PRECEQ_W_PHL 35 1.3 mrg UNSPEC_PRECEQ_W_PHR 36 1.3 mrg UNSPEC_PRECEQU_PH_QBL 37 1.3 mrg UNSPEC_PRECEQU_PH_QBR 38 1.3 mrg UNSPEC_PRECEQU_PH_QBLA 39 1.3 mrg UNSPEC_PRECEQU_PH_QBRA 40 1.3 mrg UNSPEC_PRECEU_PH_QBL 41 1.3 mrg UNSPEC_PRECEU_PH_QBR 42 1.3 mrg UNSPEC_PRECEU_PH_QBLA 43 1.3 mrg UNSPEC_PRECEU_PH_QBRA 44 1.3 mrg UNSPEC_SHLL 45 1.3 mrg UNSPEC_SHLL_S 46 1.3 mrg UNSPEC_SHRL_QB 47 1.3 mrg UNSPEC_SHRA_PH 48 1.3 mrg UNSPEC_SHRA_R 49 1.3 mrg UNSPEC_MULEU_S_PH_QBL 50 1.3 mrg UNSPEC_MULEU_S_PH_QBR 51 1.3 mrg UNSPEC_MULQ_RS_PH 52 1.3 mrg UNSPEC_MULEQ_S_W_PHL 53 1.3 mrg UNSPEC_MULEQ_S_W_PHR 54 1.3 mrg UNSPEC_DPAU_H_QBL 55 1.3 mrg UNSPEC_DPAU_H_QBR 56 1.3 mrg UNSPEC_DPSU_H_QBL 57 1.3 mrg UNSPEC_DPSU_H_QBR 58 1.3 mrg UNSPEC_DPAQ_S_W_PH 59 1.3 mrg UNSPEC_DPSQ_S_W_PH 60 1.3 mrg UNSPEC_MULSAQ_S_W_PH 61 1.3 mrg UNSPEC_DPAQ_SA_L_W 62 1.3 mrg UNSPEC_DPSQ_SA_L_W 63 1.3 mrg UNSPEC_MAQ_S_W_PHL 64 1.3 mrg UNSPEC_MAQ_S_W_PHR 65 1.3 mrg UNSPEC_MAQ_SA_W_PHL 66 1.3 mrg UNSPEC_MAQ_SA_W_PHR 67 1.3 mrg UNSPEC_BITREV 68 1.3 mrg UNSPEC_INSV 69 1.3 mrg UNSPEC_REPL_QB 70 1.3 mrg UNSPEC_REPL_PH 71 1.3 mrg UNSPEC_CMP_EQ 72 1.3 mrg UNSPEC_CMP_LT 73 1.3 mrg UNSPEC_CMP_LE 74 1.3 mrg UNSPEC_CMPGU_EQ_QB 75 1.3 mrg UNSPEC_CMPGU_LT_QB 76 1.3 mrg UNSPEC_CMPGU_LE_QB 77 1.3 mrg UNSPEC_PICK 78 1.3 mrg UNSPEC_PACKRL_PH 79 1.3 mrg UNSPEC_EXTR_W 80 1.3 mrg UNSPEC_EXTR_R_W 81 1.3 mrg UNSPEC_EXTR_RS_W 82 1.3 mrg UNSPEC_EXTR_S_H 83 1.3 mrg UNSPEC_EXTP 84 1.3 mrg UNSPEC_EXTPDP 85 1.3 mrg UNSPEC_SHILO 86 1.3 mrg UNSPEC_MTHLIP 87 1.3 mrg UNSPEC_WRDSP 88 1.3 mrg UNSPEC_RDDSP 89 1.3 mrg ]) 90 1.3 mrg 91 1.1 mrg (define_constants 92 1.1 mrg [(CCDSP_PO_REGNUM 182) 93 1.1 mrg (CCDSP_SC_REGNUM 183) 94 1.1 mrg (CCDSP_CA_REGNUM 184) 95 1.1 mrg (CCDSP_OU_REGNUM 185) 96 1.1 mrg (CCDSP_CC_REGNUM 186) 97 1.1 mrg (CCDSP_EF_REGNUM 187)]) 98 1.1 mrg 99 1.1 mrg ;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE. 100 1.1 mrg (define_mode_iterator DSP [(SI "ISA_HAS_DSP") 101 1.1 mrg (V2HI "ISA_HAS_DSP") 102 1.1 mrg (V4QI "ISA_HAS_DSP")]) 103 1.1 mrg 104 1.1 mrg ;; This mode iterator allows v2hi, v4qi for vector/SIMD data. 105 1.1 mrg (define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP") 106 1.1 mrg (V4QI "ISA_HAS_DSP")]) 107 1.1 mrg 108 1.1 mrg ;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data. 109 1.1 mrg (define_mode_iterator DSPQ [(SI "ISA_HAS_DSP") 110 1.1 mrg (V2HI "ISA_HAS_DSP")]) 111 1.1 mrg 112 1.1 mrg ;; DSP instructions use q for fixed-point data, and u for integer in the infix. 113 1.1 mrg (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) 114 1.1 mrg 115 1.1 mrg ;; DSP instructions use nothing for fixed-point data, and u for integer in 116 1.1 mrg ;; the infix. 117 1.1 mrg (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")]) 118 1.1 mrg 119 1.1 mrg ;; DSP instructions use w, ph, qb in the postfix. 120 1.1 mrg (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")]) 121 1.1 mrg 122 1.1 mrg ;; DSP shift masks for SI, V2HI, V4QI. 123 1.1 mrg (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")]) 124 1.1 mrg 125 1.1 mrg ;; MIPS DSP ASE Revision 0.98 3/24/2005 126 1.1 mrg ;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic 127 1.1 mrg ;; ADDQ* 128 1.1 mrg (define_insn "add<DSPV:mode>3" 129 1.1 mrg [(parallel 130 1.1 mrg [(set (match_operand:DSPV 0 "register_operand" "=d") 131 1.1 mrg (plus:DSPV (match_operand:DSPV 1 "register_operand" "d") 132 1.1 mrg (match_operand:DSPV 2 "register_operand" "d"))) 133 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 134 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] 135 1.3 mrg "ISA_HAS_DSP" 136 1.1 mrg "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 137 1.3 mrg [(set_attr "type" "dspalu") 138 1.1 mrg (set_attr "mode" "SI")]) 139 1.1 mrg 140 1.1 mrg (define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" 141 1.1 mrg [(parallel 142 1.1 mrg [(set (match_operand:DSP 0 "register_operand" "=d") 143 1.1 mrg (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 144 1.1 mrg (match_operand:DSP 2 "register_operand" "d")] 145 1.1 mrg UNSPEC_ADDQ_S)) 146 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 147 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] 148 1.3 mrg "ISA_HAS_DSP" 149 1.1 mrg "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 150 1.3 mrg [(set_attr "type" "dspalusat") 151 1.1 mrg (set_attr "mode" "SI")]) 152 1.1 mrg 153 1.1 mrg ;; SUBQ* 154 1.1 mrg (define_insn "sub<DSPV:mode>3" 155 1.1 mrg [(parallel 156 1.1 mrg [(set (match_operand:DSPV 0 "register_operand" "=d") 157 1.1 mrg (minus:DSPV (match_operand:DSPV 1 "register_operand" "d") 158 1.1 mrg (match_operand:DSPV 2 "register_operand" "d"))) 159 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 160 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] 161 1.1 mrg "ISA_HAS_DSP" 162 1.1 mrg "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 163 1.3 mrg [(set_attr "type" "dspalu") 164 1.1 mrg (set_attr "mode" "SI")]) 165 1.1 mrg 166 1.1 mrg (define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" 167 1.1 mrg [(parallel 168 1.1 mrg [(set (match_operand:DSP 0 "register_operand" "=d") 169 1.1 mrg (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 170 1.1 mrg (match_operand:DSP 2 "register_operand" "d")] 171 1.1 mrg UNSPEC_SUBQ_S)) 172 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 173 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] 174 1.1 mrg "ISA_HAS_DSP" 175 1.1 mrg "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 176 1.3 mrg [(set_attr "type" "dspalusat") 177 1.1 mrg (set_attr "mode" "SI")]) 178 1.1 mrg 179 1.1 mrg ;; ADDSC 180 1.1 mrg (define_insn "mips_addsc" 181 1.1 mrg [(parallel 182 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 183 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d") 184 1.1 mrg (match_operand:SI 2 "register_operand" "d")] 185 1.1 mrg UNSPEC_ADDSC)) 186 1.1 mrg (set (reg:CCDSP CCDSP_CA_REGNUM) 187 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] 188 1.1 mrg "ISA_HAS_DSP" 189 1.1 mrg "addsc\t%0,%1,%2" 190 1.3 mrg [(set_attr "type" "dspalu") 191 1.1 mrg (set_attr "mode" "SI")]) 192 1.1 mrg 193 1.1 mrg ;; ADDWC 194 1.1 mrg (define_insn "mips_addwc" 195 1.1 mrg [(parallel 196 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 197 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d") 198 1.1 mrg (match_operand:SI 2 "register_operand" "d") 199 1.1 mrg (reg:CCDSP CCDSP_CA_REGNUM)] 200 1.1 mrg UNSPEC_ADDWC)) 201 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 202 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] 203 1.1 mrg "ISA_HAS_DSP" 204 1.1 mrg "addwc\t%0,%1,%2" 205 1.3 mrg [(set_attr "type" "dspalu") 206 1.1 mrg (set_attr "mode" "SI")]) 207 1.1 mrg 208 1.1 mrg ;; MODSUB 209 1.1 mrg (define_insn "mips_modsub" 210 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 211 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d") 212 1.1 mrg (match_operand:SI 2 "register_operand" "d")] 213 1.1 mrg UNSPEC_MODSUB))] 214 1.1 mrg "ISA_HAS_DSP" 215 1.1 mrg "modsub\t%0,%1,%2" 216 1.3 mrg [(set_attr "type" "dspalu") 217 1.1 mrg (set_attr "mode" "SI")]) 218 1.1 mrg 219 1.1 mrg ;; RADDU* 220 1.1 mrg (define_insn "mips_raddu_w_qb" 221 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 222 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] 223 1.1 mrg UNSPEC_RADDU_W_QB))] 224 1.1 mrg "ISA_HAS_DSP" 225 1.1 mrg "raddu.w.qb\t%0,%1" 226 1.3 mrg [(set_attr "type" "dspalu") 227 1.1 mrg (set_attr "mode" "SI")]) 228 1.1 mrg 229 1.1 mrg ;; ABSQ* 230 1.1 mrg (define_insn "mips_absq_s_<DSPQ:dspfmt2>" 231 1.1 mrg [(parallel 232 1.1 mrg [(set (match_operand:DSPQ 0 "register_operand" "=d") 233 1.1 mrg (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] 234 1.1 mrg UNSPEC_ABSQ_S)) 235 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 236 1.1 mrg (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] 237 1.1 mrg "ISA_HAS_DSP" 238 1.1 mrg "absq_s.<DSPQ:dspfmt2>\t%0,%1" 239 1.3 mrg [(set_attr "type" "dspalusat") 240 1.1 mrg (set_attr "mode" "SI")]) 241 1.1 mrg 242 1.1 mrg ;; PRECRQ* 243 1.1 mrg (define_insn "mips_precrq_qb_ph" 244 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d") 245 1.1 mrg (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 246 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 247 1.1 mrg UNSPEC_PRECRQ_QB_PH))] 248 1.1 mrg "ISA_HAS_DSP" 249 1.1 mrg "precrq.qb.ph\t%0,%1,%2" 250 1.3 mrg [(set_attr "type" "dspalu") 251 1.1 mrg (set_attr "mode" "SI")]) 252 1.1 mrg 253 1.1 mrg (define_insn "mips_precrq_ph_w" 254 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 255 1.1 mrg (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 256 1.1 mrg (match_operand:SI 2 "register_operand" "d")] 257 1.1 mrg UNSPEC_PRECRQ_PH_W))] 258 1.1 mrg "ISA_HAS_DSP" 259 1.1 mrg "precrq.ph.w\t%0,%1,%2" 260 1.3 mrg [(set_attr "type" "dspalu") 261 1.1 mrg (set_attr "mode" "SI")]) 262 1.1 mrg 263 1.1 mrg (define_insn "mips_precrq_rs_ph_w" 264 1.1 mrg [(parallel 265 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 266 1.1 mrg (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 267 1.1 mrg (match_operand:SI 2 "register_operand" "d")] 268 1.1 mrg UNSPEC_PRECRQ_RS_PH_W)) 269 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 270 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] 271 1.1 mrg UNSPEC_PRECRQ_RS_PH_W))])] 272 1.1 mrg "ISA_HAS_DSP" 273 1.1 mrg "precrq_rs.ph.w\t%0,%1,%2" 274 1.3 mrg [(set_attr "type" "dspalu") 275 1.1 mrg (set_attr "mode" "SI")]) 276 1.1 mrg 277 1.1 mrg ;; PRECRQU* 278 1.1 mrg (define_insn "mips_precrqu_s_qb_ph" 279 1.1 mrg [(parallel 280 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d") 281 1.1 mrg (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 282 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 283 1.1 mrg UNSPEC_PRECRQU_S_QB_PH)) 284 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 285 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] 286 1.1 mrg UNSPEC_PRECRQU_S_QB_PH))])] 287 1.1 mrg "ISA_HAS_DSP" 288 1.1 mrg "precrqu_s.qb.ph\t%0,%1,%2" 289 1.3 mrg [(set_attr "type" "dspalusat") 290 1.1 mrg (set_attr "mode" "SI")]) 291 1.1 mrg 292 1.1 mrg ;; PRECEQ* 293 1.1 mrg (define_insn "mips_preceq_w_phl" 294 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 295 1.1 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 296 1.1 mrg UNSPEC_PRECEQ_W_PHL))] 297 1.1 mrg "ISA_HAS_DSP" 298 1.1 mrg "preceq.w.phl\t%0,%1" 299 1.3 mrg [(set_attr "type" "dspalu") 300 1.1 mrg (set_attr "mode" "SI")]) 301 1.1 mrg 302 1.1 mrg (define_insn "mips_preceq_w_phr" 303 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 304 1.1 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 305 1.1 mrg UNSPEC_PRECEQ_W_PHR))] 306 1.1 mrg "ISA_HAS_DSP" 307 1.1 mrg "preceq.w.phr\t%0,%1" 308 1.3 mrg [(set_attr "type" "dspalu") 309 1.1 mrg (set_attr "mode" "SI")]) 310 1.1 mrg 311 1.1 mrg ;; PRECEQU* 312 1.1 mrg (define_insn "mips_precequ_ph_qbl" 313 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 314 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 315 1.1 mrg UNSPEC_PRECEQU_PH_QBL))] 316 1.1 mrg "ISA_HAS_DSP" 317 1.1 mrg "precequ.ph.qbl\t%0,%1" 318 1.3 mrg [(set_attr "type" "dspalu") 319 1.1 mrg (set_attr "mode" "SI")]) 320 1.1 mrg 321 1.1 mrg (define_insn "mips_precequ_ph_qbr" 322 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 323 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 324 1.1 mrg UNSPEC_PRECEQU_PH_QBR))] 325 1.1 mrg "ISA_HAS_DSP" 326 1.1 mrg "precequ.ph.qbr\t%0,%1" 327 1.3 mrg [(set_attr "type" "dspalu") 328 1.1 mrg (set_attr "mode" "SI")]) 329 1.1 mrg 330 1.1 mrg (define_insn "mips_precequ_ph_qbla" 331 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 332 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 333 1.1 mrg UNSPEC_PRECEQU_PH_QBLA))] 334 1.1 mrg "ISA_HAS_DSP" 335 1.1 mrg "precequ.ph.qbla\t%0,%1" 336 1.3 mrg [(set_attr "type" "dspalu") 337 1.1 mrg (set_attr "mode" "SI")]) 338 1.1 mrg 339 1.1 mrg (define_insn "mips_precequ_ph_qbra" 340 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 341 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 342 1.1 mrg UNSPEC_PRECEQU_PH_QBRA))] 343 1.1 mrg "ISA_HAS_DSP" 344 1.1 mrg "precequ.ph.qbra\t%0,%1" 345 1.3 mrg [(set_attr "type" "dspalu") 346 1.1 mrg (set_attr "mode" "SI")]) 347 1.1 mrg 348 1.1 mrg ;; PRECEU* 349 1.1 mrg (define_insn "mips_preceu_ph_qbl" 350 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 351 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 352 1.1 mrg UNSPEC_PRECEU_PH_QBL))] 353 1.1 mrg "ISA_HAS_DSP" 354 1.1 mrg "preceu.ph.qbl\t%0,%1" 355 1.3 mrg [(set_attr "type" "dspalu") 356 1.1 mrg (set_attr "mode" "SI")]) 357 1.1 mrg 358 1.1 mrg (define_insn "mips_preceu_ph_qbr" 359 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 360 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 361 1.1 mrg UNSPEC_PRECEU_PH_QBR))] 362 1.1 mrg "ISA_HAS_DSP" 363 1.1 mrg "preceu.ph.qbr\t%0,%1" 364 1.3 mrg [(set_attr "type" "dspalu") 365 1.1 mrg (set_attr "mode" "SI")]) 366 1.1 mrg 367 1.1 mrg (define_insn "mips_preceu_ph_qbla" 368 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 369 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 370 1.1 mrg UNSPEC_PRECEU_PH_QBLA))] 371 1.1 mrg "ISA_HAS_DSP" 372 1.1 mrg "preceu.ph.qbla\t%0,%1" 373 1.3 mrg [(set_attr "type" "dspalu") 374 1.1 mrg (set_attr "mode" "SI")]) 375 1.1 mrg 376 1.1 mrg (define_insn "mips_preceu_ph_qbra" 377 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 378 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 379 1.1 mrg UNSPEC_PRECEU_PH_QBRA))] 380 1.1 mrg "ISA_HAS_DSP" 381 1.1 mrg "preceu.ph.qbra\t%0,%1" 382 1.3 mrg [(set_attr "type" "dspalu") 383 1.1 mrg (set_attr "mode" "SI")]) 384 1.1 mrg 385 1.1 mrg ;; Table 2-2. MIPS DSP ASE Instructions: Shift 386 1.1 mrg ;; SHLL* 387 1.1 mrg (define_insn "mips_shll_<DSPV:dspfmt2>" 388 1.1 mrg [(parallel 389 1.1 mrg [(set (match_operand:DSPV 0 "register_operand" "=d,d") 390 1.1 mrg (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") 391 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 392 1.1 mrg UNSPEC_SHLL)) 393 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 394 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])] 395 1.1 mrg "ISA_HAS_DSP" 396 1.1 mrg { 397 1.1 mrg if (which_alternative == 0) 398 1.1 mrg { 399 1.1 mrg if (INTVAL (operands[2]) 400 1.1 mrg & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>) 401 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>); 402 1.1 mrg return "shll.<DSPV:dspfmt2>\t%0,%1,%2"; 403 1.1 mrg } 404 1.1 mrg return "shllv.<DSPV:dspfmt2>\t%0,%1,%2"; 405 1.1 mrg } 406 1.3 mrg [(set_attr "type" "dspalu") 407 1.1 mrg (set_attr "mode" "SI")]) 408 1.1 mrg 409 1.1 mrg (define_insn "mips_shll_s_<DSPQ:dspfmt2>" 410 1.1 mrg [(parallel 411 1.1 mrg [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 412 1.1 mrg (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 413 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 414 1.1 mrg UNSPEC_SHLL_S)) 415 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 416 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])] 417 1.1 mrg "ISA_HAS_DSP" 418 1.1 mrg { 419 1.1 mrg if (which_alternative == 0) 420 1.1 mrg { 421 1.1 mrg if (INTVAL (operands[2]) 422 1.1 mrg & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 423 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 424 1.1 mrg return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 425 1.1 mrg } 426 1.1 mrg return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 427 1.1 mrg } 428 1.3 mrg [(set_attr "type" "dspalusat") 429 1.1 mrg (set_attr "mode" "SI")]) 430 1.1 mrg 431 1.1 mrg ;; SHRL* 432 1.1 mrg (define_insn "mips_shrl_qb" 433 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d,d") 434 1.1 mrg (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") 435 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 436 1.1 mrg UNSPEC_SHRL_QB))] 437 1.1 mrg "ISA_HAS_DSP" 438 1.1 mrg { 439 1.1 mrg if (which_alternative == 0) 440 1.1 mrg { 441 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7) 442 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7); 443 1.1 mrg return "shrl.qb\t%0,%1,%2"; 444 1.1 mrg } 445 1.1 mrg return "shrlv.qb\t%0,%1,%2"; 446 1.1 mrg } 447 1.3 mrg [(set_attr "type" "dspalu") 448 1.1 mrg (set_attr "mode" "SI")]) 449 1.1 mrg 450 1.1 mrg ;; SHRA* 451 1.1 mrg (define_insn "mips_shra_ph" 452 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d,d") 453 1.1 mrg (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") 454 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 455 1.1 mrg UNSPEC_SHRA_PH))] 456 1.1 mrg "ISA_HAS_DSP" 457 1.1 mrg { 458 1.1 mrg if (which_alternative == 0) 459 1.1 mrg { 460 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf) 461 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf); 462 1.1 mrg return "shra.ph\t%0,%1,%2"; 463 1.1 mrg } 464 1.1 mrg return "shrav.ph\t%0,%1,%2"; 465 1.1 mrg } 466 1.3 mrg [(set_attr "type" "dspalu") 467 1.1 mrg (set_attr "mode" "SI")]) 468 1.1 mrg 469 1.1 mrg (define_insn "mips_shra_r_<DSPQ:dspfmt2>" 470 1.1 mrg [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 471 1.1 mrg (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 472 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 473 1.1 mrg UNSPEC_SHRA_R))] 474 1.1 mrg "ISA_HAS_DSP" 475 1.1 mrg { 476 1.1 mrg if (which_alternative == 0) 477 1.1 mrg { 478 1.1 mrg if (INTVAL (operands[2]) 479 1.1 mrg & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 480 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 481 1.1 mrg return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 482 1.1 mrg } 483 1.1 mrg return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 484 1.1 mrg } 485 1.3 mrg [(set_attr "type" "dspalu") 486 1.1 mrg (set_attr "mode" "SI")]) 487 1.1 mrg 488 1.1 mrg ;; Table 2-3. MIPS DSP ASE Instructions: Multiply 489 1.1 mrg ;; MULEU* 490 1.1 mrg (define_insn "mips_muleu_s_ph_qbl" 491 1.1 mrg [(parallel 492 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 493 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 494 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 495 1.1 mrg UNSPEC_MULEU_S_PH_QBL)) 496 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 497 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) 498 1.1 mrg (clobber (match_scratch:DI 3 "=x"))])] 499 1.1 mrg "ISA_HAS_DSP" 500 1.1 mrg "muleu_s.ph.qbl\t%0,%1,%2" 501 1.1 mrg [(set_attr "type" "imul3") 502 1.1 mrg (set_attr "mode" "SI")]) 503 1.1 mrg 504 1.1 mrg (define_insn "mips_muleu_s_ph_qbr" 505 1.1 mrg [(parallel 506 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 507 1.1 mrg (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 508 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 509 1.1 mrg UNSPEC_MULEU_S_PH_QBR)) 510 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 511 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) 512 1.1 mrg (clobber (match_scratch:DI 3 "=x"))])] 513 1.1 mrg "ISA_HAS_DSP" 514 1.1 mrg "muleu_s.ph.qbr\t%0,%1,%2" 515 1.1 mrg [(set_attr "type" "imul3") 516 1.1 mrg (set_attr "mode" "SI")]) 517 1.1 mrg 518 1.1 mrg ;; MULQ* 519 1.1 mrg (define_insn "mips_mulq_rs_ph" 520 1.1 mrg [(parallel 521 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 522 1.1 mrg (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 523 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 524 1.1 mrg UNSPEC_MULQ_RS_PH)) 525 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 526 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) 527 1.1 mrg (clobber (match_scratch:DI 3 "=x"))])] 528 1.1 mrg "ISA_HAS_DSP" 529 1.1 mrg "mulq_rs.ph\t%0,%1,%2" 530 1.1 mrg [(set_attr "type" "imul3") 531 1.1 mrg (set_attr "mode" "SI")]) 532 1.1 mrg 533 1.1 mrg ;; MULEQ* 534 1.1 mrg (define_insn "mips_muleq_s_w_phl" 535 1.1 mrg [(parallel 536 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 537 1.1 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 538 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 539 1.1 mrg UNSPEC_MULEQ_S_W_PHL)) 540 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 541 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) 542 1.1 mrg (clobber (match_scratch:DI 3 "=x"))])] 543 1.1 mrg "ISA_HAS_DSP" 544 1.1 mrg "muleq_s.w.phl\t%0,%1,%2" 545 1.1 mrg [(set_attr "type" "imul3") 546 1.1 mrg (set_attr "mode" "SI")]) 547 1.1 mrg 548 1.1 mrg (define_insn "mips_muleq_s_w_phr" 549 1.1 mrg [(parallel 550 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 551 1.1 mrg (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 552 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 553 1.1 mrg UNSPEC_MULEQ_S_W_PHR)) 554 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 555 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) 556 1.1 mrg (clobber (match_scratch:DI 3 "=x"))])] 557 1.1 mrg "ISA_HAS_DSP" 558 1.1 mrg "muleq_s.w.phr\t%0,%1,%2" 559 1.1 mrg [(set_attr "type" "imul3") 560 1.1 mrg (set_attr "mode" "SI")]) 561 1.1 mrg 562 1.1 mrg ;; DPAU* 563 1.1 mrg (define_insn "mips_dpau_h_qbl" 564 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 565 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 566 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 567 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 568 1.1 mrg UNSPEC_DPAU_H_QBL))] 569 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 570 1.1 mrg "dpau.h.qbl\t%q0,%2,%3" 571 1.3 mrg [(set_attr "type" "dspmac") 572 1.3 mrg (set_attr "accum_in" "1") 573 1.1 mrg (set_attr "mode" "SI")]) 574 1.1 mrg 575 1.1 mrg (define_insn "mips_dpau_h_qbr" 576 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 577 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 578 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 579 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 580 1.1 mrg UNSPEC_DPAU_H_QBR))] 581 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 582 1.1 mrg "dpau.h.qbr\t%q0,%2,%3" 583 1.3 mrg [(set_attr "type" "dspmac") 584 1.3 mrg (set_attr "accum_in" "1") 585 1.1 mrg (set_attr "mode" "SI")]) 586 1.1 mrg 587 1.1 mrg ;; DPSU* 588 1.1 mrg (define_insn "mips_dpsu_h_qbl" 589 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 590 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 591 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 592 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 593 1.1 mrg UNSPEC_DPSU_H_QBL))] 594 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 595 1.1 mrg "dpsu.h.qbl\t%q0,%2,%3" 596 1.3 mrg [(set_attr "type" "dspmac") 597 1.3 mrg (set_attr "accum_in" "1") 598 1.1 mrg (set_attr "mode" "SI")]) 599 1.1 mrg 600 1.1 mrg (define_insn "mips_dpsu_h_qbr" 601 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 602 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 603 1.1 mrg (match_operand:V4QI 2 "register_operand" "d") 604 1.1 mrg (match_operand:V4QI 3 "register_operand" "d")] 605 1.1 mrg UNSPEC_DPSU_H_QBR))] 606 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 607 1.1 mrg "dpsu.h.qbr\t%q0,%2,%3" 608 1.3 mrg [(set_attr "type" "dspmac") 609 1.3 mrg (set_attr "accum_in" "1") 610 1.1 mrg (set_attr "mode" "SI")]) 611 1.1 mrg 612 1.1 mrg ;; DPAQ* 613 1.1 mrg (define_insn "mips_dpaq_s_w_ph" 614 1.1 mrg [(parallel 615 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 616 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 617 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 618 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 619 1.1 mrg UNSPEC_DPAQ_S_W_PH)) 620 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 621 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 622 1.1 mrg UNSPEC_DPAQ_S_W_PH))])] 623 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 624 1.1 mrg "dpaq_s.w.ph\t%q0,%2,%3" 625 1.3 mrg [(set_attr "type" "dspmac") 626 1.3 mrg (set_attr "accum_in" "1") 627 1.1 mrg (set_attr "mode" "SI")]) 628 1.1 mrg 629 1.1 mrg ;; DPSQ* 630 1.1 mrg (define_insn "mips_dpsq_s_w_ph" 631 1.1 mrg [(parallel 632 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 633 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 634 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 635 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 636 1.1 mrg UNSPEC_DPSQ_S_W_PH)) 637 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 638 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 639 1.1 mrg UNSPEC_DPSQ_S_W_PH))])] 640 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 641 1.1 mrg "dpsq_s.w.ph\t%q0,%2,%3" 642 1.3 mrg [(set_attr "type" "dspmac") 643 1.3 mrg (set_attr "accum_in" "1") 644 1.1 mrg (set_attr "mode" "SI")]) 645 1.1 mrg 646 1.1 mrg ;; MULSAQ* 647 1.1 mrg (define_insn "mips_mulsaq_s_w_ph" 648 1.1 mrg [(parallel 649 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 650 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 651 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 652 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 653 1.1 mrg UNSPEC_MULSAQ_S_W_PH)) 654 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 655 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 656 1.1 mrg UNSPEC_MULSAQ_S_W_PH))])] 657 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 658 1.1 mrg "mulsaq_s.w.ph\t%q0,%2,%3" 659 1.3 mrg [(set_attr "type" "dspmac") 660 1.3 mrg (set_attr "accum_in" "1") 661 1.1 mrg (set_attr "mode" "SI")]) 662 1.1 mrg 663 1.1 mrg ;; DPAQ* 664 1.1 mrg (define_insn "mips_dpaq_sa_l_w" 665 1.1 mrg [(parallel 666 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 667 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 668 1.1 mrg (match_operand:SI 2 "register_operand" "d") 669 1.1 mrg (match_operand:SI 3 "register_operand" "d")] 670 1.1 mrg UNSPEC_DPAQ_SA_L_W)) 671 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 672 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 673 1.1 mrg UNSPEC_DPAQ_SA_L_W))])] 674 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 675 1.1 mrg "dpaq_sa.l.w\t%q0,%2,%3" 676 1.3 mrg [(set_attr "type" "dspmacsat") 677 1.3 mrg (set_attr "accum_in" "1") 678 1.1 mrg (set_attr "mode" "SI")]) 679 1.1 mrg 680 1.1 mrg ;; DPSQ* 681 1.1 mrg (define_insn "mips_dpsq_sa_l_w" 682 1.1 mrg [(parallel 683 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 684 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 685 1.1 mrg (match_operand:SI 2 "register_operand" "d") 686 1.1 mrg (match_operand:SI 3 "register_operand" "d")] 687 1.1 mrg UNSPEC_DPSQ_SA_L_W)) 688 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 689 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 690 1.1 mrg UNSPEC_DPSQ_SA_L_W))])] 691 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 692 1.1 mrg "dpsq_sa.l.w\t%q0,%2,%3" 693 1.3 mrg [(set_attr "type" "dspmacsat") 694 1.3 mrg (set_attr "accum_in" "1") 695 1.1 mrg (set_attr "mode" "SI")]) 696 1.1 mrg 697 1.1 mrg ;; MAQ* 698 1.1 mrg (define_insn "mips_maq_s_w_phl" 699 1.1 mrg [(parallel 700 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 701 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 702 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 703 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 704 1.1 mrg UNSPEC_MAQ_S_W_PHL)) 705 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 706 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 707 1.1 mrg UNSPEC_MAQ_S_W_PHL))])] 708 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 709 1.1 mrg "maq_s.w.phl\t%q0,%2,%3" 710 1.3 mrg [(set_attr "type" "dspmac") 711 1.3 mrg (set_attr "accum_in" "1") 712 1.1 mrg (set_attr "mode" "SI")]) 713 1.1 mrg 714 1.1 mrg (define_insn "mips_maq_s_w_phr" 715 1.1 mrg [(parallel 716 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 717 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 718 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 719 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 720 1.1 mrg UNSPEC_MAQ_S_W_PHR)) 721 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 722 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 723 1.1 mrg UNSPEC_MAQ_S_W_PHR))])] 724 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 725 1.1 mrg "maq_s.w.phr\t%q0,%2,%3" 726 1.3 mrg [(set_attr "type" "dspmac") 727 1.3 mrg (set_attr "accum_in" "1") 728 1.1 mrg (set_attr "mode" "SI")]) 729 1.1 mrg 730 1.1 mrg ;; MAQ_SA* 731 1.1 mrg (define_insn "mips_maq_sa_w_phl" 732 1.1 mrg [(parallel 733 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 734 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 735 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 736 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 737 1.1 mrg UNSPEC_MAQ_SA_W_PHL)) 738 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 739 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 740 1.1 mrg UNSPEC_MAQ_SA_W_PHL))])] 741 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 742 1.1 mrg "maq_sa.w.phl\t%q0,%2,%3" 743 1.3 mrg [(set_attr "type" "dspmacsat") 744 1.3 mrg (set_attr "accum_in" "1") 745 1.1 mrg (set_attr "mode" "SI")]) 746 1.1 mrg 747 1.1 mrg (define_insn "mips_maq_sa_w_phr" 748 1.1 mrg [(parallel 749 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 750 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 751 1.1 mrg (match_operand:V2HI 2 "register_operand" "d") 752 1.1 mrg (match_operand:V2HI 3 "register_operand" "d")] 753 1.1 mrg UNSPEC_MAQ_SA_W_PHR)) 754 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 755 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 756 1.1 mrg UNSPEC_MAQ_SA_W_PHR))])] 757 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 758 1.1 mrg "maq_sa.w.phr\t%q0,%2,%3" 759 1.3 mrg [(set_attr "type" "dspmacsat") 760 1.3 mrg (set_attr "accum_in" "1") 761 1.1 mrg (set_attr "mode" "SI")]) 762 1.1 mrg 763 1.1 mrg ;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation 764 1.1 mrg ;; BITREV 765 1.1 mrg (define_insn "mips_bitrev" 766 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 767 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "d")] 768 1.1 mrg UNSPEC_BITREV))] 769 1.1 mrg "ISA_HAS_DSP" 770 1.1 mrg "bitrev\t%0,%1" 771 1.3 mrg [(set_attr "type" "dspalu") 772 1.1 mrg (set_attr "mode" "SI")]) 773 1.1 mrg 774 1.1 mrg ;; INSV 775 1.1 mrg (define_insn "mips_insv" 776 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 777 1.1 mrg (unspec:SI [(match_operand:SI 1 "register_operand" "0") 778 1.1 mrg (match_operand:SI 2 "register_operand" "d") 779 1.1 mrg (reg:CCDSP CCDSP_SC_REGNUM) 780 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 781 1.1 mrg UNSPEC_INSV))] 782 1.1 mrg "ISA_HAS_DSP" 783 1.1 mrg "insv\t%0,%2" 784 1.3 mrg [(set_attr "type" "dspalu") 785 1.1 mrg (set_attr "mode" "SI")]) 786 1.1 mrg 787 1.1 mrg ;; REPL* 788 1.1 mrg (define_insn "mips_repl_qb" 789 1.1 mrg [(set (match_operand:V4QI 0 "register_operand" "=d,d") 790 1.1 mrg (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] 791 1.1 mrg UNSPEC_REPL_QB))] 792 1.1 mrg "ISA_HAS_DSP" 793 1.1 mrg { 794 1.1 mrg if (which_alternative == 0) 795 1.1 mrg { 796 1.1 mrg if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff) 797 1.1 mrg operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); 798 1.1 mrg return "repl.qb\t%0,%1"; 799 1.1 mrg } 800 1.1 mrg return "replv.qb\t%0,%1"; 801 1.1 mrg } 802 1.3 mrg [(set_attr "type" "dspalu") 803 1.1 mrg (set_attr "mode" "SI")]) 804 1.1 mrg 805 1.1 mrg (define_insn "mips_repl_ph" 806 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d,d") 807 1.1 mrg (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] 808 1.1 mrg UNSPEC_REPL_PH))] 809 1.1 mrg "ISA_HAS_DSP" 810 1.1 mrg "@ 811 1.1 mrg repl.ph\t%0,%1 812 1.1 mrg replv.ph\t%0,%1" 813 1.3 mrg [(set_attr "type" "dspalu") 814 1.1 mrg (set_attr "mode" "SI")]) 815 1.1 mrg 816 1.1 mrg ;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick 817 1.1 mrg ;; CMPU.* CMP.* 818 1.1 mrg (define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>" 819 1.1 mrg [(set (reg:CCDSP CCDSP_CC_REGNUM) 820 1.1 mrg (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 821 1.1 mrg (match_operand:DSPV 1 "register_operand" "d") 822 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 823 1.1 mrg UNSPEC_CMP_EQ))] 824 1.1 mrg "ISA_HAS_DSP" 825 1.1 mrg "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1" 826 1.3 mrg [(set_attr "type" "dspalu") 827 1.1 mrg (set_attr "mode" "SI")]) 828 1.1 mrg 829 1.1 mrg (define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>" 830 1.1 mrg [(set (reg:CCDSP CCDSP_CC_REGNUM) 831 1.1 mrg (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 832 1.1 mrg (match_operand:DSPV 1 "register_operand" "d") 833 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 834 1.1 mrg UNSPEC_CMP_LT))] 835 1.1 mrg "ISA_HAS_DSP" 836 1.1 mrg "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1" 837 1.3 mrg [(set_attr "type" "dspalu") 838 1.1 mrg (set_attr "mode" "SI")]) 839 1.1 mrg 840 1.1 mrg (define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>" 841 1.1 mrg [(set (reg:CCDSP CCDSP_CC_REGNUM) 842 1.1 mrg (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 843 1.1 mrg (match_operand:DSPV 1 "register_operand" "d") 844 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 845 1.1 mrg UNSPEC_CMP_LE))] 846 1.1 mrg "ISA_HAS_DSP" 847 1.1 mrg "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1" 848 1.3 mrg [(set_attr "type" "dspalu") 849 1.1 mrg (set_attr "mode" "SI")]) 850 1.1 mrg 851 1.1 mrg (define_insn "mips_cmpgu_eq_qb" 852 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 853 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 854 1.1 mrg (match_operand:V4QI 2 "register_operand" "d")] 855 1.1 mrg UNSPEC_CMPGU_EQ_QB))] 856 1.1 mrg "ISA_HAS_DSP" 857 1.1 mrg "cmpgu.eq.qb\t%0,%1,%2" 858 1.3 mrg [(set_attr "type" "dspalu") 859 1.1 mrg (set_attr "mode" "SI")]) 860 1.1 mrg 861 1.1 mrg (define_insn "mips_cmpgu_lt_qb" 862 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 863 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 864 1.1 mrg (match_operand:V4QI 2 "register_operand" "d")] 865 1.1 mrg UNSPEC_CMPGU_LT_QB))] 866 1.1 mrg "ISA_HAS_DSP" 867 1.1 mrg "cmpgu.lt.qb\t%0,%1,%2" 868 1.3 mrg [(set_attr "type" "dspalu") 869 1.1 mrg (set_attr "mode" "SI")]) 870 1.1 mrg 871 1.1 mrg (define_insn "mips_cmpgu_le_qb" 872 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 873 1.1 mrg (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 874 1.1 mrg (match_operand:V4QI 2 "register_operand" "d")] 875 1.1 mrg UNSPEC_CMPGU_LE_QB))] 876 1.1 mrg "ISA_HAS_DSP" 877 1.1 mrg "cmpgu.le.qb\t%0,%1,%2" 878 1.3 mrg [(set_attr "type" "dspalu") 879 1.1 mrg (set_attr "mode" "SI")]) 880 1.1 mrg 881 1.1 mrg ;; PICK* 882 1.1 mrg (define_insn "mips_pick_<DSPV:dspfmt2>" 883 1.1 mrg [(set (match_operand:DSPV 0 "register_operand" "=d") 884 1.1 mrg (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d") 885 1.1 mrg (match_operand:DSPV 2 "register_operand" "d") 886 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM)] 887 1.1 mrg UNSPEC_PICK))] 888 1.1 mrg "ISA_HAS_DSP" 889 1.1 mrg "pick.<DSPV:dspfmt2>\t%0,%1,%2" 890 1.3 mrg [(set_attr "type" "dspalu") 891 1.1 mrg (set_attr "mode" "SI")]) 892 1.1 mrg 893 1.1 mrg ;; PACKRL* 894 1.1 mrg (define_insn "mips_packrl_ph" 895 1.1 mrg [(set (match_operand:V2HI 0 "register_operand" "=d") 896 1.1 mrg (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 897 1.1 mrg (match_operand:V2HI 2 "register_operand" "d")] 898 1.1 mrg UNSPEC_PACKRL_PH))] 899 1.1 mrg "ISA_HAS_DSP" 900 1.1 mrg "packrl.ph\t%0,%1,%2" 901 1.3 mrg [(set_attr "type" "dspalu") 902 1.1 mrg (set_attr "mode" "SI")]) 903 1.1 mrg 904 1.1 mrg ;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access 905 1.1 mrg ;; EXTR* 906 1.1 mrg (define_insn "mips_extr_w" 907 1.1 mrg [(parallel 908 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 909 1.1 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 910 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 911 1.1 mrg UNSPEC_EXTR_W)) 912 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 913 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])] 914 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 915 1.1 mrg { 916 1.1 mrg if (which_alternative == 0) 917 1.1 mrg { 918 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 919 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 920 1.1 mrg return "extr.w\t%0,%q1,%2"; 921 1.1 mrg } 922 1.1 mrg return "extrv.w\t%0,%q1,%2"; 923 1.1 mrg } 924 1.3 mrg [(set_attr "type" "accext") 925 1.1 mrg (set_attr "mode" "SI")]) 926 1.1 mrg 927 1.1 mrg (define_insn "mips_extr_r_w" 928 1.1 mrg [(parallel 929 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 930 1.1 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 931 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 932 1.1 mrg UNSPEC_EXTR_R_W)) 933 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 934 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])] 935 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 936 1.1 mrg { 937 1.1 mrg if (which_alternative == 0) 938 1.1 mrg { 939 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 940 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 941 1.1 mrg return "extr_r.w\t%0,%q1,%2"; 942 1.1 mrg } 943 1.1 mrg return "extrv_r.w\t%0,%q1,%2"; 944 1.1 mrg } 945 1.3 mrg [(set_attr "type" "accext") 946 1.1 mrg (set_attr "mode" "SI")]) 947 1.1 mrg 948 1.1 mrg (define_insn "mips_extr_rs_w" 949 1.1 mrg [(parallel 950 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 951 1.1 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 952 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 953 1.1 mrg UNSPEC_EXTR_RS_W)) 954 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 955 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])] 956 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 957 1.1 mrg { 958 1.1 mrg if (which_alternative == 0) 959 1.1 mrg { 960 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 961 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 962 1.1 mrg return "extr_rs.w\t%0,%q1,%2"; 963 1.1 mrg } 964 1.1 mrg return "extrv_rs.w\t%0,%q1,%2"; 965 1.1 mrg } 966 1.3 mrg [(set_attr "type" "accext") 967 1.1 mrg (set_attr "mode" "SI")]) 968 1.1 mrg 969 1.1 mrg ;; EXTR*_S.H 970 1.1 mrg (define_insn "mips_extr_s_h" 971 1.1 mrg [(parallel 972 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 973 1.1 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 974 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 975 1.1 mrg UNSPEC_EXTR_S_H)) 976 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 977 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])] 978 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 979 1.1 mrg { 980 1.1 mrg if (which_alternative == 0) 981 1.1 mrg { 982 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 983 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 984 1.1 mrg return "extr_s.h\t%0,%q1,%2"; 985 1.1 mrg } 986 1.1 mrg return "extrv_s.h\t%0,%q1,%2"; 987 1.1 mrg } 988 1.3 mrg [(set_attr "type" "accext") 989 1.1 mrg (set_attr "mode" "SI")]) 990 1.1 mrg 991 1.1 mrg ;; EXTP* 992 1.1 mrg (define_insn "mips_extp" 993 1.1 mrg [(parallel 994 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 995 1.1 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 996 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d") 997 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 998 1.1 mrg UNSPEC_EXTP)) 999 1.1 mrg (set (reg:CCDSP CCDSP_EF_REGNUM) 1000 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])] 1001 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 1002 1.1 mrg { 1003 1.1 mrg if (which_alternative == 0) 1004 1.1 mrg { 1005 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 1006 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 1007 1.1 mrg return "extp\t%0,%q1,%2"; 1008 1.1 mrg } 1009 1.1 mrg return "extpv\t%0,%q1,%2"; 1010 1.1 mrg } 1011 1.3 mrg [(set_attr "type" "accext") 1012 1.1 mrg (set_attr "mode" "SI")]) 1013 1.1 mrg 1014 1.1 mrg (define_insn "mips_extpdp" 1015 1.1 mrg [(parallel 1016 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d,d") 1017 1.1 mrg (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 1018 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d") 1019 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 1020 1.1 mrg UNSPEC_EXTPDP)) 1021 1.1 mrg (set (reg:CCDSP CCDSP_PO_REGNUM) 1022 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) 1023 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) 1024 1.1 mrg (set (reg:CCDSP CCDSP_EF_REGNUM) 1025 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])] 1026 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 1027 1.1 mrg { 1028 1.1 mrg if (which_alternative == 0) 1029 1.1 mrg { 1030 1.1 mrg if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 1031 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 1032 1.1 mrg return "extpdp\t%0,%q1,%2"; 1033 1.1 mrg } 1034 1.1 mrg return "extpdpv\t%0,%q1,%2"; 1035 1.1 mrg } 1036 1.3 mrg [(set_attr "type" "accext") 1037 1.1 mrg (set_attr "mode" "SI")]) 1038 1.1 mrg 1039 1.1 mrg ;; SHILO* 1040 1.1 mrg (define_insn "mips_shilo" 1041 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a,a") 1042 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") 1043 1.1 mrg (match_operand:SI 2 "arith_operand" "I,d")] 1044 1.1 mrg UNSPEC_SHILO))] 1045 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 1046 1.1 mrg { 1047 1.1 mrg if (which_alternative == 0) 1048 1.1 mrg { 1049 1.1 mrg if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31) 1050 1.1 mrg operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 1051 1.1 mrg return "shilo\t%q0,%2"; 1052 1.1 mrg } 1053 1.1 mrg return "shilov\t%q0,%2"; 1054 1.1 mrg } 1055 1.3 mrg [(set_attr "type" "accmod") 1056 1.1 mrg (set_attr "mode" "SI")]) 1057 1.1 mrg 1058 1.1 mrg ;; MTHLIP* 1059 1.1 mrg (define_insn "mips_mthlip" 1060 1.1 mrg [(parallel 1061 1.1 mrg [(set (match_operand:DI 0 "register_operand" "=a") 1062 1.1 mrg (unspec:DI [(match_operand:DI 1 "register_operand" "0") 1063 1.1 mrg (match_operand:SI 2 "register_operand" "d") 1064 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] 1065 1.1 mrg UNSPEC_MTHLIP)) 1066 1.1 mrg (set (reg:CCDSP CCDSP_PO_REGNUM) 1067 1.1 mrg (unspec:CCDSP [(match_dup 1) (match_dup 2) 1068 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] 1069 1.1 mrg "ISA_HAS_DSP && !TARGET_64BIT" 1070 1.1 mrg "mthlip\t%2,%q0" 1071 1.3 mrg [(set_attr "type" "accmod") 1072 1.1 mrg (set_attr "mode" "SI")]) 1073 1.1 mrg 1074 1.1 mrg ;; WRDSP 1075 1.1 mrg (define_insn "mips_wrdsp" 1076 1.1 mrg [(parallel 1077 1.1 mrg [(set (reg:CCDSP CCDSP_PO_REGNUM) 1078 1.1 mrg (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") 1079 1.1 mrg (match_operand:SI 1 "const_uimm6_operand" "YA")] 1080 1.1 mrg UNSPEC_WRDSP)) 1081 1.1 mrg (set (reg:CCDSP CCDSP_SC_REGNUM) 1082 1.1 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1083 1.1 mrg (set (reg:CCDSP CCDSP_CA_REGNUM) 1084 1.1 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1085 1.1 mrg (set (reg:CCDSP CCDSP_OU_REGNUM) 1086 1.1 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1087 1.1 mrg (set (reg:CCDSP CCDSP_CC_REGNUM) 1088 1.1 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1089 1.1 mrg (set (reg:CCDSP CCDSP_EF_REGNUM) 1090 1.1 mrg (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] 1091 1.1 mrg "ISA_HAS_DSP" 1092 1.1 mrg "wrdsp\t%0,%1" 1093 1.3 mrg [(set_attr "type" "dspalu") 1094 1.1 mrg (set_attr "mode" "SI")]) 1095 1.1 mrg 1096 1.1 mrg ;; RDDSP 1097 1.1 mrg (define_insn "mips_rddsp" 1098 1.1 mrg [(set (match_operand:SI 0 "register_operand" "=d") 1099 1.1 mrg (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA") 1100 1.1 mrg (reg:CCDSP CCDSP_PO_REGNUM) 1101 1.1 mrg (reg:CCDSP CCDSP_SC_REGNUM) 1102 1.1 mrg (reg:CCDSP CCDSP_CA_REGNUM) 1103 1.1 mrg (reg:CCDSP CCDSP_OU_REGNUM) 1104 1.1 mrg (reg:CCDSP CCDSP_CC_REGNUM) 1105 1.1 mrg (reg:CCDSP CCDSP_EF_REGNUM)] 1106 1.1 mrg UNSPEC_RDDSP))] 1107 1.1 mrg "ISA_HAS_DSP" 1108 1.1 mrg "rddsp\t%0,%1" 1109 1.3 mrg [(set_attr "type" "dspalu") 1110 1.1 mrg (set_attr "mode" "SI")]) 1111 1.1 mrg 1112 1.1 mrg ;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load 1113 1.1 mrg ;; L*X 1114 1.1 mrg (define_expand "mips_lbux" 1115 1.1 mrg [(match_operand:SI 0 "register_operand") 1116 1.1 mrg (match_operand 1 "pmode_register_operand") 1117 1.1 mrg (match_operand:SI 2 "register_operand")] 1118 1.1 mrg "ISA_HAS_DSP" 1119 1.1 mrg { 1120 1.1 mrg operands[2] = convert_to_mode (Pmode, operands[2], false); 1121 1.3 mrg emit_insn (PMODE_INSN (gen_mips_lbux_extsi, 1122 1.3 mrg (operands[0], operands[1], operands[2]))); 1123 1.1 mrg DONE; 1124 1.1 mrg }) 1125 1.1 mrg 1126 1.3 mrg (define_insn "mips_l<SHORT:size><u>x_ext<GPR:mode>_<P:mode>" 1127 1.3 mrg [(set (match_operand:GPR 0 "register_operand" "=d") 1128 1.3 mrg (any_extend:GPR 1129 1.3 mrg (mem:SHORT (plus:P (match_operand:P 1 "register_operand" "d") 1130 1.3 mrg (match_operand:P 2 "register_operand" "d")))))] 1131 1.3 mrg "ISA_HAS_L<SHORT:SIZE><U>X" 1132 1.3 mrg "l<SHORT:size><u>x\t%0,%2(%1)" 1133 1.1 mrg [(set_attr "type" "load") 1134 1.3 mrg (set_attr "mode" "<GPR:MODE>") 1135 1.3 mrg (set_attr "length" "4")]) 1136 1.1 mrg 1137 1.1 mrg (define_expand "mips_lhx" 1138 1.1 mrg [(match_operand:SI 0 "register_operand") 1139 1.1 mrg (match_operand 1 "pmode_register_operand") 1140 1.1 mrg (match_operand:SI 2 "register_operand")] 1141 1.1 mrg "ISA_HAS_DSP" 1142 1.1 mrg { 1143 1.1 mrg operands[2] = convert_to_mode (Pmode, operands[2], false); 1144 1.3 mrg emit_insn (PMODE_INSN (gen_mips_lhx_extsi, 1145 1.3 mrg (operands[0], operands[1], operands[2]))); 1146 1.1 mrg DONE; 1147 1.1 mrg }) 1148 1.1 mrg 1149 1.3 mrg (define_expand "mips_l<size>x" 1150 1.3 mrg [(match_operand:GPR 0 "register_operand") 1151 1.1 mrg (match_operand 1 "pmode_register_operand") 1152 1.1 mrg (match_operand:SI 2 "register_operand")] 1153 1.1 mrg "ISA_HAS_DSP" 1154 1.1 mrg { 1155 1.1 mrg operands[2] = convert_to_mode (Pmode, operands[2], false); 1156 1.3 mrg emit_insn (PMODE_INSN (gen_mips_l<size>x, 1157 1.3 mrg (operands[0], operands[1], operands[2]))); 1158 1.1 mrg DONE; 1159 1.1 mrg }) 1160 1.1 mrg 1161 1.3 mrg (define_insn "mips_l<GPR:size>x_<P:mode>" 1162 1.3 mrg [(set (match_operand:GPR 0 "register_operand" "=d") 1163 1.3 mrg (mem:GPR (plus:P (match_operand:P 1 "register_operand" "d") 1164 1.3 mrg (match_operand:P 2 "register_operand" "d"))))] 1165 1.3 mrg "ISA_HAS_L<GPR:SIZE>X" 1166 1.3 mrg "l<GPR:size>x\t%0,%2(%1)" 1167 1.3 mrg [(set_attr "type" "load") 1168 1.3 mrg (set_attr "mode" "<GPR:MODE>") 1169 1.3 mrg (set_attr "length" "4")]) 1170 1.3 mrg 1171 1.3 mrg (define_insn "*mips_lw<u>x_<P:mode>_ext" 1172 1.3 mrg [(set (match_operand:DI 0 "register_operand" "=d") 1173 1.3 mrg (any_extend:DI 1174 1.3 mrg (mem:SI (plus:P (match_operand:P 1 "register_operand" "d") 1175 1.3 mrg (match_operand:P 2 "register_operand" "d")))))] 1176 1.3 mrg "ISA_HAS_LW<U>X && TARGET_64BIT" 1177 1.3 mrg "lw<u>x\t%0,%2(%1)" 1178 1.1 mrg [(set_attr "type" "load") 1179 1.3 mrg (set_attr "mode" "DI") 1180 1.3 mrg (set_attr "length" "4")]) 1181 1.1 mrg 1182 1.1 mrg ;; Table 2-8. MIPS DSP ASE Instructions: Branch 1183 1.1 mrg ;; BPOSGE32 1184 1.1 mrg (define_insn "mips_bposge" 1185 1.1 mrg [(set (pc) 1186 1.1 mrg (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM) 1187 1.1 mrg (match_operand:SI 1 "immediate_operand" "I")) 1188 1.1 mrg (label_ref (match_operand 0 "" "")) 1189 1.1 mrg (pc)))] 1190 1.1 mrg "ISA_HAS_DSP" 1191 1.1 mrg "%*bposge%1\t%0%/" 1192 1.1 mrg [(set_attr "type" "branch")]) 1193 1.1 mrg 1194 1.3 mrg (define_expand "mips_madd<u>" 1195 1.3 mrg [(set (match_operand:DI 0 "register_operand") 1196 1.3 mrg (plus:DI 1197 1.3 mrg (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) 1198 1.3 mrg (any_extend:DI (match_operand:SI 3 "register_operand"))) 1199 1.3 mrg (match_operand:DI 1 "register_operand")))] 1200 1.3 mrg "ISA_HAS_DSP && !TARGET_64BIT") 1201 1.3 mrg 1202 1.3 mrg (define_expand "mips_msub<u>" 1203 1.3 mrg [(set (match_operand:DI 0 "register_operand") 1204 1.3 mrg (minus:DI 1205 1.3 mrg (match_operand:DI 1 "register_operand") 1206 1.3 mrg (mult:DI (any_extend:DI (match_operand:SI 2 "register_operand")) 1207 1.3 mrg (any_extend:DI (match_operand:SI 3 "register_operand")))))] 1208 1.3 mrg "ISA_HAS_DSP && !TARGET_64BIT") 1209
Indexes created Sun Jun 28 00:24:58 UTC 2026