nds32.cc revision 1.1.1.1
1 /* Subroutines used for code generation of Andes NDS32 cpu for GNU compiler 2 Copyright (C) 2012-2022 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 /* ------------------------------------------------------------------------ */ 22 23 #define IN_TARGET_CODE 1 24 25 #include "config.h" 26 #include "system.h" 27 #include "coretypes.h" 28 #include "backend.h" 29 #include "target.h" 30 #include "rtl.h" 31 #include "tree.h" 32 #include "tree-pass.h" 33 #include "stringpool.h" 34 #include "attribs.h" 35 #include "df.h" 36 #include "memmodel.h" 37 #include "tm_p.h" 38 #include "optabs.h" /* For GEN_FCN. */ 39 #include "regs.h" 40 #include "emit-rtl.h" 41 #include "recog.h" 42 #include "diagnostic-core.h" 43 #include "stor-layout.h" 44 #include "varasm.h" 45 #include "calls.h" 46 #include "output.h" 47 #include "explow.h" 48 #include "expr.h" 49 #include "tm-constrs.h" 50 #include "builtins.h" 51 #include "cpplib.h" 52 #include "context.h" 53 54 /* This file should be included last. */ 55 #include "target-def.h" 56 57 /* ------------------------------------------------------------------------ */ 58 59 /* This file is divided into five parts: 60 61 PART 1: Auxiliary static variable definitions and 62 target hook static variable definitions. 63 64 PART 2: Auxiliary static function definitions. 65 66 PART 3: Implement target hook stuff definitions. 67 68 PART 4: Implemet extern function definitions, 69 the prototype is in nds32-protos.h. 70 71 PART 5: Initialize target hook structure and definitions. */ 72 73 /* ------------------------------------------------------------------------ */ 74 75 /* PART 1: Auxiliary static variable definitions and 76 target hook static variable definitions. */ 77 78 /* Define intrinsic register names. 79 Please refer to nds32_intrinsic.h file, the index is corresponding to 80 'enum nds32_intrinsic_registers' data type values. 81 NOTE that the base value starting from 1024. */ 82 static const char * const nds32_intrinsic_register_names[] = 83 { 84 "$CPU_VER", 85 "$ICM_CFG", 86 "$DCM_CFG", 87 "$MMU_CFG", 88 "$MSC_CFG", 89 "$MSC_CFG2", 90 "$CORE_ID", 91 "$FUCOP_EXIST", 92 93 "$PSW", 94 "$IPSW", 95 "$P_IPSW", 96 "$IVB", 97 "$EVA", 98 "$P_EVA", 99 "$ITYPE", 100 "$P_ITYPE", 101 102 "$MERR", 103 "$IPC", 104 "$P_IPC", 105 "$OIPC", 106 "$P_P0", 107 "$P_P1", 108 109 "$INT_MASK", 110 "$INT_MASK2", 111 "$INT_MASK3", 112 "$INT_PEND", 113 "$INT_PEND2", 114 "$INT_PEND3", 115 "$SP_USR", 116 "$SP_PRIV", 117 "$INT_PRI", 118 "$INT_PRI2", 119 "$INT_PRI3", 120 "$INT_PRI4", 121 "$INT_CTRL", 122 "$INT_TRIGGER", 123 "$INT_TRIGGER2", 124 "$INT_GPR_PUSH_DIS", 125 126 "$MMU_CTL", 127 "$L1_PPTB", 128 "$TLB_VPN", 129 "$TLB_DATA", 130 "$TLB_MISC", 131 "$VLPT_IDX", 132 "$ILMB", 133 "$DLMB", 134 135 "$CACHE_CTL", 136 "$HSMP_SADDR", 137 "$HSMP_EADDR", 138 "$SDZ_CTL", 139 "$N12MISC_CTL", 140 "$MISC_CTL", 141 "$ECC_MISC", 142 143 "$BPC0", 144 "$BPC1", 145 "$BPC2", 146 "$BPC3", 147 "$BPC4", 148 "$BPC5", 149 "$BPC6", 150 "$BPC7", 151 152 "$BPA0", 153 "$BPA1", 154 "$BPA2", 155 "$BPA3", 156 "$BPA4", 157 "$BPA5", 158 "$BPA6", 159 "$BPA7", 160 161 "$BPAM0", 162 "$BPAM1", 163 "$BPAM2", 164 "$BPAM3", 165 "$BPAM4", 166 "$BPAM5", 167 "$BPAM6", 168 "$BPAM7", 169 170 "$BPV0", 171 "$BPV1", 172 "$BPV2", 173 "$BPV3", 174 "$BPV4", 175 "$BPV5", 176 "$BPV6", 177 "$BPV7", 178 179 "$BPCID0", 180 "$BPCID1", 181 "$BPCID2", 182 "$BPCID3", 183 "$BPCID4", 184 "$BPCID5", 185 "$BPCID6", 186 "$BPCID7", 187 188 "$EDM_CFG", 189 "$EDMSW", 190 "$EDM_CTL", 191 "$EDM_DTR", 192 "$BPMTC", 193 "$DIMBR", 194 195 "$TECR0", 196 "$TECR1", 197 "$PFMC0", 198 "$PFMC1", 199 "$PFMC2", 200 "$PFM_CTL", 201 "$PFT_CTL", 202 "$HSP_CTL", 203 "$SP_BOUND", 204 "$SP_BOUND_PRIV", 205 "$SP_BASE", 206 "$SP_BASE_PRIV", 207 "$FUCOP_CTL", 208 "$PRUSR_ACC_CTL", 209 210 "$DMA_CFG", 211 "$DMA_GCSW", 212 "$DMA_CHNSEL", 213 "$DMA_ACT", 214 "$DMA_SETUP", 215 "$DMA_ISADDR", 216 "$DMA_ESADDR", 217 "$DMA_TCNT", 218 "$DMA_STATUS", 219 "$DMA_2DSET", 220 "$DMA_2DSCTL", 221 "$DMA_RCNT", 222 "$DMA_HSTATUS", 223 224 "$PC", 225 "$SP_USR1", 226 "$SP_USR2", 227 "$SP_USR3", 228 "$SP_PRIV1", 229 "$SP_PRIV2", 230 "$SP_PRIV3", 231 "$BG_REGION", 232 "$SFCR", 233 "$SIGN", 234 "$ISIGN", 235 "$P_ISIGN", 236 "$IFC_LP", 237 "$ITB" 238 }; 239 240 /* Define instrinsic cctl names. */ 241 static const char * const nds32_cctl_names[] = 242 { 243 "L1D_VA_FILLCK", 244 "L1D_VA_ULCK", 245 "L1I_VA_FILLCK", 246 "L1I_VA_ULCK", 247 248 "L1D_IX_WBINVAL", 249 "L1D_IX_INVAL", 250 "L1D_IX_WB", 251 "L1I_IX_INVAL", 252 253 "L1D_VA_INVAL", 254 "L1D_VA_WB", 255 "L1D_VA_WBINVAL", 256 "L1I_VA_INVAL", 257 258 "L1D_IX_RTAG", 259 "L1D_IX_RWD", 260 "L1I_IX_RTAG", 261 "L1I_IX_RWD", 262 263 "L1D_IX_WTAG", 264 "L1D_IX_WWD", 265 "L1I_IX_WTAG", 266 "L1I_IX_WWD" 267 }; 268 269 static const char * const nds32_dpref_names[] = 270 { 271 "SRD", 272 "MRD", 273 "SWR", 274 "MWR", 275 "PTE", 276 "CLWR" 277 }; 278 279 /* Defining register allocation order for performance. 280 We want to allocate callee-saved registers after others. 281 It may be used by nds32_adjust_reg_alloc_order(). */ 282 static const int nds32_reg_alloc_order_for_speed[] = 283 { 284 0, 1, 2, 3, 4, 5, 16, 17, 285 18, 19, 20, 21, 22, 23, 24, 25, 286 26, 27, 6, 7, 8, 9, 10, 11, 287 12, 13, 14, 15 288 }; 289 290 /* Defining target-specific uses of __attribute__. */ 291 static const struct attribute_spec nds32_attribute_table[] = 292 { 293 /* Syntax: { name, min_len, max_len, decl_required, type_required, 294 function_type_required, affects_type_identity, handler, 295 exclude } */ 296 297 /* The interrupt vid: [0-63]+ (actual vector number starts from 9 to 72). */ 298 { "interrupt", 1, 64, false, false, false, false, NULL, NULL }, 299 /* The exception vid: [1-8]+ (actual vector number starts from 1 to 8). */ 300 { "exception", 1, 8, false, false, false, false, NULL, NULL }, 301 /* Argument is user's interrupt numbers. The vector number is always 0. */ 302 { "reset", 1, 1, false, false, false, false, NULL, NULL }, 303 304 /* The attributes describing isr nested type. */ 305 { "nested", 0, 0, false, false, false, false, NULL, NULL }, 306 { "not_nested", 0, 0, false, false, false, false, NULL, NULL }, 307 { "nested_ready", 0, 0, false, false, false, false, NULL, NULL }, 308 { "critical", 0, 0, false, false, false, false, NULL, NULL }, 309 310 /* The attributes describing isr register save scheme. */ 311 { "save_all", 0, 0, false, false, false, false, NULL, NULL }, 312 { "partial_save", 0, 0, false, false, false, false, NULL, NULL }, 313 314 /* The attributes used by reset attribute. */ 315 { "nmi", 1, 1, false, false, false, false, NULL, NULL }, 316 { "warm", 1, 1, false, false, false, false, NULL, NULL }, 317 318 /* The attributes describing isr security level. */ 319 { "secure", 1, 1, false, false, false, false, NULL, NULL }, 320 321 /* The attribute telling no prologue/epilogue. */ 322 { "naked", 0, 0, false, false, false, false, NULL, NULL }, 323 324 /* The attribute is used to tell this function to be ROM patch. */ 325 { "indirect_call",0, 0, false, false, false, false, NULL, NULL }, 326 327 /* FOR BACKWARD COMPATIBILITY, 328 this attribute also tells no prologue/epilogue. */ 329 { "no_prologue", 0, 0, false, false, false, false, NULL, NULL }, 330 331 /* The last attribute spec is set to be NULL. */ 332 { NULL, 0, 0, false, false, false, false, NULL, NULL } 333 }; 334 335 336 /* ------------------------------------------------------------------------ */ 337 338 /* PART 2: Auxiliary static function definitions. */ 339 340 /* Function to save and restore machine-specific function data. */ 341 static struct machine_function * 342 nds32_init_machine_status (void) 343 { 344 struct machine_function *machine; 345 machine = ggc_cleared_alloc<machine_function> (); 346 347 /* Initially assume this function does not use __builtin_eh_return. */ 348 machine->use_eh_return_p = 0; 349 350 /* Initially assume this function needs prologue/epilogue. */ 351 machine->naked_p = 0; 352 353 /* Initially assume this function does NOT use fp_as_gp optimization. */ 354 machine->fp_as_gp_p = 0; 355 356 /* Initially this function is not under strictly aligned situation. */ 357 machine->strict_aligned_p = 0; 358 359 /* Initially this function has no naked and no_prologue attributes. */ 360 machine->attr_naked_p = 0; 361 machine->attr_no_prologue_p = 0; 362 363 return machine; 364 } 365 366 /* Function to compute stack frame size and 367 store into cfun->machine structure. */ 368 static void 369 nds32_compute_stack_frame (void) 370 { 371 int r; 372 int block_size; 373 bool v3pushpop_p; 374 375 /* Because nds32_compute_stack_frame() will be called from different place, 376 everytime we enter this function, we have to assume this function 377 needs prologue/epilogue. */ 378 cfun->machine->naked_p = 0; 379 380 /* We need to mark whether this function has naked and no_prologue 381 attribute so that we can distinguish the difference if users applies 382 -mret-in-naked-func option. */ 383 cfun->machine->attr_naked_p 384 = lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) 385 ? 1 : 0; 386 cfun->machine->attr_no_prologue_p 387 = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) 388 ? 1 : 0; 389 390 /* If __builtin_eh_return is used, we better have frame pointer needed 391 so that we can easily locate the stack slot of return address. */ 392 if (crtl->calls_eh_return) 393 { 394 frame_pointer_needed = 1; 395 396 /* We need to mark eh data registers that need to be saved 397 in the stack. */ 398 cfun->machine->eh_return_data_first_regno = EH_RETURN_DATA_REGNO (0); 399 for (r = 0; EH_RETURN_DATA_REGNO (r) != INVALID_REGNUM; r++) 400 cfun->machine->eh_return_data_last_regno = r; 401 402 cfun->machine->eh_return_data_regs_size 403 = 4 * (cfun->machine->eh_return_data_last_regno 404 - cfun->machine->eh_return_data_first_regno 405 + 1); 406 cfun->machine->use_eh_return_p = 1; 407 } 408 else 409 { 410 /* Assigning SP_REGNUM to eh_first_regno and eh_last_regno means we 411 do not need to handle __builtin_eh_return case in this function. */ 412 cfun->machine->eh_return_data_first_regno = SP_REGNUM; 413 cfun->machine->eh_return_data_last_regno = SP_REGNUM; 414 415 cfun->machine->eh_return_data_regs_size = 0; 416 cfun->machine->use_eh_return_p = 0; 417 } 418 419 /* Get variadic arguments size to prepare pretend arguments and 420 we will push them into stack at prologue by ourself. */ 421 cfun->machine->va_args_size = crtl->args.pretend_args_size; 422 if (cfun->machine->va_args_size != 0) 423 { 424 cfun->machine->va_args_first_regno 425 = NDS32_GPR_ARG_FIRST_REGNUM 426 + NDS32_MAX_GPR_REGS_FOR_ARGS 427 - (crtl->args.pretend_args_size / UNITS_PER_WORD); 428 cfun->machine->va_args_last_regno 429 = NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS - 1; 430 } 431 else 432 { 433 cfun->machine->va_args_first_regno = SP_REGNUM; 434 cfun->machine->va_args_last_regno = SP_REGNUM; 435 } 436 437 /* Important: We need to make sure that varargs area is 8-byte alignment. */ 438 block_size = cfun->machine->va_args_size; 439 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) 440 { 441 cfun->machine->va_args_area_padding_bytes 442 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; 443 } 444 445 /* Get local variables, incoming variables, and temporary variables size. 446 Note that we need to make sure it is 8-byte alignment because 447 there may be no padding bytes if we are using LRA. */ 448 cfun->machine->local_size = NDS32_ROUND_UP_DOUBLE_WORD (get_frame_size ()); 449 450 /* Get outgoing arguments size. */ 451 cfun->machine->out_args_size = crtl->outgoing_args_size; 452 453 /* If $fp value is required to be saved on stack, it needs 4 bytes space. 454 Check whether $fp is ever live. */ 455 cfun->machine->fp_size = (df_regs_ever_live_p (FP_REGNUM)) ? 4 : 0; 456 457 /* If $gp value is required to be saved on stack, it needs 4 bytes space. 458 Check whether we are using PIC code genration. */ 459 cfun->machine->gp_size = 460 (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) ? 4 : 0; 461 462 /* If $lp value is required to be saved on stack, it needs 4 bytes space. 463 Check whether $lp is ever live. */ 464 cfun->machine->lp_size 465 = (flag_always_save_lp || df_regs_ever_live_p (LP_REGNUM)) ? 4 : 0; 466 467 /* Initially there is no padding bytes. */ 468 cfun->machine->callee_saved_area_gpr_padding_bytes = 0; 469 470 /* Calculate the bytes of saving callee-saved registers on stack. */ 471 cfun->machine->callee_saved_gpr_regs_size = 0; 472 cfun->machine->callee_saved_first_gpr_regno = SP_REGNUM; 473 cfun->machine->callee_saved_last_gpr_regno = SP_REGNUM; 474 cfun->machine->callee_saved_fpr_regs_size = 0; 475 cfun->machine->callee_saved_first_fpr_regno = SP_REGNUM; 476 cfun->machine->callee_saved_last_fpr_regno = SP_REGNUM; 477 478 /* Currently, there is no need to check $r28~$r31 479 because we will save them in another way. */ 480 for (r = 0; r < 28; r++) 481 { 482 if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) 483 { 484 /* Mark the first required callee-saved register 485 (only need to set it once). 486 If first regno == SP_REGNUM, we can tell that 487 it is the first time to be here. */ 488 if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) 489 cfun->machine->callee_saved_first_gpr_regno = r; 490 /* Mark the last required callee-saved register. */ 491 cfun->machine->callee_saved_last_gpr_regno = r; 492 } 493 } 494 495 /* Recording fpu callee-saved register. */ 496 if (TARGET_HARD_FLOAT) 497 { 498 for (r = NDS32_FIRST_FPR_REGNUM; r < NDS32_LAST_FPR_REGNUM; r++) 499 { 500 if (NDS32_REQUIRED_CALLEE_SAVED_P (r)) 501 { 502 /* Mark the first required callee-saved register. */ 503 if (cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM) 504 { 505 /* Make first callee-saved number is even, 506 bacause we use doubleword access, and this way 507 promise 8-byte alignemt. */ 508 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (r)) 509 cfun->machine->callee_saved_first_fpr_regno = r - 1; 510 else 511 cfun->machine->callee_saved_first_fpr_regno = r; 512 } 513 cfun->machine->callee_saved_last_fpr_regno = r; 514 } 515 } 516 517 /* Make last callee-saved register number is odd, 518 we hope callee-saved register is even. */ 519 int last_fpr = cfun->machine->callee_saved_last_fpr_regno; 520 if (NDS32_FPR_REGNO_OK_FOR_DOUBLE (last_fpr)) 521 cfun->machine->callee_saved_last_fpr_regno++; 522 } 523 524 /* Check if this function can omit prologue/epilogue code fragment. 525 If there is 'no_prologue'/'naked'/'secure' attribute in this function, 526 we can set 'naked_p' flag to indicate that 527 we do not have to generate prologue/epilogue. 528 Or, if all the following conditions succeed, 529 we can set this function 'naked_p' as well: 530 condition 1: first_regno == last_regno == SP_REGNUM, 531 which means we do not have to save 532 any callee-saved registers. 533 condition 2: Both $lp and $fp are NOT live in this function, 534 which means we do not need to save them and there 535 is no outgoing size. 536 condition 3: There is no local_size, which means 537 we do not need to adjust $sp. */ 538 if (lookup_attribute ("no_prologue", DECL_ATTRIBUTES (current_function_decl)) 539 || lookup_attribute ("naked", DECL_ATTRIBUTES (current_function_decl)) 540 || lookup_attribute ("secure", DECL_ATTRIBUTES (current_function_decl)) 541 || (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM 542 && cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM 543 && cfun->machine->callee_saved_first_fpr_regno == SP_REGNUM 544 && cfun->machine->callee_saved_last_fpr_regno == SP_REGNUM 545 && !df_regs_ever_live_p (FP_REGNUM) 546 && !df_regs_ever_live_p (LP_REGNUM) 547 && cfun->machine->local_size == 0 548 && !flag_pic)) 549 { 550 /* Set this function 'naked_p' and other functions can check this flag. 551 Note that in nds32 port, the 'naked_p = 1' JUST means there is no 552 callee-saved, local size, and outgoing size. 553 The varargs space and ret instruction may still present in 554 the prologue/epilogue expanding. */ 555 cfun->machine->naked_p = 1; 556 557 /* No need to save $fp, $gp, and $lp. 558 We should set these value to be zero 559 so that nds32_initial_elimination_offset() can work properly. */ 560 cfun->machine->fp_size = 0; 561 cfun->machine->gp_size = 0; 562 cfun->machine->lp_size = 0; 563 564 /* If stack usage computation is required, 565 we need to provide the static stack size. */ 566 if (flag_stack_usage_info) 567 current_function_static_stack_size = 0; 568 569 /* No need to do following adjustment, return immediately. */ 570 return; 571 } 572 573 v3pushpop_p = NDS32_V3PUSH_AVAILABLE_P; 574 575 /* Adjustment for v3push instructions: 576 If we are using v3push (push25/pop25) instructions, 577 we need to make sure Rb is $r6 and Re is 578 located on $r6, $r8, $r10, or $r14. 579 Some results above will be discarded and recomputed. 580 Note that it is only available under V3/V3M ISA and we 581 DO NOT setup following stuff for isr or variadic function. */ 582 if (v3pushpop_p) 583 { 584 /* Recompute: 585 cfun->machine->fp_size 586 cfun->machine->gp_size 587 cfun->machine->lp_size 588 cfun->machine->callee_saved_first_gpr_regno 589 cfun->machine->callee_saved_last_gpr_regno */ 590 591 /* For v3push instructions, $fp, $gp, and $lp are always saved. */ 592 cfun->machine->fp_size = 4; 593 cfun->machine->gp_size = 4; 594 cfun->machine->lp_size = 4; 595 596 /* Remember to set Rb = $r6. */ 597 cfun->machine->callee_saved_first_gpr_regno = 6; 598 599 if (cfun->machine->callee_saved_last_gpr_regno <= 6) 600 { 601 /* Re = $r6 */ 602 cfun->machine->callee_saved_last_gpr_regno = 6; 603 } 604 else if (cfun->machine->callee_saved_last_gpr_regno <= 8) 605 { 606 /* Re = $r8 */ 607 cfun->machine->callee_saved_last_gpr_regno = 8; 608 } 609 else if (cfun->machine->callee_saved_last_gpr_regno <= 10) 610 { 611 /* Re = $r10 */ 612 cfun->machine->callee_saved_last_gpr_regno = 10; 613 } 614 else if (cfun->machine->callee_saved_last_gpr_regno <= 14) 615 { 616 /* Re = $r14 */ 617 cfun->machine->callee_saved_last_gpr_regno = 14; 618 } 619 else if (cfun->machine->callee_saved_last_gpr_regno == SP_REGNUM) 620 { 621 /* If last_regno is SP_REGNUM, which means 622 it is never changed, so set it to Re = $r6. */ 623 cfun->machine->callee_saved_last_gpr_regno = 6; 624 } 625 else 626 { 627 /* The program flow should not go here. */ 628 gcc_unreachable (); 629 } 630 } 631 632 int sp_adjust = cfun->machine->local_size 633 + cfun->machine->out_args_size 634 + cfun->machine->callee_saved_area_gpr_padding_bytes 635 + cfun->machine->callee_saved_fpr_regs_size; 636 637 if (!v3pushpop_p 638 && sp_adjust == 0 639 && !frame_pointer_needed) 640 { 641 block_size = cfun->machine->fp_size 642 + cfun->machine->gp_size 643 + cfun->machine->lp_size; 644 645 if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) 646 block_size += (4 * (cfun->machine->callee_saved_last_gpr_regno 647 - cfun->machine->callee_saved_first_gpr_regno 648 + 1)); 649 650 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) 651 { 652 /* $r14 is last callee save register. */ 653 if (cfun->machine->callee_saved_last_gpr_regno 654 < NDS32_LAST_CALLEE_SAVE_GPR_REGNUM) 655 { 656 cfun->machine->callee_saved_last_gpr_regno++; 657 } 658 else if (cfun->machine->callee_saved_first_gpr_regno == SP_REGNUM) 659 { 660 cfun->machine->callee_saved_first_gpr_regno 661 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; 662 cfun->machine->callee_saved_last_gpr_regno 663 = NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM; 664 } 665 } 666 } 667 668 /* We have correctly set callee_saved_first_gpr_regno 669 and callee_saved_last_gpr_regno. 670 Initially, the callee_saved_gpr_regs_size is supposed to be 0. 671 As long as callee_saved_last_gpr_regno is not SP_REGNUM, 672 we can update callee_saved_gpr_regs_size with new size. */ 673 if (cfun->machine->callee_saved_last_gpr_regno != SP_REGNUM) 674 { 675 /* Compute pushed size of callee-saved registers. */ 676 cfun->machine->callee_saved_gpr_regs_size 677 = 4 * (cfun->machine->callee_saved_last_gpr_regno 678 - cfun->machine->callee_saved_first_gpr_regno 679 + 1); 680 } 681 682 if (TARGET_HARD_FLOAT) 683 { 684 /* Compute size of callee svaed floating-point registers. */ 685 if (cfun->machine->callee_saved_last_fpr_regno != SP_REGNUM) 686 { 687 cfun->machine->callee_saved_fpr_regs_size 688 = 4 * (cfun->machine->callee_saved_last_fpr_regno 689 - cfun->machine->callee_saved_first_fpr_regno 690 + 1); 691 } 692 } 693 694 /* Important: We need to make sure that 695 (fp_size + gp_size + lp_size + callee_saved_gpr_regs_size) 696 is 8-byte alignment. 697 If it is not, calculate the padding bytes. */ 698 block_size = cfun->machine->fp_size 699 + cfun->machine->gp_size 700 + cfun->machine->lp_size 701 + cfun->machine->callee_saved_gpr_regs_size; 702 if (!NDS32_DOUBLE_WORD_ALIGN_P (block_size)) 703 { 704 cfun->machine->callee_saved_area_gpr_padding_bytes 705 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) - block_size; 706 } 707 708 /* If stack usage computation is required, 709 we need to provide the static stack size. */ 710 if (flag_stack_usage_info) 711 { 712 current_function_static_stack_size 713 = NDS32_ROUND_UP_DOUBLE_WORD (block_size) 714 + cfun->machine->local_size 715 + cfun->machine->out_args_size; 716 } 717 } 718 719 /* Function to create a parallel rtx pattern 720 which presents stack push multiple behavior. 721 The overall concept are: 722 "push registers to memory", 723 "adjust stack pointer". */ 724 static void 725 nds32_emit_stack_push_multiple (unsigned Rb, unsigned Re, 726 bool save_fp_p, bool save_gp_p, bool save_lp_p, 727 bool vaarg_p) 728 { 729 unsigned regno; 730 int extra_count; 731 int num_use_regs; 732 int par_index; 733 int offset; 734 735 rtx reg; 736 rtx mem; 737 rtx push_rtx; 738 rtx adjust_sp_rtx; 739 rtx parallel_insn; 740 rtx dwarf; 741 742 /* We need to provide a customized rtx which contains 743 necessary information for data analysis, 744 so we create a parallel rtx like this: 745 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) 746 (reg:SI Rb)) 747 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) 748 (reg:SI Rb+1)) 749 ... 750 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) 751 (reg:SI Re)) 752 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) 753 (reg:SI FP_REGNUM)) 754 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) 755 (reg:SI GP_REGNUM)) 756 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) 757 (reg:SI LP_REGNUM)) 758 (set (reg:SI SP_REGNUM) 759 (plus (reg:SI SP_REGNUM) (const_int -32)))]) */ 760 761 /* Calculate the number of registers that will be pushed. */ 762 extra_count = 0; 763 if (save_fp_p) 764 extra_count++; 765 if (save_gp_p) 766 extra_count++; 767 if (save_lp_p) 768 extra_count++; 769 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ 770 if (Rb == SP_REGNUM && Re == SP_REGNUM) 771 num_use_regs = extra_count; 772 else 773 num_use_regs = Re - Rb + 1 + extra_count; 774 775 /* In addition to used registers, 776 we need one more space for (set sp sp-x) rtx. */ 777 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 778 rtvec_alloc (num_use_regs + 1)); 779 par_index = 0; 780 781 /* Initialize offset and start to create push behavior. */ 782 offset = -(num_use_regs * 4); 783 784 /* Create (set mem regX) from Rb, Rb+1 up to Re. */ 785 for (regno = Rb; regno <= Re; regno++) 786 { 787 /* Rb and Re may be SP_REGNUM. 788 We need to break this loop immediately. */ 789 if (regno == SP_REGNUM) 790 break; 791 792 reg = gen_rtx_REG (SImode, regno); 793 mem = gen_frame_mem (SImode, plus_constant (Pmode, 794 stack_pointer_rtx, 795 offset)); 796 push_rtx = gen_rtx_SET (mem, reg); 797 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 798 RTX_FRAME_RELATED_P (push_rtx) = 1; 799 offset = offset + 4; 800 par_index++; 801 } 802 803 /* Create (set mem fp), (set mem gp), and (set mem lp) if necessary. */ 804 if (save_fp_p) 805 { 806 reg = gen_rtx_REG (SImode, FP_REGNUM); 807 mem = gen_frame_mem (SImode, plus_constant (Pmode, 808 stack_pointer_rtx, 809 offset)); 810 push_rtx = gen_rtx_SET (mem, reg); 811 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 812 RTX_FRAME_RELATED_P (push_rtx) = 1; 813 offset = offset + 4; 814 par_index++; 815 } 816 if (save_gp_p) 817 { 818 reg = gen_rtx_REG (SImode, GP_REGNUM); 819 mem = gen_frame_mem (SImode, plus_constant (Pmode, 820 stack_pointer_rtx, 821 offset)); 822 push_rtx = gen_rtx_SET (mem, reg); 823 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 824 RTX_FRAME_RELATED_P (push_rtx) = 1; 825 offset = offset + 4; 826 par_index++; 827 } 828 if (save_lp_p) 829 { 830 reg = gen_rtx_REG (SImode, LP_REGNUM); 831 mem = gen_frame_mem (SImode, plus_constant (Pmode, 832 stack_pointer_rtx, 833 offset)); 834 push_rtx = gen_rtx_SET (mem, reg); 835 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 836 RTX_FRAME_RELATED_P (push_rtx) = 1; 837 offset = offset + 4; 838 par_index++; 839 } 840 841 /* Create (set sp sp-x). */ 842 843 /* We need to re-calculate the offset value again for adjustment. */ 844 offset = -(num_use_regs * 4); 845 adjust_sp_rtx 846 = gen_rtx_SET (stack_pointer_rtx, 847 plus_constant (Pmode, stack_pointer_rtx, offset)); 848 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 849 RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; 850 851 parallel_insn = emit_insn (parallel_insn); 852 853 /* The insn rtx 'parallel_insn' will change frame layout. 854 We need to use RTX_FRAME_RELATED_P so that GCC is able to 855 generate CFI (Call Frame Information) stuff. */ 856 RTX_FRAME_RELATED_P (parallel_insn) = 1; 857 858 /* Don't use GCC's logic for CFI info if we are generate a push for VAARG 859 since we will not restore those register at epilogue. */ 860 if (vaarg_p) 861 { 862 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, 863 copy_rtx (adjust_sp_rtx), NULL_RTX); 864 REG_NOTES (parallel_insn) = dwarf; 865 } 866 } 867 868 /* Function to create a parallel rtx pattern 869 which presents stack pop multiple behavior. 870 The overall concept are: 871 "pop registers from memory", 872 "adjust stack pointer". */ 873 static void 874 nds32_emit_stack_pop_multiple (unsigned Rb, unsigned Re, 875 bool save_fp_p, bool save_gp_p, bool save_lp_p) 876 { 877 unsigned regno; 878 int extra_count; 879 int num_use_regs; 880 int par_index; 881 int offset; 882 883 rtx reg; 884 rtx mem; 885 rtx pop_rtx; 886 rtx adjust_sp_rtx; 887 rtx parallel_insn; 888 rtx dwarf = NULL_RTX; 889 890 /* We need to provide a customized rtx which contains 891 necessary information for data analysis, 892 so we create a parallel rtx like this: 893 (parallel [(set (reg:SI Rb) 894 (mem (reg:SI SP_REGNUM))) 895 (set (reg:SI Rb+1) 896 (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) 897 ... 898 (set (reg:SI Re) 899 (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) 900 (set (reg:SI FP_REGNUM) 901 (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) 902 (set (reg:SI GP_REGNUM) 903 (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) 904 (set (reg:SI LP_REGNUM) 905 (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) 906 (set (reg:SI SP_REGNUM) 907 (plus (reg:SI SP_REGNUM) (const_int 32)))]) */ 908 909 /* Calculate the number of registers that will be poped. */ 910 extra_count = 0; 911 if (save_fp_p) 912 extra_count++; 913 if (save_gp_p) 914 extra_count++; 915 if (save_lp_p) 916 extra_count++; 917 /* Note that Rb and Re may be SP_REGNUM. DO NOT count it in. */ 918 if (Rb == SP_REGNUM && Re == SP_REGNUM) 919 num_use_regs = extra_count; 920 else 921 num_use_regs = Re - Rb + 1 + extra_count; 922 923 /* In addition to used registers, 924 we need one more space for (set sp sp+x) rtx. */ 925 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 926 rtvec_alloc (num_use_regs + 1)); 927 par_index = 0; 928 929 /* Initialize offset and start to create pop behavior. */ 930 offset = 0; 931 932 /* Create (set regX mem) from Rb, Rb+1 up to Re. */ 933 for (regno = Rb; regno <= Re; regno++) 934 { 935 /* Rb and Re may be SP_REGNUM. 936 We need to break this loop immediately. */ 937 if (regno == SP_REGNUM) 938 break; 939 940 reg = gen_rtx_REG (SImode, regno); 941 mem = gen_frame_mem (SImode, plus_constant (Pmode, 942 stack_pointer_rtx, 943 offset)); 944 pop_rtx = gen_rtx_SET (reg, mem); 945 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 946 RTX_FRAME_RELATED_P (pop_rtx) = 1; 947 offset = offset + 4; 948 par_index++; 949 950 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 951 } 952 953 /* Create (set fp mem), (set gp mem), and (set lp mem) if necessary. */ 954 if (save_fp_p) 955 { 956 reg = gen_rtx_REG (SImode, FP_REGNUM); 957 mem = gen_frame_mem (SImode, plus_constant (Pmode, 958 stack_pointer_rtx, 959 offset)); 960 pop_rtx = gen_rtx_SET (reg, mem); 961 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 962 RTX_FRAME_RELATED_P (pop_rtx) = 1; 963 offset = offset + 4; 964 par_index++; 965 966 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 967 } 968 if (save_gp_p) 969 { 970 reg = gen_rtx_REG (SImode, GP_REGNUM); 971 mem = gen_frame_mem (SImode, plus_constant (Pmode, 972 stack_pointer_rtx, 973 offset)); 974 pop_rtx = gen_rtx_SET (reg, mem); 975 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 976 RTX_FRAME_RELATED_P (pop_rtx) = 1; 977 offset = offset + 4; 978 par_index++; 979 980 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 981 } 982 if (save_lp_p) 983 { 984 reg = gen_rtx_REG (SImode, LP_REGNUM); 985 mem = gen_frame_mem (SImode, plus_constant (Pmode, 986 stack_pointer_rtx, 987 offset)); 988 pop_rtx = gen_rtx_SET (reg, mem); 989 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 990 RTX_FRAME_RELATED_P (pop_rtx) = 1; 991 offset = offset + 4; 992 par_index++; 993 994 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 995 } 996 997 /* Create (set sp sp+x). */ 998 999 /* The offset value is already in place. No need to re-calculate it. */ 1000 adjust_sp_rtx 1001 = gen_rtx_SET (stack_pointer_rtx, 1002 plus_constant (Pmode, stack_pointer_rtx, offset)); 1003 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 1004 1005 /* Tell gcc we adjust SP in this insn. */ 1006 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, copy_rtx (adjust_sp_rtx), dwarf); 1007 1008 parallel_insn = emit_insn (parallel_insn); 1009 1010 /* The insn rtx 'parallel_insn' will change frame layout. 1011 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1012 generate CFI (Call Frame Information) stuff. */ 1013 RTX_FRAME_RELATED_P (parallel_insn) = 1; 1014 1015 /* Add CFI info by manual. */ 1016 REG_NOTES (parallel_insn) = dwarf; 1017 } 1018 1019 /* Function to create a parallel rtx pattern 1020 which presents stack v3push behavior. 1021 The overall concept are: 1022 "push registers to memory", 1023 "adjust stack pointer". */ 1024 static void 1025 nds32_emit_stack_v3push (unsigned Rb, 1026 unsigned Re, 1027 unsigned imm8u) 1028 { 1029 unsigned regno; 1030 int num_use_regs; 1031 int par_index; 1032 int offset; 1033 1034 rtx reg; 1035 rtx mem; 1036 rtx push_rtx; 1037 rtx adjust_sp_rtx; 1038 rtx parallel_insn; 1039 1040 /* We need to provide a customized rtx which contains 1041 necessary information for data analysis, 1042 so we create a parallel rtx like this: 1043 (parallel [(set (mem (plus (reg:SI SP_REGNUM) (const_int -32))) 1044 (reg:SI Rb)) 1045 (set (mem (plus (reg:SI SP_REGNUM) (const_int -28))) 1046 (reg:SI Rb+1)) 1047 ... 1048 (set (mem (plus (reg:SI SP_REGNUM) (const_int -16))) 1049 (reg:SI Re)) 1050 (set (mem (plus (reg:SI SP_REGNUM) (const_int -12))) 1051 (reg:SI FP_REGNUM)) 1052 (set (mem (plus (reg:SI SP_REGNUM) (const_int -8))) 1053 (reg:SI GP_REGNUM)) 1054 (set (mem (plus (reg:SI SP_REGNUM) (const_int -4))) 1055 (reg:SI LP_REGNUM)) 1056 (set (reg:SI SP_REGNUM) 1057 (plus (reg:SI SP_REGNUM) (const_int -32-imm8u)))]) */ 1058 1059 /* Calculate the number of registers that will be pushed. 1060 Since $fp, $gp, and $lp is always pushed with v3push instruction, 1061 we need to count these three registers. 1062 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1063 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1064 num_use_regs = Re - Rb + 1 + 3; 1065 1066 /* In addition to used registers, 1067 we need one more space for (set sp sp-x-imm8u) rtx. */ 1068 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 1069 rtvec_alloc (num_use_regs + 1)); 1070 par_index = 0; 1071 1072 /* Initialize offset and start to create push behavior. */ 1073 offset = -(num_use_regs * 4); 1074 1075 /* Create (set mem regX) from Rb, Rb+1 up to Re. 1076 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1077 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1078 for (regno = Rb; regno <= Re; regno++) 1079 { 1080 reg = gen_rtx_REG (SImode, regno); 1081 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1082 stack_pointer_rtx, 1083 offset)); 1084 push_rtx = gen_rtx_SET (mem, reg); 1085 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1086 RTX_FRAME_RELATED_P (push_rtx) = 1; 1087 offset = offset + 4; 1088 par_index++; 1089 } 1090 1091 /* Create (set mem fp). */ 1092 reg = gen_rtx_REG (SImode, FP_REGNUM); 1093 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1094 stack_pointer_rtx, 1095 offset)); 1096 push_rtx = gen_rtx_SET (mem, reg); 1097 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1098 RTX_FRAME_RELATED_P (push_rtx) = 1; 1099 offset = offset + 4; 1100 par_index++; 1101 /* Create (set mem gp). */ 1102 reg = gen_rtx_REG (SImode, GP_REGNUM); 1103 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1104 stack_pointer_rtx, 1105 offset)); 1106 push_rtx = gen_rtx_SET (mem, reg); 1107 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1108 RTX_FRAME_RELATED_P (push_rtx) = 1; 1109 offset = offset + 4; 1110 par_index++; 1111 /* Create (set mem lp). */ 1112 reg = gen_rtx_REG (SImode, LP_REGNUM); 1113 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1114 stack_pointer_rtx, 1115 offset)); 1116 push_rtx = gen_rtx_SET (mem, reg); 1117 XVECEXP (parallel_insn, 0, par_index) = push_rtx; 1118 RTX_FRAME_RELATED_P (push_rtx) = 1; 1119 offset = offset + 4; 1120 par_index++; 1121 1122 /* Create (set sp sp-x-imm8u). */ 1123 1124 /* We need to re-calculate the offset value again for adjustment. */ 1125 offset = -(num_use_regs * 4); 1126 adjust_sp_rtx 1127 = gen_rtx_SET (stack_pointer_rtx, 1128 plus_constant (Pmode, 1129 stack_pointer_rtx, 1130 offset - imm8u)); 1131 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 1132 RTX_FRAME_RELATED_P (adjust_sp_rtx) = 1; 1133 1134 parallel_insn = emit_insn (parallel_insn); 1135 1136 /* The insn rtx 'parallel_insn' will change frame layout. 1137 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1138 generate CFI (Call Frame Information) stuff. */ 1139 RTX_FRAME_RELATED_P (parallel_insn) = 1; 1140 } 1141 1142 /* Function to create a parallel rtx pattern 1143 which presents stack v3pop behavior. 1144 The overall concept are: 1145 "pop registers from memory", 1146 "adjust stack pointer". */ 1147 static void 1148 nds32_emit_stack_v3pop (unsigned Rb, 1149 unsigned Re, 1150 unsigned imm8u) 1151 { 1152 unsigned regno; 1153 int num_use_regs; 1154 int par_index; 1155 int offset; 1156 1157 rtx reg; 1158 rtx mem; 1159 rtx pop_rtx; 1160 rtx adjust_sp_rtx; 1161 rtx parallel_insn; 1162 rtx dwarf = NULL_RTX; 1163 1164 /* We need to provide a customized rtx which contains 1165 necessary information for data analysis, 1166 so we create a parallel rtx like this: 1167 (parallel [(set (reg:SI Rb) 1168 (mem (reg:SI SP_REGNUM))) 1169 (set (reg:SI Rb+1) 1170 (mem (plus (reg:SI SP_REGNUM) (const_int 4)))) 1171 ... 1172 (set (reg:SI Re) 1173 (mem (plus (reg:SI SP_REGNUM) (const_int 16)))) 1174 (set (reg:SI FP_REGNUM) 1175 (mem (plus (reg:SI SP_REGNUM) (const_int 20)))) 1176 (set (reg:SI GP_REGNUM) 1177 (mem (plus (reg:SI SP_REGNUM) (const_int 24)))) 1178 (set (reg:SI LP_REGNUM) 1179 (mem (plus (reg:SI SP_REGNUM) (const_int 28)))) 1180 (set (reg:SI SP_REGNUM) 1181 (plus (reg:SI SP_REGNUM) (const_int 32+imm8u)))]) */ 1182 1183 /* Calculate the number of registers that will be poped. 1184 Since $fp, $gp, and $lp is always poped with v3pop instruction, 1185 we need to count these three registers. 1186 Under v3push, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1187 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1188 num_use_regs = Re - Rb + 1 + 3; 1189 1190 /* In addition to used registers, 1191 we need one more space for (set sp sp+x+imm8u) rtx. */ 1192 parallel_insn = gen_rtx_PARALLEL (VOIDmode, 1193 rtvec_alloc (num_use_regs + 1)); 1194 par_index = 0; 1195 1196 /* Initialize offset and start to create pop behavior. */ 1197 offset = 0; 1198 1199 /* Create (set regX mem) from Rb, Rb+1 up to Re. 1200 Under v3pop, Rb is $r6, while Re is $r6, $r8, $r10, or $r14. 1201 So there is no need to worry about Rb=Re=SP_REGNUM case. */ 1202 for (regno = Rb; regno <= Re; regno++) 1203 { 1204 reg = gen_rtx_REG (SImode, regno); 1205 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1206 stack_pointer_rtx, 1207 offset)); 1208 pop_rtx = gen_rtx_SET (reg, mem); 1209 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1210 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1211 offset = offset + 4; 1212 par_index++; 1213 1214 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1215 } 1216 1217 /* Create (set fp mem). */ 1218 reg = gen_rtx_REG (SImode, FP_REGNUM); 1219 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1220 stack_pointer_rtx, 1221 offset)); 1222 pop_rtx = gen_rtx_SET (reg, mem); 1223 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1224 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1225 offset = offset + 4; 1226 par_index++; 1227 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1228 1229 /* Create (set gp mem). */ 1230 reg = gen_rtx_REG (SImode, GP_REGNUM); 1231 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1232 stack_pointer_rtx, 1233 offset)); 1234 pop_rtx = gen_rtx_SET (reg, mem); 1235 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1236 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1237 offset = offset + 4; 1238 par_index++; 1239 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1240 1241 /* Create (set lp mem ). */ 1242 reg = gen_rtx_REG (SImode, LP_REGNUM); 1243 mem = gen_frame_mem (SImode, plus_constant (Pmode, 1244 stack_pointer_rtx, 1245 offset)); 1246 pop_rtx = gen_rtx_SET (reg, mem); 1247 XVECEXP (parallel_insn, 0, par_index) = pop_rtx; 1248 RTX_FRAME_RELATED_P (pop_rtx) = 1; 1249 offset = offset + 4; 1250 par_index++; 1251 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 1252 1253 /* Create (set sp sp+x+imm8u). */ 1254 1255 /* The offset value is already in place. No need to re-calculate it. */ 1256 adjust_sp_rtx 1257 = gen_rtx_SET (stack_pointer_rtx, 1258 plus_constant (Pmode, 1259 stack_pointer_rtx, 1260 offset + imm8u)); 1261 XVECEXP (parallel_insn, 0, par_index) = adjust_sp_rtx; 1262 1263 if (frame_pointer_needed) 1264 { 1265 /* (expr_list:REG_CFA_DEF_CFA (plus:SI (reg/f:SI $sp) 1266 (const_int 0)) 1267 mean reset frame pointer to $sp and reset to offset 0. */ 1268 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 1269 const0_rtx); 1270 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 1271 } 1272 else 1273 { 1274 /* Tell gcc we adjust SP in this insn. */ 1275 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, 1276 copy_rtx (adjust_sp_rtx), dwarf); 1277 } 1278 1279 parallel_insn = emit_insn (parallel_insn); 1280 1281 /* The insn rtx 'parallel_insn' will change frame layout. 1282 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1283 generate CFI (Call Frame Information) stuff. */ 1284 RTX_FRAME_RELATED_P (parallel_insn) = 1; 1285 1286 /* Add CFI info by manual. */ 1287 REG_NOTES (parallel_insn) = dwarf; 1288 } 1289 1290 static void 1291 nds32_emit_load_gp (void) 1292 { 1293 rtx got_symbol, pat; 1294 1295 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ 1296 emit_insn (gen_blockage ()); 1297 1298 got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 1299 /* sethi $gp, _GLOBAL_OFFSET_TABLE_ -8 */ 1300 pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); 1301 pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-8))); 1302 emit_insn (gen_sethi (pic_offset_table_rtx,pat)); 1303 1304 /* ori $gp, $gp, _GLOBAL_OFFSET_TABLE_ -4 */ 1305 pat = gen_rtx_UNSPEC (SImode, gen_rtvec (1, got_symbol), UNSPEC_GOTINIT); 1306 pat = gen_rtx_CONST (SImode, gen_rtx_PLUS (Pmode, pat, GEN_INT (-4))); 1307 emit_insn (gen_lo_sum (pic_offset_table_rtx, pic_offset_table_rtx, pat)); 1308 1309 /* add5.pc $gp */ 1310 emit_insn (gen_add_pc (pic_offset_table_rtx, pic_offset_table_rtx)); 1311 1312 /* Initial GLOBAL OFFSET TABLE don't do the scheduling. */ 1313 emit_insn (gen_blockage ()); 1314 } 1315 1316 /* Function that may creates more instructions 1317 for large value on adjusting stack pointer. 1318 1319 In nds32 target, 'addi' can be used for stack pointer 1320 adjustment in prologue/epilogue stage. 1321 However, sometimes there are too many local variables so that 1322 the adjustment value is not able to be fit in the 'addi' instruction. 1323 One solution is to move value into a register 1324 and then use 'add' instruction. 1325 In practice, we use TA_REGNUM ($r15) to accomplish this purpose. */ 1326 static void 1327 nds32_emit_adjust_frame (rtx to_reg, rtx from_reg, int adjust_value) 1328 { 1329 rtx tmp_reg; 1330 rtx frame_adjust_insn; 1331 rtx adjust_value_rtx = GEN_INT (adjust_value); 1332 1333 if (adjust_value == 0) 1334 return; 1335 1336 if (!satisfies_constraint_Is15 (adjust_value_rtx)) 1337 { 1338 /* The value is not able to fit in single addi instruction. 1339 Create more instructions of moving value into a register 1340 and then add stack pointer with it. */ 1341 1342 /* $r15 is going to be temporary register to hold the value. */ 1343 tmp_reg = gen_rtx_REG (SImode, TA_REGNUM); 1344 1345 /* Create one more instruction to move value 1346 into the temporary register. */ 1347 emit_move_insn (tmp_reg, adjust_value_rtx); 1348 1349 /* Create new 'add' rtx. */ 1350 frame_adjust_insn = gen_addsi3 (to_reg, 1351 from_reg, 1352 tmp_reg); 1353 /* Emit rtx into insn list and receive its transformed insn rtx. */ 1354 frame_adjust_insn = emit_insn (frame_adjust_insn); 1355 1356 /* Because (tmp_reg <- full_value) may be split into two 1357 rtl patterns, we cannot set its RTX_FRAME_RELATED_P. 1358 We need to construct another (sp <- sp + full_value) 1359 and then insert it into sp_adjust_insn's reg note to 1360 represent a frame related expression. 1361 GCC knows how to refer it and output debug information. */ 1362 1363 rtx plus_rtx; 1364 rtx set_rtx; 1365 1366 plus_rtx = plus_constant (Pmode, from_reg, adjust_value); 1367 set_rtx = gen_rtx_SET (to_reg, plus_rtx); 1368 add_reg_note (frame_adjust_insn, REG_FRAME_RELATED_EXPR, set_rtx); 1369 } 1370 else 1371 { 1372 /* Generate sp adjustment instruction if and only if sp_adjust != 0. */ 1373 frame_adjust_insn = gen_addsi3 (to_reg, 1374 from_reg, 1375 adjust_value_rtx); 1376 /* Emit rtx into instructions list and receive INSN rtx form. */ 1377 frame_adjust_insn = emit_insn (frame_adjust_insn); 1378 } 1379 1380 /* The insn rtx 'sp_adjust_insn' will change frame layout. 1381 We need to use RTX_FRAME_RELATED_P so that GCC is able to 1382 generate CFI (Call Frame Information) stuff. */ 1383 RTX_FRAME_RELATED_P (frame_adjust_insn) = 1; 1384 } 1385 1386 /* Return true if MODE/TYPE need double word alignment. */ 1387 static bool 1388 nds32_needs_double_word_align (machine_mode mode, const_tree type) 1389 { 1390 unsigned int align; 1391 1392 /* Pick up the alignment according to the mode or type. */ 1393 align = NDS32_MODE_TYPE_ALIGN (mode, type); 1394 1395 return (align > PARM_BOUNDARY); 1396 } 1397 1398 /* Return true if FUNC is a naked function. */ 1399 bool 1400 nds32_naked_function_p (tree func) 1401 { 1402 /* FOR BACKWARD COMPATIBILITY, 1403 we need to support 'no_prologue' attribute as well. */ 1404 tree t_naked; 1405 tree t_no_prologue; 1406 1407 if (TREE_CODE (func) != FUNCTION_DECL) 1408 abort (); 1409 1410 /* We have to use lookup_attribute() to check attributes. 1411 Because attr_naked_p and attr_no_prologue_p are set in 1412 nds32_compute_stack_frame() and the function has not been 1413 invoked yet. */ 1414 t_naked = lookup_attribute ("naked", DECL_ATTRIBUTES (func)); 1415 t_no_prologue = lookup_attribute ("no_prologue", DECL_ATTRIBUTES (func)); 1416 1417 return ((t_naked != NULL_TREE) || (t_no_prologue != NULL_TREE)); 1418 } 1419 1420 /* Function that determine whether a load postincrement is a good thing to use 1421 for a given mode. */ 1422 bool 1423 nds32_use_load_post_increment (machine_mode mode) 1424 { 1425 return (GET_MODE_SIZE (mode) <= GET_MODE_SIZE(E_DImode)); 1426 } 1427 1428 /* Function that check if 'X' is a valid address register. 1429 The variable 'STRICT' is very important to 1430 make decision for register number. 1431 1432 STRICT : true 1433 => We are in reload pass or after reload pass. 1434 The register number should be strictly limited in general registers. 1435 1436 STRICT : false 1437 => Before reload pass, we are free to use any register number. */ 1438 static bool 1439 nds32_address_register_rtx_p (rtx x, bool strict) 1440 { 1441 int regno; 1442 1443 if (GET_CODE (x) != REG) 1444 return false; 1445 1446 regno = REGNO (x); 1447 1448 if (strict) 1449 return REGNO_OK_FOR_BASE_P (regno); 1450 else 1451 return true; 1452 } 1453 1454 /* Function that check if 'INDEX' is valid to be a index rtx for address. 1455 1456 OUTER_MODE : Machine mode of outer address rtx. 1457 INDEX : Check if this rtx is valid to be a index for address. 1458 STRICT : If it is true, we are in reload pass or after reload pass. */ 1459 static bool 1460 nds32_legitimate_index_p (machine_mode outer_mode, 1461 rtx index, 1462 bool strict) 1463 { 1464 int regno; 1465 rtx op0; 1466 rtx op1; 1467 1468 switch (GET_CODE (index)) 1469 { 1470 case REG: 1471 regno = REGNO (index); 1472 /* If we are in reload pass or after reload pass, 1473 we need to limit it to general register. */ 1474 if (strict) 1475 return REGNO_OK_FOR_INDEX_P (regno); 1476 else 1477 return true; 1478 1479 case CONST_INT: 1480 /* The alignment of the integer value is determined by 'outer_mode'. */ 1481 switch (GET_MODE_SIZE (outer_mode)) 1482 { 1483 case 1: 1484 /* Further check if the value is legal for the 'outer_mode'. */ 1485 if (satisfies_constraint_Is15 (index)) 1486 return true; 1487 break; 1488 1489 case 2: 1490 /* Further check if the value is legal for the 'outer_mode'. */ 1491 if (satisfies_constraint_Is16 (index)) 1492 { 1493 /* If it is not under strictly aligned situation, 1494 we can return true without checking alignment. */ 1495 if (!cfun->machine->strict_aligned_p) 1496 return true; 1497 /* Make sure address is half word alignment. */ 1498 else if (NDS32_HALF_WORD_ALIGN_P (INTVAL (index))) 1499 return true; 1500 } 1501 break; 1502 1503 case 4: 1504 /* Further check if the value is legal for the 'outer_mode'. */ 1505 if (satisfies_constraint_Is17 (index)) 1506 { 1507 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) 1508 { 1509 if (!satisfies_constraint_Is14 (index)) 1510 return false; 1511 } 1512 1513 /* If it is not under strictly aligned situation, 1514 we can return true without checking alignment. */ 1515 if (!cfun->machine->strict_aligned_p) 1516 return true; 1517 /* Make sure address is word alignment. */ 1518 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) 1519 return true; 1520 } 1521 break; 1522 1523 case 8: 1524 if (satisfies_constraint_Is17 (gen_int_mode (INTVAL (index) + 4, 1525 SImode))) 1526 { 1527 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) 1528 { 1529 if (!satisfies_constraint_Is14 (index)) 1530 return false; 1531 } 1532 1533 /* If it is not under strictly aligned situation, 1534 we can return true without checking alignment. */ 1535 if (!cfun->machine->strict_aligned_p) 1536 return true; 1537 /* Make sure address is word alignment. 1538 Currently we do not have 64-bit load/store yet, 1539 so we will use two 32-bit load/store instructions to do 1540 memory access and they are single word alignment. */ 1541 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (index))) 1542 return true; 1543 } 1544 break; 1545 1546 default: 1547 return false; 1548 } 1549 1550 return false; 1551 1552 case MULT: 1553 op0 = XEXP (index, 0); 1554 op1 = XEXP (index, 1); 1555 1556 if (REG_P (op0) && CONST_INT_P (op1)) 1557 { 1558 int multiplier; 1559 multiplier = INTVAL (op1); 1560 1561 /* We only allow (mult reg const_int_1), (mult reg const_int_2), 1562 (mult reg const_int_4) or (mult reg const_int_8). */ 1563 if (multiplier != 1 && multiplier != 2 1564 && multiplier != 4 && multiplier != 8) 1565 return false; 1566 1567 regno = REGNO (op0); 1568 /* Limit it in general registers if we are 1569 in reload pass or after reload pass. */ 1570 if(strict) 1571 return REGNO_OK_FOR_INDEX_P (regno); 1572 else 1573 return true; 1574 } 1575 1576 return false; 1577 1578 case ASHIFT: 1579 op0 = XEXP (index, 0); 1580 op1 = XEXP (index, 1); 1581 1582 if (REG_P (op0) && CONST_INT_P (op1)) 1583 { 1584 int sv; 1585 /* op1 is already the sv value for use to do left shift. */ 1586 sv = INTVAL (op1); 1587 1588 /* We only allow (ashift reg const_int_0) 1589 or (ashift reg const_int_1) or (ashift reg const_int_2) or 1590 (ashift reg const_int_3). */ 1591 if (sv != 0 && sv != 1 && sv !=2 && sv != 3) 1592 return false; 1593 1594 regno = REGNO (op0); 1595 /* Limit it in general registers if we are 1596 in reload pass or after reload pass. */ 1597 if(strict) 1598 return REGNO_OK_FOR_INDEX_P (regno); 1599 else 1600 return true; 1601 } 1602 1603 return false; 1604 1605 default: 1606 return false; 1607 } 1608 } 1609 1610 static void 1611 nds32_register_pass ( 1612 rtl_opt_pass *(*make_pass_func) (gcc::context *), 1613 enum pass_positioning_ops pass_pos, 1614 const char *ref_pass_name) 1615 { 1616 opt_pass *new_opt_pass = make_pass_func (g); 1617 1618 struct register_pass_info insert_pass = 1619 { 1620 new_opt_pass, /* pass */ 1621 ref_pass_name, /* reference_pass_name */ 1622 1, /* ref_pass_instance_number */ 1623 pass_pos /* po_op */ 1624 }; 1625 1626 register_pass (&insert_pass); 1627 } 1628 1629 /* This function is called from nds32_option_override (). 1630 All new passes should be registered here. */ 1631 static void 1632 nds32_register_passes (void) 1633 { 1634 nds32_register_pass ( 1635 make_pass_nds32_fp_as_gp, 1636 PASS_POS_INSERT_BEFORE, 1637 "ira"); 1638 1639 nds32_register_pass ( 1640 make_pass_nds32_relax_opt, 1641 PASS_POS_INSERT_AFTER, 1642 "mach"); 1643 } 1644 1645 /* ------------------------------------------------------------------------ */ 1646 1647 /* PART 3: Implement target hook stuff definitions. */ 1648 1649 1651 /* Computing the Length of an Insn. 1652 Modifies the length assigned to instruction INSN. 1653 LEN is the initially computed length of the insn. */ 1654 int 1655 nds32_adjust_insn_length (rtx_insn *insn, int length) 1656 { 1657 int adjust_value = 0; 1658 switch (recog_memoized (insn)) 1659 { 1660 case CODE_FOR_call_internal: 1661 case CODE_FOR_call_value_internal: 1662 { 1663 if (NDS32_ALIGN_P ()) 1664 { 1665 rtx_insn *next_insn = next_active_insn (insn); 1666 if (next_insn && get_attr_length (next_insn) != 2) 1667 adjust_value += 2; 1668 } 1669 /* We need insert a nop after a noretun function call 1670 to prevent software breakpoint corrupt the next function. */ 1671 if (find_reg_note (insn, REG_NORETURN, NULL_RTX)) 1672 { 1673 if (TARGET_16_BIT) 1674 adjust_value += 2; 1675 else 1676 adjust_value += 4; 1677 } 1678 } 1679 return length + adjust_value; 1680 1681 default: 1682 return length; 1683 } 1684 } 1685 1686 /* Storage Layout. */ 1687 1688 /* This function will be called just before expansion into rtl. */ 1689 static void 1690 nds32_expand_to_rtl_hook (void) 1691 { 1692 /* We need to set strictly aligned situation. 1693 After that, the memory address checking in nds32_legitimate_address_p() 1694 will take alignment offset into consideration so that it will not create 1695 unaligned [base + offset] access during the rtl optimization. */ 1696 cfun->machine->strict_aligned_p = 1; 1697 } 1698 1699 1700 /* Register Usage. */ 1702 1703 static void 1704 nds32_conditional_register_usage (void) 1705 { 1706 int regno; 1707 1708 if (TARGET_LINUX_ABI) 1709 fixed_regs[TP_REGNUM] = 1; 1710 1711 if (TARGET_HARD_FLOAT) 1712 { 1713 for (regno = NDS32_FIRST_FPR_REGNUM; 1714 regno <= NDS32_LAST_FPR_REGNUM; regno++) 1715 { 1716 fixed_regs[regno] = 0; 1717 if (regno < NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS) 1718 call_used_regs[regno] = 1; 1719 else if (regno >= NDS32_FIRST_FPR_REGNUM + 22 1720 && regno < NDS32_FIRST_FPR_REGNUM + 48) 1721 call_used_regs[regno] = 1; 1722 else 1723 call_used_regs[regno] = 0; 1724 } 1725 } 1726 else if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 1727 { 1728 for (regno = NDS32_FIRST_FPR_REGNUM; 1729 regno <= NDS32_LAST_FPR_REGNUM; 1730 regno++) 1731 fixed_regs[regno] = 0; 1732 } 1733 } 1734 1735 1736 /* Register Classes. */ 1738 1739 static unsigned char 1740 nds32_class_max_nregs (reg_class_t rclass ATTRIBUTE_UNUSED, 1741 machine_mode mode) 1742 { 1743 /* Return the maximum number of consecutive registers 1744 needed to represent "mode" in a register of "rclass". */ 1745 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); 1746 } 1747 1748 static int 1749 nds32_register_priority (int hard_regno) 1750 { 1751 /* Encourage to use r0-r7 for LRA when optimize for size. */ 1752 if (optimize_size) 1753 { 1754 if (hard_regno < 8) 1755 return 4; 1756 else if (hard_regno < 16) 1757 return 3; 1758 else if (hard_regno < 28) 1759 return 2; 1760 else 1761 return 1; 1762 } 1763 else 1764 { 1765 if (hard_regno > 27) 1766 return 1; 1767 else 1768 return 4; 1769 } 1770 } 1771 1772 static bool 1773 nds32_can_change_mode_class (machine_mode from, 1774 machine_mode to, 1775 reg_class_t rclass) 1776 { 1777 /* Don't spill double-precision register to two singal-precision 1778 registers */ 1779 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 1780 && GET_MODE_SIZE (from) != GET_MODE_SIZE (to)) 1781 { 1782 return !reg_classes_intersect_p (rclass, FP_REGS); 1783 } 1784 1785 return true; 1786 } 1787 1788 1789 /* Stack Layout and Calling Conventions. */ 1791 1792 /* There are three kinds of pointer concepts using in GCC compiler: 1793 1794 frame pointer: A pointer to the first location of local variables. 1795 stack pointer: A pointer to the top of a stack frame. 1796 argument pointer: A pointer to the incoming arguments. 1797 1798 In nds32 target calling convention, we are using 8-byte alignment. 1799 Besides, we would like to have each stack frame of a function includes: 1800 1801 [Block A] 1802 1. previous hard frame pointer 1803 2. return address 1804 3. callee-saved registers 1805 4. <padding bytes> (we will calculte in nds32_compute_stack_frame() 1806 and save it at 1807 cfun->machine->callee_saved_area_padding_bytes) 1808 1809 [Block B] 1810 1. local variables 1811 2. spilling location 1812 3. <padding bytes> (it will be calculated by GCC itself) 1813 4. incoming arguments 1814 5. <padding bytes> (it will be calculated by GCC itself) 1815 1816 [Block C] 1817 1. <padding bytes> (it will be calculated by GCC itself) 1818 2. outgoing arguments 1819 1820 We 'wrap' these blocks together with 1821 hard frame pointer ($r28) and stack pointer ($r31). 1822 By applying the basic frame/stack/argument pointers concept, 1823 the layout of a stack frame shoule be like this: 1824 1825 | | 1826 old stack pointer -> ---- 1827 | | \ 1828 | | saved arguments for 1829 | | vararg functions 1830 | | / 1831 hard frame pointer -> -- 1832 & argument pointer | | \ 1833 | | previous hardware frame pointer 1834 | | return address 1835 | | callee-saved registers 1836 | | / 1837 frame pointer -> -- 1838 | | \ 1839 | | local variables 1840 | | and incoming arguments 1841 | | / 1842 -- 1843 | | \ 1844 | | outgoing 1845 | | arguments 1846 | | / 1847 stack pointer -> ---- 1848 1849 $SFP and $AP are used to represent frame pointer and arguments pointer, 1850 which will be both eliminated as hard frame pointer. */ 1851 1852 /* -- Eliminating Frame Pointer and Arg Pointer. */ 1853 1854 static bool 1855 nds32_can_eliminate (const int from_reg, const int to_reg) 1856 { 1857 if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) 1858 return true; 1859 1860 if (from_reg == ARG_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) 1861 return true; 1862 1863 if (from_reg == FRAME_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) 1864 return true; 1865 1866 if (from_reg == FRAME_POINTER_REGNUM && to_reg == HARD_FRAME_POINTER_REGNUM) 1867 return true; 1868 1869 return false; 1870 } 1871 1872 /* -- Passing Arguments in Registers. */ 1873 1874 static rtx 1875 nds32_function_arg (cumulative_args_t ca, const function_arg_info &arg) 1876 { 1877 unsigned int regno; 1878 CUMULATIVE_ARGS *cum = get_cumulative_args (ca); 1879 tree type = arg.type; 1880 machine_mode mode = arg.mode; 1881 1882 /* The last time this hook is called, 1883 it is called with an end marker. */ 1884 if (arg.end_marker_p ()) 1885 return NULL_RTX; 1886 1887 /* For nameless arguments, we need to take care it individually. */ 1888 if (!arg.named) 1889 { 1890 /* If we are under hard float abi, we have arguments passed on the 1891 stack and all situation can be handled by GCC itself. */ 1892 if (TARGET_HARD_FLOAT) 1893 return NULL_RTX; 1894 1895 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) 1896 { 1897 /* If we still have enough registers to pass argument, pick up 1898 next available register number. */ 1899 regno 1900 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); 1901 return gen_rtx_REG (mode, regno); 1902 } 1903 1904 /* No register available, return NULL_RTX. 1905 The compiler will use stack to pass argument instead. */ 1906 return NULL_RTX; 1907 } 1908 1909 /* The following is to handle named argument. 1910 Note that the strategies of TARGET_HARD_FLOAT and !TARGET_HARD_FLOAT 1911 are different. */ 1912 if (TARGET_HARD_FLOAT) 1913 { 1914 /* For TARGET_HARD_FLOAT calling convention, we use GPR and FPR 1915 to pass argument. We have to further check TYPE and MODE so 1916 that we can determine which kind of register we shall use. */ 1917 1918 /* Note that we need to pass argument entirely in registers under 1919 hard float abi. */ 1920 if (GET_MODE_CLASS (mode) == MODE_FLOAT 1921 && NDS32_ARG_ENTIRE_IN_FPR_REG_P (cum->fpr_offset, mode, type)) 1922 { 1923 /* Pick up the next available FPR register number. */ 1924 regno 1925 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type); 1926 return gen_rtx_REG (mode, regno); 1927 } 1928 else if (GET_MODE_CLASS (mode) != MODE_FLOAT 1929 && NDS32_ARG_ENTIRE_IN_GPR_REG_P (cum->gpr_offset, mode, type)) 1930 { 1931 /* Pick up the next available GPR register number. */ 1932 regno 1933 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); 1934 return gen_rtx_REG (mode, regno); 1935 } 1936 } 1937 else 1938 { 1939 /* For !TARGET_HARD_FLOAT calling convention, we always use GPR to pass 1940 argument. Since we allow to pass argument partially in registers, 1941 we can just return it if there are still registers available. */ 1942 if (NDS32_ARG_PARTIAL_IN_GPR_REG_P (cum->gpr_offset, mode, type)) 1943 { 1944 /* Pick up the next available register number. */ 1945 regno 1946 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type); 1947 return gen_rtx_REG (mode, regno); 1948 } 1949 1950 } 1951 1952 /* No register available, return NULL_RTX. 1953 The compiler will use stack to pass argument instead. */ 1954 return NULL_RTX; 1955 } 1956 1957 static bool 1958 nds32_must_pass_in_stack (const function_arg_info &arg) 1959 { 1960 /* Return true if a type must be passed in memory. 1961 If it is NOT using hard float abi, small aggregates can be 1962 passed in a register even we are calling a variadic function. 1963 So there is no need to take padding into consideration. */ 1964 if (TARGET_HARD_FLOAT) 1965 return must_pass_in_stack_var_size_or_pad (arg); 1966 else 1967 return must_pass_in_stack_var_size (arg); 1968 } 1969 1970 static int 1971 nds32_arg_partial_bytes (cumulative_args_t ca, const function_arg_info &arg) 1972 { 1973 /* Returns the number of bytes at the beginning of an argument that 1974 must be put in registers. The value must be zero for arguments that are 1975 passed entirely in registers or that are entirely pushed on the stack. 1976 Besides, TARGET_FUNCTION_ARG for these arguments should return the 1977 first register to be used by the caller for this argument. */ 1978 unsigned int needed_reg_count; 1979 unsigned int remaining_reg_count; 1980 CUMULATIVE_ARGS *cum; 1981 1982 cum = get_cumulative_args (ca); 1983 1984 /* Under hard float abi, we better have argument entirely passed in 1985 registers or pushed on the stack so that we can reduce the complexity 1986 of dealing with cum->gpr_offset and cum->fpr_offset. */ 1987 if (TARGET_HARD_FLOAT) 1988 return 0; 1989 1990 /* If we have already runned out of argument registers, return zero 1991 so that the argument will be entirely pushed on the stack. */ 1992 if (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) 1993 >= NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) 1994 return 0; 1995 1996 /* Calculate how many registers do we need for this argument. */ 1997 needed_reg_count = NDS32_NEED_N_REGS_FOR_ARG (arg.mode, arg.type); 1998 1999 /* Calculate how many argument registers have left for passing argument. 2000 Note that we should count it from next available register number. */ 2001 remaining_reg_count 2002 = NDS32_MAX_GPR_REGS_FOR_ARGS 2003 - (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, 2004 arg.mode, arg.type) 2005 - NDS32_GPR_ARG_FIRST_REGNUM); 2006 2007 /* Note that we have to return the nubmer of bytes, not registers count. */ 2008 if (needed_reg_count > remaining_reg_count) 2009 return remaining_reg_count * UNITS_PER_WORD; 2010 2011 return 0; 2012 } 2013 2014 static void 2015 nds32_function_arg_advance (cumulative_args_t ca, 2016 const function_arg_info &arg) 2017 { 2018 CUMULATIVE_ARGS *cum = get_cumulative_args (ca); 2019 tree type = arg.type; 2020 machine_mode mode = arg.mode; 2021 2022 if (arg.named) 2023 { 2024 /* We need to further check TYPE and MODE so that we can determine 2025 which kind of register we shall advance. */ 2026 2027 /* Under hard float abi, we may advance FPR registers. */ 2028 if (TARGET_HARD_FLOAT && GET_MODE_CLASS (mode) == MODE_FLOAT) 2029 { 2030 cum->fpr_offset 2031 = NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (cum->fpr_offset, mode, type) 2032 - NDS32_FPR_ARG_FIRST_REGNUM 2033 + NDS32_NEED_N_REGS_FOR_ARG (mode, type); 2034 } 2035 else 2036 { 2037 cum->gpr_offset 2038 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) 2039 - NDS32_GPR_ARG_FIRST_REGNUM 2040 + NDS32_NEED_N_REGS_FOR_ARG (mode, type); 2041 } 2042 } 2043 else 2044 { 2045 /* If this nameless argument is NOT under TARGET_HARD_FLOAT, 2046 we can advance next register as well so that caller is 2047 able to pass arguments in registers and callee must be 2048 in charge of pushing all of them into stack. */ 2049 if (!TARGET_HARD_FLOAT) 2050 { 2051 cum->gpr_offset 2052 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, mode, type) 2053 - NDS32_GPR_ARG_FIRST_REGNUM 2054 + NDS32_NEED_N_REGS_FOR_ARG (mode, type); 2055 } 2056 } 2057 } 2058 2059 static unsigned int 2060 nds32_function_arg_boundary (machine_mode mode, const_tree type) 2061 { 2062 return (nds32_needs_double_word_align (mode, type) 2063 ? NDS32_DOUBLE_WORD_ALIGNMENT 2064 : PARM_BOUNDARY); 2065 } 2066 2067 bool 2068 nds32_vector_mode_supported_p (machine_mode mode) 2069 { 2070 if (mode == V4QImode 2071 || mode == V2HImode) 2072 return NDS32_EXT_DSP_P (); 2073 2074 return false; 2075 } 2076 2077 /* -- How Scalar Function Values Are Returned. */ 2078 2079 static rtx 2080 nds32_function_value (const_tree ret_type, 2081 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 2082 bool outgoing ATTRIBUTE_UNUSED) 2083 { 2084 machine_mode mode; 2085 int unsignedp; 2086 2087 mode = TYPE_MODE (ret_type); 2088 unsignedp = TYPE_UNSIGNED (ret_type); 2089 2090 if (INTEGRAL_TYPE_P (ret_type)) 2091 mode = promote_mode (ret_type, mode, &unsignedp); 2092 2093 if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) 2094 return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); 2095 else 2096 return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); 2097 } 2098 2099 static rtx 2100 nds32_libcall_value (machine_mode mode, 2101 const_rtx fun ATTRIBUTE_UNUSED) 2102 { 2103 if (TARGET_HARD_FLOAT && (mode == SFmode || mode == DFmode)) 2104 return gen_rtx_REG (mode, NDS32_FPR_RET_FIRST_REGNUM); 2105 2106 return gen_rtx_REG (mode, NDS32_GPR_RET_FIRST_REGNUM); 2107 } 2108 2109 static bool 2110 nds32_function_value_regno_p (const unsigned int regno) 2111 { 2112 if (regno == NDS32_GPR_RET_FIRST_REGNUM 2113 || (TARGET_HARD_FLOAT 2114 && regno == NDS32_FPR_RET_FIRST_REGNUM)) 2115 return true; 2116 2117 return false; 2118 } 2119 2120 /* -- How Large Values Are Returned. */ 2121 2122 static bool 2123 nds32_return_in_memory (const_tree type, 2124 const_tree fntype ATTRIBUTE_UNUSED) 2125 { 2126 /* Note that int_size_in_bytes can return -1 if the size can vary 2127 or is larger than an integer. */ 2128 HOST_WIDE_INT size = int_size_in_bytes (type); 2129 2130 /* For COMPLEX_TYPE, if the total size cannot be hold within two registers, 2131 the return value is supposed to be in memory. We need to be aware of 2132 that the size may be -1. */ 2133 if (TREE_CODE (type) == COMPLEX_TYPE) 2134 if (size < 0 || size > 2 * UNITS_PER_WORD) 2135 return true; 2136 2137 /* If it is BLKmode and the total size cannot be hold within two registers, 2138 the return value is supposed to be in memory. We need to be aware of 2139 that the size may be -1. */ 2140 if (TYPE_MODE (type) == BLKmode) 2141 if (size < 0 || size > 2 * UNITS_PER_WORD) 2142 return true; 2143 2144 /* For other cases, having result in memory is unnecessary. */ 2145 return false; 2146 } 2147 2148 /* -- Function Entry and Exit. */ 2149 2150 /* The content produced from this function 2151 will be placed before prologue body. */ 2152 static void 2153 nds32_asm_function_prologue (FILE *file) 2154 { 2155 int r; 2156 const char *func_name; 2157 tree attrs; 2158 tree name; 2159 2160 /* All stack frame information is supposed to be 2161 already computed when expanding prologue. 2162 The result is in cfun->machine. 2163 DO NOT call nds32_compute_stack_frame() here 2164 because it may corrupt the essential information. */ 2165 2166 fprintf (file, "\t! BEGIN PROLOGUE\n"); 2167 fprintf (file, "\t! fp needed: %d\n", frame_pointer_needed); 2168 fprintf (file, "\t! pretend_args: %d\n", cfun->machine->va_args_size); 2169 fprintf (file, "\t! local_size: %d\n", cfun->machine->local_size); 2170 fprintf (file, "\t! out_args_size: %d\n", cfun->machine->out_args_size); 2171 2172 /* Use df_regs_ever_live_p() to detect if the register 2173 is ever used in the current function. */ 2174 fprintf (file, "\t! registers ever_live: "); 2175 for (r = 0; r < 65; r++) 2176 { 2177 if (df_regs_ever_live_p (r)) 2178 fprintf (file, "%s, ", reg_names[r]); 2179 } 2180 fputc ('\n', file); 2181 2182 /* Display the attributes of this function. */ 2183 fprintf (file, "\t! function attributes: "); 2184 /* Get the attributes tree list. 2185 Note that GCC builds attributes list with reverse order. */ 2186 attrs = DECL_ATTRIBUTES (current_function_decl); 2187 2188 /* If there is no any attribute, print out "None". */ 2189 if (!attrs) 2190 fprintf (file, "None"); 2191 2192 /* If there are some attributes, try if we need to 2193 construct isr vector information. */ 2194 func_name = IDENTIFIER_POINTER (DECL_NAME (current_function_decl)); 2195 nds32_construct_isr_vectors_information (attrs, func_name); 2196 2197 /* Display all attributes of this function. */ 2198 while (attrs) 2199 { 2200 name = TREE_PURPOSE (attrs); 2201 fprintf (file, "%s ", IDENTIFIER_POINTER (name)); 2202 2203 /* Pick up the next attribute. */ 2204 attrs = TREE_CHAIN (attrs); 2205 } 2206 fputc ('\n', file); 2207 } 2208 2209 /* After rtl prologue has been expanded, this function is used. */ 2210 static void 2211 nds32_asm_function_end_prologue (FILE *file) 2212 { 2213 fprintf (file, "\t! END PROLOGUE\n"); 2214 } 2215 2216 /* Before rtl epilogue has been expanded, this function is used. */ 2217 static void 2218 nds32_asm_function_begin_epilogue (FILE *file) 2219 { 2220 fprintf (file, "\t! BEGIN EPILOGUE\n"); 2221 } 2222 2223 /* The content produced from this function 2224 will be placed after epilogue body. */ 2225 static void 2226 nds32_asm_function_epilogue (FILE *file) 2227 { 2228 fprintf (file, "\t! END EPILOGUE\n"); 2229 } 2230 2231 static void 2232 nds32_asm_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, 2233 HOST_WIDE_INT delta, 2234 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED, 2235 tree function) 2236 { 2237 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk)); 2238 int this_regno; 2239 2240 assemble_start_function (thunk, fnname); 2241 /* Make sure unwind info is emitted for the thunk if needed. */ 2242 final_start_function (emit_barrier (), file, 1); 2243 2244 this_regno = (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function) 2245 ? 1 2246 : 0); 2247 2248 if (flag_pic) 2249 { 2250 fprintf (file, "\tsmw.adm\t$r31, [$r31], $r31, 4\n"); 2251 fprintf (file, "\tsethi\t%s, hi20(_GLOBAL_OFFSET_TABLE_-8)\n", 2252 reg_names [PIC_OFFSET_TABLE_REGNUM]); 2253 fprintf (file, "\tori\t%s, %s, lo12(_GLOBAL_OFFSET_TABLE_-4)\n", 2254 reg_names [PIC_OFFSET_TABLE_REGNUM], 2255 reg_names [PIC_OFFSET_TABLE_REGNUM]); 2256 2257 if (TARGET_ISA_V3) 2258 fprintf (file, "\tadd5.pc\t$gp\n"); 2259 else 2260 { 2261 fprintf (file, "\tmfusr\t$ta, $pc\n"); 2262 fprintf (file, "\tadd\t%s, $ta, %s\n", 2263 reg_names [PIC_OFFSET_TABLE_REGNUM], 2264 reg_names [PIC_OFFSET_TABLE_REGNUM]); 2265 } 2266 } 2267 2268 if (delta != 0) 2269 { 2270 if (satisfies_constraint_Is15 (GEN_INT (delta))) 2271 { 2272 fprintf (file, "\taddi\t$r%d, $r%d, " HOST_WIDE_INT_PRINT_DEC "\n", 2273 this_regno, this_regno, delta); 2274 } 2275 else if (satisfies_constraint_Is20 (GEN_INT (delta))) 2276 { 2277 fprintf (file, "\tmovi\t$ta, " HOST_WIDE_INT_PRINT_DEC "\n", delta); 2278 fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); 2279 } 2280 else 2281 { 2282 fprintf (file, 2283 "\tsethi\t$ta, hi20(" HOST_WIDE_INT_PRINT_DEC ")\n", 2284 delta); 2285 fprintf (file, 2286 "\tori\t$ta, $ta, lo12(" HOST_WIDE_INT_PRINT_DEC ")\n", 2287 delta); 2288 fprintf (file, "\tadd\t$r%d, $r%d, $ta\n", this_regno, this_regno); 2289 } 2290 } 2291 2292 if (flag_pic) 2293 { 2294 fprintf (file, "\tla\t$ta, "); 2295 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); 2296 fprintf (file, "@PLT\n"); 2297 fprintf (file, "\t! epilogue\n"); 2298 fprintf (file, "\tlwi.bi\t%s, [%s], 4\n", 2299 reg_names[PIC_OFFSET_TABLE_REGNUM], 2300 reg_names[STACK_POINTER_REGNUM]); 2301 fprintf (file, "\tbr\t$ta\n"); 2302 } 2303 else 2304 { 2305 fprintf (file, "\tb\t"); 2306 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0)); 2307 fprintf (file, "\n"); 2308 } 2309 2310 final_end_function (); 2311 assemble_end_function (thunk, fnname); 2312 } 2313 2314 /* -- Permitting tail calls. */ 2315 2316 /* Return true if it is ok to do sibling call optimization. */ 2317 static bool 2318 nds32_function_ok_for_sibcall (tree decl, 2319 tree exp ATTRIBUTE_UNUSED) 2320 { 2321 /* The DECL is NULL if it is an indirect call. */ 2322 2323 /* 1. Do not apply sibling call if -mv3push is enabled, 2324 because pop25 instruction also represents return behavior. 2325 2. If this function is a isr function, do not apply sibling call 2326 because it may perform the behavior that user does not expect. 2327 3. If this function is a variadic function, do not apply sibling call 2328 because the stack layout may be a mess. 2329 4. We don't want to apply sibling call optimization for indirect 2330 sibcall because the pop behavior in epilogue may pollute the 2331 content of caller-saved regsiter when the register is used for 2332 indirect sibcall. 2333 5. In pic mode, it may use some registers for PLT call. */ 2334 return (!TARGET_V3PUSH 2335 && !nds32_isr_function_p (current_function_decl) 2336 && (cfun->machine->va_args_size == 0) 2337 && decl 2338 && !flag_pic); 2339 } 2340 2341 /* Determine whether we need to enable warning for function return check. */ 2342 static bool 2343 nds32_warn_func_return (tree decl) 2344 { 2345 /* Naked functions are implemented entirely in assembly, including the 2346 return sequence, so suppress warnings about this. */ 2347 return !nds32_naked_function_p (decl); 2348 } 2349 2350 2351 /* Implementing the Varargs Macros. */ 2353 2354 static void 2355 nds32_setup_incoming_varargs (cumulative_args_t ca, 2356 const function_arg_info &arg, 2357 int *pretend_args_size, 2358 int second_time ATTRIBUTE_UNUSED) 2359 { 2360 unsigned int total_args_regs; 2361 unsigned int num_of_used_regs; 2362 unsigned int remaining_reg_count; 2363 CUMULATIVE_ARGS *cum; 2364 2365 /* If we are under hard float abi, we do not need to set *pretend_args_size. 2366 So that all nameless arguments are pushed by caller and all situation 2367 can be handled by GCC itself. */ 2368 if (TARGET_HARD_FLOAT) 2369 return; 2370 2371 /* We are using NDS32_MAX_GPR_REGS_FOR_ARGS registers, 2372 counting from NDS32_GPR_ARG_FIRST_REGNUM, for saving incoming arguments. 2373 However, for nameless(anonymous) arguments, we should push them on the 2374 stack so that all the nameless arguments appear to have been passed 2375 consecutively in the memory for accessing. Hence, we need to check and 2376 exclude the registers that are used for named arguments. */ 2377 2378 cum = get_cumulative_args (ca); 2379 2380 /* ARG describes the last argument. 2381 We need those information to determine the remaining registers 2382 for varargs. */ 2383 total_args_regs 2384 = NDS32_MAX_GPR_REGS_FOR_ARGS + NDS32_GPR_ARG_FIRST_REGNUM; 2385 num_of_used_regs 2386 = NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (cum->gpr_offset, arg.mode, arg.type) 2387 + NDS32_NEED_N_REGS_FOR_ARG (arg.mode, arg.type); 2388 2389 remaining_reg_count = total_args_regs - num_of_used_regs; 2390 *pretend_args_size = remaining_reg_count * UNITS_PER_WORD; 2391 2392 return; 2393 } 2394 2395 static bool 2396 nds32_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) 2397 { 2398 /* If this hook returns true, the named argument of FUNCTION_ARG is always 2399 true for named arguments, and false for unnamed arguments. */ 2400 return true; 2401 } 2402 2403 2404 /* Trampolines for Nested Functions. */ 2406 2407 static void 2408 nds32_asm_trampoline_template (FILE *f) 2409 { 2410 if (TARGET_REDUCED_REGS) 2411 { 2412 /* Trampoline is not supported on reduced-set registers yet. */ 2413 sorry ("a nested function is not supported for reduced registers"); 2414 } 2415 else 2416 { 2417 asm_fprintf (f, "\t! Trampoline code template\n"); 2418 asm_fprintf (f, "\t! This code fragment will be copied " 2419 "into stack on demand\n"); 2420 2421 asm_fprintf (f, "\tmfusr\t$r16,$pc\n"); 2422 asm_fprintf (f, "\tlwi\t$r15,[$r16 + 20] " 2423 "! load nested function address\n"); 2424 asm_fprintf (f, "\tlwi\t$r16,[$r16 + 16] " 2425 "! load chain_value\n"); 2426 asm_fprintf (f, "\tjr\t$r15\n"); 2427 } 2428 2429 /* Preserve space ($pc + 16) for saving chain_value, 2430 nds32_trampoline_init will fill the value in this slot. */ 2431 asm_fprintf (f, "\t! space for saving chain_value\n"); 2432 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); 2433 2434 /* Preserve space ($pc + 20) for saving nested function address, 2435 nds32_trampoline_init will fill the value in this slot. */ 2436 asm_fprintf (f, "\t! space for saving nested function address\n"); 2437 assemble_aligned_integer (UNITS_PER_WORD, const0_rtx); 2438 } 2439 2440 /* Emit RTL insns to initialize the variable parts of a trampoline. */ 2441 static void 2442 nds32_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 2443 { 2444 int i; 2445 2446 /* Nested function address. */ 2447 rtx fnaddr; 2448 /* The memory rtx that is going to 2449 be filled with chain_value. */ 2450 rtx chain_value_mem; 2451 /* The memory rtx that is going to 2452 be filled with nested function address. */ 2453 rtx nested_func_mem; 2454 2455 /* Start address of trampoline code in stack, for doing cache sync. */ 2456 rtx sync_cache_addr; 2457 /* Temporary register for sync instruction. */ 2458 rtx tmp_reg; 2459 /* Instruction-cache sync instruction, 2460 requesting an argument as starting address. */ 2461 rtx isync_insn; 2462 /* For convenience reason of doing comparison. */ 2463 int tramp_align_in_bytes; 2464 2465 /* Trampoline is not supported on reduced-set registers yet. */ 2466 if (TARGET_REDUCED_REGS) 2467 sorry ("a nested function is not supported for reduced registers"); 2468 2469 /* STEP 1: Copy trampoline code template into stack, 2470 fill up essential data into stack. */ 2471 2472 /* Extract nested function address rtx. */ 2473 fnaddr = XEXP (DECL_RTL (fndecl), 0); 2474 2475 /* m_tramp is memory rtx that is going to be filled with trampoline code. 2476 We have nds32_asm_trampoline_template() to emit template pattern. */ 2477 emit_block_move (m_tramp, assemble_trampoline_template (), 2478 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); 2479 2480 /* After copying trampoline code into stack, 2481 fill chain_value into stack. */ 2482 chain_value_mem = adjust_address (m_tramp, SImode, 16); 2483 emit_move_insn (chain_value_mem, chain_value); 2484 /* After copying trampoline code int stack, 2485 fill nested function address into stack. */ 2486 nested_func_mem = adjust_address (m_tramp, SImode, 20); 2487 emit_move_insn (nested_func_mem, fnaddr); 2488 2489 /* STEP 2: Sync instruction-cache. */ 2490 2491 /* We have successfully filled trampoline code into stack. 2492 However, in order to execute code in stack correctly, 2493 we must sync instruction cache. */ 2494 sync_cache_addr = XEXP (m_tramp, 0); 2495 tmp_reg = gen_reg_rtx (SImode); 2496 isync_insn = gen_unspec_volatile_isync (tmp_reg); 2497 2498 /* Because nds32_cache_block_size is in bytes, 2499 we get trampoline alignment in bytes for convenient comparison. */ 2500 tramp_align_in_bytes = TRAMPOLINE_ALIGNMENT / BITS_PER_UNIT; 2501 2502 if (tramp_align_in_bytes >= nds32_cache_block_size 2503 && (tramp_align_in_bytes % nds32_cache_block_size) == 0) 2504 { 2505 /* Under this condition, the starting address of trampoline 2506 must be aligned to the starting address of each cache block 2507 and we do not have to worry about cross-boundary issue. */ 2508 for (i = 0; 2509 i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) 2510 / nds32_cache_block_size; 2511 i++) 2512 { 2513 emit_move_insn (tmp_reg, 2514 plus_constant (Pmode, sync_cache_addr, 2515 nds32_cache_block_size * i)); 2516 emit_insn (isync_insn); 2517 } 2518 } 2519 else if (TRAMPOLINE_SIZE > nds32_cache_block_size) 2520 { 2521 /* The starting address of trampoline code 2522 may not be aligned to the cache block, 2523 so the trampoline code may be across two cache block. 2524 We need to sync the last element, which is 4-byte size, 2525 of trampoline template. */ 2526 for (i = 0; 2527 i < (TRAMPOLINE_SIZE + nds32_cache_block_size - 1) 2528 / nds32_cache_block_size; 2529 i++) 2530 { 2531 emit_move_insn (tmp_reg, 2532 plus_constant (Pmode, sync_cache_addr, 2533 nds32_cache_block_size * i)); 2534 emit_insn (isync_insn); 2535 } 2536 2537 /* The last element of trampoline template is 4-byte size. */ 2538 emit_move_insn (tmp_reg, 2539 plus_constant (Pmode, sync_cache_addr, 2540 TRAMPOLINE_SIZE - 4)); 2541 emit_insn (isync_insn); 2542 } 2543 else 2544 { 2545 /* This is the simplest case. 2546 Because TRAMPOLINE_SIZE is less than or 2547 equal to nds32_cache_block_size, 2548 we can just sync start address and 2549 the last element of trampoline code. */ 2550 2551 /* Sync starting address of tampoline code. */ 2552 emit_move_insn (tmp_reg, sync_cache_addr); 2553 emit_insn (isync_insn); 2554 /* Sync the last element, which is 4-byte size, 2555 of trampoline template. */ 2556 emit_move_insn (tmp_reg, 2557 plus_constant (Pmode, sync_cache_addr, 2558 TRAMPOLINE_SIZE - 4)); 2559 emit_insn (isync_insn); 2560 } 2561 2562 /* Set instruction serialization barrier 2563 to guarantee the correct operations. */ 2564 emit_insn (gen_unspec_volatile_isb ()); 2565 } 2566 2567 2568 /* Addressing Modes. */ 2570 2571 static bool 2572 nds32_legitimate_address_p (machine_mode mode, rtx x, bool strict) 2573 { 2574 if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 2575 { 2576 /* When using floating-point instructions, 2577 we don't allow 'addr' to be [symbol_ref], [CONST] pattern. */ 2578 if ((mode == DFmode || mode == SFmode) 2579 && (GET_CODE (x) == SYMBOL_REF 2580 || GET_CODE(x) == CONST)) 2581 return false; 2582 2583 /* Allow [post_modify] addressing mode, when using FPU instructions. */ 2584 if (GET_CODE (x) == POST_MODIFY 2585 && mode == DFmode) 2586 { 2587 if (GET_CODE (XEXP (x, 0)) == REG 2588 && GET_CODE (XEXP (x, 1)) == PLUS) 2589 { 2590 rtx plus_op = XEXP (x, 1); 2591 rtx op0 = XEXP (plus_op, 0); 2592 rtx op1 = XEXP (plus_op, 1); 2593 2594 if (nds32_address_register_rtx_p (op0, strict) 2595 && CONST_INT_P (op1)) 2596 { 2597 if (satisfies_constraint_Is14 (op1)) 2598 { 2599 /* If it is not under strictly aligned situation, 2600 we can return true without checking alignment. */ 2601 if (!cfun->machine->strict_aligned_p) 2602 return true; 2603 /* Make sure address is word alignment. 2604 Currently we do not have 64-bit load/store yet, 2605 so we will use two 32-bit load/store instructions to do 2606 memory access and they are single word alignment. */ 2607 else if (NDS32_SINGLE_WORD_ALIGN_P (INTVAL (op1))) 2608 return true; 2609 } 2610 } 2611 } 2612 } 2613 } 2614 2615 /* For (mem:DI addr) or (mem:DF addr) case, 2616 we only allow 'addr' to be [reg], [symbol_ref], 2617 [const], or [reg + const_int] pattern. */ 2618 if (mode == DImode || mode == DFmode) 2619 { 2620 /* Allow [Reg + const_int] addressing mode. */ 2621 if (GET_CODE (x) == PLUS) 2622 { 2623 if (nds32_address_register_rtx_p (XEXP (x, 0), strict) 2624 && nds32_legitimate_index_p (mode, XEXP (x, 1), strict) 2625 && CONST_INT_P (XEXP (x, 1))) 2626 return true; 2627 else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) 2628 && nds32_legitimate_index_p (mode, XEXP (x, 0), strict) 2629 && CONST_INT_P (XEXP (x, 0))) 2630 return true; 2631 } 2632 2633 /* Allow [post_inc] and [post_dec] addressing mode. */ 2634 if (GET_CODE (x) == POST_INC || GET_CODE (x) == POST_DEC) 2635 { 2636 if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) 2637 return true; 2638 } 2639 2640 /* Now check [reg], [symbol_ref], and [const]. */ 2641 if (GET_CODE (x) != REG 2642 && GET_CODE (x) != SYMBOL_REF 2643 && GET_CODE (x) != CONST) 2644 return false; 2645 } 2646 2647 /* Check if 'x' is a valid address. */ 2648 switch (GET_CODE (x)) 2649 { 2650 case REG: 2651 /* (mem (reg A)) => [Ra] */ 2652 return nds32_address_register_rtx_p (x, strict); 2653 2654 case SYMBOL_REF: 2655 /* (mem (symbol_ref A)) => [symbol_ref] */ 2656 2657 if (flag_pic || SYMBOL_REF_TLS_MODEL (x)) 2658 return false; 2659 2660 if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) 2661 return false; 2662 2663 /* If -mcmodel=large, the 'symbol_ref' is not a valid address 2664 during or after LRA/reload phase. */ 2665 if (TARGET_CMODEL_LARGE 2666 && (reload_completed 2667 || reload_in_progress 2668 || lra_in_progress)) 2669 return false; 2670 /* If -mcmodel=medium and the symbol references to rodata section, 2671 the 'symbol_ref' is not a valid address during or after 2672 LRA/reload phase. */ 2673 if (TARGET_CMODEL_MEDIUM 2674 && (NDS32_SYMBOL_REF_RODATA_P (x) 2675 || CONSTANT_POOL_ADDRESS_P (x)) 2676 && (reload_completed 2677 || reload_in_progress 2678 || lra_in_progress)) 2679 return false; 2680 2681 return true; 2682 2683 case CONST: 2684 /* (mem (const (...))) 2685 => [ + const_addr ], where const_addr = symbol_ref + const_int */ 2686 if (GET_CODE (XEXP (x, 0)) == PLUS) 2687 { 2688 rtx plus_op = XEXP (x, 0); 2689 2690 rtx op0 = XEXP (plus_op, 0); 2691 rtx op1 = XEXP (plus_op, 1); 2692 2693 if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) 2694 { 2695 /* Now we see the [ + const_addr ] pattern, but we need 2696 some further checking. */ 2697 2698 if (flag_pic || SYMBOL_REF_TLS_MODEL (op0)) 2699 return false; 2700 2701 /* If -mcmodel=large, the 'const_addr' is not a valid address 2702 during or after LRA/reload phase. */ 2703 if (TARGET_CMODEL_LARGE 2704 && (reload_completed 2705 || reload_in_progress 2706 || lra_in_progress)) 2707 return false; 2708 /* If -mcmodel=medium and the symbol references to rodata section, 2709 the 'const_addr' is not a valid address during or after 2710 LRA/reload phase. */ 2711 if (TARGET_CMODEL_MEDIUM 2712 && NDS32_SYMBOL_REF_RODATA_P (op0) 2713 && (reload_completed 2714 || reload_in_progress 2715 || lra_in_progress)) 2716 return false; 2717 2718 /* At this point we can make sure 'const_addr' is a 2719 valid address. */ 2720 return true; 2721 } 2722 } 2723 2724 return false; 2725 2726 case POST_MODIFY: 2727 /* (mem (post_modify (reg) (plus (reg) (reg)))) 2728 => [Ra], Rb */ 2729 /* (mem (post_modify (reg) (plus (reg) (const_int)))) 2730 => [Ra], const_int */ 2731 if (GET_CODE (XEXP (x, 0)) == REG 2732 && GET_CODE (XEXP (x, 1)) == PLUS) 2733 { 2734 rtx plus_op = XEXP (x, 1); 2735 2736 rtx op0 = XEXP (plus_op, 0); 2737 rtx op1 = XEXP (plus_op, 1); 2738 2739 if (nds32_address_register_rtx_p (op0, strict) 2740 && nds32_legitimate_index_p (mode, op1, strict)) 2741 return true; 2742 else 2743 return false; 2744 } 2745 2746 return false; 2747 2748 case POST_INC: 2749 case POST_DEC: 2750 /* (mem (post_inc reg)) => [Ra], 1/2/4 */ 2751 /* (mem (post_dec reg)) => [Ra], -1/-2/-4 */ 2752 /* The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. 2753 We only need to deal with register Ra. */ 2754 if (nds32_address_register_rtx_p (XEXP (x, 0), strict)) 2755 return true; 2756 else 2757 return false; 2758 2759 case PLUS: 2760 /* (mem (plus reg const_int)) 2761 => [Ra + imm] */ 2762 /* (mem (plus reg reg)) 2763 => [Ra + Rb] */ 2764 /* (mem (plus (mult reg const_int) reg)) 2765 => [Ra + Rb << sv] */ 2766 if (nds32_address_register_rtx_p (XEXP (x, 0), strict) 2767 && nds32_legitimate_index_p (mode, XEXP (x, 1), strict)) 2768 return true; 2769 else if (nds32_address_register_rtx_p (XEXP (x, 1), strict) 2770 && nds32_legitimate_index_p (mode, XEXP (x, 0), strict)) 2771 return true; 2772 else 2773 return false; 2774 2775 case LO_SUM: 2776 /* (mem (lo_sum (reg) (symbol_ref))) */ 2777 /* (mem (lo_sum (reg) (const (plus (symbol_ref) (reg)))) */ 2778 /* TLS case: (mem (lo_sum (reg) (const (unspec symbol_ref X)))) */ 2779 /* The LO_SUM is a valid address if and only if we would like to 2780 generate 32-bit full address memory access with any of following 2781 circumstance: 2782 1. -mcmodel=large. 2783 2. -mcmodel=medium and the symbol_ref references to rodata. */ 2784 { 2785 rtx sym = NULL_RTX; 2786 2787 if (flag_pic) 2788 return false; 2789 2790 if (!REG_P (XEXP (x, 0))) 2791 return false; 2792 2793 if (GET_CODE (XEXP (x, 1)) == SYMBOL_REF) 2794 sym = XEXP (x, 1); 2795 else if (GET_CODE (XEXP (x, 1)) == CONST) 2796 { 2797 rtx plus = XEXP(XEXP (x, 1), 0); 2798 if (GET_CODE (plus) == PLUS) 2799 sym = XEXP (plus, 0); 2800 else if (GET_CODE (plus) == UNSPEC) 2801 sym = XVECEXP (plus, 0, 0); 2802 } 2803 else 2804 return false; 2805 2806 gcc_assert (GET_CODE (sym) == SYMBOL_REF); 2807 2808 if (TARGET_ICT_MODEL_LARGE 2809 && nds32_indirect_call_referenced_p (sym)) 2810 return true; 2811 2812 if (TARGET_CMODEL_LARGE) 2813 return true; 2814 else if (TARGET_CMODEL_MEDIUM 2815 && NDS32_SYMBOL_REF_RODATA_P (sym)) 2816 return true; 2817 else 2818 return false; 2819 } 2820 2821 default: 2822 return false; 2823 } 2824 } 2825 2826 static rtx 2827 nds32_legitimize_address (rtx x, 2828 rtx oldx ATTRIBUTE_UNUSED, 2829 machine_mode mode ATTRIBUTE_UNUSED) 2830 { 2831 if (nds32_tls_referenced_p (x)) 2832 x = nds32_legitimize_tls_address (x); 2833 else if (flag_pic && SYMBOLIC_CONST_P (x)) 2834 x = nds32_legitimize_pic_address (x); 2835 else if (TARGET_ICT_MODEL_LARGE && nds32_indirect_call_referenced_p (x)) 2836 x = nds32_legitimize_ict_address (x); 2837 2838 return x; 2839 } 2840 2841 static bool 2842 nds32_legitimate_constant_p (machine_mode mode, rtx x) 2843 { 2844 switch (GET_CODE (x)) 2845 { 2846 case CONST_DOUBLE: 2847 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 2848 && (mode == DFmode || mode == SFmode)) 2849 return false; 2850 break; 2851 case CONST: 2852 x = XEXP (x, 0); 2853 2854 if (GET_CODE (x) == PLUS) 2855 { 2856 if (!CONST_INT_P (XEXP (x, 1))) 2857 return false; 2858 x = XEXP (x, 0); 2859 } 2860 2861 if (GET_CODE (x) == UNSPEC) 2862 { 2863 switch (XINT (x, 1)) 2864 { 2865 case UNSPEC_GOT: 2866 case UNSPEC_GOTOFF: 2867 case UNSPEC_PLT: 2868 case UNSPEC_TLSGD: 2869 case UNSPEC_TLSLD: 2870 case UNSPEC_TLSIE: 2871 case UNSPEC_TLSLE: 2872 case UNSPEC_ICT: 2873 return false; 2874 default: 2875 return true; 2876 } 2877 } 2878 break; 2879 case SYMBOL_REF: 2880 /* TLS symbols need a call to resolve in 2881 precompute_register_parameters. */ 2882 if (SYMBOL_REF_TLS_MODEL (x)) 2883 return false; 2884 break; 2885 default: 2886 return true; 2887 } 2888 2889 return true; 2890 } 2891 2892 /* Reorgnize the UNSPEC CONST and return its direct symbol. */ 2893 static rtx 2894 nds32_delegitimize_address (rtx x) 2895 { 2896 x = delegitimize_mem_from_attrs (x); 2897 2898 if (GET_CODE(x) == CONST) 2899 { 2900 rtx inner = XEXP (x, 0); 2901 2902 /* Handle for GOTOFF. */ 2903 if (GET_CODE (inner) == PLUS) 2904 inner = XEXP (inner, 0); 2905 2906 if (GET_CODE (inner) == UNSPEC) 2907 { 2908 switch (XINT (inner, 1)) 2909 { 2910 case UNSPEC_GOTINIT: 2911 case UNSPEC_GOT: 2912 case UNSPEC_GOTOFF: 2913 case UNSPEC_PLT: 2914 case UNSPEC_TLSGD: 2915 case UNSPEC_TLSLD: 2916 case UNSPEC_TLSIE: 2917 case UNSPEC_TLSLE: 2918 case UNSPEC_ICT: 2919 x = XVECEXP (inner, 0, 0); 2920 break; 2921 default: 2922 break; 2923 } 2924 } 2925 } 2926 return x; 2927 } 2928 2929 static machine_mode 2930 nds32_vectorize_preferred_simd_mode (scalar_mode mode) 2931 { 2932 if (!NDS32_EXT_DSP_P ()) 2933 return word_mode; 2934 2935 switch (mode) 2936 { 2937 case E_QImode: 2938 return V4QImode; 2939 case E_HImode: 2940 return V2HImode; 2941 default: 2942 return word_mode; 2943 } 2944 } 2945 2946 static bool 2947 nds32_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 2948 { 2949 switch (GET_CODE (x)) 2950 { 2951 case CONST: 2952 return !nds32_legitimate_constant_p (mode, x); 2953 case SYMBOL_REF: 2954 /* All symbols have to be accessed through gp-relative in PIC mode. */ 2955 /* We don't want to force symbol as constant pool in .text section, 2956 because we use the gp-relatived instruction to load in small 2957 or medium model. */ 2958 if (flag_pic 2959 || SYMBOL_REF_TLS_MODEL (x) 2960 || TARGET_CMODEL_SMALL 2961 || TARGET_CMODEL_MEDIUM) 2962 return true; 2963 break; 2964 case CONST_INT: 2965 case CONST_DOUBLE: 2966 if (flag_pic && (lra_in_progress || reload_completed)) 2967 return true; 2968 break; 2969 default: 2970 return false; 2971 } 2972 return false; 2973 } 2974 2975 2976 /* Condition Code Status. */ 2978 2979 /* -- Representation of condition codes using registers. */ 2980 2981 static void 2982 nds32_canonicalize_comparison (int *code, 2983 rtx *op0 ATTRIBUTE_UNUSED, 2984 rtx *op1, 2985 bool op0_preserve_value ATTRIBUTE_UNUSED) 2986 { 2987 /* When the instruction combination pass tries to combine a comparison insn 2988 with its previous insns, it also transforms the operator in order to 2989 minimize its constant field. For example, it tries to transform a 2990 comparison insn from 2991 (set (reg:SI 54) 2992 (ltu:SI (reg:SI 52) 2993 (const_int 10 [0xa]))) 2994 to 2995 (set (reg:SI 54) 2996 (leu:SI (reg:SI 52) 2997 (const_int 9 [0x9]))) 2998 2999 However, the nds32 target only provides instructions supporting the LTU 3000 operation directly, and the implementation of the pattern "cbranchsi4" 3001 only expands the LTU form. In order to handle the non-LTU operations 3002 generated from passes other than the RTL expansion pass, we have to 3003 implement this hook to revert those changes. Since we only expand the LTU 3004 operator in the RTL expansion pass, we might only need to handle the LEU 3005 case, unless we find other optimization passes perform more aggressive 3006 transformations. */ 3007 3008 if (*code == LEU && CONST_INT_P (*op1)) 3009 { 3010 *op1 = gen_int_mode (INTVAL (*op1) + 1, SImode); 3011 *code = LTU; 3012 } 3013 } 3014 3015 3016 /* Describing Relative Costs of Operations. */ 3018 3019 static int 3020 nds32_register_move_cost (machine_mode mode, 3021 reg_class_t from, 3022 reg_class_t to) 3023 { 3024 /* In garywolf cpu, FPR to GPR is chaper than other cpu. */ 3025 if (TARGET_PIPELINE_GRAYWOLF) 3026 { 3027 if (GET_MODE_SIZE (mode) == 8) 3028 { 3029 /* DPR to GPR. */ 3030 if (from == FP_REGS && to != FP_REGS) 3031 return 3; 3032 /* GPR to DPR. */ 3033 if (from != FP_REGS && to == FP_REGS) 3034 return 2; 3035 } 3036 else 3037 { 3038 if ((from == FP_REGS && to != FP_REGS) 3039 || (from != FP_REGS && to == FP_REGS)) 3040 return 2; 3041 } 3042 } 3043 3044 if ((from == FP_REGS && to != FP_REGS) 3045 || (from != FP_REGS && to == FP_REGS)) 3046 return 3; 3047 else if (from == HIGH_REGS || to == HIGH_REGS) 3048 return optimize_size ? 6 : 2; 3049 else 3050 return 2; 3051 } 3052 3053 static int 3054 nds32_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 3055 reg_class_t rclass ATTRIBUTE_UNUSED, 3056 bool in ATTRIBUTE_UNUSED) 3057 { 3058 return 8; 3059 } 3060 3061 /* This target hook describes the relative costs of RTL expressions. 3062 Return 'true' when all subexpressions of x have been processed. 3063 Return 'false' to sum the costs of sub-rtx, plus cost of this operation. 3064 Refer to gcc/rtlanal.cc for more information. */ 3065 static bool 3066 nds32_rtx_costs (rtx x, 3067 machine_mode mode, 3068 int outer_code, 3069 int opno, 3070 int *total, 3071 bool speed) 3072 { 3073 return nds32_rtx_costs_impl (x, mode, outer_code, opno, total, speed); 3074 } 3075 3076 static int 3077 nds32_address_cost (rtx address, 3078 machine_mode mode, 3079 addr_space_t as, 3080 bool speed) 3081 { 3082 return nds32_address_cost_impl (address, mode, as, speed); 3083 } 3084 3085 3086 /* Dividing the Output into Sections (Texts, Data, . . . ). */ 3088 3089 /* If references to a symbol or a constant must be treated differently 3090 depending on something about the variable or function named by the symbol 3091 (such as what section it is in), we use this hook to store flags 3092 in symbol_ref rtx. */ 3093 static void 3094 nds32_encode_section_info (tree decl, rtx rtl, int new_decl_p) 3095 { 3096 default_encode_section_info (decl, rtl, new_decl_p); 3097 3098 /* For the memory rtx, if it references to rodata section, we can store 3099 NDS32_SYMBOL_FLAG_RODATA flag into symbol_ref rtx so that the 3100 nds32_legitimate_address_p() can determine how to treat such symbol_ref 3101 based on -mcmodel=X and this information. */ 3102 if (MEM_P (rtl) && MEM_READONLY_P (rtl)) 3103 { 3104 rtx addr = XEXP (rtl, 0); 3105 3106 if (GET_CODE (addr) == SYMBOL_REF) 3107 { 3108 /* For (mem (symbol_ref X)) case. */ 3109 SYMBOL_REF_FLAGS (addr) |= NDS32_SYMBOL_FLAG_RODATA; 3110 } 3111 else if (GET_CODE (addr) == CONST 3112 && GET_CODE (XEXP (addr, 0)) == PLUS) 3113 { 3114 /* For (mem (const (plus (symbol_ref X) (const_int N)))) case. */ 3115 rtx plus_op = XEXP (addr, 0); 3116 rtx op0 = XEXP (plus_op, 0); 3117 rtx op1 = XEXP (plus_op, 1); 3118 3119 if (GET_CODE (op0) == SYMBOL_REF && CONST_INT_P (op1)) 3120 SYMBOL_REF_FLAGS (op0) |= NDS32_SYMBOL_FLAG_RODATA; 3121 } 3122 } 3123 } 3124 3125 3126 /* Defining the Output Assembler Language. */ 3128 3129 /* -- The Overall Framework of an Assembler File. */ 3130 3131 static void 3132 nds32_asm_file_start (void) 3133 { 3134 default_file_start (); 3135 3136 if (flag_pic) 3137 fprintf (asm_out_file, "\t.pic\n"); 3138 3139 /* Tell assembler which ABI we are using. */ 3140 fprintf (asm_out_file, "\t! ABI version\n"); 3141 if (TARGET_HARD_FLOAT) 3142 fprintf (asm_out_file, "\t.abi_2fp_plus\n"); 3143 else 3144 fprintf (asm_out_file, "\t.abi_2\n"); 3145 3146 /* Tell assembler that this asm code is generated by compiler. */ 3147 fprintf (asm_out_file, "\t! This asm file is generated by compiler\n"); 3148 fprintf (asm_out_file, "\t.flag\tverbatim\n"); 3149 3150 /* Insert directive for linker to distinguish object's ict flag. */ 3151 if (!TARGET_LINUX_ABI) 3152 { 3153 if (TARGET_ICT_MODEL_LARGE) 3154 fprintf (asm_out_file, "\t.ict_model\tlarge\n"); 3155 else 3156 fprintf (asm_out_file, "\t.ict_model\tsmall\n"); 3157 } 3158 3159 /* We need to provide the size of each vector for interrupt handler 3160 under elf toolchain. */ 3161 if (!TARGET_LINUX_ABI) 3162 { 3163 fprintf (asm_out_file, "\t! This vector size directive is required " 3164 "for checking inconsistency on interrupt handler\n"); 3165 fprintf (asm_out_file, "\t.vec_size\t%d\n", nds32_isr_vector_size); 3166 } 3167 3168 /* If user enables '-mforce-fp-as-gp' or compiles programs with -Os, 3169 the compiler may produce 'la $fp,_FP_BASE_' instruction 3170 at prologue for fp-as-gp optimization. 3171 We should emit weak reference of _FP_BASE_ to avoid undefined reference 3172 in case user does not pass '--relax' option to linker. */ 3173 if (!TARGET_LINUX_ABI && (TARGET_FORCE_FP_AS_GP || optimize_size)) 3174 { 3175 fprintf (asm_out_file, "\t! This weak reference is required to do " 3176 "fp-as-gp link time optimization\n"); 3177 fprintf (asm_out_file, "\t.weak\t_FP_BASE_\n"); 3178 } 3179 3180 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3181 3182 if (TARGET_ISA_V2) 3183 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V2"); 3184 if (TARGET_ISA_V3) 3185 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3"); 3186 if (TARGET_ISA_V3M) 3187 fprintf (asm_out_file, "\t! ISA family\t\t: %s\n", "V3M"); 3188 3189 switch (nds32_cpu_option) 3190 { 3191 case CPU_N6: 3192 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N6"); 3193 break; 3194 3195 case CPU_N7: 3196 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N7"); 3197 break; 3198 3199 case CPU_N8: 3200 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N8"); 3201 break; 3202 3203 case CPU_E8: 3204 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "E8"); 3205 break; 3206 3207 case CPU_N9: 3208 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N9"); 3209 break; 3210 3211 case CPU_N10: 3212 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N10"); 3213 break; 3214 3215 case CPU_GRAYWOLF: 3216 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "Graywolf"); 3217 break; 3218 3219 case CPU_N12: 3220 case CPU_N13: 3221 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "N13"); 3222 break; 3223 3224 case CPU_SIMPLE: 3225 fprintf (asm_out_file, "\t! Pipeline model\t: %s\n", "SIMPLE"); 3226 break; 3227 3228 default: 3229 gcc_unreachable (); 3230 } 3231 3232 if (TARGET_CMODEL_SMALL) 3233 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "SMALL"); 3234 if (TARGET_CMODEL_MEDIUM) 3235 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "MEDIUM"); 3236 if (TARGET_CMODEL_LARGE) 3237 fprintf (asm_out_file, "\t! Code model\t\t: %s\n", "LARGE"); 3238 3239 fprintf (asm_out_file, "\t! Endian setting\t: %s\n", 3240 ((TARGET_BIG_ENDIAN) ? "big-endian" 3241 : "little-endian")); 3242 fprintf (asm_out_file, "\t! Use SP floating-point instruction\t: %s\n", 3243 ((TARGET_FPU_SINGLE) ? "Yes" 3244 : "No")); 3245 fprintf (asm_out_file, "\t! Use DP floating-point instruction\t: %s\n", 3246 ((TARGET_FPU_DOUBLE) ? "Yes" 3247 : "No")); 3248 fprintf (asm_out_file, "\t! ABI version\t\t: %s\n", 3249 ((TARGET_HARD_FLOAT) ? "ABI2FP+" 3250 : "ABI2")); 3251 3252 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3253 3254 fprintf (asm_out_file, "\t! Use conditional move\t\t: %s\n", 3255 ((TARGET_CMOV) ? "Yes" 3256 : "No")); 3257 fprintf (asm_out_file, "\t! Use performance extension\t: %s\n", 3258 ((TARGET_EXT_PERF) ? "Yes" 3259 : "No")); 3260 fprintf (asm_out_file, "\t! Use performance extension 2\t: %s\n", 3261 ((TARGET_EXT_PERF2) ? "Yes" 3262 : "No")); 3263 fprintf (asm_out_file, "\t! Use string extension\t\t: %s\n", 3264 ((TARGET_EXT_STRING) ? "Yes" 3265 : "No")); 3266 3267 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3268 3269 fprintf (asm_out_file, "\t! V3PUSH instructions\t: %s\n", 3270 ((TARGET_V3PUSH) ? "Yes" 3271 : "No")); 3272 fprintf (asm_out_file, "\t! 16-bit instructions\t: %s\n", 3273 ((TARGET_16_BIT) ? "Yes" 3274 : "No")); 3275 fprintf (asm_out_file, "\t! Reduced registers set\t: %s\n", 3276 ((TARGET_REDUCED_REGS) ? "Yes" 3277 : "No")); 3278 3279 fprintf (asm_out_file, "\t! Support unaligned access\t\t: %s\n", 3280 (flag_unaligned_access ? "Yes" 3281 : "No")); 3282 3283 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3284 3285 if (optimize_size) 3286 fprintf (asm_out_file, "\t! Optimization level\t: -Os\n"); 3287 else if (optimize_fast) 3288 fprintf (asm_out_file, "\t! Optimization level\t: -Ofast\n"); 3289 else if (optimize_debug) 3290 fprintf (asm_out_file, "\t! Optimization level\t: -Og\n"); 3291 else 3292 fprintf (asm_out_file, "\t! Optimization level\t: -O%d\n", optimize); 3293 3294 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3295 3296 fprintf (asm_out_file, "\t! Cache block size\t: %d\n", 3297 nds32_cache_block_size); 3298 3299 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3300 3301 nds32_asm_file_start_for_isr (); 3302 } 3303 3304 static void 3305 nds32_asm_file_end (void) 3306 { 3307 nds32_asm_file_end_for_isr (); 3308 3309 /* The NDS32 Linux stack is mapped non-executable by default, so add a 3310 .note.GNU-stack section. */ 3311 if (TARGET_LINUX_ABI) 3312 file_end_indicate_exec_stack (); 3313 3314 fprintf (asm_out_file, "\t! ------------------------------------\n"); 3315 } 3316 3317 static bool 3318 nds32_asm_output_addr_const_extra (FILE *file, rtx x) 3319 { 3320 if (GET_CODE (x) == UNSPEC) 3321 { 3322 switch (XINT (x, 1)) 3323 { 3324 case UNSPEC_GOTINIT: 3325 output_addr_const (file, XVECEXP (x, 0, 0)); 3326 break; 3327 case UNSPEC_GOTOFF: 3328 output_addr_const (file, XVECEXP (x, 0, 0)); 3329 fputs ("@GOTOFF", file); 3330 break; 3331 case UNSPEC_GOT: 3332 output_addr_const (file, XVECEXP (x, 0, 0)); 3333 fputs ("@GOT", file); 3334 break; 3335 case UNSPEC_PLT: 3336 output_addr_const (file, XVECEXP (x, 0, 0)); 3337 fputs ("@PLT", file); 3338 break; 3339 case UNSPEC_TLSGD: 3340 output_addr_const (file, XVECEXP (x, 0, 0)); 3341 fputs ("@TLSDESC", file); 3342 break; 3343 case UNSPEC_TLSLD: 3344 output_addr_const (file, XVECEXP (x, 0, 0)); 3345 fputs ("@TLSDESC", file); 3346 break; 3347 case UNSPEC_TLSIE: 3348 output_addr_const (file, XVECEXP (x, 0, 0)); 3349 fputs ("@GOTTPOFF", file); 3350 break; 3351 case UNSPEC_TLSLE: 3352 output_addr_const (file, XVECEXP (x, 0, 0)); 3353 fputs ("@TPOFF", file); 3354 break; 3355 case UNSPEC_ICT: 3356 output_addr_const (file, XVECEXP (x, 0, 0)); 3357 fputs ("@ICT", file); 3358 break; 3359 default: 3360 return false; 3361 } 3362 return true; 3363 } 3364 else 3365 return false; 3366 } 3367 3368 /* -- Output and Generation of Labels. */ 3369 3370 static void 3371 nds32_asm_globalize_label (FILE *stream, const char *name) 3372 { 3373 fputs ("\t.global\t", stream); 3374 assemble_name (stream, name); 3375 fputs ("\n", stream); 3376 } 3377 3378 /* -- Output of Assembler Instructions. */ 3379 3380 static void 3381 nds32_print_operand (FILE *stream, rtx x, int code) 3382 { 3383 HOST_WIDE_INT op_value = 0; 3384 HOST_WIDE_INT one_position; 3385 HOST_WIDE_INT zero_position; 3386 bool pick_lsb_p = false; 3387 bool pick_msb_p = false; 3388 int regno; 3389 3390 if (CONST_INT_P (x)) 3391 op_value = INTVAL (x); 3392 3393 switch (code) 3394 { 3395 case 0 : 3396 /* Do nothing special. */ 3397 break; 3398 3399 case 'b': 3400 /* Use exact_log2() to search the 0-bit position. */ 3401 gcc_assert (CONST_INT_P (x)); 3402 zero_position = exact_log2 (~UINTVAL (x) & GET_MODE_MASK (SImode)); 3403 gcc_assert (zero_position != -1); 3404 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, zero_position); 3405 3406 /* No need to handle following process, so return immediately. */ 3407 return; 3408 3409 case 'e': 3410 gcc_assert (MEM_P (x) 3411 && GET_CODE (XEXP (x, 0)) == PLUS 3412 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT); 3413 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (XEXP (XEXP (x, 0), 1))); 3414 3415 /* No need to handle following process, so return immediately. */ 3416 return; 3417 3418 case 'v': 3419 gcc_assert (CONST_INT_P (x) 3420 && (INTVAL (x) == 0 3421 || INTVAL (x) == 8 3422 || INTVAL (x) == 16 3423 || INTVAL (x) == 24)); 3424 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) / 8); 3425 3426 /* No need to handle following process, so return immediately. */ 3427 return; 3428 3429 case 'B': 3430 /* Use exact_log2() to search the 1-bit position. */ 3431 gcc_assert (CONST_INT_P (x)); 3432 one_position = exact_log2 (UINTVAL (x) & GET_MODE_MASK (SImode)); 3433 gcc_assert (one_position != -1); 3434 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, one_position); 3435 3436 /* No need to handle following process, so return immediately. */ 3437 return; 3438 3439 case 'L': 3440 /* X is supposed to be REG rtx. */ 3441 gcc_assert (REG_P (x)); 3442 /* Claim that we are going to pick LSB part of X. */ 3443 pick_lsb_p = true; 3444 break; 3445 3446 case 'H': 3447 /* X is supposed to be REG rtx. */ 3448 gcc_assert (REG_P (x)); 3449 /* Claim that we are going to pick MSB part of X. */ 3450 pick_msb_p = true; 3451 break; 3452 3453 case 'V': 3454 /* 'x' is supposed to be CONST_INT, get the value. */ 3455 gcc_assert (CONST_INT_P (x)); 3456 3457 /* According to the Andes architecture, 3458 the system/user register index range is 0 ~ 1023. 3459 In order to avoid conflict between user-specified-integer value 3460 and enum-specified-register value, 3461 the 'enum nds32_intrinsic_registers' value 3462 in nds32_intrinsic.h starts from 1024. */ 3463 if (op_value < 1024 && op_value >= 0) 3464 { 3465 /* If user gives integer value directly (0~1023), 3466 we just print out the value. */ 3467 fprintf (stream, HOST_WIDE_INT_PRINT_DEC, op_value); 3468 } 3469 else if (op_value < 0 3470 || op_value >= ((int) ARRAY_SIZE (nds32_intrinsic_register_names) 3471 + 1024)) 3472 { 3473 /* The enum index value for array size is out of range. */ 3474 error ("intrinsic register index is out of range"); 3475 } 3476 else 3477 { 3478 /* If user applies normal way with __NDS32_REG_XXX__ enum data, 3479 we can print out register name. Remember to substract 1024. */ 3480 fprintf (stream, "%s", 3481 nds32_intrinsic_register_names[op_value - 1024]); 3482 } 3483 3484 /* No need to handle following process, so return immediately. */ 3485 return; 3486 3487 case 'R': /* cctl valck */ 3488 /* Note the cctl divide to 5 group and share the same name table. */ 3489 if (op_value < 0 || op_value > 4) 3490 error ("CCTL intrinsic function subtype out of range"); 3491 fprintf (stream, "%s", nds32_cctl_names[op_value]); 3492 return; 3493 3494 case 'T': /* cctl idxwbinv */ 3495 /* Note the cctl divide to 5 group and share the same name table. */ 3496 if (op_value < 0 || op_value > 4) 3497 error ("CCTL intrinsic function subtype out of range"); 3498 fprintf (stream, "%s", nds32_cctl_names[op_value + 4]); 3499 return; 3500 3501 case 'U': /* cctl vawbinv */ 3502 /* Note the cctl divide to 5 group and share the same name table. */ 3503 if (op_value < 0 || op_value > 4) 3504 error ("CCTL intrinsic function subtype out of range"); 3505 fprintf (stream, "%s", nds32_cctl_names[op_value + 8]); 3506 return; 3507 3508 case 'X': /* cctl idxread */ 3509 /* Note the cctl divide to 5 group and share the same name table. */ 3510 if (op_value < 0 || op_value > 4) 3511 error ("CCTL intrinsic function subtype out of range"); 3512 fprintf (stream, "%s", nds32_cctl_names[op_value + 12]); 3513 return; 3514 3515 case 'W': /* cctl idxwitre */ 3516 /* Note the cctl divide to 5 group and share the same name table. */ 3517 if (op_value < 0 || op_value > 4) 3518 error ("CCTL intrinsic function subtype out of range"); 3519 fprintf (stream, "%s", nds32_cctl_names[op_value + 16]); 3520 return; 3521 3522 case 'Z': /* dpref */ 3523 fprintf (stream, "%s", nds32_dpref_names[op_value]); 3524 return; 3525 3526 default : 3527 /* Unknown flag. */ 3528 output_operand_lossage ("invalid operand output code"); 3529 break; 3530 } 3531 3532 switch (GET_CODE (x)) 3533 { 3534 case LABEL_REF: 3535 output_addr_const (stream, x); 3536 break; 3537 3538 case SYMBOL_REF: 3539 output_addr_const (stream, x); 3540 3541 if (!TARGET_LINUX_ABI && nds32_indirect_call_referenced_p (x)) 3542 fprintf (stream, "@ICT"); 3543 3544 break; 3545 3546 case REG: 3547 /* Print a Double-precision register name. */ 3548 if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) 3549 && NDS32_IS_FPR_REGNUM (REGNO (x))) 3550 { 3551 regno = REGNO (x); 3552 if (!NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno)) 3553 { 3554 output_operand_lossage ("invalid operand for code '%c'", code); 3555 break; 3556 } 3557 fprintf (stream, "$fd%d", (regno - NDS32_FIRST_FPR_REGNUM) >> 1); 3558 break; 3559 } 3560 3561 /* Print LSB or MSB part of register pair if the 3562 constraint modifier 'L' or 'H' is specified. */ 3563 if ((GET_MODE (x) == DImode || GET_MODE (x) == DFmode) 3564 && NDS32_IS_GPR_REGNUM (REGNO (x))) 3565 { 3566 if ((pick_lsb_p && WORDS_BIG_ENDIAN) 3567 || (pick_msb_p && !WORDS_BIG_ENDIAN)) 3568 { 3569 /* If we would like to print out LSB register under big-endian, 3570 or print out MSB register under little-endian, we need to 3571 increase register number. */ 3572 regno = REGNO (x); 3573 regno++; 3574 fputs (reg_names[regno], stream); 3575 break; 3576 } 3577 } 3578 3579 /* Forbid using static chain register ($r16) 3580 on reduced-set registers configuration. */ 3581 if (TARGET_REDUCED_REGS 3582 && REGNO (x) == STATIC_CHAIN_REGNUM) 3583 sorry ("a nested function is not supported for reduced registers"); 3584 3585 /* Normal cases, print out register name. */ 3586 fputs (reg_names[REGNO (x)], stream); 3587 break; 3588 3589 case MEM: 3590 output_address (GET_MODE (x), XEXP (x, 0)); 3591 break; 3592 3593 case HIGH: 3594 if (GET_CODE (XEXP (x, 0)) == CONST_DOUBLE) 3595 { 3596 const REAL_VALUE_TYPE *rv; 3597 long val; 3598 gcc_assert (GET_MODE (x) == SFmode); 3599 3600 rv = CONST_DOUBLE_REAL_VALUE (XEXP (x, 0)); 3601 REAL_VALUE_TO_TARGET_SINGLE (*rv, val); 3602 3603 fprintf (stream, "hi20(0x%lx)", val); 3604 } 3605 else 3606 gcc_unreachable (); 3607 break; 3608 3609 case CONST_DOUBLE: 3610 const REAL_VALUE_TYPE *rv; 3611 long val; 3612 gcc_assert (GET_MODE (x) == SFmode); 3613 3614 rv = CONST_DOUBLE_REAL_VALUE (x); 3615 REAL_VALUE_TO_TARGET_SINGLE (*rv, val); 3616 3617 fprintf (stream, "0x%lx", val); 3618 break; 3619 3620 case CODE_LABEL: 3621 case CONST_INT: 3622 case CONST: 3623 output_addr_const (stream, x); 3624 break; 3625 3626 case CONST_VECTOR: 3627 fprintf (stream, HOST_WIDE_INT_PRINT_HEX, const_vector_to_hwint (x)); 3628 break; 3629 3630 case LO_SUM: 3631 /* This is a special case for inline assembly using memory address 'p'. 3632 The inline assembly code is expected to use pesudo instruction 3633 for the operand. EX: la */ 3634 output_addr_const (stream, XEXP(x, 1)); 3635 break; 3636 3637 default: 3638 /* Generally, output_addr_const () is able to handle most cases. 3639 We want to see what CODE could appear, 3640 so we use gcc_unreachable() to stop it. */ 3641 debug_rtx (x); 3642 gcc_unreachable (); 3643 break; 3644 } 3645 } 3646 3647 static void 3648 nds32_print_operand_address (FILE *stream, 3649 machine_mode mode ATTRIBUTE_UNUSED, 3650 rtx x) 3651 { 3652 rtx op0, op1; 3653 3654 switch (GET_CODE (x)) 3655 { 3656 case SYMBOL_REF: 3657 case CONST: 3658 /* [ + symbol_ref] */ 3659 /* [ + const_addr], where const_addr = symbol_ref + const_int */ 3660 fputs ("[ + ", stream); 3661 output_addr_const (stream, x); 3662 fputs ("]", stream); 3663 break; 3664 3665 case LO_SUM: 3666 /* This is a special case for inline assembly using memory operand 'm'. 3667 The inline assembly code is expected to use pesudo instruction 3668 for the operand. EX: [ls].[bhw] */ 3669 fputs ("[ + ", stream); 3670 op1 = XEXP (x, 1); 3671 output_addr_const (stream, op1); 3672 fputs ("]", stream); 3673 break; 3674 3675 case REG: 3676 /* Forbid using static chain register ($r16) 3677 on reduced-set registers configuration. */ 3678 if (TARGET_REDUCED_REGS 3679 && REGNO (x) == STATIC_CHAIN_REGNUM) 3680 sorry ("a nested function is not supported for reduced registers"); 3681 3682 /* [Ra] */ 3683 fprintf (stream, "[%s]", reg_names[REGNO (x)]); 3684 break; 3685 3686 case PLUS: 3687 op0 = XEXP (x, 0); 3688 op1 = XEXP (x, 1); 3689 3690 /* Checking op0, forbid using static chain register ($r16) 3691 on reduced-set registers configuration. */ 3692 if (TARGET_REDUCED_REGS 3693 && REG_P (op0) 3694 && REGNO (op0) == STATIC_CHAIN_REGNUM) 3695 sorry ("a nested function is not supported for reduced registers"); 3696 /* Checking op1, forbid using static chain register ($r16) 3697 on reduced-set registers configuration. */ 3698 if (TARGET_REDUCED_REGS 3699 && REG_P (op1) 3700 && REGNO (op1) == STATIC_CHAIN_REGNUM) 3701 sorry ("a nested function is not supported for reduced registers"); 3702 3703 if (REG_P (op0) && CONST_INT_P (op1)) 3704 { 3705 /* [Ra + imm] */ 3706 fprintf (stream, "[%s + (" HOST_WIDE_INT_PRINT_DEC ")]", 3707 reg_names[REGNO (op0)], INTVAL (op1)); 3708 } 3709 else if (REG_P (op0) && REG_P (op1)) 3710 { 3711 /* [Ra + Rb] */ 3712 fprintf (stream, "[%s + %s]", 3713 reg_names[REGNO (op0)], reg_names[REGNO (op1)]); 3714 } 3715 else if (GET_CODE (op0) == MULT && REG_P (op1)) 3716 { 3717 /* [Ra + Rb << sv] 3718 From observation, the pattern looks like: 3719 (plus:SI (mult:SI (reg:SI 58) 3720 (const_int 4 [0x4])) 3721 (reg/f:SI 57)) */ 3722 int sv; 3723 3724 /* We need to set sv to output shift value. */ 3725 if (INTVAL (XEXP (op0, 1)) == 1) 3726 sv = 0; 3727 else if (INTVAL (XEXP (op0, 1)) == 2) 3728 sv = 1; 3729 else if (INTVAL (XEXP (op0, 1)) == 4) 3730 sv = 2; 3731 else if (INTVAL (XEXP (op0, 1)) == 8) 3732 sv = 3; 3733 else 3734 gcc_unreachable (); 3735 3736 fprintf (stream, "[%s + %s << %d]", 3737 reg_names[REGNO (op1)], 3738 reg_names[REGNO (XEXP (op0, 0))], 3739 sv); 3740 } 3741 else if (GET_CODE (op0) == ASHIFT && REG_P (op1)) 3742 { 3743 /* [Ra + Rb << sv] 3744 In normal, ASHIFT can be converted to MULT like above case. 3745 But when the address rtx does not go through canonicalize_address 3746 defined in fwprop, we'll need this case. */ 3747 int sv = INTVAL (XEXP (op0, 1)); 3748 gcc_assert (sv <= 3 && sv >=0); 3749 3750 fprintf (stream, "[%s + %s << %d]", 3751 reg_names[REGNO (op1)], 3752 reg_names[REGNO (XEXP (op0, 0))], 3753 sv); 3754 } 3755 else 3756 { 3757 /* The control flow is not supposed to be here. */ 3758 debug_rtx (x); 3759 gcc_unreachable (); 3760 } 3761 3762 break; 3763 3764 case POST_MODIFY: 3765 /* (post_modify (regA) (plus (regA) (regB))) 3766 (post_modify (regA) (plus (regA) (const_int))) 3767 We would like to extract 3768 regA and regB (or const_int) from plus rtx. */ 3769 op0 = XEXP (XEXP (x, 1), 0); 3770 op1 = XEXP (XEXP (x, 1), 1); 3771 3772 /* Checking op0, forbid using static chain register ($r16) 3773 on reduced-set registers configuration. */ 3774 if (TARGET_REDUCED_REGS 3775 && REG_P (op0) 3776 && REGNO (op0) == STATIC_CHAIN_REGNUM) 3777 sorry ("a nested function is not supported for reduced registers"); 3778 /* Checking op1, forbid using static chain register ($r16) 3779 on reduced-set registers configuration. */ 3780 if (TARGET_REDUCED_REGS 3781 && REG_P (op1) 3782 && REGNO (op1) == STATIC_CHAIN_REGNUM) 3783 sorry ("a nested function is not supported for reduced registers"); 3784 3785 if (REG_P (op0) && REG_P (op1)) 3786 { 3787 /* [Ra], Rb */ 3788 fprintf (stream, "[%s], %s", 3789 reg_names[REGNO (op0)], reg_names[REGNO (op1)]); 3790 } 3791 else if (REG_P (op0) && CONST_INT_P (op1)) 3792 { 3793 /* [Ra], imm */ 3794 fprintf (stream, "[%s], " HOST_WIDE_INT_PRINT_DEC, 3795 reg_names[REGNO (op0)], INTVAL (op1)); 3796 } 3797 else 3798 { 3799 /* The control flow is not supposed to be here. */ 3800 debug_rtx (x); 3801 gcc_unreachable (); 3802 } 3803 3804 break; 3805 3806 case POST_INC: 3807 case POST_DEC: 3808 op0 = XEXP (x, 0); 3809 3810 /* Checking op0, forbid using static chain register ($r16) 3811 on reduced-set registers configuration. */ 3812 if (TARGET_REDUCED_REGS 3813 && REG_P (op0) 3814 && REGNO (op0) == STATIC_CHAIN_REGNUM) 3815 sorry ("a nested function is not supported for reduced registers"); 3816 3817 if (REG_P (op0)) 3818 { 3819 /* "[Ra], 1/2/4" or "[Ra], -1/-2/-4" 3820 The 1/2/4 or -1/-2/-4 have been displayed in nds32.md. 3821 We only need to deal with register Ra. */ 3822 fprintf (stream, "[%s]", reg_names[REGNO (op0)]); 3823 } 3824 else 3825 { 3826 /* The control flow is not supposed to be here. */ 3827 debug_rtx (x); 3828 gcc_unreachable (); 3829 } 3830 3831 break; 3832 3833 default : 3834 /* Generally, output_addr_const () is able to handle most cases. 3835 We want to see what CODE could appear, 3836 so we use gcc_unreachable() to stop it. */ 3837 debug_rtx (x); 3838 gcc_unreachable (); 3839 break; 3840 } 3841 } 3842 3843 /* -- Assembler Commands for Exception Regions. */ 3844 3845 static rtx 3846 nds32_dwarf_register_span (rtx reg) 3847 { 3848 rtx dwarf_high, dwarf_low; 3849 rtx dwarf_single; 3850 machine_mode mode; 3851 int regno; 3852 3853 mode = GET_MODE (reg); 3854 regno = REGNO (reg); 3855 3856 /* We need to adjust dwarf register information for floating-point registers 3857 rather than using default register number mapping. */ 3858 if (regno >= NDS32_FIRST_FPR_REGNUM 3859 && regno <= NDS32_LAST_FPR_REGNUM) 3860 { 3861 if (mode == DFmode || mode == SCmode) 3862 { 3863 /* By default, GCC maps increasing register numbers to increasing 3864 memory locations, but paired FPRs in NDS32 target are always 3865 big-endian, i.e.: 3866 3867 fd0 : fs0 fs1 3868 (MSB) (LSB) 3869 3870 We must return parallel rtx to represent such layout. */ 3871 dwarf_high = gen_rtx_REG (word_mode, regno); 3872 dwarf_low = gen_rtx_REG (word_mode, regno + 1); 3873 return gen_rtx_PARALLEL (VOIDmode, 3874 gen_rtvec (2, dwarf_low, dwarf_high)); 3875 } 3876 else if (mode == DCmode) 3877 { 3878 rtx dwarf_high_re = gen_rtx_REG (word_mode, regno); 3879 rtx dwarf_low_re = gen_rtx_REG (word_mode, regno + 1); 3880 rtx dwarf_high_im = gen_rtx_REG (word_mode, regno); 3881 rtx dwarf_low_im = gen_rtx_REG (word_mode, regno + 1); 3882 return gen_rtx_PARALLEL (VOIDmode, 3883 gen_rtvec (4, dwarf_low_re, dwarf_high_re, 3884 dwarf_high_im, dwarf_low_im)); 3885 } 3886 else if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) 3887 { 3888 return NULL_RTX; 3889 } 3890 else 3891 { 3892 /* We should not be here. */ 3893 gcc_unreachable (); 3894 } 3895 } 3896 3897 return NULL_RTX; 3898 } 3899 3900 /* Map internal gcc register numbers to DWARF2 register numbers. */ 3901 3902 unsigned int 3903 nds32_dbx_register_number (unsigned int regno) 3904 { 3905 /* The nds32 port in GDB maintains a mapping between dwarf register 3906 number and displayed register name. For backward compatibility to 3907 previous toolchain, currently our gdb still has four registers 3908 (d0.l, d0.h, d1.l, and d1.h) between GPR and FPR while compiler 3909 does not count those four registers in its register number table. 3910 So we have to add 4 on its register number and then create new 3911 dwarf information. Hopefully we can discard such workaround 3912 in the future. */ 3913 if (NDS32_IS_FPR_REGNUM (regno)) 3914 return regno + 4; 3915 3916 return regno; 3917 } 3918 3919 3920 /* Defining target-specific uses of __attribute__. */ 3922 3923 /* Add some checking after merging attributes. */ 3924 static tree 3925 nds32_merge_decl_attributes (tree olddecl, tree newdecl) 3926 { 3927 tree combined_attrs; 3928 3929 /* Create combined attributes. */ 3930 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), 3931 DECL_ATTRIBUTES (newdecl)); 3932 3933 /* Since newdecl is acutally a duplicate of olddecl, 3934 we can take olddecl for some operations. */ 3935 if (TREE_CODE (olddecl) == FUNCTION_DECL) 3936 { 3937 /* Check isr-specific attributes conflict. */ 3938 nds32_check_isr_attrs_conflict (olddecl, combined_attrs); 3939 } 3940 3941 return combined_attrs; 3942 } 3943 3944 /* Add some checking when inserting attributes. */ 3945 static void 3946 nds32_insert_attributes (tree decl, tree *attributes) 3947 { 3948 /* A "indirect_call" function attribute implies "noinline" and "noclone" 3949 for elf toolchain to support ROM patch mechanism. */ 3950 if (TREE_CODE (decl) == FUNCTION_DECL 3951 && lookup_attribute ("indirect_call", *attributes) != NULL) 3952 { 3953 tree new_attrs = *attributes; 3954 3955 if (TARGET_LINUX_ABI) 3956 error ("cannot use %<indirect_call%> attribute under linux toolchain"); 3957 3958 if (lookup_attribute ("noinline", new_attrs) == NULL) 3959 new_attrs = tree_cons (get_identifier ("noinline"), NULL, new_attrs); 3960 if (lookup_attribute ("noclone", new_attrs) == NULL) 3961 new_attrs = tree_cons (get_identifier ("noclone"), NULL, new_attrs); 3962 3963 if (!TREE_PUBLIC (decl)) 3964 error ("%<indirect_call%> attribute cannot apply for static function"); 3965 3966 *attributes = new_attrs; 3967 } 3968 3969 /* For function declaration, we need to check isr-specific attributes: 3970 1. Call nds32_check_isr_attrs_conflict() to check any conflict. 3971 2. Check valid integer value for interrupt/exception. 3972 3. Check valid integer value for reset. 3973 4. Check valid function for nmi/warm. */ 3974 if (TREE_CODE (decl) == FUNCTION_DECL) 3975 { 3976 tree func_attrs; 3977 tree intr, excp, reset; 3978 3979 /* Pick up function attributes. */ 3980 func_attrs = *attributes; 3981 3982 /* 1. Call nds32_check_isr_attrs_conflict() to check any conflict. */ 3983 nds32_check_isr_attrs_conflict (decl, func_attrs); 3984 3985 /* Now we are starting to check valid id value 3986 for interrupt/exception/reset. 3987 Note that we ONLY check its validity here. 3988 To construct isr vector information, it is still performed 3989 by nds32_construct_isr_vectors_information(). */ 3990 intr = lookup_attribute ("interrupt", func_attrs); 3991 excp = lookup_attribute ("exception", func_attrs); 3992 reset = lookup_attribute ("reset", func_attrs); 3993 3994 /* The following code may use attribute arguments. If there is no 3995 argument from source code, it will cause segmentation fault. 3996 Therefore, return dircetly and report error message later. */ 3997 if ((intr && TREE_VALUE (intr) == NULL) 3998 || (excp && TREE_VALUE (excp) == NULL) 3999 || (reset && TREE_VALUE (reset) == NULL)) 4000 return; 4001 4002 /* ------------------------------------------------------------- */ 4003 /* FIXME: 4004 FOR BACKWARD COMPATIBILITY, we need to support following patterns: 4005 4006 __attribute__((interrupt("XXX;YYY;id=ZZZ"))) 4007 __attribute__((exception("XXX;YYY;id=ZZZ"))) 4008 __attribute__((reset("vectors=XXX;nmi_func=YYY;warm_func=ZZZ"))) 4009 4010 If interrupt/exception/reset appears and its argument is a 4011 STRING_CST, we will use other functions to parse string in the 4012 nds32_construct_isr_vectors_information() and then set necessary 4013 isr information in the nds32_isr_vectors[] array. Here we can 4014 just return immediately to avoid new-syntax checking. */ 4015 if (intr != NULL_TREE 4016 && TREE_CODE (TREE_VALUE (TREE_VALUE (intr))) == STRING_CST) 4017 return; 4018 if (excp != NULL_TREE 4019 && TREE_CODE (TREE_VALUE (TREE_VALUE (excp))) == STRING_CST) 4020 return; 4021 if (reset != NULL_TREE 4022 && TREE_CODE (TREE_VALUE (TREE_VALUE (reset))) == STRING_CST) 4023 return; 4024 /* ------------------------------------------------------------- */ 4025 4026 if (intr || excp) 4027 { 4028 /* Deal with interrupt/exception. */ 4029 tree id_list; 4030 unsigned int lower_bound, upper_bound; 4031 4032 /* The way to handle interrupt or exception is the same, 4033 we just need to take care of actual vector number. 4034 For interrupt(0..63), the actual vector number is (9..72). 4035 For exception(1..8), the actual vector number is (1..8). */ 4036 lower_bound = (intr) ? (0) : (1); 4037 upper_bound = (intr) ? (63) : (8); 4038 4039 /* Prepare id list so that we can traverse id value. */ 4040 id_list = (intr) ? (TREE_VALUE (intr)) : (TREE_VALUE (excp)); 4041 4042 /* 2. Check valid integer value for interrupt/exception. */ 4043 while (id_list) 4044 { 4045 tree id; 4046 4047 /* Pick up each vector id value. */ 4048 id = TREE_VALUE (id_list); 4049 /* Issue error if it is not a valid integer value. */ 4050 if (TREE_CODE (id) != INTEGER_CST 4051 || wi::ltu_p (wi::to_wide (id), lower_bound) 4052 || wi::gtu_p (wi::to_wide (id), upper_bound)) 4053 error ("invalid id value for interrupt/exception attribute"); 4054 4055 /* Advance to next id. */ 4056 id_list = TREE_CHAIN (id_list); 4057 } 4058 } 4059 else if (reset) 4060 { 4061 /* Deal with reset. */ 4062 tree id_list; 4063 tree id; 4064 tree nmi, warm; 4065 unsigned int lower_bound; 4066 unsigned int upper_bound; 4067 4068 /* Prepare id_list and identify id value so that 4069 we can check if total number of vectors is valid. */ 4070 id_list = TREE_VALUE (reset); 4071 id = TREE_VALUE (id_list); 4072 4073 /* The maximum numbers for user's interrupt is 64. */ 4074 lower_bound = 0; 4075 upper_bound = 64; 4076 4077 /* 3. Check valid integer value for reset. */ 4078 if (TREE_CODE (id) != INTEGER_CST 4079 || wi::ltu_p (wi::to_wide (id), lower_bound) 4080 || wi::gtu_p (wi::to_wide (id), upper_bound)) 4081 error ("invalid id value for reset attribute"); 4082 4083 /* 4. Check valid function for nmi/warm. */ 4084 nmi = lookup_attribute ("nmi", func_attrs); 4085 warm = lookup_attribute ("warm", func_attrs); 4086 4087 if (nmi != NULL_TREE) 4088 { 4089 tree nmi_func_list; 4090 tree nmi_func; 4091 4092 nmi_func_list = TREE_VALUE (nmi); 4093 nmi_func = TREE_VALUE (nmi_func_list); 4094 4095 /* Issue error if it is not a valid nmi function. */ 4096 if (TREE_CODE (nmi_func) != IDENTIFIER_NODE) 4097 error ("invalid nmi function for reset attribute"); 4098 } 4099 4100 if (warm != NULL_TREE) 4101 { 4102 tree warm_func_list; 4103 tree warm_func; 4104 4105 warm_func_list = TREE_VALUE (warm); 4106 warm_func = TREE_VALUE (warm_func_list); 4107 4108 /* Issue error if it is not a valid warm function. */ 4109 if (TREE_CODE (warm_func) != IDENTIFIER_NODE) 4110 error ("invalid warm function for reset attribute"); 4111 } 4112 } 4113 else 4114 { 4115 /* No interrupt, exception, or reset attribute is set. */ 4116 return; 4117 } 4118 } 4119 } 4120 4121 static bool 4122 nds32_option_pragma_parse (tree args ATTRIBUTE_UNUSED, 4123 tree pop_target ATTRIBUTE_UNUSED) 4124 { 4125 /* Currently, we do not parse any pragma target by ourself, 4126 so just simply return false. */ 4127 return false; 4128 } 4129 4130 static void 4131 nds32_option_override (void) 4132 { 4133 /* After all the command options have been parsed, 4134 we shall deal with some flags for changing compiler settings. */ 4135 4136 /* At first, we check if we have to strictly 4137 set some flags based on ISA family. */ 4138 if (TARGET_ISA_V2) 4139 { 4140 /* Under V2 ISA, we need to strictly disable TARGET_V3PUSH. */ 4141 target_flags &= ~MASK_V3PUSH; 4142 } 4143 if (TARGET_ISA_V3) 4144 { 4145 /* If this is ARCH_V3J, we need to enable TARGET_REDUCED_REGS. */ 4146 if (nds32_arch_option == ARCH_V3J) 4147 target_flags |= MASK_REDUCED_REGS; 4148 } 4149 if (TARGET_ISA_V3M) 4150 { 4151 /* Under V3M ISA, we need to strictly enable TARGET_REDUCED_REGS. */ 4152 target_flags |= MASK_REDUCED_REGS; 4153 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF. */ 4154 target_flags &= ~MASK_EXT_PERF; 4155 /* Under V3M ISA, we need to strictly disable TARGET_EXT_PERF2. */ 4156 target_flags &= ~MASK_EXT_PERF2; 4157 /* Under V3M ISA, we need to strictly disable TARGET_EXT_STRING. */ 4158 target_flags &= ~MASK_EXT_STRING; 4159 4160 if (flag_pic) 4161 error ("not support %<-fpic%> option for v3m toolchain"); 4162 } 4163 4164 /* See if we are using reduced-set registers: 4165 $r0~$r5, $r6~$r10, $r15, $r28, $r29, $r30, $r31 4166 If so, we must forbid using $r11~$r14, $r16~$r27. */ 4167 if (TARGET_REDUCED_REGS) 4168 { 4169 int r; 4170 4171 /* Prevent register allocator from 4172 choosing it as doing register allocation. */ 4173 for (r = 11; r <= 14; r++) 4174 fixed_regs[r] = call_used_regs[r] = 1; 4175 for (r = 16; r <= 27; r++) 4176 fixed_regs[r] = call_used_regs[r] = 1; 4177 } 4178 4179 /* See if user explicitly would like to use fp-as-gp optimization. 4180 If so, we must prevent $fp from being allocated 4181 during register allocation. */ 4182 if (TARGET_FORCE_FP_AS_GP) 4183 fixed_regs[FP_REGNUM] = call_used_regs[FP_REGNUM] = 1; 4184 4185 if (!TARGET_16_BIT) 4186 { 4187 /* Under no 16 bit ISA, we need to strictly disable TARGET_V3PUSH. */ 4188 target_flags &= ~MASK_V3PUSH; 4189 } 4190 4191 if (TARGET_HARD_FLOAT && !(TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE)) 4192 { 4193 if (nds32_arch_option == ARCH_V3S || nds32_arch_option == ARCH_V3F) 4194 error ("Disable FPU ISA, " 4195 "the ABI option must be enable %<-mfloat-abi=soft%>"); 4196 else 4197 error ("%<-mabi=2fp+%> option only support when FPU available, " 4198 "must be enable %<-mext-fpu-sp%> or %<-mext-fpu-dp%>"); 4199 } 4200 4201 nds32_init_rtx_costs (); 4202 4203 nds32_register_passes (); 4204 } 4205 4206 4207 /* Miscellaneous Parameters. */ 4209 4210 static rtx_insn * 4211 nds32_md_asm_adjust (vec<rtx> &outputs ATTRIBUTE_UNUSED, 4212 vec<rtx> &inputs ATTRIBUTE_UNUSED, 4213 vec<machine_mode> &input_modes ATTRIBUTE_UNUSED, 4214 vec<const char *> &constraints ATTRIBUTE_UNUSED, 4215 vec<rtx> &clobbers, HARD_REG_SET &clobbered_regs, 4216 location_t /*loc*/) 4217 { 4218 if (!flag_inline_asm_r15) 4219 { 4220 clobbers.safe_push (gen_rtx_REG (SImode, TA_REGNUM)); 4221 SET_HARD_REG_BIT (clobbered_regs, TA_REGNUM); 4222 } 4223 return NULL; 4224 } 4225 4226 static void 4227 nds32_init_builtins (void) 4228 { 4229 nds32_init_builtins_impl (); 4230 } 4231 4232 static tree 4233 nds32_builtin_decl (unsigned code, bool initialize_p) 4234 { 4235 /* Implement in nds32-intrinsic.cc. */ 4236 return nds32_builtin_decl_impl (code, initialize_p); 4237 } 4238 4239 static rtx 4240 nds32_expand_builtin (tree exp, 4241 rtx target, 4242 rtx subtarget, 4243 machine_mode mode, 4244 int ignore) 4245 { 4246 return nds32_expand_builtin_impl (exp, target, subtarget, mode, ignore); 4247 } 4248 4249 /* Implement TARGET_INIT_LIBFUNCS. */ 4250 static void 4251 nds32_init_libfuncs (void) 4252 { 4253 if (TARGET_LINUX_ABI) 4254 init_sync_libfuncs (UNITS_PER_WORD); 4255 } 4256 4257 /* ------------------------------------------------------------------------ */ 4258 4259 /* PART 4: Implemet extern function definitions, 4260 the prototype is in nds32-protos.h. */ 4261 4262 /* Run-time Target Specification. */ 4264 4265 void 4266 nds32_cpu_cpp_builtins(struct cpp_reader *pfile) 4267 { 4268 #define builtin_define(TXT) cpp_define (pfile, TXT) 4269 #define builtin_assert(TXT) cpp_assert (pfile, TXT) 4270 builtin_define ("__nds32__"); 4271 builtin_define ("__NDS32__"); 4272 4273 /* We need to provide builtin macro to describe the size of 4274 each vector for interrupt handler under elf toolchain. */ 4275 if (!TARGET_LINUX_ABI) 4276 { 4277 if (TARGET_ISR_VECTOR_SIZE_4_BYTE) 4278 builtin_define ("__NDS32_ISR_VECTOR_SIZE_4__"); 4279 else 4280 builtin_define ("__NDS32_ISR_VECTOR_SIZE_16__"); 4281 } 4282 4283 if (TARGET_HARD_FLOAT) 4284 builtin_define ("__NDS32_ABI_2FP_PLUS__"); 4285 else 4286 builtin_define ("__NDS32_ABI_2__"); 4287 4288 if (TARGET_ISA_V2) 4289 builtin_define ("__NDS32_ISA_V2__"); 4290 if (TARGET_ISA_V3) 4291 builtin_define ("__NDS32_ISA_V3__"); 4292 if (TARGET_ISA_V3M) 4293 builtin_define ("__NDS32_ISA_V3M__"); 4294 4295 if (TARGET_FPU_SINGLE) 4296 builtin_define ("__NDS32_EXT_FPU_SP__"); 4297 if (TARGET_FPU_DOUBLE) 4298 builtin_define ("__NDS32_EXT_FPU_DP__"); 4299 4300 if (TARGET_EXT_FPU_FMA) 4301 builtin_define ("__NDS32_EXT_FPU_FMA__"); 4302 if (NDS32_EXT_FPU_DOT_E) 4303 builtin_define ("__NDS32_EXT_FPU_DOT_E__"); 4304 if (TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 4305 { 4306 switch (nds32_fp_regnum) 4307 { 4308 case 0: 4309 case 4: 4310 builtin_define ("__NDS32_EXT_FPU_CONFIG_0__"); 4311 break; 4312 case 1: 4313 case 5: 4314 builtin_define ("__NDS32_EXT_FPU_CONFIG_1__"); 4315 break; 4316 case 2: 4317 case 6: 4318 builtin_define ("__NDS32_EXT_FPU_CONFIG_2__"); 4319 break; 4320 case 3: 4321 case 7: 4322 builtin_define ("__NDS32_EXT_FPU_CONFIG_3__"); 4323 break; 4324 default: 4325 abort (); 4326 } 4327 } 4328 4329 if (TARGET_BIG_ENDIAN) 4330 builtin_define ("__NDS32_EB__"); 4331 else 4332 builtin_define ("__NDS32_EL__"); 4333 4334 if (TARGET_REDUCED_REGS) 4335 builtin_define ("__NDS32_REDUCED_REGS__"); 4336 if (TARGET_CMOV) 4337 builtin_define ("__NDS32_CMOV__"); 4338 if (TARGET_EXT_PERF) 4339 builtin_define ("__NDS32_EXT_PERF__"); 4340 if (TARGET_EXT_PERF2) 4341 builtin_define ("__NDS32_EXT_PERF2__"); 4342 if (TARGET_EXT_STRING) 4343 builtin_define ("__NDS32_EXT_STRING__"); 4344 if (TARGET_16_BIT) 4345 builtin_define ("__NDS32_16_BIT__"); 4346 if (TARGET_GP_DIRECT) 4347 builtin_define ("__NDS32_GP_DIRECT__"); 4348 if (TARGET_VH) 4349 builtin_define ("__NDS32_VH__"); 4350 if (NDS32_EXT_DSP_P ()) 4351 builtin_define ("__NDS32_EXT_DSP__"); 4352 4353 if (TARGET_BIG_ENDIAN) 4354 builtin_define ("__big_endian__"); 4355 4356 builtin_assert ("cpu=nds32"); 4357 builtin_assert ("machine=nds32"); 4358 4359 if (TARGET_HARD_FLOAT) 4360 builtin_define ("__NDS32_ABI_2FP_PLUS"); 4361 else 4362 builtin_define ("__NDS32_ABI_2"); 4363 4364 #undef builtin_define 4365 #undef builtin_assert 4366 } 4367 4368 4369 /* Defining Data Structures for Per-function Information. */ 4371 4372 void 4373 nds32_init_expanders (void) 4374 { 4375 /* Arrange to initialize and mark the machine per-function status. */ 4376 init_machine_status = nds32_init_machine_status; 4377 } 4378 4379 4380 /* Register Usage. */ 4382 4383 /* -- Order of Allocation of Registers. */ 4384 4385 void 4386 nds32_adjust_reg_alloc_order (void) 4387 { 4388 const int nds32_reg_alloc_order[] = REG_ALLOC_ORDER; 4389 4390 /* Copy the default register allocation order, which is designed 4391 to optimize for code size. */ 4392 memcpy(reg_alloc_order, nds32_reg_alloc_order, sizeof (reg_alloc_order)); 4393 4394 /* Adjust few register allocation order when optimizing for speed. */ 4395 if (!optimize_size) 4396 { 4397 memcpy (reg_alloc_order, nds32_reg_alloc_order_for_speed, 4398 sizeof (nds32_reg_alloc_order_for_speed)); 4399 } 4400 } 4401 4402 /* -- How Values Fit in Registers. */ 4403 4404 static unsigned 4405 nds32_hard_regno_nregs (unsigned regno ATTRIBUTE_UNUSED, 4406 machine_mode mode) 4407 { 4408 return ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD); 4409 } 4410 4411 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 4412 4413 static bool 4414 nds32_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4415 { 4416 if (regno >= FIRST_PSEUDO_REGISTER) 4417 return true; 4418 4419 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) && NDS32_IS_FPR_REGNUM (regno)) 4420 { 4421 if (NDS32_IS_EXT_FPR_REGNUM(regno)) 4422 return (NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) && (mode == DFmode)); 4423 else if (mode == SFmode || mode == SImode) 4424 return NDS32_FPR_REGNO_OK_FOR_SINGLE (regno); 4425 else if (mode == DFmode) 4426 return NDS32_FPR_REGNO_OK_FOR_DOUBLE (regno); 4427 4428 return false; 4429 } 4430 4431 /* Restrict double-word quantities to even register pairs. */ 4432 if (regno <= NDS32_LAST_GPR_REGNUM) 4433 return (targetm.hard_regno_nregs (regno, mode) == 1 4434 || !((regno) & 1)); 4435 4436 return false; 4437 } 4438 4439 /* Implement TARGET_MODES_TIEABLE_P. We can use general registers to 4440 tie QI/HI/SI modes together. */ 4441 4442 static bool 4443 nds32_modes_tieable_p (machine_mode mode1, machine_mode mode2) 4444 { 4445 if ((GET_MODE_CLASS (mode1) == MODE_INT 4446 && GET_MODE_CLASS (mode2) == MODE_INT) 4447 && GET_MODE_SIZE (mode1) <= UNITS_PER_WORD 4448 && GET_MODE_SIZE (mode2) <= UNITS_PER_WORD) 4449 return true; 4450 4451 if (GET_MODE_SIZE (mode1) == GET_MODE_SIZE (mode2)) 4452 { 4453 if ((TARGET_FPU_SINGLE && !TARGET_FPU_DOUBLE) 4454 && (mode1 == DFmode || mode2 == DFmode)) 4455 return false; 4456 else 4457 return true; 4458 } 4459 4460 return false; 4461 } 4462 4463 /* Register Classes. */ 4465 4466 enum reg_class 4467 nds32_regno_reg_class (int regno) 4468 { 4469 /* Refer to nds32.h for more register class details. */ 4470 4471 if (regno >= 0 && regno <= 7) 4472 return LOW_REGS; 4473 else if (regno >= 8 && regno <= 11) 4474 return MIDDLE_REGS; 4475 else if (regno >= 12 && regno <= 14) 4476 return HIGH_REGS; 4477 else if (regno == 15) 4478 return R15_TA_REG; 4479 else if (regno >= 16 && regno <= 19) 4480 return MIDDLE_REGS; 4481 else if (regno >= 20 && regno <= 31) 4482 return HIGH_REGS; 4483 else if (regno == 32 || regno == 33) 4484 { 4485 /* $SFP and $AP is FRAME_REGS in fact, However prevent IRA don't 4486 know how to allocate register for $SFP and $AP, just tell IRA they 4487 are GENERAL_REGS, and ARM do this hack too. */ 4488 return GENERAL_REGS; 4489 } 4490 else if (regno >= 34 && regno <= 97) 4491 return FP_REGS; 4492 else 4493 return NO_REGS; 4494 } 4495 4496 4497 /* Stack Layout and Calling Conventions. */ 4499 4500 /* -- Basic Stack Layout. */ 4501 4502 rtx 4503 nds32_dynamic_chain_address (rtx frameaddr) 4504 { 4505 if (TARGET_V3PUSH) 4506 { 4507 /* If -mv3push is specified, we push $fp, $gp, and $lp into stack. 4508 We can access dynamic chain address from stack by [$fp - 12]. */ 4509 return plus_constant (Pmode, frameaddr, -12); 4510 } 4511 else 4512 { 4513 /* For general case we push $fp and $lp into stack at prologue. 4514 We can access dynamic chain address from stack by [$fp - 8]. */ 4515 return plus_constant (Pmode, frameaddr, -8); 4516 } 4517 } 4518 4519 rtx 4520 nds32_return_addr_rtx (int count, 4521 rtx frameaddr) 4522 { 4523 int offset; 4524 rtx addr; 4525 4526 if (count != 0) 4527 { 4528 /* In nds32 ABI design, we can expect that $lp is always available 4529 from stack by [$fp - 4] location. */ 4530 offset = -4; 4531 addr = plus_constant (Pmode, frameaddr, offset); 4532 addr = memory_address (Pmode, addr); 4533 4534 return gen_rtx_MEM (Pmode, addr); 4535 } 4536 4537 /* If count == 0, it means we are at current frame, 4538 the return address is $r30 ($lp). */ 4539 return get_hard_reg_initial_val (Pmode, LP_REGNUM); 4540 } 4541 4542 /* -- Eliminating Frame Pointer and Arg Pointer. */ 4543 4544 HOST_WIDE_INT 4545 nds32_initial_elimination_offset (unsigned int from_reg, unsigned int to_reg) 4546 { 4547 HOST_WIDE_INT offset; 4548 4549 /* Compute and setup stack frame size. 4550 The result will be in cfun->machine. */ 4551 nds32_compute_stack_frame (); 4552 4553 /* Remember to consider 4554 cfun->machine->callee_saved_area_gpr_padding_bytes and 4555 cfun->machine->eh_return_data_regs_size 4556 when calculating offset. */ 4557 if (from_reg == ARG_POINTER_REGNUM && to_reg == STACK_POINTER_REGNUM) 4558 { 4559 offset = (cfun->machine->fp_size 4560 + cfun->machine->gp_size 4561 + cfun->machine->lp_size 4562 + cfun->machine->callee_saved_gpr_regs_size 4563 + cfun->machine->callee_saved_area_gpr_padding_bytes 4564 + cfun->machine->callee_saved_fpr_regs_size 4565 + cfun->machine->eh_return_data_regs_size 4566 + cfun->machine->local_size 4567 + cfun->machine->out_args_size); 4568 } 4569 else if (from_reg == ARG_POINTER_REGNUM 4570 && to_reg == HARD_FRAME_POINTER_REGNUM) 4571 { 4572 offset = 0; 4573 } 4574 else if (from_reg == FRAME_POINTER_REGNUM 4575 && to_reg == STACK_POINTER_REGNUM) 4576 { 4577 offset = (cfun->machine->local_size + cfun->machine->out_args_size); 4578 } 4579 else if (from_reg == FRAME_POINTER_REGNUM 4580 && to_reg == HARD_FRAME_POINTER_REGNUM) 4581 { 4582 offset = (-1) * (cfun->machine->fp_size 4583 + cfun->machine->gp_size 4584 + cfun->machine->lp_size 4585 + cfun->machine->callee_saved_gpr_regs_size 4586 + cfun->machine->callee_saved_area_gpr_padding_bytes 4587 + cfun->machine->callee_saved_fpr_regs_size 4588 + cfun->machine->eh_return_data_regs_size); 4589 } 4590 else 4591 { 4592 gcc_unreachable (); 4593 } 4594 4595 return offset; 4596 } 4597 4598 /* -- Passing Arguments in Registers. */ 4599 4600 void 4601 nds32_init_cumulative_args (CUMULATIVE_ARGS *cum, 4602 tree fntype ATTRIBUTE_UNUSED, 4603 rtx libname ATTRIBUTE_UNUSED, 4604 tree fndecl ATTRIBUTE_UNUSED, 4605 int n_named_args ATTRIBUTE_UNUSED) 4606 { 4607 /* Initial available registers. The values are offset against 4608 NDS32_GPR_ARG_FIRST_REGNUM and NDS32_FPR_ARG_FIRST_REGNUM 4609 for passing arguments. */ 4610 cum->gpr_offset = 0; 4611 cum->fpr_offset = 0; 4612 } 4613 4614 /* -- Function Entry and Exit. */ 4615 4616 /* Function for normal multiple push prologue. */ 4617 void 4618 nds32_expand_prologue (void) 4619 { 4620 int fp_adjust; 4621 int sp_adjust; 4622 unsigned Rb, Re; 4623 4624 /* Compute and setup stack frame size. 4625 The result will be in cfun->machine. */ 4626 nds32_compute_stack_frame (); 4627 4628 /* Check frame_pointer_needed again to prevent fp is need after reload. */ 4629 if (frame_pointer_needed) 4630 cfun->machine->fp_as_gp_p = false; 4631 4632 /* If this is a variadic function, first we need to push argument 4633 registers that hold the unnamed argument value. */ 4634 if (cfun->machine->va_args_size != 0) 4635 { 4636 Rb = cfun->machine->va_args_first_regno; 4637 Re = cfun->machine->va_args_last_regno; 4638 /* No need to push $fp, $gp, or $lp. */ 4639 nds32_emit_stack_push_multiple (Rb, Re, false, false, false, true); 4640 4641 /* We may also need to adjust stack pointer for padding bytes 4642 because varargs may cause $sp not 8-byte aligned. */ 4643 if (cfun->machine->va_args_area_padding_bytes) 4644 { 4645 /* Generate sp adjustment instruction. */ 4646 sp_adjust = cfun->machine->va_args_area_padding_bytes; 4647 4648 nds32_emit_adjust_frame (stack_pointer_rtx, 4649 stack_pointer_rtx, 4650 -1 * sp_adjust); 4651 } 4652 } 4653 4654 /* If the function is 'naked', 4655 we do not have to generate prologue code fragment. */ 4656 if (cfun->machine->naked_p && !flag_pic) 4657 return; 4658 4659 /* Get callee_first_regno and callee_last_regno. */ 4660 Rb = cfun->machine->callee_saved_first_gpr_regno; 4661 Re = cfun->machine->callee_saved_last_gpr_regno; 4662 4663 /* If $fp, $gp, $lp, and all callee-save registers are NOT required 4664 to be saved, we don't have to create multiple push instruction. 4665 Otherwise, a multiple push instruction is needed. */ 4666 if (!(Rb == SP_REGNUM && Re == SP_REGNUM 4667 && cfun->machine->fp_size == 0 4668 && cfun->machine->gp_size == 0 4669 && cfun->machine->lp_size == 0)) 4670 { 4671 /* Create multiple push instruction rtx. */ 4672 nds32_emit_stack_push_multiple ( 4673 Rb, Re, 4674 cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size, 4675 false); 4676 } 4677 4678 /* Save eh data registers. */ 4679 if (cfun->machine->use_eh_return_p) 4680 { 4681 Rb = cfun->machine->eh_return_data_first_regno; 4682 Re = cfun->machine->eh_return_data_last_regno; 4683 4684 /* No need to push $fp, $gp, or $lp. 4685 Also, this is not variadic arguments push. */ 4686 nds32_emit_stack_push_multiple (Rb, Re, false, false, false, false); 4687 } 4688 4689 /* Check frame_pointer_needed to see 4690 if we shall emit fp adjustment instruction. */ 4691 if (frame_pointer_needed) 4692 { 4693 /* adjust $fp = $sp + ($fp size) + ($gp size) + ($lp size) 4694 + (4 * callee-saved-registers) 4695 + (4 * exception-handling-data-registers) 4696 Note: No need to adjust 4697 cfun->machine->callee_saved_area_gpr_padding_bytes, 4698 because, at this point, stack pointer is just 4699 at the position after push instruction. */ 4700 fp_adjust = cfun->machine->fp_size 4701 + cfun->machine->gp_size 4702 + cfun->machine->lp_size 4703 + cfun->machine->callee_saved_gpr_regs_size 4704 + cfun->machine->eh_return_data_regs_size; 4705 4706 nds32_emit_adjust_frame (hard_frame_pointer_rtx, 4707 stack_pointer_rtx, 4708 fp_adjust); 4709 } 4710 4711 /* Save fpu registers. */ 4712 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 4713 { 4714 /* When $sp moved to bottom of stack, we need to check whether 4715 the range of offset in the FPU instruction. */ 4716 int fpr_offset = cfun->machine->local_size 4717 + cfun->machine->out_args_size 4718 + cfun->machine->callee_saved_fpr_regs_size; 4719 4720 /* Check FPU instruction offset imm14s. */ 4721 if (!satisfies_constraint_Is14 (GEN_INT (fpr_offset))) 4722 { 4723 int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes 4724 + cfun->machine->callee_saved_fpr_regs_size; 4725 4726 /* Save fpu registers, need to allocate stack space 4727 for fpu callee registers. And now $sp position 4728 on callee saved fpr registers. */ 4729 nds32_emit_adjust_frame (stack_pointer_rtx, 4730 stack_pointer_rtx, 4731 -1 * fpr_space); 4732 4733 /* Emit fpu store instruction, using [$sp + offset] store 4734 fpu registers. */ 4735 nds32_emit_push_fpr_callee_saved (0); 4736 4737 /* Adjust $sp = $sp - local_size - out_args_size. */ 4738 sp_adjust = cfun->machine->local_size 4739 + cfun->machine->out_args_size; 4740 4741 /* Allocate stack space for local size and out args size. */ 4742 nds32_emit_adjust_frame (stack_pointer_rtx, 4743 stack_pointer_rtx, 4744 -1 * sp_adjust); 4745 } 4746 else 4747 { 4748 /* Offset range in Is14, so $sp moved to bottom of stack. */ 4749 4750 /* Adjust $sp = $sp - local_size - out_args_size 4751 - callee_saved_area_gpr_padding_bytes 4752 - callee_saved_fpr_regs_size. */ 4753 sp_adjust = cfun->machine->local_size 4754 + cfun->machine->out_args_size 4755 + cfun->machine->callee_saved_area_gpr_padding_bytes 4756 + cfun->machine->callee_saved_fpr_regs_size; 4757 4758 nds32_emit_adjust_frame (stack_pointer_rtx, 4759 stack_pointer_rtx, 4760 -1 * sp_adjust); 4761 4762 /* Emit fpu store instruction, using [$sp + offset] store 4763 fpu registers. */ 4764 int fpr_position = cfun->machine->out_args_size 4765 + cfun->machine->local_size; 4766 nds32_emit_push_fpr_callee_saved (fpr_position); 4767 } 4768 } 4769 else 4770 { 4771 /* Adjust $sp = $sp - local_size - out_args_size 4772 - callee_saved_area_gpr_padding_bytes. */ 4773 sp_adjust = cfun->machine->local_size 4774 + cfun->machine->out_args_size 4775 + cfun->machine->callee_saved_area_gpr_padding_bytes; 4776 4777 /* sp_adjust value may be out of range of the addi instruction, 4778 create alternative add behavior with TA_REGNUM if necessary, 4779 using NEGATIVE value to tell that we are decreasing address. */ 4780 nds32_emit_adjust_frame (stack_pointer_rtx, 4781 stack_pointer_rtx, 4782 -1 * sp_adjust); 4783 } 4784 4785 /* Emit gp setup instructions for -fpic. */ 4786 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) 4787 nds32_emit_load_gp (); 4788 4789 /* If user applies -mno-sched-prolog-epilog option, 4790 we need to prevent instructions of function body from being 4791 scheduled with stack adjustment in prologue. */ 4792 if (!flag_sched_prolog_epilog) 4793 emit_insn (gen_blockage ()); 4794 } 4795 4796 /* Function for normal multiple pop epilogue. */ 4797 void 4798 nds32_expand_epilogue (bool sibcall_p) 4799 { 4800 int sp_adjust; 4801 unsigned Rb, Re; 4802 4803 /* Compute and setup stack frame size. 4804 The result will be in cfun->machine. */ 4805 nds32_compute_stack_frame (); 4806 4807 /* If user applies -mno-sched-prolog-epilog option, 4808 we need to prevent instructions of function body from being 4809 scheduled with stack adjustment in epilogue. */ 4810 if (!flag_sched_prolog_epilog) 4811 emit_insn (gen_blockage ()); 4812 4813 /* If the function is 'naked', we do not have to generate 4814 epilogue code fragment BUT 'ret' instruction. 4815 However, if this function is also a variadic function, 4816 we need to create adjust stack pointer before 'ret' instruction. */ 4817 if (cfun->machine->naked_p) 4818 { 4819 /* If this is a variadic function, we do not have to restore argument 4820 registers but need to adjust stack pointer back to previous stack 4821 frame location before return. */ 4822 if (cfun->machine->va_args_size != 0) 4823 { 4824 /* Generate sp adjustment instruction. 4825 We need to consider padding bytes here. */ 4826 sp_adjust = cfun->machine->va_args_size 4827 + cfun->machine->va_args_area_padding_bytes; 4828 4829 nds32_emit_adjust_frame (stack_pointer_rtx, 4830 stack_pointer_rtx, 4831 sp_adjust); 4832 } 4833 4834 /* Generate return instruction by using 'return_internal' pattern. 4835 Make sure this instruction is after gen_blockage(). */ 4836 if (!sibcall_p) 4837 { 4838 /* We need to further check attributes to determine whether 4839 there should be return instruction at epilogue. 4840 If the attribute naked exists but -mno-ret-in-naked-func 4841 is issued, there is NO need to generate return instruction. */ 4842 if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) 4843 return; 4844 4845 emit_jump_insn (gen_return_internal ()); 4846 } 4847 return; 4848 } 4849 4850 if (frame_pointer_needed) 4851 { 4852 /* Restore fpu registers. */ 4853 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 4854 { 4855 int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; 4856 4857 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) 4858 - (4 * callee-saved-registers) 4859 - (4 * exception-handling-data-registers) 4860 - (4 * callee-saved-gpr-registers padding byte) 4861 - (4 * callee-saved-fpr-registers) 4862 Note: we want to adjust stack pointer 4863 to the position for callee-saved fpr register, 4864 And restore fpu register use .bi instruction to adjust $sp 4865 from callee-saved fpr register to pop instruction. */ 4866 sp_adjust = cfun->machine->fp_size 4867 + cfun->machine->gp_size 4868 + cfun->machine->lp_size 4869 + cfun->machine->callee_saved_gpr_regs_size 4870 + cfun->machine->eh_return_data_regs_size 4871 + cfun->machine->callee_saved_area_gpr_padding_bytes 4872 + cfun->machine->callee_saved_fpr_regs_size; 4873 4874 nds32_emit_adjust_frame (stack_pointer_rtx, 4875 hard_frame_pointer_rtx, 4876 -1 * sp_adjust); 4877 4878 /* Emit fpu load instruction, using .bi instruction 4879 load fpu registers. */ 4880 nds32_emit_pop_fpr_callee_saved (gpr_padding); 4881 } 4882 else 4883 { 4884 /* adjust $sp = $fp - ($fp size) - ($gp size) - ($lp size) 4885 - (4 * callee-saved-registers) 4886 - (4 * exception-handling-data-registers) 4887 Note: No need to adjust 4888 cfun->machine->callee_saved_area_gpr_padding_bytes, 4889 because we want to adjust stack pointer 4890 to the position for pop instruction. */ 4891 sp_adjust = cfun->machine->fp_size 4892 + cfun->machine->gp_size 4893 + cfun->machine->lp_size 4894 + cfun->machine->callee_saved_gpr_regs_size 4895 + cfun->machine->eh_return_data_regs_size; 4896 4897 nds32_emit_adjust_frame (stack_pointer_rtx, 4898 hard_frame_pointer_rtx, 4899 -1 * sp_adjust); 4900 } 4901 } 4902 else 4903 { 4904 /* Restore fpu registers. */ 4905 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 4906 { 4907 int gpr_padding = cfun->machine->callee_saved_area_gpr_padding_bytes; 4908 4909 /* Adjust $sp = $sp + local_size + out_args_size. */ 4910 sp_adjust = cfun->machine->local_size 4911 + cfun->machine->out_args_size; 4912 4913 nds32_emit_adjust_frame (stack_pointer_rtx, 4914 stack_pointer_rtx, 4915 sp_adjust); 4916 4917 /* Emit fpu load instruction, using .bi instruction 4918 load fpu registers, and adjust $sp from callee-saved fpr register 4919 to callee-saved gpr register. */ 4920 nds32_emit_pop_fpr_callee_saved (gpr_padding); 4921 } 4922 else 4923 { 4924 /* If frame pointer is NOT needed, 4925 we cannot calculate the sp adjustment from frame pointer. 4926 Instead, we calculate the adjustment by local_size, 4927 out_args_size, and callee_saved_area_gpr_padding_bytes. 4928 Notice that such sp adjustment value may be out of range, 4929 so we have to deal with it as well. */ 4930 4931 /* Adjust $sp = $sp + local_size + out_args_size 4932 + callee_saved_area_gpr_padding_bytes. */ 4933 sp_adjust = cfun->machine->local_size 4934 + cfun->machine->out_args_size 4935 + cfun->machine->callee_saved_area_gpr_padding_bytes; 4936 4937 nds32_emit_adjust_frame (stack_pointer_rtx, 4938 stack_pointer_rtx, 4939 sp_adjust); 4940 } 4941 } 4942 4943 /* Restore eh data registers. */ 4944 if (cfun->machine->use_eh_return_p) 4945 { 4946 Rb = cfun->machine->eh_return_data_first_regno; 4947 Re = cfun->machine->eh_return_data_last_regno; 4948 4949 /* No need to pop $fp, $gp, or $lp. */ 4950 nds32_emit_stack_pop_multiple (Rb, Re, false, false, false); 4951 } 4952 4953 /* Get callee_first_regno and callee_last_regno. */ 4954 Rb = cfun->machine->callee_saved_first_gpr_regno; 4955 Re = cfun->machine->callee_saved_last_gpr_regno; 4956 4957 /* If $fp, $gp, $lp, and all callee-save registers are NOT required 4958 to be saved, we don't have to create multiple pop instruction. 4959 Otherwise, a multiple pop instruction is needed. */ 4960 if (!(Rb == SP_REGNUM && Re == SP_REGNUM 4961 && cfun->machine->fp_size == 0 4962 && cfun->machine->gp_size == 0 4963 && cfun->machine->lp_size == 0)) 4964 { 4965 /* Create multiple pop instruction rtx. */ 4966 nds32_emit_stack_pop_multiple ( 4967 Rb, Re, 4968 cfun->machine->fp_size, cfun->machine->gp_size, cfun->machine->lp_size); 4969 } 4970 4971 /* If this is a variadic function, we do not have to restore argument 4972 registers but need to adjust stack pointer back to previous stack 4973 frame location before return. */ 4974 if (cfun->machine->va_args_size != 0) 4975 { 4976 /* Generate sp adjustment instruction. 4977 We need to consider padding bytes here. */ 4978 sp_adjust = cfun->machine->va_args_size 4979 + cfun->machine->va_args_area_padding_bytes; 4980 4981 nds32_emit_adjust_frame (stack_pointer_rtx, 4982 stack_pointer_rtx, 4983 sp_adjust); 4984 } 4985 4986 /* If this function uses __builtin_eh_return, make stack adjustment 4987 for exception handler. */ 4988 if (cfun->machine->use_eh_return_p) 4989 { 4990 /* We need to unwind the stack by the offset computed by 4991 EH_RETURN_STACKADJ_RTX. However, at this point the CFA is 4992 based on SP. Ideally we would update the SP and define the 4993 CFA along the lines of: 4994 4995 SP = SP + EH_RETURN_STACKADJ_RTX 4996 (regnote CFA = SP - EH_RETURN_STACKADJ_RTX) 4997 4998 However the dwarf emitter only understands a constant 4999 register offset. 5000 5001 The solution chosen here is to use the otherwise $ta ($r15) 5002 as a temporary register to hold the current SP value. The 5003 CFA is described using $ta then SP is modified. */ 5004 5005 rtx ta_reg; 5006 rtx insn; 5007 5008 ta_reg = gen_rtx_REG (SImode, TA_REGNUM); 5009 5010 insn = emit_move_insn (ta_reg, stack_pointer_rtx); 5011 add_reg_note (insn, REG_CFA_DEF_CFA, ta_reg); 5012 RTX_FRAME_RELATED_P (insn) = 1; 5013 5014 emit_insn (gen_addsi3 (stack_pointer_rtx, 5015 stack_pointer_rtx, 5016 EH_RETURN_STACKADJ_RTX)); 5017 5018 /* Ensure the assignment to $ta does not get optimized away. */ 5019 emit_use (ta_reg); 5020 } 5021 5022 /* Generate return instruction. */ 5023 if (!sibcall_p) 5024 emit_jump_insn (gen_return_internal ()); 5025 } 5026 5027 /* Function for v3push prologue. */ 5028 void 5029 nds32_expand_prologue_v3push (void) 5030 { 5031 int fp_adjust; 5032 int sp_adjust; 5033 int fpr_space = 0; 5034 unsigned Rb, Re; 5035 5036 /* Compute and setup stack frame size. 5037 The result will be in cfun->machine. */ 5038 nds32_compute_stack_frame (); 5039 5040 if (cfun->machine->callee_saved_gpr_regs_size > 0) 5041 df_set_regs_ever_live (FP_REGNUM, 1); 5042 5043 /* Check frame_pointer_needed again to prevent fp is need after reload. */ 5044 if (frame_pointer_needed) 5045 cfun->machine->fp_as_gp_p = false; 5046 5047 /* If the function is 'naked', 5048 we do not have to generate prologue code fragment. */ 5049 if (cfun->machine->naked_p && !flag_pic) 5050 return; 5051 5052 /* Get callee_first_regno and callee_last_regno. */ 5053 Rb = cfun->machine->callee_saved_first_gpr_regno; 5054 Re = cfun->machine->callee_saved_last_gpr_regno; 5055 5056 /* Calculate sp_adjust first to test if 'push25 Re,imm8u' is available, 5057 where imm8u has to be 8-byte alignment. */ 5058 sp_adjust = cfun->machine->local_size 5059 + cfun->machine->out_args_size 5060 + cfun->machine->callee_saved_area_gpr_padding_bytes 5061 + cfun->machine->callee_saved_fpr_regs_size; 5062 5063 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) 5064 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust)) 5065 { 5066 /* We can use 'push25 Re,imm8u'. */ 5067 5068 /* nds32_emit_stack_v3push(last_regno, sp_adjust), 5069 the pattern 'stack_v3push' is implemented in nds32.md. */ 5070 nds32_emit_stack_v3push (Rb, Re, sp_adjust); 5071 5072 /* Save fpu registers. */ 5073 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5074 { 5075 /* Calculate fpr position. */ 5076 int fpr_position = cfun->machine->local_size 5077 + cfun->machine->out_args_size; 5078 /* Emit fpu store instruction, using [$sp + offset] store 5079 fpu registers. */ 5080 nds32_emit_push_fpr_callee_saved (fpr_position); 5081 } 5082 5083 /* Check frame_pointer_needed to see 5084 if we shall emit fp adjustment instruction. */ 5085 if (frame_pointer_needed) 5086 { 5087 /* adjust $fp = $sp + 4 ($fp size) 5088 + 4 ($gp size) 5089 + 4 ($lp size) 5090 + (4 * n) (callee-saved registers) 5091 + sp_adjust ('push25 Re,imm8u') 5092 Note: Since we use 'push25 Re,imm8u', 5093 the position of stack pointer is further 5094 changed after push instruction. 5095 Hence, we need to take sp_adjust value 5096 into consideration. */ 5097 fp_adjust = cfun->machine->fp_size 5098 + cfun->machine->gp_size 5099 + cfun->machine->lp_size 5100 + cfun->machine->callee_saved_gpr_regs_size 5101 + sp_adjust; 5102 5103 nds32_emit_adjust_frame (hard_frame_pointer_rtx, 5104 stack_pointer_rtx, 5105 fp_adjust); 5106 } 5107 } 5108 else 5109 { 5110 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5111 { 5112 /* Calculate fpr space. */ 5113 fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes 5114 + cfun->machine->callee_saved_fpr_regs_size; 5115 5116 /* We have to use 'push25 Re, fpr_space', to pre-allocate 5117 callee saved fpr registers space. */ 5118 nds32_emit_stack_v3push (Rb, Re, fpr_space); 5119 nds32_emit_push_fpr_callee_saved (0); 5120 } 5121 else 5122 { 5123 /* We have to use 'push25 Re,0' and 5124 expand one more instruction to adjust $sp later. */ 5125 5126 /* nds32_emit_stack_v3push(last_regno, sp_adjust), 5127 the pattern 'stack_v3push' is implemented in nds32.md. */ 5128 nds32_emit_stack_v3push (Rb, Re, 0); 5129 } 5130 5131 /* Check frame_pointer_needed to see 5132 if we shall emit fp adjustment instruction. */ 5133 if (frame_pointer_needed) 5134 { 5135 /* adjust $fp = $sp + 4 ($fp size) 5136 + 4 ($gp size) 5137 + 4 ($lp size) 5138 + (4 * n) (callee-saved registers) 5139 Note: Since we use 'push25 Re,0', 5140 the stack pointer is just at the position 5141 after push instruction. 5142 No need to take sp_adjust into consideration. */ 5143 fp_adjust = cfun->machine->fp_size 5144 + cfun->machine->gp_size 5145 + cfun->machine->lp_size 5146 + cfun->machine->callee_saved_gpr_regs_size; 5147 5148 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5149 { 5150 /* We use 'push25 Re, fpr_space', the $sp is 5151 on callee saved fpr position, so need to consider 5152 fpr space. */ 5153 fp_adjust = fp_adjust + fpr_space; 5154 } 5155 5156 nds32_emit_adjust_frame (hard_frame_pointer_rtx, 5157 stack_pointer_rtx, 5158 fp_adjust); 5159 } 5160 5161 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5162 { 5163 /* We use 'push25 Re, fpr_space', 5164 the $sp is on callee saved fpr position, 5165 no need to consider fpr space. */ 5166 sp_adjust = sp_adjust - fpr_space; 5167 } 5168 5169 /* Because we use 'push25 Re,0', 5170 we need to expand one more instruction to adjust $sp. 5171 using NEGATIVE value to tell that we are decreasing address. */ 5172 nds32_emit_adjust_frame (stack_pointer_rtx, 5173 stack_pointer_rtx, 5174 -1 * sp_adjust); 5175 } 5176 5177 /* Emit gp setup instructions for -fpic. */ 5178 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM)) 5179 nds32_emit_load_gp (); 5180 5181 /* Prevent the instruction scheduler from 5182 moving instructions across the boundary. */ 5183 emit_insn (gen_blockage ()); 5184 } 5185 5186 /* Function for v3pop epilogue. */ 5187 void 5188 nds32_expand_epilogue_v3pop (bool sibcall_p) 5189 { 5190 int sp_adjust; 5191 unsigned Rb, Re; 5192 5193 /* Compute and setup stack frame size. 5194 The result will be in cfun->machine. */ 5195 nds32_compute_stack_frame (); 5196 5197 /* Prevent the instruction scheduler from 5198 moving instructions across the boundary. */ 5199 emit_insn (gen_blockage ()); 5200 5201 /* If the function is 'naked', we do not have to generate 5202 epilogue code fragment BUT 'ret' instruction. */ 5203 if (cfun->machine->naked_p) 5204 { 5205 /* Generate return instruction by using 'return_internal' pattern. 5206 Make sure this instruction is after gen_blockage(). 5207 First we need to check this is a function without sibling call. */ 5208 if (!sibcall_p) 5209 { 5210 /* We need to further check attributes to determine whether 5211 there should be return instruction at epilogue. 5212 If the attribute naked exists but -mno-ret-in-naked-func 5213 is issued, there is NO need to generate return instruction. */ 5214 if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) 5215 return; 5216 5217 emit_jump_insn (gen_return_internal ()); 5218 } 5219 return; 5220 } 5221 5222 /* Get callee_first_regno and callee_last_regno. */ 5223 Rb = cfun->machine->callee_saved_first_gpr_regno; 5224 Re = cfun->machine->callee_saved_last_gpr_regno; 5225 5226 /* Calculate sp_adjust first to test if 'pop25 Re,imm8u' is available, 5227 where imm8u has to be 8-byte alignment. */ 5228 sp_adjust = cfun->machine->local_size 5229 + cfun->machine->out_args_size 5230 + cfun->machine->callee_saved_area_gpr_padding_bytes 5231 + cfun->machine->callee_saved_fpr_regs_size; 5232 5233 /* We have to consider alloca issue as well. 5234 If the function does call alloca(), the stack pointer is not fixed. 5235 In that case, we cannot use 'pop25 Re,imm8u' directly. 5236 We have to caculate stack pointer from frame pointer 5237 and then use 'pop25 Re,0'. 5238 Of course, the frame_pointer_needed should be nonzero 5239 if the function calls alloca(). */ 5240 if (satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) 5241 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) 5242 && !cfun->calls_alloca) 5243 { 5244 /* Restore fpu registers. */ 5245 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5246 { 5247 int fpr_position = cfun->machine->local_size 5248 + cfun->machine->out_args_size; 5249 /* Emit fpu load instruction, using [$sp + offset] restore 5250 fpu registers. */ 5251 nds32_emit_v3pop_fpr_callee_saved (fpr_position); 5252 } 5253 5254 /* We can use 'pop25 Re,imm8u'. */ 5255 5256 /* nds32_emit_stack_v3pop(last_regno, sp_adjust), 5257 the pattern 'stack_v3pop' is implementad in nds32.md. */ 5258 nds32_emit_stack_v3pop (Rb, Re, sp_adjust); 5259 } 5260 else 5261 { 5262 /* We have to use 'pop25 Re,0', and prior to it, 5263 we must expand one more instruction to adjust $sp. */ 5264 5265 if (frame_pointer_needed) 5266 { 5267 /* adjust $sp = $fp - 4 ($fp size) 5268 - 4 ($gp size) 5269 - 4 ($lp size) 5270 - (4 * n) (callee-saved registers) 5271 Note: No need to adjust 5272 cfun->machine->callee_saved_area_gpr_padding_bytes, 5273 because we want to adjust stack pointer 5274 to the position for pop instruction. */ 5275 sp_adjust = cfun->machine->fp_size 5276 + cfun->machine->gp_size 5277 + cfun->machine->lp_size 5278 + cfun->machine->callee_saved_gpr_regs_size; 5279 5280 /* Restore fpu registers. */ 5281 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5282 { 5283 /* Set $sp to callee saved fpr position, we need to restore 5284 fpr registers. */ 5285 sp_adjust = sp_adjust 5286 + cfun->machine->callee_saved_area_gpr_padding_bytes 5287 + cfun->machine->callee_saved_fpr_regs_size; 5288 5289 nds32_emit_adjust_frame (stack_pointer_rtx, 5290 hard_frame_pointer_rtx, 5291 -1 * sp_adjust); 5292 5293 /* Emit fpu load instruction, using [$sp + offset] restore 5294 fpu registers. */ 5295 nds32_emit_v3pop_fpr_callee_saved (0); 5296 } 5297 else 5298 { 5299 nds32_emit_adjust_frame (stack_pointer_rtx, 5300 hard_frame_pointer_rtx, 5301 -1 * sp_adjust); 5302 } 5303 } 5304 else 5305 { 5306 /* If frame pointer is NOT needed, 5307 we cannot calculate the sp adjustment from frame pointer. 5308 Instead, we calculate the adjustment by local_size, 5309 out_args_size, and callee_saved_area_padding_bytes. 5310 Notice that such sp adjustment value may be out of range, 5311 so we have to deal with it as well. */ 5312 5313 /* Adjust $sp = $sp + local_size + out_args_size 5314 + callee_saved_area_gpr_padding_bytes 5315 + callee_saved_fpr_regs_size. */ 5316 sp_adjust = cfun->machine->local_size 5317 + cfun->machine->out_args_size 5318 + cfun->machine->callee_saved_area_gpr_padding_bytes 5319 + cfun->machine->callee_saved_fpr_regs_size; 5320 5321 /* Restore fpu registers. */ 5322 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5323 { 5324 /* Set $sp to callee saved fpr position, we need to restore 5325 fpr registers. */ 5326 sp_adjust = sp_adjust 5327 - cfun->machine->callee_saved_area_gpr_padding_bytes 5328 - cfun->machine->callee_saved_fpr_regs_size; 5329 5330 nds32_emit_adjust_frame (stack_pointer_rtx, 5331 stack_pointer_rtx, 5332 sp_adjust); 5333 5334 /* Emit fpu load instruction, using [$sp + offset] restore 5335 fpu registers. */ 5336 nds32_emit_v3pop_fpr_callee_saved (0); 5337 } 5338 else 5339 { 5340 /* sp_adjust value may be out of range of the addi instruction, 5341 create alternative add behavior with TA_REGNUM if necessary, 5342 using POSITIVE value to tell that we are increasing 5343 address. */ 5344 nds32_emit_adjust_frame (stack_pointer_rtx, 5345 stack_pointer_rtx, 5346 sp_adjust); 5347 } 5348 } 5349 5350 if (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM) 5351 { 5352 /* We have fpr need to restore, so $sp is set on callee saved fpr 5353 position. And we use 'pop25 Re, fpr_space' to adjust $sp. */ 5354 int fpr_space = cfun->machine->callee_saved_area_gpr_padding_bytes 5355 + cfun->machine->callee_saved_fpr_regs_size; 5356 nds32_emit_stack_v3pop (Rb, Re, fpr_space); 5357 } 5358 else 5359 { 5360 /* nds32_emit_stack_v3pop(last_regno, sp_adjust), 5361 the pattern 'stack_v3pop' is implementad in nds32.md. */ 5362 nds32_emit_stack_v3pop (Rb, Re, 0); 5363 } 5364 } 5365 /* Generate return instruction. */ 5366 emit_jump_insn (gen_pop25return ()); 5367 } 5368 5369 /* Return nonzero if this function is known to have a null epilogue. 5370 This allows the optimizer to omit jumps to jumps if no stack 5371 was created. */ 5372 int 5373 nds32_can_use_return_insn (void) 5374 { 5375 int sp_adjust; 5376 5377 /* Prior to reloading, we can't tell how many registers must be saved. 5378 Thus we cannot determine whether this function has null epilogue. */ 5379 if (!reload_completed) 5380 return 0; 5381 5382 /* If attribute 'naked' appears but -mno-ret-in-naked-func is used, 5383 we cannot use return instruction. */ 5384 if (cfun->machine->attr_naked_p && !flag_ret_in_naked_func) 5385 return 0; 5386 5387 sp_adjust = cfun->machine->local_size 5388 + cfun->machine->out_args_size 5389 + cfun->machine->callee_saved_area_gpr_padding_bytes 5390 + cfun->machine->callee_saved_fpr_regs_size; 5391 if (!cfun->machine->fp_as_gp_p 5392 && satisfies_constraint_Iu08 (GEN_INT (sp_adjust)) 5393 && NDS32_DOUBLE_WORD_ALIGN_P (sp_adjust) 5394 && !cfun->calls_alloca 5395 && NDS32_V3PUSH_AVAILABLE_P 5396 && !(TARGET_HARD_FLOAT 5397 && (cfun->machine->callee_saved_first_fpr_regno != SP_REGNUM))) 5398 return 1; 5399 5400 /* If no stack was created, two conditions must be satisfied: 5401 1. This is a naked function. 5402 So there is no callee-saved, local size, or outgoing size. 5403 2. This is NOT a variadic function. 5404 So there is no pushing arguement registers into the stack. */ 5405 return (cfun->machine->naked_p && (cfun->machine->va_args_size == 0)); 5406 } 5407 5408 scalar_int_mode 5409 nds32_case_vector_shorten_mode (int min_offset, int max_offset, 5410 rtx body ATTRIBUTE_UNUSED) 5411 { 5412 if (min_offset < 0 || max_offset >= 0x2000) 5413 return SImode; 5414 else 5415 { 5416 /* The jump table maybe need to 2 byte alignment, 5417 so reserved 1 byte for check max_offset. */ 5418 if (max_offset >= 0xff) 5419 return HImode; 5420 else 5421 return QImode; 5422 } 5423 } 5424 5425 /* ------------------------------------------------------------------------ */ 5426 5427 /* Return alignment for the label. */ 5428 int 5429 nds32_target_alignment (rtx_insn *label) 5430 { 5431 rtx_insn *insn; 5432 5433 if (!NDS32_ALIGN_P ()) 5434 return 0; 5435 5436 insn = next_active_insn (label); 5437 5438 /* Always align to 4 byte when first instruction after label is jump 5439 instruction since length for that might changed, so let's always align 5440 it for make sure we don't lose any perfomance here. */ 5441 if (insn == 0 5442 || (get_attr_length (insn) == 2 5443 && !JUMP_P (insn) && !CALL_P (insn))) 5444 return 0; 5445 else 5446 return 2; 5447 } 5448 5449 /* Return alignment for data. */ 5450 unsigned int 5451 nds32_data_alignment (tree data, 5452 unsigned int basic_align) 5453 { 5454 if ((basic_align < BITS_PER_WORD) 5455 && (TREE_CODE (data) == ARRAY_TYPE 5456 || TREE_CODE (data) == UNION_TYPE 5457 || TREE_CODE (data) == RECORD_TYPE)) 5458 return BITS_PER_WORD; 5459 else 5460 return basic_align; 5461 } 5462 5463 /* Return alignment for constant value. */ 5464 static HOST_WIDE_INT 5465 nds32_constant_alignment (const_tree constant, 5466 HOST_WIDE_INT basic_align) 5467 { 5468 /* Make string literal and constant for constructor to word align. */ 5469 if (((TREE_CODE (constant) == STRING_CST 5470 || TREE_CODE (constant) == CONSTRUCTOR 5471 || TREE_CODE (constant) == UNION_TYPE 5472 || TREE_CODE (constant) == RECORD_TYPE 5473 || TREE_CODE (constant) == ARRAY_TYPE) 5474 && basic_align < BITS_PER_WORD)) 5475 return BITS_PER_WORD; 5476 else 5477 return basic_align; 5478 } 5479 5480 /* Return alignment for local variable. */ 5481 unsigned int 5482 nds32_local_alignment (tree local ATTRIBUTE_UNUSED, 5483 unsigned int basic_align) 5484 { 5485 bool at_least_align_to_word = false; 5486 /* Make local array, struct and union at least align to word for make 5487 sure it can unroll memcpy when initialize by constant. */ 5488 switch (TREE_CODE (local)) 5489 { 5490 case ARRAY_TYPE: 5491 case RECORD_TYPE: 5492 case UNION_TYPE: 5493 at_least_align_to_word = true; 5494 break; 5495 default: 5496 at_least_align_to_word = false; 5497 break; 5498 } 5499 if (at_least_align_to_word 5500 && (basic_align < BITS_PER_WORD)) 5501 return BITS_PER_WORD; 5502 else 5503 return basic_align; 5504 } 5505 5506 bool 5507 nds32_split_double_word_load_store_p(rtx *operands, bool load_p) 5508 { 5509 rtx mem = load_p ? operands[1] : operands[0]; 5510 /* Do split at split2 if -O0 or schedule 2 not enable. */ 5511 if (optimize == 0 || !flag_schedule_insns_after_reload) 5512 return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); 5513 5514 /* Split double word load store after copy propgation. */ 5515 if (current_pass == NULL) 5516 return false; 5517 5518 const char *pass_name = current_pass->name; 5519 if (pass_name && ((strcmp (pass_name, "split3") == 0) 5520 || (strcmp (pass_name, "split5") == 0))) 5521 return !satisfies_constraint_Da (mem) || MEM_VOLATILE_P (mem); 5522 5523 return false; 5524 } 5525 5526 static bool 5527 nds32_use_blocks_for_constant_p (machine_mode mode, 5528 const_rtx x ATTRIBUTE_UNUSED) 5529 { 5530 if ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) 5531 && (mode == DFmode || mode == SFmode)) 5532 return true; 5533 else 5534 return false; 5535 } 5536 5537 /* ------------------------------------------------------------------------ */ 5538 5539 /* PART 5: Initialize target hook structure and definitions. */ 5540 5541 /* Controlling the Compilation Driver. */ 5543 5544 5545 /* Run-time Target Specification. */ 5547 5548 5549 /* Defining Data Structures for Per-function Information. */ 5551 5552 5553 /* Storage Layout. */ 5555 5556 #undef TARGET_PROMOTE_FUNCTION_MODE 5557 #define TARGET_PROMOTE_FUNCTION_MODE \ 5558 default_promote_function_mode_always_promote 5559 5560 #undef TARGET_EXPAND_TO_RTL_HOOK 5561 #define TARGET_EXPAND_TO_RTL_HOOK nds32_expand_to_rtl_hook 5562 5563 #undef TARGET_CONSTANT_ALIGNMENT 5564 #define TARGET_CONSTANT_ALIGNMENT nds32_constant_alignment 5565 5566 5567 /* Layout of Source Language Data Types. */ 5569 5570 5571 /* Register Usage. */ 5573 5574 /* -- Basic Characteristics of Registers. */ 5575 5576 #undef TARGET_CONDITIONAL_REGISTER_USAGE 5577 #define TARGET_CONDITIONAL_REGISTER_USAGE nds32_conditional_register_usage 5578 5579 /* -- Order of Allocation of Registers. */ 5580 5581 /* -- How Values Fit in Registers. */ 5582 5583 #undef TARGET_HARD_REGNO_NREGS 5584 #define TARGET_HARD_REGNO_NREGS nds32_hard_regno_nregs 5585 5586 #undef TARGET_HARD_REGNO_MODE_OK 5587 #define TARGET_HARD_REGNO_MODE_OK nds32_hard_regno_mode_ok 5588 5589 #undef TARGET_MODES_TIEABLE_P 5590 #define TARGET_MODES_TIEABLE_P nds32_modes_tieable_p 5591 5592 /* -- Handling Leaf Functions. */ 5593 5594 /* -- Registers That Form a Stack. */ 5595 5596 5597 /* Register Classes. */ 5599 5600 #undef TARGET_CLASS_MAX_NREGS 5601 #define TARGET_CLASS_MAX_NREGS nds32_class_max_nregs 5602 5603 #undef TARGET_REGISTER_PRIORITY 5604 #define TARGET_REGISTER_PRIORITY nds32_register_priority 5605 5606 #undef TARGET_CAN_CHANGE_MODE_CLASS 5607 #define TARGET_CAN_CHANGE_MODE_CLASS nds32_can_change_mode_class 5608 5609 5610 /* Obsolete Macros for Defining Constraints. */ 5612 5613 5614 /* Stack Layout and Calling Conventions. */ 5616 5617 /* -- Basic Stack Layout. */ 5618 5619 /* -- Exception Handling Support. */ 5620 5621 /* -- Specifying How Stack Checking is Done. */ 5622 5623 /* -- Registers That Address the Stack Frame. */ 5624 5625 /* -- Eliminating Frame Pointer and Arg Pointer. */ 5626 5627 #undef TARGET_CAN_ELIMINATE 5628 #define TARGET_CAN_ELIMINATE nds32_can_eliminate 5629 5630 /* -- Passing Function Arguments on the Stack. */ 5631 5632 /* -- Passing Arguments in Registers. */ 5633 5634 #undef TARGET_FUNCTION_ARG 5635 #define TARGET_FUNCTION_ARG nds32_function_arg 5636 5637 #undef TARGET_MUST_PASS_IN_STACK 5638 #define TARGET_MUST_PASS_IN_STACK nds32_must_pass_in_stack 5639 5640 #undef TARGET_ARG_PARTIAL_BYTES 5641 #define TARGET_ARG_PARTIAL_BYTES nds32_arg_partial_bytes 5642 5643 #undef TARGET_FUNCTION_ARG_ADVANCE 5644 #define TARGET_FUNCTION_ARG_ADVANCE nds32_function_arg_advance 5645 5646 #undef TARGET_FUNCTION_ARG_BOUNDARY 5647 #define TARGET_FUNCTION_ARG_BOUNDARY nds32_function_arg_boundary 5648 5649 #undef TARGET_VECTOR_MODE_SUPPORTED_P 5650 #define TARGET_VECTOR_MODE_SUPPORTED_P nds32_vector_mode_supported_p 5651 5652 /* -- How Scalar Function Values Are Returned. */ 5653 5654 #undef TARGET_FUNCTION_VALUE 5655 #define TARGET_FUNCTION_VALUE nds32_function_value 5656 5657 #undef TARGET_LIBCALL_VALUE 5658 #define TARGET_LIBCALL_VALUE nds32_libcall_value 5659 5660 #undef TARGET_FUNCTION_VALUE_REGNO_P 5661 #define TARGET_FUNCTION_VALUE_REGNO_P nds32_function_value_regno_p 5662 5663 /* -- How Large Values Are Returned. */ 5664 5665 #undef TARGET_RETURN_IN_MEMORY 5666 #define TARGET_RETURN_IN_MEMORY nds32_return_in_memory 5667 5668 /* -- Caller-Saves Register Allocation. */ 5669 5670 /* -- Function Entry and Exit. */ 5671 5672 #undef TARGET_ASM_FUNCTION_PROLOGUE 5673 #define TARGET_ASM_FUNCTION_PROLOGUE nds32_asm_function_prologue 5674 5675 #undef TARGET_ASM_FUNCTION_END_PROLOGUE 5676 #define TARGET_ASM_FUNCTION_END_PROLOGUE nds32_asm_function_end_prologue 5677 5678 #undef TARGET_ASM_FUNCTION_BEGIN_EPILOGUE 5679 #define TARGET_ASM_FUNCTION_BEGIN_EPILOGUE nds32_asm_function_begin_epilogue 5680 5681 #undef TARGET_ASM_FUNCTION_EPILOGUE 5682 #define TARGET_ASM_FUNCTION_EPILOGUE nds32_asm_function_epilogue 5683 5684 #undef TARGET_ASM_OUTPUT_MI_THUNK 5685 #define TARGET_ASM_OUTPUT_MI_THUNK nds32_asm_output_mi_thunk 5686 5687 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 5688 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK default_can_output_mi_thunk_no_vcall 5689 5690 /* -- Generating Code for Profiling. */ 5691 5692 /* -- Permitting tail calls. */ 5693 5694 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 5695 #define TARGET_FUNCTION_OK_FOR_SIBCALL nds32_function_ok_for_sibcall 5696 5697 #undef TARGET_WARN_FUNC_RETURN 5698 #define TARGET_WARN_FUNC_RETURN nds32_warn_func_return 5699 5700 /* Stack smashing protection. */ 5701 5702 5703 /* Implementing the Varargs Macros. */ 5705 5706 #undef TARGET_SETUP_INCOMING_VARARGS 5707 #define TARGET_SETUP_INCOMING_VARARGS nds32_setup_incoming_varargs 5708 5709 #undef TARGET_STRICT_ARGUMENT_NAMING 5710 #define TARGET_STRICT_ARGUMENT_NAMING nds32_strict_argument_naming 5711 5712 5713 /* Trampolines for Nested Functions. */ 5715 5716 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE 5717 #define TARGET_ASM_TRAMPOLINE_TEMPLATE nds32_asm_trampoline_template 5718 5719 #undef TARGET_TRAMPOLINE_INIT 5720 #define TARGET_TRAMPOLINE_INIT nds32_trampoline_init 5721 5722 5723 /* Implicit Calls to Library Routines. */ 5725 5726 5727 /* Addressing Modes. */ 5729 5730 #undef TARGET_LEGITIMATE_ADDRESS_P 5731 #define TARGET_LEGITIMATE_ADDRESS_P nds32_legitimate_address_p 5732 5733 #undef TARGET_LEGITIMIZE_ADDRESS 5734 #define TARGET_LEGITIMIZE_ADDRESS nds32_legitimize_address 5735 5736 #undef TARGET_LEGITIMATE_CONSTANT_P 5737 #define TARGET_LEGITIMATE_CONSTANT_P nds32_legitimate_constant_p 5738 5739 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE 5740 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE nds32_vectorize_preferred_simd_mode 5741 5742 #undef TARGET_CANNOT_FORCE_CONST_MEM 5743 #define TARGET_CANNOT_FORCE_CONST_MEM nds32_cannot_force_const_mem 5744 5745 #undef TARGET_DELEGITIMIZE_ADDRESS 5746 #define TARGET_DELEGITIMIZE_ADDRESS nds32_delegitimize_address 5747 5748 5749 /* Anchored Addresses. */ 5751 5752 5753 /* Condition Code Status. */ 5755 5756 /* -- Representation of condition codes using (cc0). */ 5757 5758 /* -- Representation of condition codes using registers. */ 5759 5760 #undef TARGET_CANONICALIZE_COMPARISON 5761 #define TARGET_CANONICALIZE_COMPARISON nds32_canonicalize_comparison 5762 5763 /* -- Macros to control conditional execution. */ 5764 5765 5766 /* Describing Relative Costs of Operations. */ 5768 5769 #undef TARGET_REGISTER_MOVE_COST 5770 #define TARGET_REGISTER_MOVE_COST nds32_register_move_cost 5771 5772 #undef TARGET_MEMORY_MOVE_COST 5773 #define TARGET_MEMORY_MOVE_COST nds32_memory_move_cost 5774 5775 #undef TARGET_RTX_COSTS 5776 #define TARGET_RTX_COSTS nds32_rtx_costs 5777 5778 #undef TARGET_ADDRESS_COST 5779 #define TARGET_ADDRESS_COST nds32_address_cost 5780 5781 5782 /* Adjusting the Instruction Scheduler. */ 5784 5785 5786 /* Dividing the Output into Sections (Texts, Data, . . . ). */ 5788 5789 #undef TARGET_ENCODE_SECTION_INFO 5790 #define TARGET_ENCODE_SECTION_INFO nds32_encode_section_info 5791 5792 5793 /* Position Independent Code. */ 5795 5796 5797 /* Defining the Output Assembler Language. */ 5799 5800 /* -- The Overall Framework of an Assembler File. */ 5801 5802 #undef TARGET_ASM_FILE_START 5803 #define TARGET_ASM_FILE_START nds32_asm_file_start 5804 #undef TARGET_ASM_FILE_END 5805 #define TARGET_ASM_FILE_END nds32_asm_file_end 5806 5807 /* -- Output of Data. */ 5808 5809 #undef TARGET_ASM_ALIGNED_HI_OP 5810 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" 5811 5812 #undef TARGET_ASM_ALIGNED_SI_OP 5813 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 5814 5815 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 5816 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA nds32_asm_output_addr_const_extra 5817 5818 /* -- Output of Uninitialized Variables. */ 5819 5820 /* -- Output and Generation of Labels. */ 5821 5822 #undef TARGET_ASM_GLOBALIZE_LABEL 5823 #define TARGET_ASM_GLOBALIZE_LABEL nds32_asm_globalize_label 5824 5825 /* -- How Initialization Functions Are Handled. */ 5826 5827 /* -- Macros Controlling Initialization Routines. */ 5828 5829 /* -- Output of Assembler Instructions. */ 5830 5831 #undef TARGET_PRINT_OPERAND 5832 #define TARGET_PRINT_OPERAND nds32_print_operand 5833 #undef TARGET_PRINT_OPERAND_ADDRESS 5834 #define TARGET_PRINT_OPERAND_ADDRESS nds32_print_operand_address 5835 5836 /* -- Output of Dispatch Tables. */ 5837 5838 /* -- Assembler Commands for Exception Regions. */ 5839 5840 #undef TARGET_DWARF_REGISTER_SPAN 5841 #define TARGET_DWARF_REGISTER_SPAN nds32_dwarf_register_span 5842 5843 /* -- Assembler Commands for Alignment. */ 5844 5845 5846 /* Controlling Debugging Information Format. */ 5848 5849 /* -- Macros Affecting All Debugging Formats. */ 5850 5851 /* -- Specific Options for DBX Output. */ 5852 5853 /* -- Open-Ended Hooks for DBX Format. */ 5854 5855 /* -- File Names in DBX Format. */ 5856 5857 /* -- Macros for DWARF Output. */ 5858 5859 /* -- Macros for VMS Debug Format. */ 5860 5861 5862 /* Cross Compilation and Floating Point. */ 5864 5865 5866 /* Mode Switching Instructions. */ 5868 5869 5870 /* Defining target-specific uses of __attribute__. */ 5872 5873 #undef TARGET_ATTRIBUTE_TABLE 5874 #define TARGET_ATTRIBUTE_TABLE nds32_attribute_table 5875 5876 #undef TARGET_MERGE_DECL_ATTRIBUTES 5877 #define TARGET_MERGE_DECL_ATTRIBUTES nds32_merge_decl_attributes 5878 5879 #undef TARGET_INSERT_ATTRIBUTES 5880 #define TARGET_INSERT_ATTRIBUTES nds32_insert_attributes 5881 5882 #undef TARGET_OPTION_PRAGMA_PARSE 5883 #define TARGET_OPTION_PRAGMA_PARSE nds32_option_pragma_parse 5884 5885 #undef TARGET_OPTION_OVERRIDE 5886 #define TARGET_OPTION_OVERRIDE nds32_option_override 5887 5888 5889 /* Emulating TLS. */ 5891 5892 #undef TARGET_HAVE_TLS 5893 #define TARGET_HAVE_TLS TARGET_LINUX_ABI 5894 5895 5896 /* Defining coprocessor specifics for MIPS targets. */ 5898 5899 5900 /* Parameters for Precompiled Header Validity Checking. */ 5902 5903 5904 /* C++ ABI parameters. */ 5906 5907 5908 /* Adding support for named address spaces. */ 5910 5911 5912 /* Miscellaneous Parameters. */ 5914 5915 #undef TARGET_MD_ASM_ADJUST 5916 #define TARGET_MD_ASM_ADJUST nds32_md_asm_adjust 5917 5918 #undef TARGET_INIT_BUILTINS 5919 #define TARGET_INIT_BUILTINS nds32_init_builtins 5920 5921 #undef TARGET_BUILTIN_DECL 5922 #define TARGET_BUILTIN_DECL nds32_builtin_decl 5923 5924 #undef TARGET_EXPAND_BUILTIN 5925 #define TARGET_EXPAND_BUILTIN nds32_expand_builtin 5926 5927 #undef TARGET_INIT_LIBFUNCS 5928 #define TARGET_INIT_LIBFUNCS nds32_init_libfuncs 5929 5930 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 5931 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P nds32_use_blocks_for_constant_p 5932 5933 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE 5934 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 5935 5936 5937 /* ------------------------------------------------------------------------ */ 5939 5940 /* Initialize the GCC target structure. */ 5941 5942 struct gcc_target targetm = TARGET_INITIALIZER; 5943 5944 /* ------------------------------------------------------------------------ */ 5945
Indexes created Fri Mar 06 19:51:54 UTC 2026