pa.h revision 1.1.1.6 1 1.1 mrg /* Definitions of target machine for GNU compiler, for the HP Spectrum.
2 1.1.1.5 mrg Copyright (C) 1992-2016 Free Software Foundation, Inc.
3 1.1 mrg Contributed by Michael Tiemann (tiemann (at) cygnus.com) of Cygnus Support
4 1.1 mrg and Tim Moore (moore (at) defmacro.cs.utah.edu) of the Center for
5 1.1 mrg Software Science at the University of Utah.
6 1.1 mrg
7 1.1 mrg This file is part of GCC.
8 1.1 mrg
9 1.1 mrg GCC is free software; you can redistribute it and/or modify
10 1.1 mrg it under the terms of the GNU General Public License as published by
11 1.1 mrg the Free Software Foundation; either version 3, or (at your option)
12 1.1 mrg any later version.
13 1.1 mrg
14 1.1 mrg GCC is distributed in the hope that it will be useful,
15 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of
16 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 1.1 mrg GNU General Public License for more details.
18 1.1 mrg
19 1.1 mrg You should have received a copy of the GNU General Public License
20 1.1 mrg along with GCC; see the file COPYING3. If not see
21 1.1 mrg <http://www.gnu.org/licenses/>. */
22 1.1 mrg
23 1.1 mrg /* For long call handling. */
24 1.1 mrg extern unsigned long total_code_bytes;
25 1.1 mrg
26 1.1 mrg #define pa_cpu_attr ((enum attr_cpu)pa_cpu)
27 1.1 mrg
28 1.1 mrg #define TARGET_PA_10 (!TARGET_PA_11 && !TARGET_PA_20)
29 1.1 mrg
30 1.1 mrg /* Generate code for the HPPA 2.0 architecture in 64bit mode. */
31 1.1 mrg #ifndef TARGET_64BIT
32 1.1 mrg #define TARGET_64BIT 0
33 1.1 mrg #endif
34 1.1 mrg
35 1.1 mrg /* Generate code for ELF32 ABI. */
36 1.1 mrg #ifndef TARGET_ELF32
37 1.1 mrg #define TARGET_ELF32 0
38 1.1 mrg #endif
39 1.1 mrg
40 1.1 mrg /* Generate code for SOM 32bit ABI. */
41 1.1 mrg #ifndef TARGET_SOM
42 1.1 mrg #define TARGET_SOM 0
43 1.1 mrg #endif
44 1.1 mrg
45 1.1 mrg /* HP-UX UNIX features. */
46 1.1 mrg #ifndef TARGET_HPUX
47 1.1 mrg #define TARGET_HPUX 0
48 1.1 mrg #endif
49 1.1 mrg
50 1.1 mrg /* HP-UX 10.10 UNIX 95 features. */
51 1.1 mrg #ifndef TARGET_HPUX_10_10
52 1.1 mrg #define TARGET_HPUX_10_10 0
53 1.1 mrg #endif
54 1.1 mrg
55 1.1 mrg /* HP-UX 11.* features (11.00, 11.11, 11.23, etc.) */
56 1.1 mrg #ifndef TARGET_HPUX_11
57 1.1 mrg #define TARGET_HPUX_11 0
58 1.1 mrg #endif
59 1.1 mrg
60 1.1 mrg /* HP-UX 11i multibyte and UNIX 98 extensions. */
61 1.1 mrg #ifndef TARGET_HPUX_11_11
62 1.1 mrg #define TARGET_HPUX_11_11 0
63 1.1 mrg #endif
64 1.1 mrg
65 1.1.1.2 mrg /* HP-UX 11i multibyte and UNIX 2003 extensions. */
66 1.1.1.2 mrg #ifndef TARGET_HPUX_11_31
67 1.1.1.2 mrg #define TARGET_HPUX_11_31 0
68 1.1.1.2 mrg #endif
69 1.1.1.2 mrg
70 1.1.1.2 mrg /* HP-UX long double library. */
71 1.1.1.2 mrg #ifndef HPUX_LONG_DOUBLE_LIBRARY
72 1.1.1.2 mrg #define HPUX_LONG_DOUBLE_LIBRARY 0
73 1.1.1.2 mrg #endif
74 1.1.1.2 mrg
75 1.1.1.2 mrg /* Linux kernel atomic operation support. */
76 1.1.1.2 mrg #ifndef TARGET_SYNC_LIBCALL
77 1.1.1.2 mrg #define TARGET_SYNC_LIBCALL 0
78 1.1.1.2 mrg #endif
79 1.1.1.2 mrg
80 1.1 mrg /* The following three defines are potential target switches. The current
81 1.1 mrg defines are optimal given the current capabilities of GAS and GNU ld. */
82 1.1 mrg
83 1.1 mrg /* Define to a C expression evaluating to true to use long absolute calls.
84 1.1 mrg Currently, only the HP assembler and SOM linker support long absolute
85 1.1 mrg calls. They are used only in non-pic code. */
86 1.1 mrg #define TARGET_LONG_ABS_CALL (TARGET_SOM && !TARGET_GAS)
87 1.1 mrg
88 1.1 mrg /* Define to a C expression evaluating to true to use long PIC symbol
89 1.1 mrg difference calls. Long PIC symbol difference calls are only used with
90 1.1 mrg the HP assembler and linker. The HP assembler detects this instruction
91 1.1 mrg sequence and treats it as long pc-relative call. Currently, GAS only
92 1.1 mrg allows a difference of two symbols in the same subspace, and it doesn't
93 1.1 mrg detect the sequence as a pc-relative call. */
94 1.1 mrg #define TARGET_LONG_PIC_SDIFF_CALL (!TARGET_GAS && TARGET_HPUX)
95 1.1 mrg
96 1.1 mrg /* Define to a C expression evaluating to true to use long PIC
97 1.1 mrg pc-relative calls. Long PIC pc-relative calls are only used with
98 1.1 mrg GAS. Currently, they are usable for calls which bind local to a
99 1.1 mrg module but not for external calls. */
100 1.1 mrg #define TARGET_LONG_PIC_PCREL_CALL 0
101 1.1 mrg
102 1.1 mrg /* Define to a C expression evaluating to true to use SOM secondary
103 1.1 mrg definition symbols for weak support. Linker support for secondary
104 1.1 mrg definition symbols is buggy prior to HP-UX 11.X. */
105 1.1 mrg #define TARGET_SOM_SDEF 0
106 1.1 mrg
107 1.1 mrg /* Define to a C expression evaluating to true to save the entry value
108 1.1 mrg of SP in the current frame marker. This is normally unnecessary.
109 1.1 mrg However, the HP-UX unwind library looks at the SAVE_SP callinfo flag.
110 1.1 mrg HP compilers don't use this flag but it is supported by the assembler.
111 1.1 mrg We set this flag to indicate that register %r3 has been saved at the
112 1.1 mrg start of the frame. Thus, when the HP unwind library is used, we
113 1.1 mrg need to generate additional code to save SP into the frame marker. */
114 1.1 mrg #define TARGET_HPUX_UNWIND_LIBRARY 0
115 1.1 mrg
116 1.1 mrg #ifndef TARGET_DEFAULT
117 1.1.1.3 mrg #define TARGET_DEFAULT MASK_GAS
118 1.1 mrg #endif
119 1.1 mrg
120 1.1 mrg #ifndef TARGET_CPU_DEFAULT
121 1.1 mrg #define TARGET_CPU_DEFAULT 0
122 1.1 mrg #endif
123 1.1 mrg
124 1.1 mrg #ifndef TARGET_SCHED_DEFAULT
125 1.1 mrg #define TARGET_SCHED_DEFAULT PROCESSOR_8000
126 1.1 mrg #endif
127 1.1 mrg
128 1.1 mrg /* Support for a compile-time default CPU, et cetera. The rules are:
129 1.1 mrg --with-schedule is ignored if -mschedule is specified.
130 1.1 mrg --with-arch is ignored if -march is specified. */
131 1.1 mrg #define OPTION_DEFAULT_SPECS \
132 1.1 mrg {"arch", "%{!march=*:-march=%(VALUE)}" }, \
133 1.1 mrg {"schedule", "%{!mschedule=*:-mschedule=%(VALUE)}" }
134 1.1 mrg
135 1.1 mrg /* Specify the dialect of assembler to use. New mnemonics is dialect one
136 1.1 mrg and the old mnemonics are dialect zero. */
137 1.1 mrg #define ASSEMBLER_DIALECT (TARGET_PA_20 ? 1 : 0)
138 1.1 mrg
139 1.1 mrg /* Override some settings from dbxelf.h. */
140 1.1 mrg
141 1.1 mrg /* We do not have to be compatible with dbx, so we enable gdb extensions
142 1.1 mrg by default. */
143 1.1 mrg #define DEFAULT_GDB_EXTENSIONS 1
144 1.1 mrg
145 1.1 mrg /* This used to be zero (no max length), but big enums and such can
146 1.1 mrg cause huge strings which killed gas.
147 1.1 mrg
148 1.1 mrg We also have to avoid lossage in dbxout.c -- it does not compute the
149 1.1 mrg string size accurately, so we are real conservative here. */
150 1.1 mrg #undef DBX_CONTIN_LENGTH
151 1.1 mrg #define DBX_CONTIN_LENGTH 3000
152 1.1 mrg
153 1.1 mrg /* GDB always assumes the current function's frame begins at the value
154 1.1 mrg of the stack pointer upon entry to the current function. Accessing
155 1.1 mrg local variables and parameters passed on the stack is done using the
156 1.1 mrg base of the frame + an offset provided by GCC.
157 1.1 mrg
158 1.1 mrg For functions which have frame pointers this method works fine;
159 1.1 mrg the (frame pointer) == (stack pointer at function entry) and GCC provides
160 1.1 mrg an offset relative to the frame pointer.
161 1.1 mrg
162 1.1 mrg This loses for functions without a frame pointer; GCC provides an offset
163 1.1 mrg which is relative to the stack pointer after adjusting for the function's
164 1.1 mrg frame size. GDB would prefer the offset to be relative to the value of
165 1.1 mrg the stack pointer at the function's entry. Yuk! */
166 1.1 mrg #define DEBUGGER_AUTO_OFFSET(X) \
167 1.1 mrg ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \
168 1.1.1.2 mrg + (frame_pointer_needed ? 0 : pa_compute_frame_size (get_frame_size (), 0)))
169 1.1 mrg
170 1.1 mrg #define DEBUGGER_ARG_OFFSET(OFFSET, X) \
171 1.1 mrg ((GET_CODE (X) == PLUS ? OFFSET : 0) \
172 1.1.1.2 mrg + (frame_pointer_needed ? 0 : pa_compute_frame_size (get_frame_size (), 0)))
173 1.1 mrg
174 1.1 mrg #define TARGET_CPU_CPP_BUILTINS() \
175 1.1 mrg do { \
176 1.1 mrg builtin_assert("cpu=hppa"); \
177 1.1 mrg builtin_assert("machine=hppa"); \
178 1.1 mrg builtin_define("__hppa"); \
179 1.1 mrg builtin_define("__hppa__"); \
180 1.1 mrg if (TARGET_PA_20) \
181 1.1 mrg builtin_define("_PA_RISC2_0"); \
182 1.1 mrg else if (TARGET_PA_11) \
183 1.1 mrg builtin_define("_PA_RISC1_1"); \
184 1.1 mrg else \
185 1.1 mrg builtin_define("_PA_RISC1_0"); \
186 1.1 mrg } while (0)
187 1.1 mrg
188 1.1 mrg /* An old set of OS defines for various BSD-like systems. */
189 1.1 mrg #define TARGET_OS_CPP_BUILTINS() \
190 1.1 mrg do \
191 1.1 mrg { \
192 1.1 mrg builtin_define_std ("REVARGV"); \
193 1.1 mrg builtin_define_std ("hp800"); \
194 1.1 mrg builtin_define_std ("hp9000"); \
195 1.1 mrg builtin_define_std ("hp9k8"); \
196 1.1 mrg if (!c_dialect_cxx () && !flag_iso) \
197 1.1 mrg builtin_define ("hppa"); \
198 1.1 mrg builtin_define_std ("spectrum"); \
199 1.1 mrg builtin_define_std ("unix"); \
200 1.1 mrg builtin_assert ("system=bsd"); \
201 1.1 mrg builtin_assert ("system=unix"); \
202 1.1 mrg } \
203 1.1 mrg while (0)
204 1.1 mrg
205 1.1 mrg #define CC1_SPEC "%{pg:} %{p:}"
206 1.1 mrg
207 1.1 mrg #define LINK_SPEC "%{mlinker-opt:-O} %{!shared:-u main} %{shared:-b}"
208 1.1 mrg
209 1.1 mrg /* We don't want -lg. */
210 1.1 mrg #ifndef LIB_SPEC
211 1.1 mrg #define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}"
212 1.1 mrg #endif
213 1.1 mrg
214 1.1 mrg /* Make gcc agree with <machine/ansi.h> */
215 1.1 mrg
216 1.1 mrg #define SIZE_TYPE "unsigned int"
217 1.1 mrg #define PTRDIFF_TYPE "int"
218 1.1 mrg #define WCHAR_TYPE "unsigned int"
219 1.1 mrg #define WCHAR_TYPE_SIZE 32
220 1.1 mrg
221 1.1 mrg /* target machine storage layout */
223 1.1 mrg typedef struct GTY(()) machine_function
224 1.1 mrg {
225 1.1 mrg /* Flag indicating that a .NSUBSPA directive has been output for
226 1.1 mrg this function. */
227 1.1 mrg int in_nsubspa;
228 1.1 mrg } machine_function;
229 1.1 mrg
230 1.1 mrg /* Define this macro if it is advisable to hold scalars in registers
231 1.1 mrg in a wider mode than that declared by the program. In such cases,
232 1.1 mrg the value is constrained to be within the bounds of the declared
233 1.1 mrg type, but kept valid in the wider mode. The signedness of the
234 1.1 mrg extension may differ from that of the type. */
235 1.1 mrg
236 1.1 mrg #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \
237 1.1 mrg if (GET_MODE_CLASS (MODE) == MODE_INT \
238 1.1 mrg && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \
239 1.1 mrg (MODE) = word_mode;
240 1.1 mrg
241 1.1 mrg /* Define this if most significant bit is lowest numbered
242 1.1 mrg in instructions that operate on numbered bit-fields. */
243 1.1 mrg #define BITS_BIG_ENDIAN 1
244 1.1 mrg
245 1.1 mrg /* Define this if most significant byte of a word is the lowest numbered. */
246 1.1 mrg /* That is true on the HP-PA. */
247 1.1 mrg #define BYTES_BIG_ENDIAN 1
248 1.1 mrg
249 1.1 mrg /* Define this if most significant word of a multiword number is lowest
250 1.1 mrg numbered. */
251 1.1 mrg #define WORDS_BIG_ENDIAN 1
252 1.1 mrg
253 1.1 mrg #define MAX_BITS_PER_WORD 64
254 1.1 mrg
255 1.1 mrg /* Width of a word, in units (bytes). */
256 1.1 mrg #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4)
257 1.1 mrg
258 1.1 mrg /* Minimum number of units in a word. If this is undefined, the default
259 1.1 mrg is UNITS_PER_WORD. Otherwise, it is the constant value that is the
260 1.1 mrg smallest value that UNITS_PER_WORD can have at run-time.
261 1.1 mrg
262 1.1 mrg FIXME: This needs to be 4 when TARGET_64BIT is true to suppress the
263 1.1 mrg building of various TImode routines in libgcc. The HP runtime
264 1.1 mrg specification doesn't provide the alignment requirements and calling
265 1.1 mrg conventions for TImode variables. */
266 1.1 mrg #define MIN_UNITS_PER_WORD 4
267 1.1 mrg
268 1.1 mrg /* The widest floating point format supported by the hardware. Note that
269 1.1 mrg setting this influences some Ada floating point type sizes, currently
270 1.1 mrg required for GNAT to operate properly. */
271 1.1 mrg #define WIDEST_HARDWARE_FP_SIZE 64
272 1.1 mrg
273 1.1 mrg /* Allocation boundary (in *bits*) for storing arguments in argument list. */
274 1.1 mrg #define PARM_BOUNDARY BITS_PER_WORD
275 1.1 mrg
276 1.1 mrg /* Largest alignment required for any stack parameter, in bits.
277 1.1 mrg Don't define this if it is equal to PARM_BOUNDARY */
278 1.1 mrg #define MAX_PARM_BOUNDARY BIGGEST_ALIGNMENT
279 1.1 mrg
280 1.1 mrg /* Boundary (in *bits*) on which stack pointer is always aligned;
281 1.1 mrg certain optimizations in combine depend on this.
282 1.1 mrg
283 1.1 mrg The HP-UX runtime documents mandate 64-byte and 16-byte alignment for
284 1.1 mrg the stack on the 32 and 64-bit ports, respectively. However, we
285 1.1 mrg are only guaranteed that the stack is aligned to BIGGEST_ALIGNMENT
286 1.1 mrg in main. Thus, we treat the former as the preferred alignment. */
287 1.1 mrg #define STACK_BOUNDARY BIGGEST_ALIGNMENT
288 1.1 mrg #define PREFERRED_STACK_BOUNDARY (TARGET_64BIT ? 128 : 512)
289 1.1 mrg
290 1.1 mrg /* Allocation boundary (in *bits*) for the code of a function. */
291 1.1 mrg #define FUNCTION_BOUNDARY BITS_PER_WORD
292 1.1 mrg
293 1.1 mrg /* Alignment of field after `int : 0' in a structure. */
294 1.1 mrg #define EMPTY_FIELD_BOUNDARY 32
295 1.1 mrg
296 1.1 mrg /* Every structure's size must be a multiple of this. */
297 1.1 mrg #define STRUCTURE_SIZE_BOUNDARY 8
298 1.1 mrg
299 1.1 mrg /* A bit-field declared as `int' forces `int' alignment for the struct. */
300 1.1 mrg #define PCC_BITFIELD_TYPE_MATTERS 1
301 1.1.1.4 mrg
302 1.1.1.4 mrg /* No data type wants to be aligned rounder than this. The long double
303 1.1.1.4 mrg type has 16-byte alignment on the 64-bit target even though it was never
304 1.1.1.4 mrg implemented in hardware. The software implementation only needs 8-byte
305 1.1 mrg alignment. This matches the biggest alignment of the HP compilers. */
306 1.1 mrg #define BIGGEST_ALIGNMENT (2 * BITS_PER_WORD)
307 1.1.1.4 mrg
308 1.1.1.4 mrg /* Alignment, in bits, a C conformant malloc implementation has to provide.
309 1.1.1.4 mrg The HP-UX malloc implementation provides a default alignment of 8 bytes.
310 1.1.1.4 mrg It should be 16 bytes on the 64-bit target since long double has 16-byte
311 1.1.1.4 mrg alignment. It can be increased with mallopt but it's non critical since
312 1.1.1.4 mrg long double was never implemented in hardware. The glibc implementation
313 1.1.1.4 mrg currently provides 8-byte alignment. It should be 16 bytes since various
314 1.1.1.4 mrg POSIX types such as pthread_mutex_t require 16-byte alignment. Again,
315 1.1.1.4 mrg this is non critical since 16-byte alignment is no longer needed for
316 1.1.1.4 mrg atomic operations. */
317 1.1.1.4 mrg #define MALLOC_ABI_ALIGNMENT (TARGET_SOM ? 64 : 128)
318 1.1 mrg
319 1.1 mrg /* Get around hp-ux assembler bug, and make strcpy of constants fast. */
320 1.1 mrg #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
321 1.1 mrg (TREE_CODE (EXP) == STRING_CST \
322 1.1 mrg && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
323 1.1 mrg
324 1.1 mrg /* Make arrays of chars word-aligned for the same reasons. */
325 1.1 mrg #define DATA_ALIGNMENT(TYPE, ALIGN) \
326 1.1 mrg (TREE_CODE (TYPE) == ARRAY_TYPE \
327 1.1 mrg && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \
328 1.1 mrg && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN))
329 1.1 mrg
330 1.1 mrg /* Set this nonzero if move instructions will actually fail to work
331 1.1 mrg when given unaligned data. */
332 1.1 mrg #define STRICT_ALIGNMENT 1
333 1.1 mrg
334 1.1 mrg /* Value is 1 if it is a good idea to tie two pseudo registers
335 1.1 mrg when one has mode MODE1 and one has mode MODE2.
336 1.1 mrg If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
337 1.1 mrg for any hard reg, then this must be 0 for correct output. */
338 1.1 mrg #define MODES_TIEABLE_P(MODE1, MODE2) \
339 1.1 mrg pa_modes_tieable_p (MODE1, MODE2)
340 1.1 mrg
341 1.1 mrg /* Specify the registers used for certain standard purposes.
342 1.1 mrg The values of these macros are register numbers. */
343 1.1 mrg
344 1.1 mrg /* The HP-PA pc isn't overloaded on a register that the compiler knows about. */
345 1.1 mrg /* #define PC_REGNUM */
346 1.1 mrg
347 1.1 mrg /* Register to use for pushing function arguments. */
348 1.1 mrg #define STACK_POINTER_REGNUM 30
349 1.1.1.2 mrg
350 1.1.1.2 mrg /* Fixed register for local variable access. Always eliminated. */
351 1.1.1.2 mrg #define FRAME_POINTER_REGNUM (TARGET_64BIT ? 61 : 89)
352 1.1 mrg
353 1.1.1.2 mrg /* Base register for access to local variables of the function. */
354 1.1 mrg #define HARD_FRAME_POINTER_REGNUM 3
355 1.1 mrg
356 1.1 mrg /* Don't allow hard registers to be renamed into r2 unless r2
357 1.1 mrg is already live or already being saved (due to eh). */
358 1.1 mrg
359 1.1 mrg #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \
360 1.1 mrg ((NEW_REG) != 2 || df_regs_ever_live_p (2) || crtl->calls_eh_return)
361 1.1 mrg
362 1.1 mrg /* Base register for access to arguments of the function. */
363 1.1 mrg #define ARG_POINTER_REGNUM (TARGET_64BIT ? 29 : 3)
364 1.1 mrg
365 1.1 mrg /* Register in which static-chain is passed to a function. */
366 1.1 mrg #define STATIC_CHAIN_REGNUM (TARGET_64BIT ? 31 : 29)
367 1.1 mrg
368 1.1 mrg /* Register used to address the offset table for position-independent
369 1.1 mrg data references. */
370 1.1 mrg #define PIC_OFFSET_TABLE_REGNUM \
371 1.1 mrg (flag_pic ? (TARGET_64BIT ? 27 : 19) : INVALID_REGNUM)
372 1.1 mrg
373 1.1 mrg #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1
374 1.1 mrg
375 1.1 mrg /* Function to return the rtx used to save the pic offset table register
376 1.1.1.2 mrg across function calls. */
377 1.1 mrg extern rtx hppa_pic_save_rtx (void);
378 1.1 mrg
379 1.1 mrg #define DEFAULT_PCC_STRUCT_RETURN 0
380 1.1 mrg
381 1.1 mrg /* Register in which address to store a structure value
382 1.1 mrg is passed to a function. */
383 1.1 mrg #define PA_STRUCT_VALUE_REGNUM 28
384 1.1.1.2 mrg
385 1.1.1.2 mrg /* Definitions for register eliminations.
386 1.1.1.2 mrg
387 1.1.1.2 mrg We have two registers that can be eliminated. First, the frame pointer
388 1.1.1.2 mrg register can often be eliminated in favor of the stack pointer register.
389 1.1.1.2 mrg Secondly, the argument pointer register can always be eliminated in the
390 1.1.1.2 mrg 32-bit runtimes. */
391 1.1.1.2 mrg
392 1.1.1.2 mrg /* This is an array of structures. Each structure initializes one pair
393 1.1.1.2 mrg of eliminable registers. The "from" register number is given first,
394 1.1.1.2 mrg followed by "to". Eliminations of the same "from" register are listed
395 1.1.1.2 mrg in order of preference.
396 1.1.1.2 mrg
397 1.1.1.2 mrg The argument pointer cannot be eliminated in the 64-bit runtime. It
398 1.1.1.2 mrg is the same register as the hard frame pointer in the 32-bit runtime.
399 1.1.1.2 mrg So, it does not need to be listed. */
400 1.1.1.2 mrg #define ELIMINABLE_REGS \
401 1.1.1.2 mrg {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
402 1.1.1.2 mrg { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \
403 1.1.1.2 mrg { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM} }
404 1.1.1.2 mrg
405 1.1.1.2 mrg /* Define the offset between two registers, one to be eliminated,
406 1.1.1.2 mrg and the other its replacement, at the start of a routine. */
407 1.1.1.2 mrg #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \
408 1.1.1.2 mrg ((OFFSET) = pa_initial_elimination_offset(FROM, TO))
409 1.1 mrg
410 1.1 mrg /* Describe how we implement __builtin_eh_return. */
411 1.1 mrg #define EH_RETURN_DATA_REGNO(N) \
412 1.1 mrg ((N) < 3 ? (N) + 20 : (N) == 3 ? 31 : INVALID_REGNUM)
413 1.1 mrg #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 29)
414 1.1 mrg #define EH_RETURN_HANDLER_RTX pa_eh_return_handler_rtx ()
415 1.1 mrg
416 1.1 mrg /* Offset from the frame pointer register value to the top of stack. */
417 1.1 mrg #define FRAME_POINTER_CFA_OFFSET(FNDECL) 0
418 1.1.1.2 mrg
419 1.1.1.2 mrg /* The maximum number of hard registers that can be saved in the call
420 1.1.1.2 mrg frame. The soft frame pointer is not included. */
421 1.1.1.2 mrg #define DWARF_FRAME_REGISTERS (FIRST_PSEUDO_REGISTER - 1)
422 1.1 mrg
423 1.1 mrg /* A C expression whose value is RTL representing the location of the
424 1.1 mrg incoming return address at the beginning of any function, before the
425 1.1 mrg prologue. You only need to define this macro if you want to support
426 1.1 mrg call frame debugging information like that provided by DWARF 2. */
427 1.1 mrg #define INCOMING_RETURN_ADDR_RTX (gen_rtx_REG (word_mode, 2))
428 1.1 mrg #define DWARF_FRAME_RETURN_COLUMN (DWARF_FRAME_REGNUM (2))
429 1.1 mrg
430 1.1 mrg /* A C expression whose value is an integer giving a DWARF 2 column
431 1.1 mrg number that may be used as an alternate return column. This should
432 1.1 mrg be defined only if DWARF_FRAME_RETURN_COLUMN is set to a general
433 1.1 mrg register, but an alternate column needs to be used for signal frames.
434 1.1 mrg
435 1.1 mrg Column 0 is not used but unfortunately its register size is set to
436 1.1.1.2 mrg 4 bytes (sizeof CCmode) so it can't be used on 64-bit targets. */
437 1.1 mrg #define DWARF_ALT_FRAME_RETURN_COLUMN (FIRST_PSEUDO_REGISTER - 1)
438 1.1 mrg
439 1.1 mrg /* This macro chooses the encoding of pointers embedded in the exception
440 1.1 mrg handling sections. If at all possible, this should be defined such
441 1.1 mrg that the exception handling section will not require dynamic relocations,
442 1.1 mrg and so may be read-only.
443 1.1 mrg
444 1.1 mrg Because the HP assembler auto aligns, it is necessary to use
445 1.1 mrg DW_EH_PE_aligned. It's not possible to make the data read-only
446 1.1 mrg on the HP-UX SOM port since the linker requires fixups for label
447 1.1 mrg differences in different sections to be word aligned. However,
448 1.1 mrg the SOM linker can do unaligned fixups for absolute pointers.
449 1.1 mrg We also need aligned pointers for global and function pointers.
450 1.1 mrg
451 1.1 mrg Although the HP-UX 64-bit ELF linker can handle unaligned pc-relative
452 1.1 mrg fixups, the runtime doesn't have a consistent relationship between
453 1.1 mrg text and data for dynamically loaded objects. Thus, it's not possible
454 1.1 mrg to use pc-relative encoding for pointers on this target. It may be
455 1.1 mrg possible to use segment relative encodings but GAS doesn't currently
456 1.1 mrg have a mechanism to generate these encodings. For other targets, we
457 1.1 mrg use pc-relative encoding for pointers. If the pointer might require
458 1.1 mrg dynamic relocation, we make it indirect. */
459 1.1 mrg #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \
460 1.1 mrg (TARGET_GAS && !TARGET_HPUX \
461 1.1 mrg ? (DW_EH_PE_pcrel \
462 1.1 mrg | ((GLOBAL) || (CODE) == 2 ? DW_EH_PE_indirect : 0) \
463 1.1 mrg | (TARGET_64BIT ? DW_EH_PE_sdata8 : DW_EH_PE_sdata4)) \
464 1.1 mrg : (!TARGET_GAS || (GLOBAL) || (CODE) == 2 \
465 1.1 mrg ? DW_EH_PE_aligned : DW_EH_PE_absptr))
466 1.1 mrg
467 1.1 mrg /* Handle special EH pointer encodings. Absolute, pc-relative, and
468 1.1 mrg indirect are handled automatically. We output pc-relative, and
469 1.1 mrg indirect pc-relative ourself since we need some special magic to
470 1.1 mrg generate pc-relative relocations, and to handle indirect function
471 1.1 mrg pointers. */
472 1.1 mrg #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \
473 1.1 mrg do { \
474 1.1 mrg if (((ENCODING) & 0x70) == DW_EH_PE_pcrel) \
475 1.1 mrg { \
476 1.1 mrg fputs (integer_asm_op (SIZE, FALSE), FILE); \
477 1.1.1.2 mrg if ((ENCODING) & DW_EH_PE_indirect) \
478 1.1 mrg output_addr_const (FILE, pa_get_deferred_plabel (ADDR)); \
479 1.1 mrg else \
480 1.1 mrg assemble_name (FILE, XSTR ((ADDR), 0)); \
481 1.1 mrg fputs ("+8-$PIC_pcrel$0", FILE); \
482 1.1 mrg goto DONE; \
483 1.1 mrg } \
484 1.1 mrg } while (0)
485 1.1 mrg
486 1.1 mrg
488 1.1 mrg /* The class value for index registers, and the one for base regs. */
489 1.1 mrg #define INDEX_REG_CLASS GENERAL_REGS
490 1.1 mrg #define BASE_REG_CLASS GENERAL_REGS
491 1.1 mrg
492 1.1 mrg #define FP_REG_CLASS_P(CLASS) \
493 1.1 mrg ((CLASS) == FP_REGS || (CLASS) == FPUPPER_REGS)
494 1.1 mrg
495 1.1 mrg /* True if register is floating-point. */
496 1.1 mrg #define FP_REGNO_P(N) ((N) >= FP_REG_FIRST && (N) <= FP_REG_LAST)
497 1.1 mrg
498 1.1 mrg #define MAYBE_FP_REG_CLASS_P(CLASS) \
499 1.1 mrg reg_classes_intersect_p ((CLASS), FP_REGS)
500 1.1 mrg
501 1.1 mrg
502 1.1 mrg /* Stack layout; function entry, exit and calling. */
504 1.1 mrg
505 1.1 mrg /* Define this if pushing a word on the stack
506 1.1 mrg makes the stack pointer a smaller address. */
507 1.1.1.5 mrg /* #define STACK_GROWS_DOWNWARD */
508 1.1 mrg
509 1.1 mrg /* Believe it or not. */
510 1.1 mrg #define ARGS_GROW_DOWNWARD 1
511 1.1 mrg
512 1.1 mrg /* Define this to nonzero if the nominal address of the stack frame
513 1.1 mrg is at the high-address end of the local variables;
514 1.1 mrg that is, each additional local variable allocated
515 1.1 mrg goes at a more negative offset in the frame. */
516 1.1 mrg #define FRAME_GROWS_DOWNWARD 0
517 1.1 mrg
518 1.1 mrg /* Offset within stack frame to start allocating local variables at.
519 1.1 mrg If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
520 1.1 mrg first local allocated. Otherwise, it is the offset to the BEGINNING
521 1.1 mrg of the first local allocated.
522 1.1 mrg
523 1.1 mrg On the 32-bit ports, we reserve one slot for the previous frame
524 1.1 mrg pointer and one fill slot. The fill slot is for compatibility
525 1.1 mrg with HP compiled programs. On the 64-bit ports, we reserve one
526 1.1 mrg slot for the previous frame pointer. */
527 1.1 mrg #define STARTING_FRAME_OFFSET 8
528 1.1 mrg
529 1.1 mrg /* Define STACK_ALIGNMENT_NEEDED to zero to disable final alignment
530 1.1 mrg of the stack. The default is to align it to STACK_BOUNDARY. */
531 1.1 mrg #define STACK_ALIGNMENT_NEEDED 0
532 1.1 mrg
533 1.1 mrg /* If we generate an insn to push BYTES bytes,
534 1.1 mrg this says how many the stack pointer really advances by.
535 1.1 mrg On the HP-PA, don't define this because there are no push insns. */
536 1.1 mrg /* #define PUSH_ROUNDING(BYTES) */
537 1.1 mrg
538 1.1 mrg /* Offset of first parameter from the argument pointer register value.
539 1.1 mrg This value will be negated because the arguments grow down.
540 1.1 mrg Also note that on STACK_GROWS_UPWARD machines (such as this one)
541 1.1 mrg this is the distance from the frame pointer to the end of the first
542 1.1 mrg argument, not it's beginning. To get the real offset of the first
543 1.1 mrg argument, the size of the argument must be added. */
544 1.1 mrg
545 1.1 mrg #define FIRST_PARM_OFFSET(FNDECL) (TARGET_64BIT ? -64 : -32)
546 1.1 mrg
547 1.1 mrg /* When a parameter is passed in a register, stack space is still
548 1.1 mrg allocated for it. */
549 1.1 mrg #define REG_PARM_STACK_SPACE(DECL) (TARGET_64BIT ? 64 : 16)
550 1.1 mrg
551 1.1 mrg /* Define this if the above stack space is to be considered part of the
552 1.1 mrg space allocated by the caller. */
553 1.1 mrg #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1
554 1.1 mrg
555 1.1 mrg /* Keep the stack pointer constant throughout the function.
556 1.1 mrg This is both an optimization and a necessity: longjmp
557 1.1 mrg doesn't behave itself when the stack pointer moves within
558 1.1 mrg the function! */
559 1.1 mrg #define ACCUMULATE_OUTGOING_ARGS 1
560 1.1 mrg
561 1.1 mrg /* The weird HPPA calling conventions require a minimum of 48 bytes on
562 1.1 mrg the stack: 16 bytes for register saves, and 32 bytes for magic.
563 1.1 mrg This is the difference between the logical top of stack and the
564 1.1 mrg actual sp.
565 1.1 mrg
566 1.1 mrg On the 64-bit port, the HP C compiler allocates a 48-byte frame
567 1.1 mrg marker, although the runtime documentation only describes a 16
568 1.1 mrg byte marker. For compatibility, we allocate 48 bytes. */
569 1.1 mrg #define STACK_POINTER_OFFSET \
570 1.1 mrg (TARGET_64BIT ? -(crtl->outgoing_args_size + 48): -32)
571 1.1 mrg
572 1.1 mrg #define STACK_DYNAMIC_OFFSET(FNDECL) \
573 1.1 mrg (TARGET_64BIT \
574 1.1 mrg ? (STACK_POINTER_OFFSET) \
575 1.1 mrg : ((STACK_POINTER_OFFSET) - crtl->outgoing_args_size))
576 1.1 mrg
577 1.1 mrg
578 1.1 mrg /* Define a data type for recording info about an argument list
580 1.1 mrg during the scan of that argument list. This data type should
581 1.1 mrg hold all necessary information about the function itself
582 1.1 mrg and about the args processed so far, enough to enable macros
583 1.1 mrg such as FUNCTION_ARG to determine where the next arg should go.
584 1.1 mrg
585 1.1 mrg On the HP-PA, the WORDS field holds the number of words
586 1.1 mrg of arguments scanned so far (including the invisible argument,
587 1.1 mrg if any, which holds the structure-value-address). Thus, 4 or
588 1.1 mrg more means all following args should go on the stack.
589 1.1.1.5 mrg
590 1.1 mrg The INCOMING field tracks whether this is an "incoming" or
591 1.1 mrg "outgoing" argument.
592 1.1 mrg
593 1.1 mrg The INDIRECT field indicates whether this is an indirect
594 1.1 mrg call or not.
595 1.1 mrg
596 1.1 mrg The NARGS_PROTOTYPE field indicates that an argument does not
597 1.1 mrg have a prototype when it less than or equal to 0. */
598 1.1 mrg
599 1.1 mrg struct hppa_args {int words, nargs_prototype, incoming, indirect; };
600 1.1 mrg
601 1.1 mrg #define CUMULATIVE_ARGS struct hppa_args
602 1.1 mrg
603 1.1 mrg /* Initialize a variable CUM of type CUMULATIVE_ARGS
604 1.1 mrg for a call to a function whose data type is FNTYPE.
605 1.1 mrg For a library call, FNTYPE is 0. */
606 1.1 mrg
607 1.1.1.2 mrg #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \
608 1.1 mrg (CUM).words = 0, \
609 1.1 mrg (CUM).incoming = 0, \
610 1.1 mrg (CUM).indirect = (FNTYPE) && !(FNDECL), \
611 1.1 mrg (CUM).nargs_prototype = (FNTYPE && prototype_p (FNTYPE) \
612 1.1 mrg ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \
613 1.1 mrg + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \
614 1.1 mrg || pa_return_in_memory (TREE_TYPE (FNTYPE), 0))) \
615 1.1 mrg : 0)
616 1.1 mrg
617 1.1 mrg
618 1.1 mrg
619 1.1 mrg /* Similar, but when scanning the definition of a procedure. We always
620 1.1 mrg set NARGS_PROTOTYPE large so we never return a PARALLEL. */
621 1.1 mrg
622 1.1 mrg #define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \
623 1.1 mrg (CUM).words = 0, \
624 1.1 mrg (CUM).incoming = 1, \
625 1.1 mrg (CUM).indirect = 0, \
626 1.1 mrg (CUM).nargs_prototype = 1000
627 1.1 mrg
628 1.1 mrg /* Figure out the size in words of the function argument. The size
629 1.1 mrg returned by this macro should always be greater than zero because
630 1.1 mrg we pass variable and zero sized objects by reference. */
631 1.1 mrg
632 1.1 mrg #define FUNCTION_ARG_SIZE(MODE, TYPE) \
633 1.1 mrg ((((MODE) != BLKmode \
634 1.1 mrg ? (HOST_WIDE_INT) GET_MODE_SIZE (MODE) \
635 1.1 mrg : int_size_in_bytes (TYPE)) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
636 1.1 mrg
637 1.1 mrg /* Determine where to put an argument to a function.
638 1.1 mrg Value is zero to push the argument on the stack,
639 1.1 mrg or a hard register in which to store the argument.
640 1.1 mrg
641 1.1 mrg MODE is the argument's machine mode.
642 1.1 mrg TYPE is the data type of the argument (as a tree).
643 1.1 mrg This is null for libcalls where that information may
644 1.1 mrg not be available.
645 1.1 mrg CUM is a variable of type CUMULATIVE_ARGS which gives info about
646 1.1 mrg the preceding args and about the function being called.
647 1.1 mrg NAMED is nonzero if this argument is a named parameter
648 1.1 mrg (otherwise it is an extra parameter matching an ellipsis).
649 1.1 mrg
650 1.1 mrg On the HP-PA the first four words of args are normally in registers
651 1.1 mrg and the rest are pushed. But any arg that won't entirely fit in regs
652 1.1 mrg is pushed.
653 1.1 mrg
654 1.1 mrg Arguments passed in registers are either 1 or 2 words long.
655 1.1 mrg
656 1.1 mrg The caller must make a distinction between calls to explicitly named
657 1.1 mrg functions and calls through pointers to functions -- the conventions
658 1.1 mrg are different! Calls through pointers to functions only use general
659 1.1 mrg registers for the first four argument words.
660 1.1 mrg
661 1.1 mrg Of course all this is different for the portable runtime model
662 1.1 mrg HP wants everyone to use for ELF. Ugh. Here's a quick description
663 1.1 mrg of how it's supposed to work.
664 1.1 mrg
665 1.1 mrg 1) callee side remains unchanged. It expects integer args to be
666 1.1 mrg in the integer registers, float args in the float registers and
667 1.1 mrg unnamed args in integer registers.
668 1.1 mrg
669 1.1 mrg 2) caller side now depends on if the function being called has
670 1.1 mrg a prototype in scope (rather than if it's being called indirectly).
671 1.1 mrg
672 1.1 mrg 2a) If there is a prototype in scope, then arguments are passed
673 1.1 mrg according to their type (ints in integer registers, floats in float
674 1.1 mrg registers, unnamed args in integer registers.
675 1.1 mrg
676 1.1 mrg 2b) If there is no prototype in scope, then floating point arguments
677 1.1 mrg are passed in both integer and float registers. egad.
678 1.1 mrg
679 1.1 mrg FYI: The portable parameter passing conventions are almost exactly like
680 1.1 mrg the standard parameter passing conventions on the RS6000. That's why
681 1.1.1.2 mrg you'll see lots of similar code in rs6000.h. */
682 1.1.1.2 mrg
683 1.1 mrg /* If defined, a C expression which determines whether, and in which
684 1.1 mrg direction, to pad out an argument with extra space. */
685 1.1 mrg #define FUNCTION_ARG_PADDING(MODE, TYPE) \
686 1.1 mrg pa_function_arg_padding ((MODE), (TYPE))
687 1.1 mrg
688 1.1 mrg /* Specify padding for the last element of a block move between registers
689 1.1 mrg and memory.
690 1.1 mrg
691 1.1 mrg The 64-bit runtime specifies that objects need to be left justified
692 1.1 mrg (i.e., the normal justification for a big endian target). The 32-bit
693 1.1 mrg runtime specifies right justification for objects smaller than 64 bits.
694 1.1.1.2 mrg We use a DImode register in the parallel for 5 to 7 byte structures
695 1.1 mrg so that there is only one element. This allows the object to be
696 1.1 mrg correctly padded. */
697 1.1 mrg #define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \
698 1.1 mrg pa_function_arg_padding ((MODE), (TYPE))
699 1.1 mrg
700 1.1 mrg
701 1.1 mrg /* On HPPA, we emit profiling code as rtl via PROFILE_HOOK rather than
703 1.1 mrg as assembly via FUNCTION_PROFILER. Just output a local label.
704 1.1 mrg We can't use the function label because the GAS SOM target can't
705 1.1 mrg handle the difference of a global symbol and a local symbol. */
706 1.1 mrg
707 1.1 mrg #ifndef FUNC_BEGIN_PROLOG_LABEL
708 1.1 mrg #define FUNC_BEGIN_PROLOG_LABEL "LFBP"
709 1.1 mrg #endif
710 1.1 mrg
711 1.1 mrg #define FUNCTION_PROFILER(FILE, LABEL) \
712 1.1 mrg (*targetm.asm_out.internal_label) (FILE, FUNC_BEGIN_PROLOG_LABEL, LABEL)
713 1.1 mrg
714 1.1 mrg #define PROFILE_HOOK(label_no) hppa_profile_hook (label_no)
715 1.1 mrg void hppa_profile_hook (int label_no);
716 1.1 mrg
717 1.1 mrg /* The profile counter if emitted must come before the prologue. */
718 1.1 mrg #define PROFILE_BEFORE_PROLOGUE 1
719 1.1 mrg
720 1.1 mrg /* We never want final.c to emit profile counters. When profile
721 1.1 mrg counters are required, we have to defer emitting them to the end
722 1.1 mrg of the current file. */
723 1.1 mrg #define NO_PROFILE_COUNTERS 1
724 1.1 mrg
725 1.1 mrg /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
726 1.1 mrg the stack pointer does not matter. The value is tested only in
727 1.1 mrg functions that have frame pointers.
728 1.1 mrg No definition is equivalent to always zero. */
729 1.1 mrg
730 1.1 mrg extern int may_call_alloca;
731 1.1 mrg
732 1.1 mrg #define EXIT_IGNORE_STACK \
733 1.1 mrg (get_frame_size () != 0 \
734 1.1 mrg || cfun->calls_alloca || crtl->outgoing_args_size)
735 1.1 mrg
736 1.1 mrg /* Length in units of the trampoline for entering a nested function. */
737 1.1 mrg
738 1.1 mrg #define TRAMPOLINE_SIZE (TARGET_64BIT ? 72 : 52)
739 1.1 mrg
740 1.1 mrg /* Alignment required by the trampoline. */
741 1.1 mrg
742 1.1 mrg #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD
743 1.1 mrg
744 1.1 mrg /* Minimum length of a cache line. A length of 16 will work on all
745 1.1 mrg PA-RISC processors. All PA 1.1 processors have a cache line of
746 1.1 mrg 32 bytes. Most but not all PA 2.0 processors have a cache line
747 1.1 mrg of 64 bytes. As cache flushes are expensive and we don't support
748 1.1 mrg PA 1.0, we use a minimum length of 32. */
749 1.1 mrg
750 1.1 mrg #define MIN_CACHELINE_SIZE 32
751 1.1 mrg
752 1.1 mrg
753 1.1 mrg /* Addressing modes, and classification of registers for them.
755 1.1 mrg
756 1.1 mrg Using autoincrement addressing modes on PA8000 class machines is
757 1.1 mrg not profitable. */
758 1.1 mrg
759 1.1 mrg #define HAVE_POST_INCREMENT (pa_cpu < PROCESSOR_8000)
760 1.1 mrg #define HAVE_POST_DECREMENT (pa_cpu < PROCESSOR_8000)
761 1.1 mrg
762 1.1 mrg #define HAVE_PRE_DECREMENT (pa_cpu < PROCESSOR_8000)
763 1.1 mrg #define HAVE_PRE_INCREMENT (pa_cpu < PROCESSOR_8000)
764 1.1 mrg
765 1.1.1.2 mrg /* Macros to check register numbers against specific register classes. */
766 1.1.1.2 mrg
767 1.1 mrg /* The following macros assume that X is a hard or pseudo reg number.
768 1.1 mrg They give nonzero only if X is a hard reg of the suitable class
769 1.1 mrg or a pseudo reg currently allocated to a suitable hard reg.
770 1.1.1.2 mrg Since they use reg_renumber, they are safe only once reg_renumber
771 1.1.1.2 mrg has been allocated, which happens in reginfo.c during register
772 1.1 mrg allocation. */
773 1.1 mrg
774 1.1 mrg #define REGNO_OK_FOR_INDEX_P(X) \
775 1.1 mrg ((X) && ((X) < 32 \
776 1.1.1.2 mrg || ((X) == FRAME_POINTER_REGNUM) \
777 1.1.1.2 mrg || ((X) >= FIRST_PSEUDO_REGISTER \
778 1.1 mrg && reg_renumber \
779 1.1 mrg && (unsigned) reg_renumber[X] < 32)))
780 1.1 mrg #define REGNO_OK_FOR_BASE_P(X) \
781 1.1 mrg ((X) && ((X) < 32 \
782 1.1 mrg || ((X) == FRAME_POINTER_REGNUM) \
783 1.1 mrg || ((X) >= FIRST_PSEUDO_REGISTER \
784 1.1 mrg && reg_renumber \
785 1.1 mrg && (unsigned) reg_renumber[X] < 32)))
786 1.1 mrg #define REGNO_OK_FOR_FP_P(X) \
787 1.1 mrg (FP_REGNO_P (X) \
788 1.1 mrg || (X >= FIRST_PSEUDO_REGISTER \
789 1.1 mrg && reg_renumber \
790 1.1 mrg && FP_REGNO_P (reg_renumber[X])))
791 1.1 mrg
792 1.1 mrg /* Now macros that check whether X is a register and also,
793 1.1 mrg strictly, whether it is in a specified class.
794 1.1 mrg
795 1.1 mrg These macros are specific to the HP-PA, and may be used only
796 1.1 mrg in code for printing assembler insns and in conditions for
797 1.1 mrg define_optimization. */
798 1.1 mrg
799 1.1 mrg /* 1 if X is an fp register. */
800 1.1 mrg
801 1.1.1.2 mrg #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
802 1.1.1.2 mrg
803 1.1.1.2 mrg /* Maximum number of registers that can appear in a valid memory address. */
805 1.1 mrg
806 1.1 mrg #define MAX_REGS_PER_ADDRESS 2
807 1.1 mrg
808 1.1 mrg /* TLS symbolic reference. */
809 1.1 mrg #define PA_SYMBOL_REF_TLS_P(X) \
810 1.1 mrg (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (X) != 0)
811 1.1 mrg
812 1.1 mrg /* Recognize any constant value that is a valid address except
813 1.1.1.2 mrg for symbolic addresses. We get better CSE by rejecting them
814 1.1.1.3 mrg here and allowing hppa_legitimize_address to break them up. We
815 1.1 mrg use most of the constants accepted by CONSTANT_P, except CONST_DOUBLE. */
816 1.1.1.2 mrg
817 1.1.1.2 mrg #define CONSTANT_ADDRESS_P(X) \
818 1.1 mrg ((GET_CODE (X) == LABEL_REF \
819 1.1 mrg || (GET_CODE (X) == SYMBOL_REF && !SYMBOL_REF_TLS_MODEL (X)) \
820 1.1 mrg || GET_CODE (X) == CONST_INT \
821 1.1 mrg || (GET_CODE (X) == CONST && !tls_referenced_p (X)) \
822 1.1 mrg || GET_CODE (X) == HIGH) \
823 1.1 mrg && (reload_in_progress || reload_completed \
824 1.1 mrg || ! pa_symbolic_expression_p (X)))
825 1.1 mrg
826 1.1 mrg /* A C expression that is nonzero if we are using the new HP assembler. */
827 1.1 mrg
828 1.1 mrg #ifndef NEW_HP_ASSEMBLER
829 1.1 mrg #define NEW_HP_ASSEMBLER 0
830 1.1 mrg #endif
831 1.1.1.5 mrg
832 1.1.1.5 mrg /* The macros below define the immediate range for CONST_INTS on
833 1.1 mrg the 64-bit port. Constants in this range can be loaded in three
834 1.1 mrg instructions using a ldil/ldo/depdi sequence. Constants outside
835 1.1 mrg this range are forced to the constant pool prior to reload. */
836 1.1 mrg
837 1.1 mrg #define MAX_LEGIT_64BIT_CONST_INT ((HOST_WIDE_INT) 32 << 31)
838 1.1 mrg #define MIN_LEGIT_64BIT_CONST_INT \
839 1.1 mrg ((HOST_WIDE_INT)((unsigned HOST_WIDE_INT) -32 << 31))
840 1.1 mrg #define LEGITIMATE_64BIT_CONST_INT_P(X) \
841 1.1 mrg ((X) >= MIN_LEGIT_64BIT_CONST_INT && (X) < MAX_LEGIT_64BIT_CONST_INT)
842 1.1 mrg
843 1.1 mrg /* Target flags set on a symbol_ref. */
844 1.1 mrg
845 1.1 mrg /* Set by ASM_OUTPUT_SYMBOL_REF when a symbol_ref is output. */
846 1.1 mrg #define SYMBOL_FLAG_REFERENCED (1 << SYMBOL_FLAG_MACH_DEP_SHIFT)
847 1.1 mrg #define SYMBOL_REF_REFERENCED_P(RTX) \
848 1.1 mrg ((SYMBOL_REF_FLAGS (RTX) & SYMBOL_FLAG_REFERENCED) != 0)
849 1.1 mrg
850 1.1 mrg /* Defines for constraints.md. */
851 1.1 mrg
852 1.1 mrg /* Return 1 iff OP is a scaled or unscaled index address. */
853 1.1 mrg #define IS_INDEX_ADDR_P(OP) \
854 1.1 mrg (GET_CODE (OP) == PLUS \
855 1.1 mrg && GET_MODE (OP) == Pmode \
856 1.1 mrg && (GET_CODE (XEXP (OP, 0)) == MULT \
857 1.1 mrg || GET_CODE (XEXP (OP, 1)) == MULT \
858 1.1 mrg || (REG_P (XEXP (OP, 0)) \
859 1.1 mrg && REG_P (XEXP (OP, 1)))))
860 1.1 mrg
861 1.1 mrg /* Return 1 iff OP is a LO_SUM DLT address. */
862 1.1 mrg #define IS_LO_SUM_DLT_ADDR_P(OP) \
863 1.1 mrg (GET_CODE (OP) == LO_SUM \
864 1.1 mrg && GET_MODE (OP) == Pmode \
865 1.1.1.2 mrg && REG_P (XEXP (OP, 0)) \
866 1.1.1.2 mrg && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
867 1.1.1.2 mrg && GET_CODE (XEXP (OP, 1)) == UNSPEC)
868 1.1 mrg
869 1.1 mrg /* Nonzero if 14-bit offsets can be used for all loads and stores.
870 1.1 mrg This is not possible when generating PA 1.x code as floating point
871 1.1 mrg loads and stores only support 5-bit offsets. Note that we do not
872 1.1 mrg forbid the use of 14-bit offsets for integer modes. Instead, we
873 1.1 mrg use secondary reloads to fix REG+D memory addresses for integer
874 1.1 mrg mode floating-point loads and stores.
875 1.1 mrg
876 1.1 mrg FIXME: the ELF32 linker clobbers the LSB of the FP register number
877 1.1 mrg in PA 2.0 floating-point insns with long displacements. This is
878 1.1 mrg because R_PARISC_DPREL14WR and other relocations like it are not
879 1.1 mrg yet supported by GNU ld. For now, we reject long displacements
880 1.1 mrg on this target. */
881 1.1 mrg
882 1.1 mrg #define INT14_OK_STRICT \
883 1.1 mrg (TARGET_SOFT_FLOAT \
884 1.1 mrg || TARGET_DISABLE_FPREGS \
885 1.1 mrg || (TARGET_PA_20 && !TARGET_ELF32))
886 1.1 mrg
887 1.1 mrg /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
888 1.1 mrg and check its validity for a certain class.
889 1.1 mrg We have two alternate definitions for each of them.
890 1.1 mrg The usual definition accepts all pseudo regs; the other rejects
891 1.1 mrg them unless they have been allocated suitable hard regs.
892 1.1 mrg
893 1.1 mrg Most source files want to accept pseudo regs in the hope that
894 1.1 mrg they will get allocated to the class that the insn wants them to be in.
895 1.1.1.2 mrg Source files for reload pass need to be strict.
896 1.1.1.2 mrg After reload, it makes no difference, since pseudo regs have
897 1.1.1.2 mrg been eliminated by then. */
898 1.1 mrg
899 1.1 mrg /* Nonzero if X is a hard reg that can be used as an index
900 1.1 mrg or if it is a pseudo reg. */
901 1.1 mrg #define REG_OK_FOR_INDEX_P(X) \
902 1.1.1.2 mrg (REGNO (X) && (REGNO (X) < 32 \
903 1.1.1.2 mrg || REGNO (X) == FRAME_POINTER_REGNUM \
904 1.1.1.2 mrg || REGNO (X) >= FIRST_PSEUDO_REGISTER))
905 1.1 mrg
906 1.1 mrg /* Nonzero if X is a hard reg that can be used as a base reg
907 1.1.1.2 mrg or if it is a pseudo reg. */
908 1.1 mrg #define REG_OK_FOR_BASE_P(X) \
909 1.1 mrg (REGNO (X) && (REGNO (X) < 32 \
910 1.1.1.2 mrg || REGNO (X) == FRAME_POINTER_REGNUM \
911 1.1 mrg || REGNO (X) >= FIRST_PSEUDO_REGISTER))
912 1.1 mrg
913 1.1 mrg /* Nonzero if X is a hard reg that can be used as an index. */
914 1.1 mrg #define STRICT_REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
915 1.1 mrg
916 1.1 mrg /* Nonzero if X is a hard reg that can be used as a base reg. */
917 1.1 mrg #define STRICT_REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
918 1.1.1.2 mrg
919 1.1.1.2 mrg #define VAL_5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x10 < 0x20)
920 1.1.1.2 mrg #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X))
921 1.1 mrg
922 1.1 mrg #define VAL_U5_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x20)
923 1.1 mrg #define INT_U5_BITS(X) VAL_U5_BITS_P (INTVAL (X))
924 1.1 mrg
925 1.1 mrg #define VAL_U6_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) < 0x40)
926 1.1 mrg #define INT_U6_BITS(X) VAL_U6_BITS_P (INTVAL (X))
927 1.1 mrg
928 1.1 mrg #define VAL_11_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x400 < 0x800)
929 1.1 mrg #define INT_11_BITS(X) VAL_11_BITS_P (INTVAL (X))
930 1.1 mrg
931 1.1 mrg #define VAL_14_BITS_P(X) ((unsigned HOST_WIDE_INT)(X) + 0x2000 < 0x4000)
932 1.1 mrg #define INT_14_BITS(X) VAL_14_BITS_P (INTVAL (X))
933 1.1 mrg
934 1.1 mrg #if HOST_BITS_PER_WIDE_INT > 32
935 1.1 mrg #define VAL_32_BITS_P(X) \
936 1.1 mrg ((unsigned HOST_WIDE_INT)(X) + ((unsigned HOST_WIDE_INT) 1 << 31) \
937 1.1 mrg < (unsigned HOST_WIDE_INT) 2 << 31)
938 1.1 mrg #else
939 1.1 mrg #define VAL_32_BITS_P(X) 1
940 1.1 mrg #endif
941 1.1 mrg #define INT_32_BITS(X) VAL_32_BITS_P (INTVAL (X))
942 1.1 mrg
943 1.1 mrg /* These are the modes that we allow for scaled indexing. */
944 1.1 mrg #define MODE_OK_FOR_SCALED_INDEXING_P(MODE) \
945 1.1 mrg ((TARGET_64BIT && (MODE) == DImode) \
946 1.1 mrg || (MODE) == SImode \
947 1.1 mrg || (MODE) == HImode \
948 1.1 mrg || (MODE) == SFmode \
949 1.1 mrg || (MODE) == DFmode)
950 1.1 mrg
951 1.1 mrg /* These are the modes that we allow for unscaled indexing. */
952 1.1 mrg #define MODE_OK_FOR_UNSCALED_INDEXING_P(MODE) \
953 1.1.1.2 mrg ((TARGET_64BIT && (MODE) == DImode) \
954 1.1.1.2 mrg || (MODE) == SImode \
955 1.1.1.2 mrg || (MODE) == HImode \
956 1.1.1.2 mrg || (MODE) == QImode \
957 1.1.1.2 mrg || (MODE) == SFmode \
958 1.1.1.2 mrg || (MODE) == DFmode)
959 1.1.1.2 mrg
960 1.1.1.2 mrg /* Try a machine-dependent way of reloading an illegitimate address
961 1.1.1.2 mrg operand. If we find one, push the reload and jump to WIN. This
962 1.1.1.2 mrg macro is used in only one place: `find_reloads_address' in reload.c. */
963 1.1.1.2 mrg
964 1.1.1.2 mrg #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND_L, WIN) \
965 1.1 mrg do { \
966 1.1 mrg rtx new_ad = pa_legitimize_reload_address (AD, MODE, OPNUM, TYPE, IND_L); \
967 1.1 mrg if (new_ad) \
968 1.1 mrg { \
969 1.1 mrg AD = new_ad; \
970 1.1 mrg goto WIN; \
971 1.1 mrg } \
972 1.1 mrg } while (0)
973 1.1.1.3 mrg
974 1.1 mrg
975 1.1 mrg #define TARGET_ASM_SELECT_SECTION pa_select_section
977 1.1 mrg
978 1.1 mrg /* Return a nonzero value if DECL has a section attribute. */
979 1.1 mrg #define IN_NAMED_SECTION_P(DECL) \
980 1.1 mrg ((TREE_CODE (DECL) == FUNCTION_DECL || TREE_CODE (DECL) == VAR_DECL) \
981 1.1 mrg && DECL_SECTION_NAME (DECL) != NULL)
982 1.1 mrg
983 1.1 mrg /* Define this macro if references to a symbol must be treated
984 1.1 mrg differently depending on something about the variable or
985 1.1 mrg function named by the symbol (such as what section it is in).
986 1.1 mrg
987 1.1 mrg The macro definition, if any, is executed immediately after the
988 1.1 mrg rtl for DECL or other node is created.
989 1.1 mrg The value of the rtl will be a `mem' whose address is a
990 1.1 mrg `symbol_ref'.
991 1.1 mrg
992 1.1 mrg The usual thing for this macro to do is to a flag in the
993 1.1 mrg `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
994 1.1 mrg name string in the `symbol_ref' (if one bit is not enough
995 1.1 mrg information).
996 1.1.1.2 mrg
997 1.1 mrg On the HP-PA we use this to indicate if a symbol is in text or
998 1.1 mrg data space. Also, function labels need special treatment. */
999 1.1 mrg
1000 1.1 mrg #define TEXT_SPACE_P(DECL)\
1001 1.1 mrg (TREE_CODE (DECL) == FUNCTION_DECL \
1002 1.1 mrg || (TREE_CODE (DECL) == VAR_DECL \
1003 1.1.1.3 mrg && TREE_READONLY (DECL) && ! TREE_SIDE_EFFECTS (DECL) \
1004 1.1.1.3 mrg && (! DECL_INITIAL (DECL) || ! pa_reloc_needed (DECL_INITIAL (DECL))) \
1005 1.1.1.3 mrg && !flag_pic) \
1006 1.1 mrg || CONSTANT_CLASS_P (DECL))
1007 1.1 mrg
1008 1.1 mrg #define FUNCTION_NAME_P(NAME) (*(NAME) == '@')
1009 1.1 mrg
1010 1.1 mrg /* Specify the machine mode that this machine uses for the index in the
1011 1.1 mrg tablejump instruction. We use a 32-bit absolute address for non-pic code,
1012 1.1 mrg and a 32-bit offset for 32 and 64-bit pic code. */
1013 1.1 mrg #define CASE_VECTOR_MODE SImode
1014 1.1 mrg
1015 1.1 mrg /* Jump tables must be 32-bit aligned, no matter the size of the element. */
1016 1.1 mrg #define ADDR_VEC_ALIGN(ADDR_VEC) 2
1017 1.1 mrg
1018 1.1 mrg /* Define this as 1 if `char' should by default be signed; else as 0. */
1019 1.1 mrg #define DEFAULT_SIGNED_CHAR 1
1020 1.1 mrg
1021 1.1 mrg /* Max number of bytes we can move from memory to memory
1022 1.1 mrg in one reasonably fast instruction. */
1023 1.1 mrg #define MOVE_MAX 8
1024 1.1 mrg
1025 1.1 mrg /* Higher than the default as we prefer to use simple move insns
1026 1.1 mrg (better scheduling and delay slot filling) and because our
1027 1.1 mrg built-in block move is really a 2X unrolled loop.
1028 1.1 mrg
1029 1.1.1.5 mrg Believe it or not, this has to be big enough to allow for copying all
1030 1.1 mrg arguments passed in registers to avoid infinite recursion during argument
1031 1.1 mrg setup for a function call. Why? Consider how we copy the stack slots
1032 1.1 mrg reserved for parameters when they may be trashed by a call. */
1033 1.1 mrg #define MOVE_RATIO(speed) (TARGET_64BIT ? 8 : 4)
1034 1.1 mrg
1035 1.1 mrg /* Define if operations between registers always perform the operation
1036 1.1 mrg on the full register even if a narrower mode is specified. */
1037 1.1 mrg #define WORD_REGISTER_OPERATIONS 1
1038 1.1 mrg
1039 1.1 mrg /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1040 1.1 mrg will either zero-extend or sign-extend. The value of this macro should
1041 1.1 mrg be the code that says which one of the two operations is implicitly
1042 1.1 mrg done, UNKNOWN if none. */
1043 1.1 mrg #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1044 1.1 mrg
1045 1.1 mrg /* Nonzero if access to memory by bytes is slow and undesirable. */
1046 1.1 mrg #define SLOW_BYTE_ACCESS 1
1047 1.1 mrg
1048 1.1 mrg /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1049 1.1 mrg is done just by pretending it is already truncated. */
1050 1.1 mrg #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1051 1.1 mrg
1052 1.1 mrg /* Specify the machine mode that pointers have.
1053 1.1 mrg After generation of rtl, the compiler makes no further distinction
1054 1.1 mrg between pointers and any other objects of this machine mode. */
1055 1.1 mrg #define Pmode word_mode
1056 1.1 mrg
1057 1.1 mrg /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1058 1.1 mrg return the mode to be used for the comparison. For floating-point, CCFPmode
1059 1.1 mrg should be used. CC_NOOVmode should be used when the first operand is a
1060 1.1 mrg PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1061 1.1 mrg needed. */
1062 1.1 mrg #define SELECT_CC_MODE(OP,X,Y) \
1063 1.1 mrg (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode : CCmode) \
1064 1.1 mrg
1065 1.1 mrg /* A function address in a call instruction
1066 1.1.1.5 mrg is a byte address (for indexing purposes)
1067 1.1 mrg so give the MEM rtx a byte's mode. */
1068 1.1 mrg #define FUNCTION_MODE SImode
1069 1.1 mrg
1070 1.1 mrg /* Define this if addresses of constant functions
1071 1.1 mrg shouldn't be put through pseudo regs where they can be cse'd.
1072 1.1 mrg Desirable on machines where ordinary constants are expensive
1073 1.1 mrg but a CALL with constant address is cheap. */
1074 1.1 mrg #define NO_FUNCTION_CSE 1
1075 1.1 mrg
1076 1.1 mrg /* Define this to be nonzero if shift instructions ignore all but the low-order
1077 1.1.1.2 mrg few bits. */
1078 1.1.1.2 mrg #define SHIFT_COUNT_TRUNCATED 1
1079 1.1 mrg
1080 1.1 mrg /* Adjust the cost of branches. */
1081 1.1 mrg #define BRANCH_COST(speed_p, predictable_p) (pa_cpu == PROCESSOR_8000 ? 2 : 1)
1082 1.1 mrg
1083 1.1 mrg /* Handling the special cases is going to get too complicated for a macro,
1084 1.1 mrg just call `pa_adjust_insn_length' to do the real work. */
1085 1.1 mrg #define ADJUST_INSN_LENGTH(INSN, LENGTH) \
1086 1.1 mrg ((LENGTH) = pa_adjust_insn_length ((INSN), (LENGTH)))
1087 1.1 mrg
1088 1.1 mrg /* Millicode insns are actually function calls with some special
1089 1.1 mrg constraints on arguments and register usage.
1090 1.1 mrg
1091 1.1 mrg Millicode calls always expect their arguments in the integer argument
1092 1.1 mrg registers, and always return their result in %r29 (ret1). They
1093 1.1 mrg are expected to clobber their arguments, %r1, %r29, and the return
1094 1.1 mrg pointer which is %r31 on 32-bit and %r2 on 64-bit, and nothing else.
1095 1.1 mrg
1096 1.1 mrg This macro tells reorg that the references to arguments and
1097 1.1 mrg millicode calls do not appear to happen until after the millicode call.
1098 1.1 mrg This allows reorg to put insns which set the argument registers into the
1099 1.1 mrg delay slot of the millicode call -- thus they act more like traditional
1100 1.1 mrg CALL_INSNs.
1101 1.1.1.2 mrg
1102 1.1 mrg Note we cannot consider side effects of the insn to be delayed because
1103 1.1 mrg the branch and link insn will clobber the return pointer. If we happened
1104 1.1 mrg to use the return pointer in the delay slot of the call, then we lose.
1105 1.1 mrg
1106 1.1 mrg get_attr_type will try to recognize the given insn, so make sure to
1107 1.1 mrg filter out things it will not accept -- SEQUENCE, USE and CLOBBER insns
1108 1.1 mrg in particular. */
1109 1.1 mrg #define INSN_REFERENCES_ARE_DELAYED(X) (pa_insn_refs_are_delayed (X))
1110 1.1 mrg
1111 1.1 mrg
1112 1.1 mrg /* Control the assembler format that we output. */
1114 1.1 mrg
1115 1.1 mrg /* A C string constant describing how to begin a comment in the target
1116 1.1 mrg assembler language. The compiler assumes that the comment will end at
1117 1.1 mrg the end of the line. */
1118 1.1 mrg
1119 1.1 mrg #define ASM_COMMENT_START ";"
1120 1.1 mrg
1121 1.1 mrg /* Output to assembler file text saying following lines
1122 1.1 mrg may contain character constants, extra white space, comments, etc. */
1123 1.1 mrg
1124 1.1 mrg #define ASM_APP_ON ""
1125 1.1 mrg
1126 1.1 mrg /* Output to assembler file text saying following lines
1127 1.1 mrg no longer contain unusual constructs. */
1128 1.1 mrg
1129 1.1 mrg #define ASM_APP_OFF ""
1130 1.1 mrg
1131 1.1 mrg /* This is how to output the definition of a user-level label named NAME,
1132 1.1 mrg such as the label on a static function or variable NAME. */
1133 1.1 mrg
1134 1.1 mrg #define ASM_OUTPUT_LABEL(FILE,NAME) \
1135 1.1 mrg do { \
1136 1.1 mrg assemble_name ((FILE), (NAME)); \
1137 1.1 mrg if (TARGET_GAS) \
1138 1.1 mrg fputs (":\n", (FILE)); \
1139 1.1 mrg else \
1140 1.1 mrg fputc ('\n', (FILE)); \
1141 1.1 mrg } while (0)
1142 1.1 mrg
1143 1.1 mrg /* This is how to output a reference to a user-level label named NAME.
1144 1.1 mrg `assemble_name' uses this. */
1145 1.1 mrg
1146 1.1 mrg #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1147 1.1 mrg do { \
1148 1.1 mrg const char *xname = (NAME); \
1149 1.1 mrg if (FUNCTION_NAME_P (NAME)) \
1150 1.1 mrg xname += 1; \
1151 1.1 mrg if (xname[0] == '*') \
1152 1.1 mrg xname += 1; \
1153 1.1 mrg else \
1154 1.1 mrg fputs (user_label_prefix, FILE); \
1155 1.1 mrg fputs (xname, FILE); \
1156 1.1 mrg } while (0)
1157 1.1 mrg
1158 1.1 mrg /* This how we output the symbol_ref X. */
1159 1.1 mrg
1160 1.1 mrg #define ASM_OUTPUT_SYMBOL_REF(FILE,X) \
1161 1.1 mrg do { \
1162 1.1.1.6 mrg SYMBOL_REF_FLAGS (X) |= SYMBOL_FLAG_REFERENCED; \
1163 1.1.1.6 mrg assemble_name (FILE, XSTR (X, 0)); \
1164 1.1.1.6 mrg } while (0)
1165 1.1.1.6 mrg
1166 1.1.1.6 mrg /* This is how to store into the string LABEL
1167 1.1.1.6 mrg the symbol_ref name of an internal numbered label where
1168 1.1.1.6 mrg PREFIX is the class of label and NUM is the number within the class.
1169 1.1.1.6 mrg This is suitable for output with `assemble_name'. */
1170 1.1.1.6 mrg
1171 1.1.1.6 mrg #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \
1172 1.1.1.6 mrg do \
1173 1.1.1.6 mrg { \
1174 1.1 mrg char *__p; \
1175 1.1 mrg (LABEL)[0] = '*'; \
1176 1.1 mrg (LABEL)[1] = (PREFIX)[0]; \
1177 1.1 mrg (LABEL)[2] = '$'; \
1178 1.1 mrg __p = stpcpy (&(LABEL)[3], &(PREFIX)[1]); \
1179 1.1 mrg sprint_ul (__p, (unsigned long) (NUM)); \
1180 1.1 mrg } \
1181 1.1 mrg while (0)
1182 1.1 mrg
1183 1.1 mrg
1184 1.1 mrg /* Output the definition of a compiler-generated label named NAME. */
1185 1.1 mrg
1186 1.1 mrg #define ASM_OUTPUT_INTERNAL_LABEL(FILE,NAME) \
1187 1.1 mrg do { \
1188 1.1 mrg assemble_name_raw ((FILE), (NAME)); \
1189 1.1.1.2 mrg if (TARGET_GAS) \
1190 1.1 mrg fputs (":\n", (FILE)); \
1191 1.1.1.6 mrg else \
1192 1.1.1.6 mrg fputc ('\n', (FILE)); \
1193 1.1.1.6 mrg } while (0)
1194 1.1.1.6 mrg
1195 1.1.1.6 mrg #define TARGET_ASM_GLOBALIZE_LABEL pa_globalize_label
1196 1.1.1.6 mrg
1197 1.1.1.3 mrg #define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
1198 1.1.1.6 mrg pa_output_ascii ((FILE), (P), (SIZE))
1199 1.1.1.3 mrg
1200 1.1.1.6 mrg /* Jump tables are always placed in the text section. We have to do
1201 1.1.1.3 mrg this for the HP-UX SOM target as we can't switch sections in the
1202 1.1 mrg middle of a function.
1203 1.1 mrg
1204 1.1.1.6 mrg On ELF targets, it is possible to put them in the readonly-data section.
1205 1.1.1.6 mrg This would get the table out of .text and reduce branch lengths.
1206 1.1.1.6 mrg
1207 1.1.1.6 mrg A downside is that an additional insn (addil) is needed to access
1208 1.1 mrg the table when generating PIC code. The address difference table
1209 1.1 mrg also has to use 32-bit pc-relative relocations.
1210 1.1 mrg
1211 1.1 mrg The table entries need to look like "$L1+(.+8-$L0)-$PIC_pcrel$0"
1212 1.1 mrg when using ELF GAS. A simple difference can be used when using
1213 1.1 mrg the HP assembler.
1214 1.1.1.6 mrg
1215 1.1 mrg The final downside is GDB complains about the nesting of the label
1216 1.1 mrg for the table. */
1217 1.1 mrg
1218 1.1 mrg #define JUMP_TABLES_IN_TEXT_SECTION 1
1219 1.1 mrg
1220 1.1 mrg /* This is how to output an element of a case-vector that is absolute. */
1221 1.1.1.6 mrg
1222 1.1.1.3 mrg #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1223 1.1.1.3 mrg fprintf (FILE, "\t.word L$%d\n", VALUE)
1224 1.1.1.3 mrg
1225 1.1.1.3 mrg /* This is how to output an element of a case-vector that is relative.
1226 1.1.1.3 mrg Since we always place jump tables in the text section, the difference
1227 1.1.1.3 mrg is absolute and requires no relocation. */
1228 1.1.1.3 mrg
1229 1.1.1.3 mrg #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \
1230 1.1.1.3 mrg fprintf (FILE, "\t.word L$%d-L$%d\n", VALUE, REL)
1231 1.1.1.3 mrg
1232 1.1 mrg /* This is how to output an absolute case-vector. */
1233 1.1 mrg
1234 1.1 mrg #define ASM_OUTPUT_ADDR_VEC(LAB,BODY) \
1235 1.1 mrg pa_output_addr_vec ((LAB),(BODY))
1236 1.1 mrg
1237 1.1 mrg /* This is how to output a relative case-vector. */
1238 1.1 mrg
1239 1.1 mrg #define ASM_OUTPUT_ADDR_DIFF_VEC(LAB,BODY) \
1240 1.1.1.5 mrg pa_output_addr_diff_vec ((LAB),(BODY))
1241 1.1 mrg
1242 1.1 mrg /* This is how to output an assembler line that says to advance the
1243 1.1 mrg location counter to a multiple of 2**LOG bytes. */
1244 1.1 mrg
1245 1.1 mrg #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1246 1.1 mrg fprintf (FILE, "\t.align %d\n", (1<<(LOG)))
1247 1.1 mrg
1248 1.1 mrg #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1249 1.1 mrg fprintf (FILE, "\t.blockz " HOST_WIDE_INT_PRINT_UNSIGNED"\n", \
1250 1.1 mrg (unsigned HOST_WIDE_INT)(SIZE))
1251 1.1 mrg
1252 1.1 mrg /* This says how to output an assembler line to define an uninitialized
1253 1.1 mrg global variable with size SIZE (in bytes) and alignment ALIGN (in bits).
1254 1.1 mrg This macro exists to properly support languages like C++ which do not
1255 1.1 mrg have common data. */
1256 1.1 mrg
1257 1.1 mrg #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \
1258 1.1 mrg pa_asm_output_aligned_bss (FILE, NAME, SIZE, ALIGN)
1259 1.1 mrg
1260 1.1 mrg /* This says how to output an assembler line to define a global common symbol
1261 1.1 mrg with size SIZE (in bytes) and alignment ALIGN (in bits). */
1262 1.1 mrg
1263 1.1 mrg #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \
1264 1.1 mrg pa_asm_output_aligned_common (FILE, NAME, SIZE, ALIGN)
1265 1.1 mrg
1266 1.1 mrg /* This says how to output an assembler line to define a local common symbol
1267 1.1 mrg with size SIZE (in bytes) and alignment ALIGN (in bits). This macro
1268 1.1 mrg controls how the assembler definitions of uninitialized static variables
1269 1.1 mrg are output. */
1270 1.1 mrg
1271 1.1 mrg #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1272 1.1 mrg pa_asm_output_aligned_local (FILE, NAME, SIZE, ALIGN)
1273 1.1 mrg
1274 1.1 mrg /* All HP assemblers use "!" to separate logical lines. */
1275 1.1 mrg #define IS_ASM_LOGICAL_LINE_SEPARATOR(C, STR) ((C) == '!')
1276 1.1 mrg
1277 1.1 mrg /* Print operand X (an rtx) in assembler syntax to file FILE.
1278 1.1 mrg CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1279 1.1 mrg For `%' followed by punctuation, CODE is the punctuation and X is null.
1280 1.1 mrg
1281 1.1 mrg On the HP-PA, the CODE can be `r', meaning this is a register-only operand
1282 1.1.1.2 mrg and an immediate zero should be represented as `r0'.
1283 1.1 mrg
1284 1.1 mrg Several % codes are defined:
1285 1.1 mrg O an operation
1286 1.1 mrg C compare conditions
1287 1.1 mrg N extract conditions
1288 1.1 mrg M modifier to handle preincrement addressing for memory refs.
1289 1.1 mrg F modifier to handle preincrement addressing for fp memory refs */
1290 1.1 mrg
1291 1.1 mrg #define PRINT_OPERAND(FILE, X, CODE) pa_print_operand (FILE, X, CODE)
1292 1.1 mrg
1293 1.1 mrg
1294 1.1 mrg /* Print a memory address as an operand to reference that memory location. */
1296 1.1 mrg
1297 1.1 mrg #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1298 1.1 mrg { rtx addr = ADDR; \
1299 1.1 mrg switch (GET_CODE (addr)) \
1300 1.1 mrg { \
1301 1.1 mrg case REG: \
1302 1.1 mrg fprintf (FILE, "0(%s)", reg_names [REGNO (addr)]); \
1303 1.1 mrg break; \
1304 1.1 mrg case PLUS: \
1305 1.1 mrg gcc_assert (GET_CODE (XEXP (addr, 1)) == CONST_INT); \
1306 1.1.1.2 mrg fprintf (FILE, "%d(%s)", (int)INTVAL (XEXP (addr, 1)), \
1307 1.1 mrg reg_names [REGNO (XEXP (addr, 0))]); \
1308 1.1 mrg break; \
1309 1.1 mrg case LO_SUM: \
1310 1.1 mrg if (!symbolic_operand (XEXP (addr, 1), VOIDmode)) \
1311 1.1 mrg fputs ("R'", FILE); \
1312 1.1 mrg else if (flag_pic == 0) \
1313 1.1 mrg fputs ("RR'", FILE); \
1314 1.1 mrg else \
1315 1.1 mrg fputs ("RT'", FILE); \
1316 1.1 mrg pa_output_global_address (FILE, XEXP (addr, 1), 0); \
1317 1.1 mrg fputs ("(", FILE); \
1318 1.1 mrg output_operand (XEXP (addr, 0), 0); \
1319 1.1 mrg fputs (")", FILE); \
1320 1.1 mrg break; \
1321 1.1 mrg case CONST_INT: \
1322 1.1.1.2 mrg fprintf (FILE, HOST_WIDE_INT_PRINT_DEC "(%%r0)", INTVAL (addr)); \
1323 1.1 mrg break; \
1324 1.1 mrg default: \
1325 1.1 mrg output_addr_const (FILE, addr); \
1326 1.1 mrg }}
1327 1.1 mrg
1328 1.1 mrg
1329 1.1 mrg /* Find the return address associated with the frame given by
1331 1.1 mrg FRAMEADDR. */
1332 1.1 mrg #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \
1333 1.1 mrg (pa_return_addr_rtx (COUNT, FRAMEADDR))
1334 1.1 mrg
1335 1.1 mrg /* Used to mask out junk bits from the return address, such as
1336 1.1 mrg processor state, interrupt status, condition codes and the like. */
1337 1.1 mrg #define MASK_RETURN_ADDR \
1338 1.1 mrg /* The privilege level is in the two low order bits, mask em out \
1339 1.1.1.2 mrg of the return address. */ \
1340 1.1.1.2 mrg (GEN_INT (-4))
1341 1.1.1.2 mrg
1342 1.1.1.2 mrg /* We need a libcall to canonicalize function pointers on TARGET_ELF32. */
1343 1.1.1.2 mrg #define CANONICALIZE_FUNCPTR_FOR_COMPARE_LIBCALL \
1344 1.1.1.2 mrg "__canonicalize_funcptr_for_compare"
1345 1.1.1.2 mrg
1346 1.1.1.2 mrg #ifdef HAVE_AS_TLS
1347 1.1.1.2 mrg #undef TARGET_HAVE_TLS
1348 #define TARGET_HAVE_TLS true
1349 #endif
1350
1351 /* The maximum offset in bytes for a PA 1.X pc-relative call to the
1352 head of the preceding stub table. The selected offsets have been
1353 chosen so that approximately one call stub is allocated for every
1354 86.7 instructions. A long branch stub is two instructions when
1355 not generating PIC code. For HP-UX and ELF targets, PIC stubs are
1356 seven and four instructions, respectively. */
1357 #define MAX_PCREL17F_OFFSET \
1358 (flag_pic ? (TARGET_HPUX ? 198164 : 221312) : 240000)
1359