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constraints.md revision 1.1
      1  1.1  mrg ;;  Machine Description for Renesas RL78 processors
      2  1.1  mrg ;;  Copyright (C) 2011-2013 Free Software Foundation, Inc.
      3  1.1  mrg ;;  Contributed by Red Hat.
      4  1.1  mrg 
      5  1.1  mrg ;; This file is part of GCC.
      6  1.1  mrg 
      7  1.1  mrg ;; GCC is free software; you can redistribute it and/or modify
      8  1.1  mrg ;; it under the terms of the GNU General Public License as published by
      9  1.1  mrg ;; the Free Software Foundation; either version 3, or (at your option)
     10  1.1  mrg ;; any later version.
     11  1.1  mrg 
     12  1.1  mrg ;; GCC is distributed in the hope that it will be useful,
     13  1.1  mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
     14  1.1  mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15  1.1  mrg ;; GNU General Public License for more details.
     16  1.1  mrg 
     17  1.1  mrg ;; You should have received a copy of the GNU General Public License
     18  1.1  mrg ;; along with GCC; see the file COPYING3.  If not see
     19  1.1  mrg ;; <http://www.gnu.org/licenses/>.
     20  1.1  mrg 
     22  1.1  mrg ; Constraints in use:
     23  1.1  mrg 
     24  1.1  mrg ; core:
     25  1.1  mrg ; V X g i m n o p r s < >
     26  1.1  mrg ; 0..9
     27  1.1  mrg ; I..Q - integers
     28  1.1  mrg ;   Int8 = 0..255
     29  1.1  mrg ;   Int3 = 1..7
     30  1.1  mrg ;   J = -255..0
     31  1.1  mrg ;   K = 1
     32  1.1  mrg ;   L = -1
     33  1.1  mrg ;   M = 0
     34  1.1  mrg ;   N = 2
     35  1.1  mrg ;   O = -2
     36  1.1  mrg ;   P = 1..15
     37  1.1  mrg 
     38  1.1  mrg ; E..H - float constants
     39  1.1  mrg 
     40  1.1  mrg ; RL78-specific
     41  1.1  mrg ; a x b c d e h l w - 8-bit regs
     42  1.1  mrg ; A B D T S - 16-bit regs
     43  1.1  mrg ; R = all regular registers (A-L)
     44  1.1  mrg ; Y - any valid memory
     45  1.1  mrg ; Wxx - various memory addressing modes
     46  1.1  mrg ; Qxx - conditionals
     47  1.1  mrg ; v = virtual registers
     48  1.1  mrg ; Zxx = specific virtual registers
     49  1.1  mrg 
     50  1.1  mrg (define_constraint "Int8"
     51  1.1  mrg   "Integer constant in the range 0 @dots{} 255."
     52  1.1  mrg   (and (match_code "const_int")
     53  1.1  mrg        (match_test "IN_RANGE (ival, 0, 255)")))
     54  1.1  mrg 
     55  1.1  mrg (define_constraint "Int3"
     56  1.1  mrg   "Integer constant in the range 1 @dots{} 7."
     57  1.1  mrg   (and (match_code "const_int")
     58  1.1  mrg        (match_test "IN_RANGE (ival, 1, 7)")))
     59  1.1  mrg 
     60  1.1  mrg (define_constraint "J"
     61  1.1  mrg   "Integer constant in the range -255 @dots{} 0"
     62  1.1  mrg   (and (match_code "const_int")
     63  1.1  mrg        (match_test "IN_RANGE (ival, -255, 0)")))
     64  1.1  mrg 
     65  1.1  mrg (define_constraint "K"
     66  1.1  mrg   "Integer constant 1."
     67  1.1  mrg   (and (match_code "const_int")
     68  1.1  mrg        (match_test "IN_RANGE (ival, 1, 1)")))
     69  1.1  mrg 
     70  1.1  mrg (define_constraint "L"
     71  1.1  mrg   "Integer constant -1."
     72  1.1  mrg   (and (match_code "const_int")
     73  1.1  mrg        (match_test "IN_RANGE (ival, -1, -1)")))
     74  1.1  mrg 
     75  1.1  mrg (define_constraint "M"
     76  1.1  mrg   "Integer constant 0."
     77  1.1  mrg   (and (match_code "const_int")
     78  1.1  mrg        (match_test "IN_RANGE (ival, 0, 0)")))
     79  1.1  mrg 
     80  1.1  mrg (define_constraint "N"
     81  1.1  mrg   "Integer constant 2."
     82  1.1  mrg   (and (match_code "const_int")
     83  1.1  mrg        (match_test "IN_RANGE (ival, 2, 2)")))
     84  1.1  mrg 
     85  1.1  mrg (define_constraint "O"
     86  1.1  mrg   "Integer constant -2."
     87  1.1  mrg   (and (match_code "const_int")
     88  1.1  mrg        (match_test "IN_RANGE (ival, -2, -2)")))
     89  1.1  mrg 
     90  1.1  mrg (define_constraint "P"
     91  1.1  mrg   "Integer constant 1..15"
     92  1.1  mrg   (and (match_code "const_int")
     93  1.1  mrg        (match_test "IN_RANGE (ival, 1, 15)")))
     94  1.1  mrg 
     95  1.1  mrg (define_register_constraint "R" "QI_REGS"
     96  1.1  mrg  "@code{A} through @code{L} registers.")
     97  1.1  mrg 
     98  1.1  mrg (define_register_constraint "a" "AREG"
     99  1.1  mrg  "The @code{A} register.")
    100  1.1  mrg 
    101  1.1  mrg (define_register_constraint "x" "XREG"
    102  1.1  mrg  "The @code{X} register.")
    103  1.1  mrg 
    104  1.1  mrg (define_register_constraint "b" "BREG"
    105  1.1  mrg  "The @code{B} register.")
    106  1.1  mrg 
    107  1.1  mrg (define_register_constraint "c" "CREG"
    108  1.1  mrg  "The @code{C} register.")
    109  1.1  mrg 
    110  1.1  mrg (define_register_constraint "d" "DREG"
    111  1.1  mrg  "The @code{D} register.")
    112  1.1  mrg 
    113  1.1  mrg (define_register_constraint "e" "EREG"
    114  1.1  mrg  "The @code{E} register.")
    115  1.1  mrg 
    116  1.1  mrg (define_register_constraint "h" "HREG"
    117  1.1  mrg  "The @code{H} register.")
    118  1.1  mrg 
    119  1.1  mrg (define_register_constraint "l" "LREG"
    120  1.1  mrg  "The @code{L} register.")
    121  1.1  mrg 
    122  1.1  mrg (define_register_constraint "w" "PSWREG"
    123  1.1  mrg  "The @code{PSW} register.")
    124  1.1  mrg 
    125  1.1  mrg (define_register_constraint "A" "AXREG"
    126  1.1  mrg  "The @code{AX} register.")
    127  1.1  mrg 
    128  1.1  mrg (define_register_constraint "B" "BCREG"
    129  1.1  mrg  "The @code{BC} register.")
    130  1.1  mrg 
    131  1.1  mrg (define_register_constraint "D" "DEREG"
    132  1.1  mrg  "The @code{DE} register.")
    133  1.1  mrg 
    134  1.1  mrg ; because H + L = T, assuming A=1.
    135  1.1  mrg (define_register_constraint "T" "HLREG"
    136  1.1  mrg  "The @code{HL} register.")
    137  1.1  mrg 
    138  1.1  mrg (define_register_constraint "S" "SPREG"
    139  1.1  mrg  "The @code{SP} register.")
    140  1.1  mrg 
    141  1.1  mrg (define_register_constraint "v" "V_REGS"
    142  1.1  mrg  "The virtual registers.")
    143  1.1  mrg 
    144  1.1  mrg (define_register_constraint "Z08W" "R8W_REGS"
    145  1.1  mrg  "The R8 register, HImode.")
    146  1.1  mrg 
    147  1.1  mrg (define_register_constraint "Z10W" "R10W_REGS"
    148  1.1  mrg  "The R10 register, HImode.")
    149  1.1  mrg 
    150  1.1  mrg (define_register_constraint "Zint" "INT_REGS"
    151  1.1  mrg  "The interrupt registers.")
    152  1.1  mrg 
    153  1.1  mrg ; All the memory addressing schemes the RL78 supports
    154  1.1  mrg ; of the form W {register} {bytes of offset}
    155  1.1  mrg ;          or W {register} {register}
    156  1.1  mrg 
    157  1.1  mrg ; absolute address
    158  1.1  mrg (define_memory_constraint "Wab"
    159  1.1  mrg   "[addr]"
    160  1.1  mrg   (and (match_code "mem")
    161  1.1  mrg        (ior (match_test "CONSTANT_P (XEXP (op, 0))")
    162  1.1  mrg 	    (match_test "GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF"))
    163  1.1  mrg 	    )
    164  1.1  mrg   )
    165  1.1  mrg 
    166  1.1  mrg (define_memory_constraint "Wbc"
    167  1.1  mrg   "word16[BC]"
    168  1.1  mrg   (and (match_code "mem")
    169  1.1  mrg        (ior
    170  1.1  mrg 	(and (match_code "reg" "0")
    171  1.1  mrg 	     (match_test "REGNO (XEXP (op, 0)) == BC_REG"))
    172  1.1  mrg 	(and (match_code "plus" "0")
    173  1.1  mrg 	     (and (and (match_code "reg" "00")
    174  1.1  mrg 		       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == BC_REG"))
    175  1.1  mrg 		       (match_test "uword_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
    176  1.1  mrg        )
    177  1.1  mrg   )
    178  1.1  mrg 
    179  1.1  mrg (define_memory_constraint "Wde"
    180  1.1  mrg   "[DE]"
    181  1.1  mrg   (and (match_code "mem")
    182  1.1  mrg        (and (match_code "reg" "0")
    183  1.1  mrg 	    (match_test "REGNO (XEXP (op, 0)) == DE_REG")))
    184  1.1  mrg   )
    185  1.1  mrg 
    186  1.1  mrg (define_memory_constraint "Wca"
    187  1.1  mrg   "[AX..HL] for calls"
    188  1.1  mrg   (and (match_code "mem")
    189  1.1  mrg        (and (match_code "reg" "0")
    190  1.1  mrg 	    (match_test "REGNO (XEXP (op, 0)) <= HL_REG")))
    191  1.1  mrg   )
    192  1.1  mrg 
    193  1.1  mrg (define_memory_constraint "Wcv"
    194  1.1  mrg   "[AX..HL,r8-r23] for calls"
    195  1.1  mrg   (and (match_code "mem")
    196  1.1  mrg        (and (match_code "reg" "0")
    197  1.1  mrg 	    (match_test "REGNO (XEXP (op, 0)) < 24")))
    198  1.1  mrg   )
    199  1.1  mrg 
    200  1.1  mrg (define_memory_constraint "Wd2"
    201  1.1  mrg   "word16[DE]"
    202  1.1  mrg   (and (match_code "mem")
    203  1.1  mrg        (ior
    204  1.1  mrg 	(and (match_code "reg" "0")
    205  1.1  mrg 	     (match_test "REGNO (XEXP (op, 0)) == DE_REG"))
    206  1.1  mrg 	(and (match_code "plus" "0")
    207  1.1  mrg 	     (and (and (match_code "reg" "00")
    208  1.1  mrg 		       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == DE_REG"))
    209  1.1  mrg 		       (match_test "uword_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
    210  1.1  mrg        )
    211  1.1  mrg   )
    212  1.1  mrg 
    213  1.1  mrg (define_memory_constraint "Whl"
    214  1.1  mrg   "[HL]"
    215  1.1  mrg   (and (match_code "mem")
    216  1.1  mrg        (and (match_code "reg" "0")
    217  1.1  mrg 	    (match_test "REGNO (XEXP (op, 0)) == HL_REG")))
    218  1.1  mrg   )
    219  1.1  mrg 
    220  1.1  mrg (define_memory_constraint "Wh1"
    221  1.1  mrg   "byte8[HL]"
    222  1.1  mrg   (and (match_code "mem")
    223  1.1  mrg        (and (match_code "plus" "0")
    224  1.1  mrg 	    (and (and (match_code "reg" "00")
    225  1.1  mrg 		      (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == HL_REG"))
    226  1.1  mrg 		      (match_test "ubyte_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
    227  1.1  mrg   )
    228  1.1  mrg 
    229  1.1  mrg (define_memory_constraint "Whb"
    230  1.1  mrg   "[HL+B]"
    231  1.1  mrg   (and (match_code "mem")
    232  1.1  mrg        (match_test "rl78_hl_b_c_addr_p (XEXP (op, 0))"))
    233  1.1  mrg   )
    234  1.1  mrg 
    235  1.1  mrg (define_memory_constraint "Ws1"
    236  1.1  mrg   "word8[SP]"
    237  1.1  mrg   (and (match_code "mem")
    238  1.1  mrg        (ior
    239  1.1  mrg 	(and (match_code "reg" "0")
    240  1.1  mrg 	     (match_test "REGNO (XEXP (op, 0)) == SP_REG"))
    241  1.1  mrg 	(and (match_code "plus" "0")
    242  1.1  mrg 	     (and (and (match_code "reg" "00")
    243  1.1  mrg 		       (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG"))
    244  1.1  mrg 		       (match_test "ubyte_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
    245  1.1  mrg        )
    246  1.1  mrg   )
    247  1.1  mrg 
    248  1.1  mrg (define_memory_constraint "Wfr"
    249  1.1  mrg   "ES/CS far pointer"
    250  1.1  mrg   (and (match_code "mem")
    251  1.1  mrg        (match_test "rl78_far_p (op)"))
    252  1.1  mrg   )
    253  1.1  mrg 
    254  1.1  mrg (define_memory_constraint "Y"
    255  1.1  mrg   "any near legitimate memory access"
    256  1.1  mrg   (and (match_code "mem")
    257  1.1  mrg        (match_test "!rl78_far_p (op) && rl78_as_legitimate_address (VOIDmode, XEXP (op, 0), true, ADDR_SPACE_GENERIC)"))
    258  1.1  mrg )
    259  1.1  mrg 
    260  1.1  mrg 
    261  1.1  mrg (define_memory_constraint "Qbi"
    262  1.1  mrg   "built-in compare types"
    263  1.1  mrg   (match_code "eq,ne,gtu,ltu,geu,leu"))
    264  1.1  mrg 
    265  1.1  mrg (define_memory_constraint "Qsc"
    266  1.1  mrg   "synthetic compares"
    267             (match_code "gt,lt,ge,le"))
    268