constraints.md revision 1.6 1 1.1 mrg ;; Machine Description for Renesas RL78 processors
2 1.6 mrg ;; Copyright (C) 2011-2017 Free Software Foundation, Inc.
3 1.1 mrg ;; Contributed by Red Hat.
4 1.1 mrg
5 1.1 mrg ;; This file is part of GCC.
6 1.1 mrg
7 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify
8 1.1 mrg ;; it under the terms of the GNU General Public License as published by
9 1.1 mrg ;; the Free Software Foundation; either version 3, or (at your option)
10 1.1 mrg ;; any later version.
11 1.1 mrg
12 1.1 mrg ;; GCC is distributed in the hope that it will be useful,
13 1.1 mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 1.1 mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 1.1 mrg ;; GNU General Public License for more details.
16 1.1 mrg
17 1.1 mrg ;; You should have received a copy of the GNU General Public License
18 1.1 mrg ;; along with GCC; see the file COPYING3. If not see
19 1.1 mrg ;; <http://www.gnu.org/licenses/>.
20 1.1 mrg
22 1.1 mrg ; Constraints in use:
23 1.1 mrg
24 1.1 mrg ; core:
25 1.1 mrg ; V X g i m n o p r s < >
26 1.1 mrg ; 0..9
27 1.1 mrg ; I..Q - integers
28 1.1 mrg ; Int8 = 0..255
29 1.1 mrg ; Int3 = 1..7
30 1.1 mrg ; J = -255..0
31 1.1 mrg ; K = 1
32 1.1 mrg ; L = -1
33 1.1 mrg ; M = 0
34 1.1 mrg ; N = 2
35 1.1 mrg ; O = -2
36 1.1 mrg ; P = 1..15
37 1.1 mrg
38 1.1 mrg ; E..H - float constants
39 1.1 mrg
40 1.1 mrg ; RL78-specific
41 1.1 mrg ; a x b c d e h l w - 8-bit regs
42 1.1 mrg ; A B D T S - 16-bit regs
43 1.1 mrg ; R = all regular registers (A-L)
44 1.1 mrg ; Y - any valid memory
45 1.1 mrg ; Wxx - various memory addressing modes
46 1.3 mrg ; Qxx - conditionals
47 1.1 mrg ; U = usual memory references mov-able to/from AX
48 1.1 mrg ; v = virtual registers
49 1.1 mrg ; Zxx = specific virtual registers
50 1.1 mrg
51 1.1 mrg (define_constraint "Int8"
52 1.1 mrg "Integer constant in the range 0 @dots{} 255."
53 1.1 mrg (and (match_code "const_int")
54 1.1 mrg (match_test "IN_RANGE (ival, 0, 255)")))
55 1.1 mrg
56 1.1 mrg (define_constraint "Int3"
57 1.1 mrg "Integer constant in the range 1 @dots{} 7."
58 1.1 mrg (and (match_code "const_int")
59 1.1 mrg (match_test "IN_RANGE (ival, 1, 7)")))
60 1.3 mrg
61 1.3 mrg (define_constraint "Iv08"
62 1.3 mrg "@internal
63 1.3 mrg Integer constant equal to 8."
64 1.3 mrg (and (match_code "const_int")
65 1.3 mrg (match_test "IN_RANGE (ival, 8, 8)")))
66 1.3 mrg
67 1.3 mrg (define_constraint "Iv16"
68 1.3 mrg "@internal
69 1.3 mrg Integer constant equal to 16."
70 1.3 mrg (and (match_code "const_int")
71 1.3 mrg (match_test "IN_RANGE (ival, 16, 16)")))
72 1.3 mrg
73 1.3 mrg (define_constraint "Iv24"
74 1.3 mrg "@internal
75 1.3 mrg Integer constant equal to 24."
76 1.3 mrg (and (match_code "const_int")
77 1.3 mrg (match_test "IN_RANGE (ival, 24, 24)")))
78 1.3 mrg
79 1.3 mrg (define_constraint "Is09"
80 1.3 mrg "@internal
81 1.3 mrg Integer constant in the range 9 @dots{} 15 (for shifts)."
82 1.3 mrg (and (match_code "const_int")
83 1.3 mrg (match_test "IN_RANGE (ival, 9, 15)")))
84 1.3 mrg
85 1.3 mrg (define_constraint "Is17"
86 1.3 mrg "@internal
87 1.3 mrg Integer constant in the range 17 @dots{} 23 (for shifts)."
88 1.3 mrg (and (match_code "const_int")
89 1.3 mrg (match_test "IN_RANGE (ival, 17, 23)")))
90 1.3 mrg
91 1.3 mrg (define_constraint "Is25"
92 1.3 mrg "@internal
93 1.3 mrg Integer constant in the range 25 @dots{} 31 (for shifts)."
94 1.3 mrg (and (match_code "const_int")
95 1.3 mrg (match_test "IN_RANGE (ival, 25, 31)")))
96 1.3 mrg
97 1.3 mrg (define_constraint "ISsi"
98 1.3 mrg "@internal
99 1.3 mrg Integer constant with bit 31 set."
100 1.3 mrg (and (match_code "const_int")
101 1.3 mrg (match_test "(ival & 0x80000000) != 0")))
102 1.3 mrg
103 1.3 mrg (define_constraint "IShi"
104 1.3 mrg "@internal
105 1.3 mrg Integer constant with bit 15 set."
106 1.3 mrg (and (match_code "const_int")
107 1.3 mrg (match_test "(ival & 0x8000) != 0")))
108 1.3 mrg
109 1.3 mrg (define_constraint "ISqi"
110 1.3 mrg "@internal
111 1.3 mrg Integer constant with bit 7 set."
112 1.3 mrg (and (match_code "const_int")
113 1.3 mrg (match_test "(ival & 0x80) != 0")))
114 1.3 mrg
115 1.3 mrg (define_constraint "Ibqi"
116 1.3 mrg "@internal
117 1.3 mrg Integer constant with one bit in 0..7 set."
118 1.3 mrg (and (match_code "const_int")
119 1.3 mrg (match_test "(ival & 0xff) && (exact_log2 (ival & 0xff) >= 0)")))
120 1.3 mrg (define_constraint "IBqi"
121 1.3 mrg "@internal
122 1.3 mrg Integer constant with one bit in 0..7 clear."
123 1.3 mrg (and (match_code "const_int")
124 1.3 mrg (match_test "(~ival & 0xff) && (exact_log2 (~ival & 0xff) >= 0)")))
125 1.1 mrg
126 1.1 mrg (define_constraint "J"
127 1.1 mrg "Integer constant in the range -255 @dots{} 0"
128 1.1 mrg (and (match_code "const_int")
129 1.1 mrg (match_test "IN_RANGE (ival, -255, 0)")))
130 1.1 mrg
131 1.1 mrg (define_constraint "K"
132 1.1 mrg "Integer constant 1."
133 1.1 mrg (and (match_code "const_int")
134 1.1 mrg (match_test "IN_RANGE (ival, 1, 1)")))
135 1.1 mrg
136 1.1 mrg (define_constraint "L"
137 1.1 mrg "Integer constant -1."
138 1.1 mrg (and (match_code "const_int")
139 1.1 mrg (match_test "IN_RANGE (ival, -1, -1)")))
140 1.1 mrg
141 1.1 mrg (define_constraint "M"
142 1.1 mrg "Integer constant 0."
143 1.1 mrg (and (match_code "const_int")
144 1.1 mrg (match_test "IN_RANGE (ival, 0, 0)")))
145 1.1 mrg
146 1.1 mrg (define_constraint "N"
147 1.1 mrg "Integer constant 2."
148 1.1 mrg (and (match_code "const_int")
149 1.1 mrg (match_test "IN_RANGE (ival, 2, 2)")))
150 1.1 mrg
151 1.1 mrg (define_constraint "O"
152 1.1 mrg "Integer constant -2."
153 1.1 mrg (and (match_code "const_int")
154 1.1 mrg (match_test "IN_RANGE (ival, -2, -2)")))
155 1.1 mrg
156 1.1 mrg (define_constraint "P"
157 1.1 mrg "Integer constant 1..15"
158 1.1 mrg (and (match_code "const_int")
159 1.1 mrg (match_test "IN_RANGE (ival, 1, 15)")))
160 1.1 mrg
161 1.1 mrg (define_register_constraint "R" "QI_REGS"
162 1.1 mrg "@code{A} through @code{L} registers.")
163 1.1 mrg
164 1.1 mrg (define_register_constraint "a" "AREG"
165 1.1 mrg "The @code{A} register.")
166 1.1 mrg
167 1.1 mrg (define_register_constraint "x" "XREG"
168 1.1 mrg "The @code{X} register.")
169 1.1 mrg
170 1.1 mrg (define_register_constraint "b" "BREG"
171 1.1 mrg "The @code{B} register.")
172 1.1 mrg
173 1.1 mrg (define_register_constraint "c" "CREG"
174 1.1 mrg "The @code{C} register.")
175 1.1 mrg
176 1.1 mrg (define_register_constraint "d" "DREG"
177 1.1 mrg "The @code{D} register.")
178 1.1 mrg
179 1.1 mrg (define_register_constraint "e" "EREG"
180 1.1 mrg "The @code{E} register.")
181 1.1 mrg
182 1.1 mrg (define_register_constraint "h" "HREG"
183 1.1 mrg "The @code{H} register.")
184 1.1 mrg
185 1.1 mrg (define_register_constraint "l" "LREG"
186 1.1 mrg "The @code{L} register.")
187 1.1 mrg
188 1.1 mrg (define_register_constraint "w" "PSWREG"
189 1.1 mrg "The @code{PSW} register.")
190 1.1 mrg
191 1.1 mrg (define_register_constraint "A" "AXREG"
192 1.1 mrg "The @code{AX} register.")
193 1.1 mrg
194 1.1 mrg (define_register_constraint "B" "BCREG"
195 1.1 mrg "The @code{BC} register.")
196 1.1 mrg
197 1.1 mrg (define_register_constraint "D" "DEREG"
198 1.1 mrg "The @code{DE} register.")
199 1.1 mrg
200 1.1 mrg ; because H + L = T, assuming A=1.
201 1.1 mrg (define_register_constraint "T" "HLREG"
202 1.1 mrg "The @code{HL} register.")
203 1.1 mrg
204 1.1 mrg (define_register_constraint "S" "SPREG"
205 1.1 mrg "The @code{SP} register.")
206 1.1 mrg
207 1.1 mrg (define_register_constraint "v" "V_REGS"
208 1.1 mrg "The virtual registers.")
209 1.1 mrg
210 1.1 mrg (define_register_constraint "Z08W" "R8W_REGS"
211 1.1 mrg "The R8 register, HImode.")
212 1.1 mrg
213 1.1 mrg (define_register_constraint "Z10W" "R10W_REGS"
214 1.1 mrg "The R10 register, HImode.")
215 1.1 mrg
216 1.1 mrg (define_register_constraint "Zint" "INT_REGS"
217 1.1 mrg "The interrupt registers.")
218 1.1 mrg
219 1.1 mrg ; All the memory addressing schemes the RL78 supports
220 1.1 mrg ; of the form W {register} {bytes of offset}
221 1.3 mrg ; or W {register} {register}
222 1.3 mrg ; Additionally, the Cxx forms are the same as the Wxx forms, but without
223 1.1 mrg ; the ES: override.
224 1.1 mrg
225 1.3 mrg ; absolute address
226 1.1 mrg (define_memory_constraint "Cab"
227 1.1 mrg "[addr]"
228 1.1 mrg (and (match_code "mem")
229 1.1 mrg (ior (match_test "CONSTANT_P (XEXP (op, 0))")
230 1.1 mrg (match_test "GET_CODE (XEXP (op, 0)) == PLUS && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF"))
231 1.1 mrg )
232 1.3 mrg )
233 1.3 mrg (define_memory_constraint "Wab"
234 1.3 mrg "es:[addr]"
235 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Cab (rl78_es_base (op)))
236 1.3 mrg || satisfies_constraint_Cab (op)")
237 1.1 mrg )
238 1.3 mrg
239 1.1 mrg (define_memory_constraint "Cbc"
240 1.1 mrg "word16[BC]"
241 1.1 mrg (and (match_code "mem")
242 1.1 mrg (ior
243 1.1 mrg (and (match_code "reg" "0")
244 1.1 mrg (match_test "REGNO (XEXP (op, 0)) == BC_REG"))
245 1.1 mrg (and (match_code "plus" "0")
246 1.1 mrg (and (and (match_code "reg" "00")
247 1.1 mrg (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == BC_REG"))
248 1.1 mrg (match_test "uword_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
249 1.1 mrg )
250 1.3 mrg )
251 1.3 mrg (define_memory_constraint "Wbc"
252 1.3 mrg "es:word16[BC]"
253 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Cbc (rl78_es_base (op)))
254 1.3 mrg || satisfies_constraint_Cbc (op)")
255 1.1 mrg )
256 1.3 mrg
257 1.1 mrg (define_memory_constraint "Cde"
258 1.1 mrg "[DE]"
259 1.1 mrg (and (match_code "mem")
260 1.1 mrg (and (match_code "reg" "0")
261 1.1 mrg (match_test "REGNO (XEXP (op, 0)) == DE_REG")))
262 1.3 mrg )
263 1.3 mrg (define_memory_constraint "Wde"
264 1.3 mrg "es:[DE]"
265 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Cde (rl78_es_base (op)))
266 1.3 mrg || satisfies_constraint_Cde (op)")
267 1.1 mrg )
268 1.3 mrg
269 1.1 mrg (define_memory_constraint "Cca"
270 1.1 mrg "[AX..HL] for calls"
271 1.1 mrg (and (match_code "mem")
272 1.1 mrg (and (match_code "reg" "0")
273 1.1 mrg (match_test "REGNO (XEXP (op, 0)) <= HL_REG")))
274 1.3 mrg )
275 1.3 mrg (define_memory_constraint "Wca"
276 1.3 mrg "es:[AX..HL] for calls"
277 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Cca (rl78_es_base (op)))
278 1.3 mrg || satisfies_constraint_Cca (op)")
279 1.1 mrg )
280 1.3 mrg
281 1.3 mrg (define_memory_constraint "Ccv"
282 1.1 mrg "[AX..HL,r8-r31] for calls"
283 1.1 mrg (and (match_code "mem")
284 1.3 mrg (and (match_code "reg" "0")
285 1.3 mrg (match_test "REGNO (XEXP (op, 0)) < 32")))
286 1.3 mrg )
287 1.3 mrg (define_memory_constraint "Wcv"
288 1.3 mrg "es:[AX..HL,r8-r31] for calls"
289 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Ccv (rl78_es_base (op)))
290 1.1 mrg || satisfies_constraint_Ccv (op)")
291 1.1 mrg )
292 1.3 mrg
293 1.1 mrg (define_memory_constraint "Cd2"
294 1.1 mrg "word16[DE]"
295 1.1 mrg (and (match_code "mem")
296 1.1 mrg (ior
297 1.1 mrg (and (match_code "reg" "0")
298 1.1 mrg (match_test "REGNO (XEXP (op, 0)) == DE_REG"))
299 1.1 mrg (and (match_code "plus" "0")
300 1.1 mrg (and (and (match_code "reg" "00")
301 1.1 mrg (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == DE_REG"))
302 1.1 mrg (match_test "uword_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
303 1.1 mrg )
304 1.3 mrg )
305 1.3 mrg (define_memory_constraint "Wd2"
306 1.3 mrg "es:word16[DE]"
307 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Cd2 (rl78_es_base (op)))
308 1.3 mrg || satisfies_constraint_Cd2 (op)")
309 1.1 mrg )
310 1.3 mrg
311 1.1 mrg (define_memory_constraint "Chl"
312 1.1 mrg "[HL]"
313 1.1 mrg (and (match_code "mem")
314 1.1 mrg (and (match_code "reg" "0")
315 1.1 mrg (match_test "REGNO (XEXP (op, 0)) == HL_REG")))
316 1.3 mrg )
317 1.3 mrg (define_memory_constraint "Whl"
318 1.3 mrg "es:[HL]"
319 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Chl (rl78_es_base (op)))
320 1.3 mrg || satisfies_constraint_Chl (op)")
321 1.1 mrg )
322 1.3 mrg
323 1.1 mrg (define_memory_constraint "Ch1"
324 1.1 mrg "byte8[HL]"
325 1.1 mrg (and (match_code "mem")
326 1.1 mrg (and (match_code "plus" "0")
327 1.1 mrg (and (and (match_code "reg" "00")
328 1.1 mrg (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == HL_REG"))
329 1.1 mrg (match_test "ubyte_operand (XEXP (XEXP (op, 0), 1), VOIDmode)"))))
330 1.3 mrg )
331 1.3 mrg (define_memory_constraint "Wh1"
332 1.3 mrg "es:byte8[HL]"
333 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Ch1 (rl78_es_base (op)))
334 1.3 mrg || satisfies_constraint_Ch1 (op)")
335 1.1 mrg )
336 1.3 mrg
337 1.1 mrg (define_memory_constraint "Chb"
338 1.1 mrg "[HL+B]"
339 1.1 mrg (and (match_code "mem")
340 1.1 mrg (match_test "rl78_hl_b_c_addr_p (XEXP (op, 0))"))
341 1.3 mrg )
342 1.3 mrg (define_memory_constraint "Whb"
343 1.3 mrg "es:[HL+B]"
344 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Chb (rl78_es_base (op)))
345 1.3 mrg || satisfies_constraint_Chb (op)")
346 1.1 mrg )
347 1.3 mrg
348 1.1 mrg (define_memory_constraint "Cs1"
349 1.1 mrg "word8[SP]"
350 1.1 mrg (and (match_code "mem")
351 1.1 mrg (ior
352 1.1 mrg (and (match_code "reg" "0")
353 1.1 mrg (match_test "REGNO (XEXP (op, 0)) == SP_REG"))
354 1.1 mrg (and (match_code "plus" "0")
355 1.1 mrg (and (and (match_code "reg" "00")
356 1.3 mrg (match_test "REGNO (XEXP (XEXP (op, 0), 0)) == SP_REG"))
357 1.3 mrg (and (match_code "const_int" "01")
358 1.1 mrg (match_test "IN_RANGE (INTVAL (XEXP (XEXP (op, 0), 1)), 0, 256 - GET_MODE_SIZE (GET_MODE (op)))")))))
359 1.1 mrg )
360 1.1 mrg )
361 1.3 mrg
362 1.3 mrg (define_memory_constraint "Ws1"
363 1.3 mrg "es:word8[SP]"
364 1.3 mrg (match_test "(rl78_es_addr (op) && satisfies_constraint_Cs1 (rl78_es_base (op)))
365 1.3 mrg || satisfies_constraint_Cs1 (op)")
366 1.3 mrg )
367 1.4 mrg
368 1.1 mrg (define_constraint "Wfr"
369 1.1 mrg "ES/CS far pointer"
370 1.1 mrg (and (match_code "mem")
371 1.1 mrg (match_test "rl78_far_p (op)"))
372 1.1 mrg )
373 1.3 mrg
374 1.3 mrg (define_memory_constraint "Wsa"
375 1.3 mrg "any SADDR memory access"
376 1.3 mrg (and (match_code "mem")
377 1.3 mrg (match_test "rl78_saddr_p (op)"))
378 1.3 mrg )
379 1.3 mrg
380 1.3 mrg (define_memory_constraint "Wsf"
381 1.3 mrg "any SFR memory access"
382 1.3 mrg (and (match_code "mem")
383 1.3 mrg (match_test "rl78_sfr_p (op)"))
384 1.3 mrg )
385 1.1 mrg
386 1.1 mrg (define_memory_constraint "Y"
387 1.1 mrg "any near legitimate memory access"
388 1.1 mrg (and (match_code "mem")
389 1.1 mrg (match_test "!rl78_far_p (op) && rl78_as_legitimate_address (VOIDmode, XEXP (op, 0), true, ADDR_SPACE_GENERIC)"))
390 1.1 mrg )
391 1.3 mrg
392 1.3 mrg (define_memory_constraint "U"
393 1.3 mrg "memory references valid with mov to/from a/ax"
394 1.3 mrg (and (match_code "mem")
395 1.3 mrg (match_test "rl78_virt_insns_ok ()
396 1.3 mrg || satisfies_constraint_Wab (op)
397 1.3 mrg || satisfies_constraint_Wbc (op)
398 1.3 mrg || satisfies_constraint_Wde (op)
399 1.3 mrg || satisfies_constraint_Wd2 (op)
400 1.3 mrg || satisfies_constraint_Whl (op)
401 1.3 mrg || satisfies_constraint_Wh1 (op)
402 1.3 mrg || satisfies_constraint_Whb (op)
403 1.3 mrg || satisfies_constraint_Ws1 (op)
404 1.1 mrg || satisfies_constraint_Wfr (op) ")))
405 1.1 mrg
406 1.1 mrg (define_memory_constraint "Qbi"
407 1.1 mrg "built-in compare types"
408 1.1 mrg (match_code "eq,ne,gtu,ltu,geu,leu"))
409 1.1 mrg
410 1.1 mrg (define_memory_constraint "Qsc"
411 1.1 mrg "synthetic compares"
412 1.3 mrg (match_code "gt,lt,ge,le"))
413 1.3 mrg
414 1.3 mrg (define_constraint "Qs8"
415 1.3 mrg "Integer constant computed from (SUBREG (SYMREF))."
416 1.3 mrg (and (match_code "subreg")
417 1.3 mrg (match_test "GET_CODE (XEXP (op, 0)) == SYMBOL_REF"))
418 )
419