htm.md revision 1.1
1 1.1 mrg ;; Hardware Transactional Memory (HTM) patterns. 2 1.1 mrg ;; Copyright (C) 2013-2015 Free Software Foundation, Inc. 3 1.1 mrg ;; Contributed by Peter Bergner <bergner (a] vnet.ibm.com>. 4 1.1 mrg 5 1.1 mrg ;; This file is part of GCC. 6 1.1 mrg 7 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify it 8 1.1 mrg ;; under the terms of the GNU General Public License as published 9 1.1 mrg ;; by the Free Software Foundation; either version 3, or (at your 10 1.1 mrg ;; option) any later version. 11 1.1 mrg 12 1.1 mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT 13 1.1 mrg ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 1.1 mrg ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 1.1 mrg ;; License for more details. 16 1.1 mrg 17 1.1 mrg ;; You should have received a copy of the GNU General Public License 18 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ;; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg (define_constants 22 1.1 mrg [(TFHAR_SPR 128) 23 1.1 mrg (TFIAR_SPR 129) 24 1.1 mrg (TEXASR_SPR 130) 25 1.1 mrg (TEXASRU_SPR 131) 26 1.1 mrg (MAX_HTM_OPERANDS 4) 27 1.1 mrg ]) 28 1.1 mrg 29 1.1 mrg ;; 30 1.1 mrg ;; UNSPEC_VOLATILE usage 31 1.1 mrg ;; 32 1.1 mrg 33 1.1 mrg (define_c_enum "unspecv" 34 1.1 mrg [UNSPECV_HTM_TABORT 35 1.1 mrg UNSPECV_HTM_TABORTXC 36 1.1 mrg UNSPECV_HTM_TABORTXCI 37 1.1 mrg UNSPECV_HTM_TBEGIN 38 1.1 mrg UNSPECV_HTM_TCHECK 39 1.1 mrg UNSPECV_HTM_TEND 40 1.1 mrg UNSPECV_HTM_TRECHKPT 41 1.1 mrg UNSPECV_HTM_TRECLAIM 42 1.1 mrg UNSPECV_HTM_TSR 43 1.1 mrg UNSPECV_HTM_TTEST 44 1.1 mrg UNSPECV_HTM_MFSPR 45 1.1 mrg UNSPECV_HTM_MTSPR 46 1.1 mrg ]) 47 1.1 mrg 48 1.1 mrg 49 1.1 mrg (define_insn "tabort" 50 1.1 mrg [(set (match_operand:CC 1 "cc_reg_operand" "=x") 51 1.1 mrg (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")] 52 1.1 mrg UNSPECV_HTM_TABORT))] 53 1.1 mrg "TARGET_HTM" 54 1.1 mrg "tabort. %0" 55 1.1 mrg [(set_attr "type" "htm") 56 1.1 mrg (set_attr "length" "4")]) 57 1.1 mrg 58 1.1 mrg (define_insn "tabort<wd>c" 59 1.1 mrg [(set (match_operand:CC 3 "cc_reg_operand" "=x") 60 1.1 mrg (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") 61 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r") 62 1.1 mrg (match_operand:GPR 2 "gpc_reg_operand" "r")] 63 1.1 mrg UNSPECV_HTM_TABORTXC))] 64 1.1 mrg "TARGET_HTM" 65 1.1 mrg "tabort<wd>c. %0,%1,%2" 66 1.1 mrg [(set_attr "type" "htm") 67 1.1 mrg (set_attr "length" "4")]) 68 1.1 mrg 69 1.1 mrg (define_insn "tabort<wd>ci" 70 1.1 mrg [(set (match_operand:CC 3 "cc_reg_operand" "=x") 71 1.1 mrg (unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n") 72 1.1 mrg (match_operand:GPR 1 "gpc_reg_operand" "r") 73 1.1 mrg (match_operand 2 "s5bit_cint_operand" "n")] 74 1.1 mrg UNSPECV_HTM_TABORTXCI))] 75 1.1 mrg "TARGET_HTM" 76 1.1 mrg "tabort<wd>ci. %0,%1,%2" 77 1.1 mrg [(set_attr "type" "htm") 78 1.1 mrg (set_attr "length" "4")]) 79 1.1 mrg 80 1.1 mrg (define_insn "tbegin" 81 1.1 mrg [(set (match_operand:CC 1 "cc_reg_operand" "=x") 82 1.1 mrg (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] 83 1.1 mrg UNSPECV_HTM_TBEGIN))] 84 1.1 mrg "TARGET_HTM" 85 1.1 mrg "tbegin. %0" 86 1.1 mrg [(set_attr "type" "htm") 87 1.1 mrg (set_attr "length" "4")]) 88 1.1 mrg 89 1.1 mrg (define_insn "tcheck" 90 1.1 mrg [(set (match_operand:CC 0 "cc_reg_operand" "=y") 91 1.1 mrg (unspec_volatile:CC [(const_int 0)] 92 1.1 mrg UNSPECV_HTM_TCHECK))] 93 1.1 mrg "TARGET_HTM" 94 1.1 mrg "tcheck %0" 95 1.1 mrg [(set_attr "type" "htm") 96 1.1 mrg (set_attr "length" "4")]) 97 1.1 mrg 98 1.1 mrg (define_insn "tend" 99 1.1 mrg [(set (match_operand:CC 1 "cc_reg_operand" "=x") 100 1.1 mrg (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] 101 1.1 mrg UNSPECV_HTM_TEND))] 102 1.1 mrg "TARGET_HTM" 103 1.1 mrg "tend. %0" 104 1.1 mrg [(set_attr "type" "htm") 105 1.1 mrg (set_attr "length" "4")]) 106 1.1 mrg 107 1.1 mrg (define_insn "trechkpt" 108 1.1 mrg [(set (match_operand:CC 0 "cc_reg_operand" "=x") 109 1.1 mrg (unspec_volatile:CC [(const_int 0)] 110 1.1 mrg UNSPECV_HTM_TRECHKPT))] 111 1.1 mrg "TARGET_HTM" 112 1.1 mrg "trechkpt." 113 1.1 mrg [(set_attr "type" "htm") 114 1.1 mrg (set_attr "length" "4")]) 115 1.1 mrg 116 1.1 mrg (define_insn "treclaim" 117 1.1 mrg [(set (match_operand:CC 1 "cc_reg_operand" "=x") 118 1.1 mrg (unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")] 119 1.1 mrg UNSPECV_HTM_TRECLAIM))] 120 1.1 mrg "TARGET_HTM" 121 1.1 mrg "treclaim. %0" 122 1.1 mrg [(set_attr "type" "htm") 123 1.1 mrg (set_attr "length" "4")]) 124 1.1 mrg 125 1.1 mrg (define_insn "tsr" 126 1.1 mrg [(set (match_operand:CC 1 "cc_reg_operand" "=x") 127 1.1 mrg (unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")] 128 1.1 mrg UNSPECV_HTM_TSR))] 129 1.1 mrg "TARGET_HTM" 130 1.1 mrg "tsr. %0" 131 1.1 mrg [(set_attr "type" "htm") 132 1.1 mrg (set_attr "length" "4")]) 133 1.1 mrg 134 1.1 mrg (define_insn "ttest" 135 1.1 mrg [(set (match_operand:CC 0 "cc_reg_operand" "=x") 136 1.1 mrg (unspec_volatile:CC [(const_int 0)] 137 1.1 mrg UNSPECV_HTM_TTEST))] 138 1.1 mrg "TARGET_HTM" 139 1.1 mrg "tabortwci. 0,1,0" 140 1.1 mrg [(set_attr "type" "htm") 141 1.1 mrg (set_attr "length" "4")]) 142 1.1 mrg 143 1.1 mrg (define_insn "htm_mfspr_<mode>" 144 1.1 mrg [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 145 1.1 mrg (unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n") 146 1.1 mrg (match_operand:GPR 2 "htm_spr_reg_operand" "")] 147 1.1 mrg UNSPECV_HTM_MFSPR))] 148 1.1 mrg "TARGET_HTM" 149 1.1 mrg "mfspr %0,%1"; 150 1.1 mrg [(set_attr "type" "htm") 151 1.1 mrg (set_attr "length" "4")]) 152 1.1 mrg 153 1.1 mrg (define_insn "htm_mtspr_<mode>" 154 1.1 mrg [(set (match_operand:GPR 2 "htm_spr_reg_operand" "") 155 1.1 mrg (unspec_volatile:GPR [(match_operand:GPR 0 "gpc_reg_operand" "r") 156 1.1 mrg (match_operand 1 "u10bit_cint_operand" "n")] 157 1.1 mrg UNSPECV_HTM_MTSPR))] 158 1.1 mrg "TARGET_HTM" 159 1.1 mrg "mtspr %1,%0"; 160 1.1 mrg [(set_attr "type" "htm") 161 1.1 mrg (set_attr "length" "4")]) 162
Indexes created Sun Apr 26 00:22:38 UTC 2026