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mpc.md revision 1.1.1.4 
      1      1.1  mrg ;; Scheduling description for Motorola PowerPC processor cores.
      2  1.1.1.4  mrg ;;   Copyright (C) 2003-2016 Free Software Foundation, Inc.
      3      1.1  mrg ;;
      4      1.1  mrg ;; This file is part of GCC.
      5      1.1  mrg ;;
      6      1.1  mrg ;; GCC is free software; you can redistribute it and/or modify it
      7      1.1  mrg ;; under the terms of the GNU General Public License as published
      8      1.1  mrg ;; by the Free Software Foundation; either version 3, or (at your
      9      1.1  mrg ;; option) any later version.
     10      1.1  mrg ;;
     11      1.1  mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT
     12      1.1  mrg ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     13      1.1  mrg ;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     14      1.1  mrg ;; License for more details.
     15      1.1  mrg ;;
     16      1.1  mrg ;; You should have received a copy of the GNU General Public License
     17      1.1  mrg ;; along with GCC; see the file COPYING3.  If not see
     18      1.1  mrg ;; <http://www.gnu.org/licenses/>.
     19      1.1  mrg 
     20      1.1  mrg (define_automaton "mpc,mpcfp")
     21      1.1  mrg (define_cpu_unit "iu_mpc,mciu_mpc" "mpc")
     22      1.1  mrg (define_cpu_unit "fpu_mpc" "mpcfp")
     23      1.1  mrg (define_cpu_unit "lsu_mpc,bpu_mpc" "mpc")
     24      1.1  mrg 
     25      1.1  mrg ;; MPCCORE 32-bit SCIU, MCIU, LSU, FPU, BPU
     26      1.1  mrg ;; 505/801/821/823
     27      1.1  mrg 
     28      1.1  mrg (define_insn_reservation "mpccore-load" 2
     29  1.1.1.3  mrg   (and (eq_attr "type" "load,load_l,store_c,sync")
     30      1.1  mrg        (eq_attr "cpu" "mpccore"))
     31      1.1  mrg   "lsu_mpc")
     32      1.1  mrg 
     33      1.1  mrg (define_insn_reservation "mpccore-store" 2
     34  1.1.1.3  mrg   (and (eq_attr "type" "store,fpstore")
     35      1.1  mrg        (eq_attr "cpu" "mpccore"))
     36      1.1  mrg   "lsu_mpc")
     37      1.1  mrg 
     38      1.1  mrg (define_insn_reservation "mpccore-fpload" 2
     39  1.1.1.3  mrg   (and (eq_attr "type" "fpload")
     40      1.1  mrg        (eq_attr "cpu" "mpccore"))
     41      1.1  mrg   "lsu_mpc")
     42      1.1  mrg 
     43      1.1  mrg (define_insn_reservation "mpccore-integer" 1
     44  1.1.1.3  mrg   (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel")
     45  1.1.1.3  mrg 	    (and (eq_attr "type" "add,logical,shift,exts")
     46  1.1.1.3  mrg 		 (eq_attr "dot" "no")))
     47      1.1  mrg        (eq_attr "cpu" "mpccore"))
     48      1.1  mrg   "iu_mpc")
     49      1.1  mrg 
     50      1.1  mrg (define_insn_reservation "mpccore-two" 1
     51      1.1  mrg   (and (eq_attr "type" "two")
     52      1.1  mrg        (eq_attr "cpu" "mpccore"))
     53      1.1  mrg   "iu_mpc,iu_mpc")
     54      1.1  mrg 
     55      1.1  mrg (define_insn_reservation "mpccore-three" 1
     56      1.1  mrg   (and (eq_attr "type" "three")
     57      1.1  mrg        (eq_attr "cpu" "mpccore"))
     58      1.1  mrg   "iu_mpc,iu_mpc,iu_mpc")
     59      1.1  mrg 
     60      1.1  mrg (define_insn_reservation "mpccore-imul" 2
     61  1.1.1.3  mrg   (and (eq_attr "type" "mul")
     62      1.1  mrg        (eq_attr "cpu" "mpccore"))
     63      1.1  mrg   "mciu_mpc")
     64      1.1  mrg 
     65      1.1  mrg ; Divide latency varies greatly from 2-11, use 6 as average
     66      1.1  mrg (define_insn_reservation "mpccore-idiv" 6
     67  1.1.1.3  mrg   (and (eq_attr "type" "div")
     68      1.1  mrg        (eq_attr "cpu" "mpccore"))
     69      1.1  mrg   "mciu_mpc*6")
     70      1.1  mrg 
     71      1.1  mrg (define_insn_reservation "mpccore-compare" 3
     72  1.1.1.3  mrg   (and (ior (eq_attr "type" "cmp")
     73  1.1.1.3  mrg 	    (and (eq_attr "type" "add,logical,shift,exts")
     74  1.1.1.3  mrg 		 (eq_attr "dot" "yes")))
     75      1.1  mrg        (eq_attr "cpu" "mpccore"))
     76      1.1  mrg   "iu_mpc,nothing,bpu_mpc")
     77      1.1  mrg 
     78      1.1  mrg (define_insn_reservation "mpccore-fpcompare" 2
     79      1.1  mrg   (and (eq_attr "type" "fpcompare")
     80      1.1  mrg        (eq_attr "cpu" "mpccore"))
     81      1.1  mrg   "fpu_mpc,bpu_mpc")
     82      1.1  mrg 
     83      1.1  mrg (define_insn_reservation "mpccore-fp" 4
     84  1.1.1.4  mrg   (and (eq_attr "type" "fp,fpsimple")
     85      1.1  mrg        (eq_attr "cpu" "mpccore"))
     86      1.1  mrg   "fpu_mpc*2")
     87      1.1  mrg 
     88      1.1  mrg (define_insn_reservation "mpccore-dmul" 5
     89      1.1  mrg   (and (eq_attr "type" "dmul")
     90      1.1  mrg        (eq_attr "cpu" "mpccore"))
     91      1.1  mrg   "fpu_mpc*5")
     92      1.1  mrg 
     93      1.1  mrg (define_insn_reservation "mpccore-sdiv" 10
     94      1.1  mrg   (and (eq_attr "type" "sdiv")
     95      1.1  mrg        (eq_attr "cpu" "mpccore"))
     96      1.1  mrg   "fpu_mpc*10")
     97      1.1  mrg 
     98      1.1  mrg (define_insn_reservation "mpccore-ddiv" 17
     99      1.1  mrg   (and (eq_attr "type" "ddiv")
    100      1.1  mrg        (eq_attr "cpu" "mpccore"))
    101      1.1  mrg   "fpu_mpc*17")
    102      1.1  mrg 
    103      1.1  mrg (define_insn_reservation "mpccore-mtjmpr" 4
    104      1.1  mrg   (and (eq_attr "type" "mtjmpr,mfjmpr")
    105      1.1  mrg        (eq_attr "cpu" "mpccore"))
    106      1.1  mrg   "bpu_mpc")
    107      1.1  mrg 
    108      1.1  mrg (define_insn_reservation "mpccore-jmpreg" 1
    109      1.1  mrg   (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr,mfcr,mtcr,isync")
    110      1.1  mrg        (eq_attr "cpu" "mpccore"))
    111      1.1  mrg   "bpu_mpc")
    112      1.1  mrg 
    113