1 1.1 mrg ;; Scheduling description for IBM RS64 processors. 2 1.12 mrg ;; Copyright (C) 2003-2022 Free Software Foundation, Inc. 3 1.1 mrg ;; 4 1.1 mrg ;; This file is part of GCC. 5 1.1 mrg 6 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify it 7 1.1 mrg ;; under the terms of the GNU General Public License as published 8 1.1 mrg ;; by the Free Software Foundation; either version 3, or (at your 9 1.1 mrg ;; option) any later version. 10 1.1 mrg 11 1.1 mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT 12 1.1 mrg ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 1.1 mrg ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 1.1 mrg ;; License for more details. 15 1.1 mrg 16 1.1 mrg ;; You should have received a copy of the GNU General Public License 17 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 18 1.1 mrg ;; <http://www.gnu.org/licenses/>. 19 1.1 mrg 20 1.1 mrg (define_automaton "rs64,rs64fp") 21 1.1 mrg (define_cpu_unit "iu_rs64" "rs64") 22 1.1 mrg (define_cpu_unit "mciu_rs64" "rs64") 23 1.1 mrg (define_cpu_unit "fpu_rs64" "rs64fp") 24 1.1 mrg (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64") 25 1.1 mrg 26 1.1 mrg ;; RS64a 64-bit IU, LSU, FPU, BPU 27 1.1 mrg 28 1.1 mrg (define_insn_reservation "rs64a-load" 2 29 1.5 mrg (and (eq_attr "type" "load") 30 1.1 mrg (eq_attr "cpu" "rs64a")) 31 1.1 mrg "lsu_rs64") 32 1.1 mrg 33 1.1 mrg (define_insn_reservation "rs64a-store" 2 34 1.5 mrg (and (eq_attr "type" "store,fpstore") 35 1.1 mrg (eq_attr "cpu" "rs64a")) 36 1.1 mrg "lsu_rs64") 37 1.1 mrg 38 1.1 mrg (define_insn_reservation "rs64a-fpload" 3 39 1.5 mrg (and (eq_attr "type" "fpload") 40 1.1 mrg (eq_attr "cpu" "rs64a")) 41 1.1 mrg "lsu_rs64") 42 1.1 mrg 43 1.1 mrg (define_insn_reservation "rs64a-llsc" 2 44 1.1 mrg (and (eq_attr "type" "load_l,store_c") 45 1.1 mrg (eq_attr "cpu" "rs64a")) 46 1.1 mrg "lsu_rs64") 47 1.1 mrg 48 1.1 mrg (define_insn_reservation "rs64a-integer" 1 49 1.5 mrg (and (ior (eq_attr "type" "integer,insert,trap,cntlz,isel") 50 1.5 mrg (and (eq_attr "type" "add,logical,shift,exts") 51 1.5 mrg (eq_attr "dot" "no"))) 52 1.1 mrg (eq_attr "cpu" "rs64a")) 53 1.1 mrg "iu_rs64") 54 1.1 mrg 55 1.1 mrg (define_insn_reservation "rs64a-two" 1 56 1.1 mrg (and (eq_attr "type" "two") 57 1.1 mrg (eq_attr "cpu" "rs64a")) 58 1.1 mrg "iu_rs64,iu_rs64") 59 1.1 mrg 60 1.1 mrg (define_insn_reservation "rs64a-three" 1 61 1.1 mrg (and (eq_attr "type" "three") 62 1.1 mrg (eq_attr "cpu" "rs64a")) 63 1.1 mrg "iu_rs64,iu_rs64,iu_rs64") 64 1.1 mrg 65 1.1 mrg (define_insn_reservation "rs64a-imul" 20 66 1.5 mrg (and (eq_attr "type" "mul") 67 1.5 mrg (eq_attr "size" "32") 68 1.1 mrg (eq_attr "cpu" "rs64a")) 69 1.1 mrg "mciu_rs64*13") 70 1.1 mrg 71 1.1 mrg (define_insn_reservation "rs64a-imul2" 12 72 1.5 mrg (and (eq_attr "type" "mul") 73 1.5 mrg (eq_attr "size" "16") 74 1.1 mrg (eq_attr "cpu" "rs64a")) 75 1.1 mrg "mciu_rs64*5") 76 1.1 mrg 77 1.1 mrg (define_insn_reservation "rs64a-imul3" 8 78 1.5 mrg (and (eq_attr "type" "mul") 79 1.5 mrg (eq_attr "size" "8") 80 1.1 mrg (eq_attr "cpu" "rs64a")) 81 1.1 mrg "mciu_rs64*2") 82 1.1 mrg 83 1.1 mrg (define_insn_reservation "rs64a-lmul" 34 84 1.5 mrg (and (eq_attr "type" "mul") 85 1.5 mrg (eq_attr "size" "64") 86 1.1 mrg (eq_attr "cpu" "rs64a")) 87 1.1 mrg "mciu_rs64*34") 88 1.1 mrg 89 1.1 mrg (define_insn_reservation "rs64a-idiv" 66 90 1.5 mrg (and (eq_attr "type" "div") 91 1.5 mrg (eq_attr "size" "32") 92 1.1 mrg (eq_attr "cpu" "rs64a")) 93 1.1 mrg "mciu_rs64*66") 94 1.1 mrg 95 1.1 mrg (define_insn_reservation "rs64a-ldiv" 66 96 1.5 mrg (and (eq_attr "type" "div") 97 1.5 mrg (eq_attr "size" "64") 98 1.1 mrg (eq_attr "cpu" "rs64a")) 99 1.1 mrg "mciu_rs64*66") 100 1.1 mrg 101 1.1 mrg (define_insn_reservation "rs64a-compare" 3 102 1.5 mrg (and (ior (eq_attr "type" "cmp") 103 1.5 mrg (and (eq_attr "type" "add,logical,shift,exts") 104 1.5 mrg (eq_attr "dot" "yes"))) 105 1.1 mrg (eq_attr "cpu" "rs64a")) 106 1.1 mrg "iu_rs64,nothing,bpu_rs64") 107 1.1 mrg 108 1.1 mrg (define_insn_reservation "rs64a-fpcompare" 5 109 1.1 mrg (and (eq_attr "type" "fpcompare") 110 1.1 mrg (eq_attr "cpu" "rs64a")) 111 1.1 mrg "mciu_rs64,fpu_rs64,bpu_rs64") 112 1.1 mrg 113 1.1 mrg (define_insn_reservation "rs64a-fp" 4 114 1.6 mrg (and (eq_attr "type" "fp,fpsimple,dmul") 115 1.1 mrg (eq_attr "cpu" "rs64a")) 116 1.1 mrg "mciu_rs64,fpu_rs64") 117 1.1 mrg 118 1.1 mrg (define_insn_reservation "rs64a-sdiv" 31 119 1.1 mrg (and (eq_attr "type" "sdiv,ddiv") 120 1.1 mrg (eq_attr "cpu" "rs64a")) 121 1.1 mrg "mciu_rs64,fpu_rs64*31") 122 1.1 mrg 123 1.1 mrg (define_insn_reservation "rs64a-sqrt" 49 124 1.1 mrg (and (eq_attr "type" "ssqrt,dsqrt") 125 1.1 mrg (eq_attr "cpu" "rs64a")) 126 1.1 mrg "mciu_rs64,fpu_rs64*49") 127 1.1 mrg 128 1.1 mrg (define_insn_reservation "rs64a-mfcr" 2 129 1.1 mrg (and (eq_attr "type" "mfcr") 130 1.1 mrg (eq_attr "cpu" "rs64a")) 131 1.1 mrg "lsu_rs64") 132 1.1 mrg 133 1.1 mrg (define_insn_reservation "rs64a-mtcr" 3 134 1.1 mrg (and (eq_attr "type" "mtcr") 135 1.1 mrg (eq_attr "cpu" "rs64a")) 136 1.1 mrg "lsu_rs64") 137 1.1 mrg 138 1.1 mrg (define_insn_reservation "rs64a-mtjmpr" 3 139 1.1 mrg (and (eq_attr "type" "mtjmpr") 140 1.1 mrg (eq_attr "cpu" "rs64a")) 141 1.1 mrg "lsu_rs64") 142 1.1 mrg 143 1.1 mrg (define_insn_reservation "rs64a-mfjmpr" 2 144 1.1 mrg (and (eq_attr "type" "mfjmpr") 145 1.1 mrg (eq_attr "cpu" "rs64a")) 146 1.1 mrg "lsu_rs64") 147 1.1 mrg 148 1.1 mrg (define_insn_reservation "rs64a-jmpreg" 1 149 1.9 mrg (and (eq_attr "type" "jmpreg,branch,cr_logical") 150 1.1 mrg (eq_attr "cpu" "rs64a")) 151 1.1 mrg "bpu_rs64") 152 1.1 mrg 153 1.1 mrg (define_insn_reservation "rs64a-isync" 6 154 1.1 mrg (and (eq_attr "type" "isync") 155 1.1 mrg (eq_attr "cpu" "rs64a")) 156 1.1 mrg "bpu_rs64") 157 1.1 mrg 158 1.1 mrg (define_insn_reservation "rs64a-sync" 1 159 1.1 mrg (and (eq_attr "type" "sync") 160 1.1 mrg (eq_attr "cpu" "rs64a")) 161 1.1 mrg "lsu_rs64") 162 1.1 mrg 163
Indexes created Wed Apr 15 00:22:22 UTC 2026