rs64.md revision 1.1.1.2
1 1.1 mrg ;; Scheduling description for IBM RS64 processors. 2 1.1.1.2 mrg ;; Copyright (C) 2003-2013 Free Software Foundation, Inc. 3 1.1 mrg ;; 4 1.1 mrg ;; This file is part of GCC. 5 1.1 mrg 6 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify it 7 1.1 mrg ;; under the terms of the GNU General Public License as published 8 1.1 mrg ;; by the Free Software Foundation; either version 3, or (at your 9 1.1 mrg ;; option) any later version. 10 1.1 mrg 11 1.1 mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT 12 1.1 mrg ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 1.1 mrg ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 1.1 mrg ;; License for more details. 15 1.1 mrg 16 1.1 mrg ;; You should have received a copy of the GNU General Public License 17 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 18 1.1 mrg ;; <http://www.gnu.org/licenses/>. 19 1.1 mrg 20 1.1 mrg (define_automaton "rs64,rs64fp") 21 1.1 mrg (define_cpu_unit "iu_rs64" "rs64") 22 1.1 mrg (define_cpu_unit "mciu_rs64" "rs64") 23 1.1 mrg (define_cpu_unit "fpu_rs64" "rs64fp") 24 1.1 mrg (define_cpu_unit "lsu_rs64,bpu_rs64" "rs64") 25 1.1 mrg 26 1.1 mrg ;; RS64a 64-bit IU, LSU, FPU, BPU 27 1.1 mrg 28 1.1 mrg (define_insn_reservation "rs64a-load" 2 29 1.1 mrg (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") 30 1.1 mrg (eq_attr "cpu" "rs64a")) 31 1.1 mrg "lsu_rs64") 32 1.1 mrg 33 1.1 mrg (define_insn_reservation "rs64a-store" 2 34 1.1 mrg (and (eq_attr "type" "store,store_ux,store_u,fpstore,fpstore_ux,fpstore_u") 35 1.1 mrg (eq_attr "cpu" "rs64a")) 36 1.1 mrg "lsu_rs64") 37 1.1 mrg 38 1.1 mrg (define_insn_reservation "rs64a-fpload" 3 39 1.1 mrg (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 40 1.1 mrg (eq_attr "cpu" "rs64a")) 41 1.1 mrg "lsu_rs64") 42 1.1 mrg 43 1.1 mrg (define_insn_reservation "rs64a-llsc" 2 44 1.1 mrg (and (eq_attr "type" "load_l,store_c") 45 1.1 mrg (eq_attr "cpu" "rs64a")) 46 1.1 mrg "lsu_rs64") 47 1.1 mrg 48 1.1 mrg (define_insn_reservation "rs64a-integer" 1 49 1.1 mrg (and (eq_attr "type" "integer,insert_word,insert_dword,shift,trap,\ 50 1.1 mrg var_shift_rotate,cntlz,exts,isel") 51 1.1 mrg (eq_attr "cpu" "rs64a")) 52 1.1 mrg "iu_rs64") 53 1.1 mrg 54 1.1 mrg (define_insn_reservation "rs64a-two" 1 55 1.1 mrg (and (eq_attr "type" "two") 56 1.1 mrg (eq_attr "cpu" "rs64a")) 57 1.1 mrg "iu_rs64,iu_rs64") 58 1.1 mrg 59 1.1 mrg (define_insn_reservation "rs64a-three" 1 60 1.1 mrg (and (eq_attr "type" "three") 61 1.1 mrg (eq_attr "cpu" "rs64a")) 62 1.1 mrg "iu_rs64,iu_rs64,iu_rs64") 63 1.1 mrg 64 1.1 mrg (define_insn_reservation "rs64a-imul" 20 65 1.1 mrg (and (eq_attr "type" "imul,imul_compare") 66 1.1 mrg (eq_attr "cpu" "rs64a")) 67 1.1 mrg "mciu_rs64*13") 68 1.1 mrg 69 1.1 mrg (define_insn_reservation "rs64a-imul2" 12 70 1.1 mrg (and (eq_attr "type" "imul2") 71 1.1 mrg (eq_attr "cpu" "rs64a")) 72 1.1 mrg "mciu_rs64*5") 73 1.1 mrg 74 1.1 mrg (define_insn_reservation "rs64a-imul3" 8 75 1.1 mrg (and (eq_attr "type" "imul3") 76 1.1 mrg (eq_attr "cpu" "rs64a")) 77 1.1 mrg "mciu_rs64*2") 78 1.1 mrg 79 1.1 mrg (define_insn_reservation "rs64a-lmul" 34 80 1.1 mrg (and (eq_attr "type" "lmul,lmul_compare") 81 1.1 mrg (eq_attr "cpu" "rs64a")) 82 1.1 mrg "mciu_rs64*34") 83 1.1 mrg 84 1.1 mrg (define_insn_reservation "rs64a-idiv" 66 85 1.1 mrg (and (eq_attr "type" "idiv") 86 1.1 mrg (eq_attr "cpu" "rs64a")) 87 1.1 mrg "mciu_rs64*66") 88 1.1 mrg 89 1.1 mrg (define_insn_reservation "rs64a-ldiv" 66 90 1.1 mrg (and (eq_attr "type" "ldiv") 91 1.1 mrg (eq_attr "cpu" "rs64a")) 92 1.1 mrg "mciu_rs64*66") 93 1.1 mrg 94 1.1 mrg (define_insn_reservation "rs64a-compare" 3 95 1.1 mrg (and (eq_attr "type" "cmp,fast_compare,compare,\ 96 1.1 mrg delayed_compare,var_delayed_compare") 97 1.1 mrg (eq_attr "cpu" "rs64a")) 98 1.1 mrg "iu_rs64,nothing,bpu_rs64") 99 1.1 mrg 100 1.1 mrg (define_insn_reservation "rs64a-fpcompare" 5 101 1.1 mrg (and (eq_attr "type" "fpcompare") 102 1.1 mrg (eq_attr "cpu" "rs64a")) 103 1.1 mrg "mciu_rs64,fpu_rs64,bpu_rs64") 104 1.1 mrg 105 1.1 mrg (define_insn_reservation "rs64a-fp" 4 106 1.1 mrg (and (eq_attr "type" "fp,dmul") 107 1.1 mrg (eq_attr "cpu" "rs64a")) 108 1.1 mrg "mciu_rs64,fpu_rs64") 109 1.1 mrg 110 1.1 mrg (define_insn_reservation "rs64a-sdiv" 31 111 1.1 mrg (and (eq_attr "type" "sdiv,ddiv") 112 1.1 mrg (eq_attr "cpu" "rs64a")) 113 1.1 mrg "mciu_rs64,fpu_rs64*31") 114 1.1 mrg 115 1.1 mrg (define_insn_reservation "rs64a-sqrt" 49 116 1.1 mrg (and (eq_attr "type" "ssqrt,dsqrt") 117 1.1 mrg (eq_attr "cpu" "rs64a")) 118 1.1 mrg "mciu_rs64,fpu_rs64*49") 119 1.1 mrg 120 1.1 mrg (define_insn_reservation "rs64a-mfcr" 2 121 1.1 mrg (and (eq_attr "type" "mfcr") 122 1.1 mrg (eq_attr "cpu" "rs64a")) 123 1.1 mrg "lsu_rs64") 124 1.1 mrg 125 1.1 mrg (define_insn_reservation "rs64a-mtcr" 3 126 1.1 mrg (and (eq_attr "type" "mtcr") 127 1.1 mrg (eq_attr "cpu" "rs64a")) 128 1.1 mrg "lsu_rs64") 129 1.1 mrg 130 1.1 mrg (define_insn_reservation "rs64a-mtjmpr" 3 131 1.1 mrg (and (eq_attr "type" "mtjmpr") 132 1.1 mrg (eq_attr "cpu" "rs64a")) 133 1.1 mrg "lsu_rs64") 134 1.1 mrg 135 1.1 mrg (define_insn_reservation "rs64a-mfjmpr" 2 136 1.1 mrg (and (eq_attr "type" "mfjmpr") 137 1.1 mrg (eq_attr "cpu" "rs64a")) 138 1.1 mrg "lsu_rs64") 139 1.1 mrg 140 1.1 mrg (define_insn_reservation "rs64a-jmpreg" 1 141 1.1 mrg (and (eq_attr "type" "jmpreg,branch,cr_logical,delayed_cr") 142 1.1 mrg (eq_attr "cpu" "rs64a")) 143 1.1 mrg "bpu_rs64") 144 1.1 mrg 145 1.1 mrg (define_insn_reservation "rs64a-isync" 6 146 1.1 mrg (and (eq_attr "type" "isync") 147 1.1 mrg (eq_attr "cpu" "rs64a")) 148 1.1 mrg "bpu_rs64") 149 1.1 mrg 150 1.1 mrg (define_insn_reservation "rs64a-sync" 1 151 1.1 mrg (and (eq_attr "type" "sync") 152 1.1 mrg (eq_attr "cpu" "rs64a")) 153 1.1 mrg "lsu_rs64") 154 1.1 mrg 155
Indexes created Fri Apr 24 00:22:58 UTC 2026