1 1.1 mrg ;;- Instruction patterns for the System z vector facility 2 1.7 mrg ;; Copyright (C) 2015-2022 Free Software Foundation, Inc. 3 1.1 mrg ;; Contributed by Andreas Krebbel (Andreas.Krebbel (a] de.ibm.com) 4 1.1 mrg 5 1.1 mrg ;; This file is part of GCC. 6 1.1 mrg 7 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify it under 8 1.1 mrg ;; the terms of the GNU General Public License as published by the Free 9 1.1 mrg ;; Software Foundation; either version 3, or (at your option) any later 10 1.1 mrg ;; version. 11 1.1 mrg 12 1.1 mrg ;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 1.1 mrg ;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 1.1 mrg ;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 1.1 mrg ;; for more details. 16 1.1 mrg 17 1.1 mrg ;; You should have received a copy of the GNU General Public License 18 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 19 1.1 mrg ;; <http://www.gnu.org/licenses/>. 20 1.1 mrg 21 1.1 mrg ; All vector modes supported in a vector register 22 1.1 mrg (define_mode_iterator V 23 1.1 mrg [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF 24 1.1 mrg V2SF V4SF V1DF V2DF]) 25 1.1 mrg (define_mode_iterator VT 26 1.1 mrg [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF 27 1.1 mrg V2SF V4SF V1DF V2DF V1TF V1TI TI]) 28 1.1 mrg 29 1.3 mrg ; All modes directly supported by the hardware having full vector reg size 30 1.7 mrg ; V_HW2 is for having two iterators expanding independently e.g. vcond. 31 1.7 mrg ; It's similar to V_HW, but not fully identical: V1TI is not included, because 32 1.7 mrg ; there are no 128-bit compares. 33 1.7 mrg (define_mode_iterator V_HW [V16QI V8HI V4SI V2DI (V1TI "TARGET_VXE") V2DF 34 1.7 mrg (V4SF "TARGET_VXE") (V1TF "TARGET_VXE") 35 1.7 mrg (TF "TARGET_VXE")]) 36 1.7 mrg (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE") 37 1.7 mrg (V1TF "TARGET_VXE") (TF "TARGET_VXE")]) 38 1.3 mrg 39 1.5 mrg (define_mode_iterator VT_HW_HSDT [V8HI V4SI V4SF V2DI V2DF V1TI V1TF TI TF]) 40 1.5 mrg (define_mode_iterator V_HW_HSD [V8HI V4SI (V4SF "TARGET_VXE") V2DI V2DF]) 41 1.3 mrg 42 1.1 mrg ; Including TI for instructions that support it (va, vn, ...) 43 1.3 mrg (define_mode_iterator VT_HW [V16QI V8HI V4SI V2DI V2DF V1TI TI (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")]) 44 1.1 mrg 45 1.1 mrg ; All full size integer vector modes supported in a vector register + TImode 46 1.1 mrg (define_mode_iterator VIT_HW [V16QI V8HI V4SI V2DI V1TI TI]) 47 1.1 mrg (define_mode_iterator VI_HW [V16QI V8HI V4SI V2DI]) 48 1.1 mrg (define_mode_iterator VI_HW_QHS [V16QI V8HI V4SI]) 49 1.3 mrg (define_mode_iterator VI_HW_HSD [V8HI V4SI V2DI]) 50 1.3 mrg (define_mode_iterator VI_HW_HS [V8HI V4SI]) 51 1.1 mrg (define_mode_iterator VI_HW_QH [V16QI V8HI]) 52 1.7 mrg 53 1.7 mrg ; Directly supported vector modes with a certain number of elements 54 1.7 mrg (define_mode_iterator V_HW_2 [V2DI V2DF]) 55 1.7 mrg (define_mode_iterator V_HW_4 [V4SI V4SF]) 56 1.1 mrg 57 1.1 mrg ; All integer vector modes supported in a vector register + TImode 58 1.1 mrg (define_mode_iterator VIT [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1TI TI]) 59 1.1 mrg (define_mode_iterator VI [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI]) 60 1.1 mrg (define_mode_iterator VI_QHS [V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI]) 61 1.1 mrg 62 1.3 mrg (define_mode_iterator VFT [(V1SF "TARGET_VXE") (V2SF "TARGET_VXE") (V4SF "TARGET_VXE") 63 1.3 mrg V1DF V2DF 64 1.7 mrg (V1TF "TARGET_VXE") (TF "TARGET_VXE")]) 65 1.7 mrg 66 1.7 mrg ; All modes present in V_HW and VFT. 67 1.7 mrg (define_mode_iterator V_HW_FT [V16QI V8HI V4SI V2DI (V1TI "TARGET_VXE") V1DF 68 1.7 mrg V2DF (V1SF "TARGET_VXE") (V2SF "TARGET_VXE") 69 1.7 mrg (V4SF "TARGET_VXE") (V1TF "TARGET_VXE") 70 1.7 mrg (TF "TARGET_VXE")]) 71 1.3 mrg 72 1.3 mrg ; FP vector modes directly supported by the HW. This does not include 73 1.3 mrg ; vector modes using only part of a vector register and should be used 74 1.3 mrg ; for instructions which might trigger IEEE exceptions. 75 1.7 mrg (define_mode_iterator VF_HW [(V4SF "TARGET_VXE") V2DF (V1TF "TARGET_VXE") 76 1.7 mrg (TF "TARGET_VXE")]) 77 1.3 mrg 78 1.1 mrg (define_mode_iterator V_8 [V1QI]) 79 1.1 mrg (define_mode_iterator V_16 [V2QI V1HI]) 80 1.1 mrg (define_mode_iterator V_32 [V4QI V2HI V1SI V1SF]) 81 1.1 mrg (define_mode_iterator V_64 [V8QI V4HI V2SI V2SF V1DI V1DF]) 82 1.7 mrg (define_mode_iterator V_128 [V16QI V8HI V4SI V4SF V2DI V2DF V1TI V1TF 83 1.7 mrg (TF "TARGET_VXE")]) 84 1.3 mrg (define_mode_iterator V_128_NOSINGLE [V16QI V8HI V4SI V4SF V2DI V2DF]) 85 1.3 mrg 86 1.5 mrg ; 32 bit int<->fp vector conversion instructions are available since VXE2 (z15). 87 1.5 mrg (define_mode_iterator VX_VEC_CONV_BFP [V2DF (V4SF "TARGET_VXE2")]) 88 1.5 mrg (define_mode_iterator VX_VEC_CONV_INT [V2DI (V4SI "TARGET_VXE2")]) 89 1.5 mrg 90 1.3 mrg ; Empty string for all but TImode. This is used to hide the TImode 91 1.3 mrg ; expander name in case it is defined already. See addti3 for an 92 1.3 mrg ; example. 93 1.3 mrg (define_mode_attr ti* [(V1QI "") (V2QI "") (V4QI "") (V8QI "") (V16QI "") 94 1.3 mrg (V1HI "") (V2HI "") (V4HI "") (V8HI "") 95 1.3 mrg (V1SI "") (V2SI "") (V4SI "") 96 1.3 mrg (V1DI "") (V2DI "") 97 1.3 mrg (V1TI "") (TI "*") 98 1.3 mrg (V1SF "") (V2SF "") (V4SF "") 99 1.3 mrg (V1DF "") (V2DF "") 100 1.3 mrg (V1TF "") (TF "")]) 101 1.1 mrg 102 1.7 mrg ;; Facilitate dispatching TFmode expanders on z14+. 103 1.7 mrg (define_mode_attr tf_vr [(TF "_vr") (V4SF "") (V2DF "") (V1TF "") (V1SF "") 104 1.7 mrg (V2SF "") (V1DF "") (V16QI "") (V8HI "") (V4SI "") 105 1.7 mrg (V2DI "") (V1TI "")]) 106 1.7 mrg 107 1.1 mrg ; The element type of the vector. 108 1.1 mrg (define_mode_attr non_vec[(V1QI "QI") (V2QI "QI") (V4QI "QI") (V8QI "QI") (V16QI "QI") 109 1.1 mrg (V1HI "HI") (V2HI "HI") (V4HI "HI") (V8HI "HI") 110 1.1 mrg (V1SI "SI") (V2SI "SI") (V4SI "SI") 111 1.1 mrg (V1DI "DI") (V2DI "DI") 112 1.3 mrg (V1TI "TI") (TI "TI") 113 1.1 mrg (V1SF "SF") (V2SF "SF") (V4SF "SF") 114 1.1 mrg (V1DF "DF") (V2DF "DF") 115 1.3 mrg (V1TF "TF") (TF "TF")]) 116 1.1 mrg 117 1.4 mrg ; Like above, but in lower case. 118 1.4 mrg (define_mode_attr non_vec_l[(V1QI "qi") (V2QI "qi") (V4QI "qi") (V8QI "qi") 119 1.4 mrg (V16QI "qi") 120 1.4 mrg (V1HI "hi") (V2HI "hi") (V4HI "hi") (V8HI "hi") 121 1.4 mrg (V1SI "si") (V2SI "si") (V4SI "si") 122 1.4 mrg (V1DI "di") (V2DI "di") 123 1.4 mrg (V1TI "ti") (TI "ti") 124 1.4 mrg (V1SF "sf") (V2SF "sf") (V4SF "sf") 125 1.4 mrg (V1DF "df") (V2DF "df") 126 1.4 mrg (V1TF "tf") (TF "tf")]) 127 1.4 mrg 128 1.3 mrg ; The instruction suffix for integer instructions and instructions 129 1.3 mrg ; which do not care about whether it is floating point or integer. 130 1.1 mrg (define_mode_attr bhfgq[(V1QI "b") (V2QI "b") (V4QI "b") (V8QI "b") (V16QI "b") 131 1.1 mrg (V1HI "h") (V2HI "h") (V4HI "h") (V8HI "h") 132 1.1 mrg (V1SI "f") (V2SI "f") (V4SI "f") 133 1.1 mrg (V1DI "g") (V2DI "g") 134 1.1 mrg (V1TI "q") (TI "q") 135 1.1 mrg (V1SF "f") (V2SF "f") (V4SF "f") 136 1.1 mrg (V1DF "g") (V2DF "g") 137 1.7 mrg (V1TF "q") (TF "q")]) 138 1.1 mrg 139 1.1 mrg ; This is for vmalhw. It gets an 'w' attached to avoid confusion with 140 1.1 mrg ; multiply and add logical high vmalh. 141 1.1 mrg (define_mode_attr w [(V1QI "") (V2QI "") (V4QI "") (V8QI "") (V16QI "") 142 1.1 mrg (V1HI "w") (V2HI "w") (V4HI "w") (V8HI "w") 143 1.1 mrg (V1SI "") (V2SI "") (V4SI "") 144 1.1 mrg (V1DI "") (V2DI "")]) 145 1.1 mrg 146 1.1 mrg ; Resulting mode of a vector comparison. For floating point modes an 147 1.1 mrg ; integer vector mode with the same element size is picked. 148 1.7 mrg (define_mode_attr TOINTVEC [(V1QI "V1QI") (V2QI "V2QI") (V4QI "V4QI") (V8QI "V8QI") (V16QI "V16QI") 149 1.1 mrg (V1HI "V1HI") (V2HI "V2HI") (V4HI "V4HI") (V8HI "V8HI") 150 1.1 mrg (V1SI "V1SI") (V2SI "V2SI") (V4SI "V4SI") 151 1.1 mrg (V1DI "V1DI") (V2DI "V2DI") 152 1.1 mrg (V1TI "V1TI") 153 1.1 mrg (V1SF "V1SI") (V2SF "V2SI") (V4SF "V4SI") 154 1.1 mrg (V1DF "V1DI") (V2DF "V2DI") 155 1.7 mrg (V1TF "V1TI") (TF "V1TI")]) 156 1.7 mrg 157 1.7 mrg (define_mode_attr tointvec [(V1QI "v1qi") (V2QI "v2qi") (V4QI "v4qi") (V8QI "v8qi") (V16QI "v16qi") 158 1.7 mrg (V1HI "v1hi") (V2HI "v2hi") (V4HI "v4hi") (V8HI "v8hi") 159 1.7 mrg (V1SI "v1si") (V2SI "v2si") (V4SI "v4si") 160 1.7 mrg (V1DI "v1di") (V2DI "v2di") 161 1.7 mrg (V1TI "v1ti") 162 1.7 mrg (V1SF "v1si") (V2SF "v2si") (V4SF "v4si") 163 1.7 mrg (V1DF "v1di") (V2DF "v2di") 164 1.7 mrg (V1TF "v1ti") (TF "v1ti")]) 165 1.7 mrg 166 1.3 mrg (define_mode_attr vw [(SF "w") (V1SF "w") (V2SF "v") (V4SF "v") 167 1.3 mrg (DF "w") (V1DF "w") (V2DF "v") 168 1.3 mrg (TF "w") (V1TF "w")]) 169 1.3 mrg 170 1.3 mrg (define_mode_attr sdx [(SF "s") (V1SF "s") (V2SF "s") (V4SF "s") 171 1.3 mrg (DF "d") (V1DF "d") (V2DF "d") 172 1.3 mrg (TF "x") (V1TF "x")]) 173 1.1 mrg 174 1.7 mrg ; Vector with widened element size but half the number of elements. 175 1.1 mrg (define_mode_attr vec_double [(V1QI "V1HI") (V2QI "V1HI") (V4QI "V2HI") (V8QI "V4HI") (V16QI "V8HI") 176 1.1 mrg (V1HI "V1SI") (V2HI "V1SI") (V4HI "V2SI") (V8HI "V4SI") 177 1.1 mrg (V1SI "V1DI") (V2SI "V1DI") (V4SI "V2DI") 178 1.1 mrg (V1DI "V1TI") (V2DI "V1TI") 179 1.1 mrg (V1SF "V1DF") (V2SF "V1DF") (V4SF "V2DF")]) 180 1.1 mrg 181 1.7 mrg ; Vector with shrinked element size but twice the number of elements. 182 1.1 mrg (define_mode_attr vec_half [(V1HI "V2QI") (V2HI "V4QI") (V4HI "V8QI") (V8HI "V16QI") 183 1.1 mrg (V1SI "V2HI") (V2SI "V4HI") (V4SI "V8HI") 184 1.1 mrg (V1DI "V2SI") (V2DI "V4SI") 185 1.1 mrg (V1TI "V2DI") 186 1.1 mrg (V1DF "V2SF") (V2DF "V4SF") 187 1.1 mrg (V1TF "V1DF")]) 188 1.1 mrg 189 1.7 mrg ; Vector with twice the number of elements but same element size. 190 1.7 mrg (define_mode_attr vec_2x_nelts [(V1QI "V2QI") (V2QI "V4QI") (V4QI "V8QI") (V8QI "V16QI") (V16QI "V32QI") 191 1.7 mrg (V1HI "V2HI") (V2HI "V4HI") (V4HI "V8HI") (V8HI "V16HI") 192 1.7 mrg (V1SI "V2SI") (V2SI "V4SI") (V4SI "V8SI") 193 1.7 mrg (V1DI "V2DI") (V2DI "V4DI") 194 1.7 mrg (V1SF "V2SF") (V2SF "V4SF") (V4SF "V8SF") 195 1.7 mrg (V1DF "V2DF") (V2DF "V4DF")]) 196 1.7 mrg 197 1.7 mrg ; Vector with widened element size and the same number of elements. 198 1.7 mrg (define_mode_attr vec_2x_wide [(V1QI "V1HI") (V2QI "V2HI") (V4QI "V4HI") (V8QI "V8HI") (V16QI "V16HI") 199 1.7 mrg (V1HI "V1SI") (V2HI "V2SI") (V4HI "V4SI") (V8HI "V8SI") 200 1.7 mrg (V1SI "V1DI") (V2SI "V2DI") (V4SI "V4DI") 201 1.7 mrg (V1DI "V1TI") (V2DI "V2TI") 202 1.7 mrg (V1SF "V1DF") (V2SF "V2DF") (V4SF "V4DF") 203 1.7 mrg (V1DF "V1TF") (V2DF "V2TF")]) 204 1.7 mrg 205 1.3 mrg ; Vector with half the element size AND half the number of elements. 206 1.3 mrg (define_mode_attr vec_halfhalf 207 1.3 mrg [(V2HI "V2QI") (V4HI "V4QI") (V8HI "V8QI") 208 1.3 mrg (V2SI "V2HI") (V4SI "V4HI") 209 1.3 mrg (V2DI "V2SI") 210 1.3 mrg (V2DF "V2SF")]) 211 1.3 mrg 212 1.3 mrg (define_mode_attr vec_halfnumelts 213 1.3 mrg [(V4SF "V2SF") (V4SI "V2SI")]) 214 1.3 mrg 215 1.1 mrg 216 1.1 mrg 217 1.1 mrg ; Comparison operators on int and fp compares which are directly 218 1.1 mrg ; supported by the HW. 219 1.1 mrg (define_code_iterator VICMP_HW_OP [eq gt gtu]) 220 1.1 mrg ; For int insn_cmp_op can be used in the insn name as well as in the asm output. 221 1.1 mrg (define_code_attr insn_cmp_op [(eq "eq") (gt "h") (gtu "hl") (ge "he")]) 222 1.1 mrg 223 1.1 mrg ; Flags for vector string instructions (vfae all 4, vfee only ZS and CS, vstrc all 4) 224 1.1 mrg (define_constants 225 1.1 mrg [(VSTRING_FLAG_IN 8) ; invert result 226 1.1 mrg (VSTRING_FLAG_RT 4) ; result type 227 1.1 mrg (VSTRING_FLAG_ZS 2) ; zero search 228 1.1 mrg (VSTRING_FLAG_CS 1)]) ; condition code set 229 1.1 mrg 230 1.1 mrg (include "vx-builtins.md") 231 1.1 mrg 232 1.1 mrg ; Full HW vector size moves 233 1.3 mrg 234 1.3 mrg ; We don't use lm/stm for 128 bit moves since these are slower than 235 1.3 mrg ; splitting it into separate moves. 236 1.3 mrg 237 1.3 mrg ; FIXME: More constants are possible by enabling jxx, jyy constraints 238 1.3 mrg ; for TImode (use double-int for the calculations) 239 1.3 mrg 240 1.3 mrg ; vgmb, vgmh, vgmf, vgmg, vrepib, vrepih, vrepif, vrepig 241 1.7 mrg (define_insn "mov<mode><tf_vr>" 242 1.3 mrg [(set (match_operand:V_128 0 "nonimmediate_operand" "=v,v,R, v, v, v, v, v,v,*d,*d,?o") 243 1.3 mrg (match_operand:V_128 1 "general_operand" " v,R,v,j00,jm1,jyy,jxx,jKK,d, v,dT,*d"))] 244 1.3 mrg "" 245 1.1 mrg "@ 246 1.1 mrg vlr\t%v0,%v1 247 1.5 mrg vl\t%v0,%1%A1 248 1.5 mrg vst\t%v1,%0%A0 249 1.1 mrg vzero\t%v0 250 1.1 mrg vone\t%v0 251 1.1 mrg vgbm\t%v0,%t1 252 1.1 mrg vgm<bhfgq>\t%v0,%s1,%e1 253 1.1 mrg vrepi<bhfgq>\t%v0,%h1 254 1.1 mrg vlvgp\t%v0,%1,%N1 255 1.3 mrg # 256 1.3 mrg # 257 1.1 mrg #" 258 1.3 mrg [(set_attr "cpu_facility" "vx,vx,vx,vx,vx,vx,vx,vx,vx,vx,*,*") 259 1.3 mrg (set_attr "op_type" "VRR,VRX,VRX,VRI,VRI,VRI,VRI,VRI,VRR,*,*,*")]) 260 1.1 mrg 261 1.7 mrg (define_expand "movtf" 262 1.7 mrg [(match_operand:TF 0 "nonimmediate_operand" "") 263 1.7 mrg (match_operand:TF 1 "general_operand" "")] 264 1.7 mrg "" 265 1.7 mrg { EXPAND_MOVTF(movtf); }) 266 1.7 mrg 267 1.3 mrg ; VR -> GPR, no instruction so split it into 64 element sets. 268 1.1 mrg (define_split 269 1.1 mrg [(set (match_operand:V_128 0 "register_operand" "") 270 1.1 mrg (match_operand:V_128 1 "register_operand" ""))] 271 1.1 mrg "TARGET_VX && GENERAL_REG_P (operands[0]) && VECTOR_REG_P (operands[1])" 272 1.1 mrg [(set (match_dup 2) 273 1.1 mrg (unspec:DI [(subreg:V2DI (match_dup 1) 0) 274 1.1 mrg (const_int 0)] UNSPEC_VEC_EXTRACT)) 275 1.1 mrg (set (match_dup 3) 276 1.1 mrg (unspec:DI [(subreg:V2DI (match_dup 1) 0) 277 1.1 mrg (const_int 1)] UNSPEC_VEC_EXTRACT))] 278 1.1 mrg { 279 1.1 mrg operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 280 1.1 mrg operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 281 1.1 mrg }) 282 1.1 mrg 283 1.3 mrg ; Split the 128 bit GPR move into two word mode moves 284 1.3 mrg ; s390_split_ok_p decides which part needs to be moved first. 285 1.3 mrg 286 1.3 mrg (define_split 287 1.3 mrg [(set (match_operand:V_128 0 "nonimmediate_operand" "") 288 1.3 mrg (match_operand:V_128 1 "general_operand" ""))] 289 1.3 mrg "reload_completed 290 1.3 mrg && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 291 1.3 mrg [(set (match_dup 2) (match_dup 4)) 292 1.3 mrg (set (match_dup 3) (match_dup 5))] 293 1.3 mrg { 294 1.3 mrg operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 295 1.3 mrg operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 296 1.3 mrg operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 297 1.3 mrg operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 298 1.3 mrg }) 299 1.3 mrg 300 1.3 mrg (define_split 301 1.3 mrg [(set (match_operand:V_128 0 "nonimmediate_operand" "") 302 1.3 mrg (match_operand:V_128 1 "general_operand" ""))] 303 1.3 mrg "reload_completed 304 1.3 mrg && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 305 1.3 mrg [(set (match_dup 2) (match_dup 4)) 306 1.3 mrg (set (match_dup 3) (match_dup 5))] 307 1.3 mrg { 308 1.3 mrg operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 309 1.3 mrg operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 310 1.3 mrg operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 311 1.3 mrg operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 312 1.3 mrg }) 313 1.3 mrg 314 1.3 mrg ; This is the vector equivalent to the TImode splitter in s390.md. It 315 1.3 mrg ; is required if both target GPRs occur in the source address operand. 316 1.3 mrg 317 1.3 mrg ; For non-s_operands at least one of the target GPRs does not conflict 318 1.3 mrg ; with the address operand and one of the splitters above will take 319 1.3 mrg ; over. 320 1.3 mrg (define_split 321 1.3 mrg [(set (match_operand:V_128 0 "register_operand" "") 322 1.3 mrg (match_operand:V_128 1 "memory_operand" ""))] 323 1.3 mrg "TARGET_ZARCH && reload_completed 324 1.3 mrg && !VECTOR_REG_P (operands[0]) 325 1.3 mrg && !s_operand (operands[1], VOIDmode)" 326 1.3 mrg [(set (match_dup 0) (match_dup 1))] 327 1.3 mrg { 328 1.3 mrg rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 329 1.3 mrg addr = gen_lowpart (Pmode, addr); 330 1.3 mrg s390_load_address (addr, XEXP (operands[1], 0)); 331 1.3 mrg operands[1] = replace_equiv_address (operands[1], addr); 332 1.3 mrg }) 333 1.3 mrg 334 1.1 mrg ; Moves for smaller vector modes. 335 1.1 mrg 336 1.1 mrg ; In these patterns only the vlr, vone, and vzero instructions write 337 1.1 mrg ; VR bytes outside the mode. This should be ok since we disallow 338 1.1 mrg ; formerly bigger modes being accessed with smaller modes via 339 1.1 mrg ; subreg. Note: The vone, vzero instructions could easily be replaced 340 1.1 mrg ; with vlei which would only access the bytes belonging to the mode. 341 1.1 mrg ; However, this would probably be slower. 342 1.1 mrg 343 1.1 mrg (define_insn "mov<mode>" 344 1.4 mrg [(set (match_operand:V_8 0 "nonimmediate_operand" "=v,v,d,v,R, v, v, v, v,d, Q, S, Q, S, d, d,d,R,T") 345 1.4 mrg (match_operand:V_8 1 "general_operand" " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,j00,jm1,jm1,j00,jm1,T,d,d"))] 346 1.4 mrg "TARGET_VX" 347 1.1 mrg "@ 348 1.1 mrg vlr\t%v0,%v1 349 1.1 mrg vlvgb\t%v0,%1,0 350 1.1 mrg vlgvb\t%0,%v1,0 351 1.1 mrg vleb\t%v0,%1,0 352 1.1 mrg vsteb\t%v1,%0,0 353 1.1 mrg vzero\t%v0 354 1.1 mrg vone\t%v0 355 1.1 mrg vgbm\t%v0,%t1 356 1.1 mrg vgm\t%v0,%s1,%e1 357 1.1 mrg lr\t%0,%1 358 1.1 mrg mvi\t%0,0 359 1.1 mrg mviy\t%0,0 360 1.7 mrg mvi\t%0,255 361 1.7 mrg mviy\t%0,255 362 1.1 mrg lhi\t%0,0 363 1.1 mrg lhi\t%0,-1 364 1.4 mrg llc\t%0,%1 365 1.1 mrg stc\t%1,%0 366 1.1 mrg stcy\t%1,%0" 367 1.4 mrg [(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SI,SIY,SI,SIY,RI,RI,RXY,RX,RXY")]) 368 1.1 mrg 369 1.1 mrg (define_insn "mov<mode>" 370 1.3 mrg [(set (match_operand:V_16 0 "nonimmediate_operand" "=v,v,d,v,R, v, v, v, v,d, Q, Q, d, d,d,d,d,R,T,b") 371 1.3 mrg (match_operand:V_16 1 "general_operand" " v,d,v,R,v,j00,jm1,jyy,jxx,d,j00,jm1,j00,jm1,R,T,b,d,d,d"))] 372 1.1 mrg "" 373 1.1 mrg "@ 374 1.1 mrg vlr\t%v0,%v1 375 1.1 mrg vlvgh\t%v0,%1,0 376 1.1 mrg vlgvh\t%0,%v1,0 377 1.1 mrg vleh\t%v0,%1,0 378 1.1 mrg vsteh\t%v1,%0,0 379 1.1 mrg vzero\t%v0 380 1.1 mrg vone\t%v0 381 1.1 mrg vgbm\t%v0,%t1 382 1.1 mrg vgm\t%v0,%s1,%e1 383 1.1 mrg lr\t%0,%1 384 1.1 mrg mvhhi\t%0,0 385 1.1 mrg mvhhi\t%0,-1 386 1.1 mrg lhi\t%0,0 387 1.1 mrg lhi\t%0,-1 388 1.1 mrg lh\t%0,%1 389 1.1 mrg lhy\t%0,%1 390 1.1 mrg lhrl\t%0,%1 391 1.1 mrg sth\t%1,%0 392 1.1 mrg sthy\t%1,%0 393 1.1 mrg sthrl\t%1,%0" 394 1.1 mrg [(set_attr "op_type" "VRR,VRS,VRS,VRX,VRX,VRI,VRI,VRI,VRI,RR,SIL,SIL,RI,RI,RX,RXY,RIL,RX,RXY,RIL")]) 395 1.1 mrg 396 1.1 mrg (define_insn "mov<mode>" 397 1.3 mrg [(set (match_operand:V_32 0 "nonimmediate_operand" "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, Q, Q, d, d,d,d,d,d,R,T,b") 398 1.3 mrg (match_operand:V_32 1 "general_operand" " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,b,d,R,T,d,d,d"))] 399 1.1 mrg "TARGET_VX" 400 1.1 mrg "@ 401 1.3 mrg ldr\t%v0,%v1 402 1.1 mrg lde\t%0,%1 403 1.1 mrg ley\t%0,%1 404 1.1 mrg ste\t%1,%0 405 1.1 mrg stey\t%1,%0 406 1.1 mrg vlr\t%v0,%v1 407 1.1 mrg vlvgf\t%v0,%1,0 408 1.1 mrg vlgvf\t%0,%v1,0 409 1.1 mrg vlef\t%v0,%1,0 410 1.1 mrg vstef\t%1,%0,0 411 1.1 mrg lzer\t%v0 412 1.1 mrg vzero\t%v0 413 1.1 mrg vone\t%v0 414 1.1 mrg vgbm\t%v0,%t1 415 1.1 mrg vgm\t%v0,%s1,%e1 416 1.1 mrg mvhi\t%0,0 417 1.1 mrg mvhi\t%0,-1 418 1.1 mrg lhi\t%0,0 419 1.1 mrg lhi\t%0,-1 420 1.1 mrg lrl\t%0,%1 421 1.1 mrg lr\t%0,%1 422 1.1 mrg l\t%0,%1 423 1.1 mrg ly\t%0,%1 424 1.1 mrg st\t%1,%0 425 1.1 mrg sty\t%1,%0 426 1.1 mrg strl\t%1,%0" 427 1.3 mrg [(set_attr "op_type" "RR,RXE,RXY,RX,RXY,VRR,VRS,VRS,VRX,VRX,RRE,VRI,VRI,VRI,VRI,SIL,SIL,RI,RI, 428 1.1 mrg RIL,RR,RX,RXY,RX,RXY,RIL")]) 429 1.1 mrg 430 1.1 mrg (define_insn "mov<mode>" 431 1.1 mrg [(set (match_operand:V_64 0 "nonimmediate_operand" 432 1.3 mrg "=f,f,f,R,T,v,v,d,v,R, f, v, v, v, v, Q, Q, d, d,f,d,d,d,d,T,b") 433 1.1 mrg (match_operand:V_64 1 "general_operand" 434 1.3 mrg " f,R,T,f,f,v,d,v,R,v,j00,j00,jm1,jyy,jxx,j00,jm1,j00,jm1,d,f,b,d,T,d,d"))] 435 1.1 mrg "TARGET_ZARCH" 436 1.1 mrg "@ 437 1.1 mrg ldr\t%0,%1 438 1.1 mrg ld\t%0,%1 439 1.1 mrg ldy\t%0,%1 440 1.1 mrg std\t%1,%0 441 1.1 mrg stdy\t%1,%0 442 1.1 mrg vlr\t%v0,%v1 443 1.1 mrg vlvgg\t%v0,%1,0 444 1.1 mrg vlgvg\t%0,%v1,0 445 1.1 mrg vleg\t%v0,%1,0 446 1.1 mrg vsteg\t%v1,%0,0 447 1.1 mrg lzdr\t%0 448 1.1 mrg vzero\t%v0 449 1.1 mrg vone\t%v0 450 1.1 mrg vgbm\t%v0,%t1 451 1.1 mrg vgm\t%v0,%s1,%e1 452 1.1 mrg mvghi\t%0,0 453 1.1 mrg mvghi\t%0,-1 454 1.1 mrg lghi\t%0,0 455 1.1 mrg lghi\t%0,-1 456 1.1 mrg ldgr\t%0,%1 457 1.1 mrg lgdr\t%0,%1 458 1.1 mrg lgrl\t%0,%1 459 1.1 mrg lgr\t%0,%1 460 1.1 mrg lg\t%0,%1 461 1.1 mrg stg\t%1,%0 462 1.1 mrg stgrl\t%1,%0" 463 1.1 mrg [(set_attr "op_type" "RRE,RX,RXY,RX,RXY,VRR,VRS,VRS,VRX,VRX,RRE,VRI,VRI,VRI,VRI, 464 1.1 mrg SIL,SIL,RI,RI,RRE,RRE,RIL,RR,RXY,RXY,RIL")]) 465 1.1 mrg 466 1.1 mrg 467 1.1 mrg ; vec_load_lanes? 468 1.1 mrg 469 1.1 mrg ; vec_store_lanes? 470 1.1 mrg 471 1.3 mrg ; vec_set is supposed to *modify* an existing vector so operand 0 is 472 1.3 mrg ; duplicated as input operand. 473 1.3 mrg (define_expand "vec_set<mode>" 474 1.3 mrg [(set (match_operand:V 0 "register_operand" "") 475 1.3 mrg (unspec:V [(match_operand:<non_vec> 1 "general_operand" "") 476 1.3 mrg (match_operand:SI 2 "nonmemory_operand" "") 477 1.3 mrg (match_dup 0)] 478 1.3 mrg UNSPEC_VEC_SET))] 479 1.3 mrg "TARGET_VX") 480 1.3 mrg 481 1.1 mrg ; FIXME: Support also vector mode operands for 1 482 1.1 mrg ; FIXME: A target memory operand seems to be useful otherwise we end 483 1.1 mrg ; up with vl vlvgg vst. Shouldn't the middle-end be able to handle 484 1.1 mrg ; that itself? 485 1.3 mrg ; vlvgb, vlvgh, vlvgf, vlvgg, vleb, vleh, vlef, vleg, vleib, vleih, vleif, vleig 486 1.1 mrg (define_insn "*vec_set<mode>" 487 1.3 mrg [(set (match_operand:V 0 "register_operand" "=v,v,v") 488 1.3 mrg (unspec:V [(match_operand:<non_vec> 1 "general_operand" "d,R,K") 489 1.3 mrg (match_operand:SI 2 "nonmemory_operand" "an,I,I") 490 1.3 mrg (match_operand:V 3 "register_operand" "0,0,0")] 491 1.1 mrg UNSPEC_VEC_SET))] 492 1.3 mrg "TARGET_VX 493 1.3 mrg && (!CONST_INT_P (operands[2]) 494 1.3 mrg || UINTVAL (operands[2]) < GET_MODE_NUNITS (<V:MODE>mode))" 495 1.1 mrg "@ 496 1.1 mrg vlvg<bhfgq>\t%v0,%1,%Y2 497 1.1 mrg vle<bhfgq>\t%v0,%1,%2 498 1.1 mrg vlei<bhfgq>\t%v0,%1,%2" 499 1.1 mrg [(set_attr "op_type" "VRS,VRX,VRI")]) 500 1.1 mrg 501 1.3 mrg ; vlvgb, vlvgh, vlvgf, vlvgg 502 1.3 mrg (define_insn "*vec_set<mode>_plus" 503 1.3 mrg [(set (match_operand:V 0 "register_operand" "=v") 504 1.3 mrg (unspec:V [(match_operand:<non_vec> 1 "general_operand" "d") 505 1.3 mrg (plus:SI (match_operand:SI 2 "register_operand" "a") 506 1.3 mrg (match_operand:SI 4 "const_int_operand" "n")) 507 1.3 mrg (match_operand:V 3 "register_operand" "0")] 508 1.3 mrg UNSPEC_VEC_SET))] 509 1.3 mrg "TARGET_VX" 510 1.3 mrg "vlvg<bhfgq>\t%v0,%1,%Y4(%2)" 511 1.3 mrg [(set_attr "op_type" "VRS")]) 512 1.3 mrg 513 1.1 mrg 514 1.1 mrg ; FIXME: Support also vector mode operands for 0 515 1.1 mrg ; FIXME: This should be (vec_select ..) or something but it does only allow constant selectors :( 516 1.1 mrg ; This is used via RTL standard name as well as for expanding the builtin 517 1.4 mrg (define_expand "vec_extract<mode><non_vec_l>" 518 1.3 mrg [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "") 519 1.3 mrg (unspec:<non_vec> [(match_operand:V 1 "register_operand" "") 520 1.3 mrg (match_operand:SI 2 "nonmemory_operand" "")] 521 1.3 mrg UNSPEC_VEC_EXTRACT))] 522 1.3 mrg "TARGET_VX") 523 1.3 mrg 524 1.3 mrg ; vlgvb, vlgvh, vlgvf, vlgvg, vsteb, vsteh, vstef, vsteg 525 1.3 mrg (define_insn "*vec_extract<mode>" 526 1.3 mrg [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d,R") 527 1.3 mrg (unspec:<non_vec> [(match_operand:V 1 "register_operand" "v,v") 528 1.3 mrg (match_operand:SI 2 "nonmemory_operand" "an,I")] 529 1.1 mrg UNSPEC_VEC_EXTRACT))] 530 1.3 mrg "TARGET_VX 531 1.3 mrg && (!CONST_INT_P (operands[2]) 532 1.3 mrg || UINTVAL (operands[2]) < GET_MODE_NUNITS (<V:MODE>mode))" 533 1.1 mrg "@ 534 1.1 mrg vlgv<bhfgq>\t%0,%v1,%Y2 535 1.1 mrg vste<bhfgq>\t%v1,%0,%2" 536 1.1 mrg [(set_attr "op_type" "VRS,VRX")]) 537 1.1 mrg 538 1.3 mrg ; vlgvb, vlgvh, vlgvf, vlgvg 539 1.3 mrg (define_insn "*vec_extract<mode>_plus" 540 1.3 mrg [(set (match_operand:<non_vec> 0 "nonimmediate_operand" "=d") 541 1.3 mrg (unspec:<non_vec> [(match_operand:V 1 "register_operand" "v") 542 1.3 mrg (plus:SI (match_operand:SI 2 "nonmemory_operand" "a") 543 1.3 mrg (match_operand:SI 3 "const_int_operand" "n"))] 544 1.3 mrg UNSPEC_VEC_EXTRACT))] 545 1.3 mrg "TARGET_VX" 546 1.3 mrg "vlgv<bhfgq>\t%0,%v1,%Y3(%2)" 547 1.3 mrg [(set_attr "op_type" "VRS")]) 548 1.3 mrg 549 1.4 mrg (define_expand "vec_init<mode><non_vec_l>" 550 1.3 mrg [(match_operand:V_128 0 "register_operand" "") 551 1.3 mrg (match_operand:V_128 1 "nonmemory_operand" "")] 552 1.1 mrg "TARGET_VX" 553 1.1 mrg { 554 1.1 mrg s390_expand_vec_init (operands[0], operands[1]); 555 1.1 mrg DONE; 556 1.1 mrg }) 557 1.1 mrg 558 1.3 mrg (define_insn "*vec_vllezlf<mode>" 559 1.7 mrg [(set (match_operand:V_HW_4 0 "register_operand" "=v") 560 1.7 mrg (vec_concat:V_HW_4 561 1.3 mrg (vec_concat:<vec_halfnumelts> 562 1.3 mrg (match_operand:<non_vec> 1 "memory_operand" "R") 563 1.3 mrg (const_int 0)) 564 1.3 mrg (vec_concat:<vec_halfnumelts> 565 1.3 mrg (const_int 0) 566 1.3 mrg (const_int 0))))] 567 1.3 mrg "TARGET_VXE" 568 1.3 mrg "vllezlf\t%v0,%1" 569 1.3 mrg [(set_attr "op_type" "VRX")]) 570 1.3 mrg 571 1.1 mrg ; Replicate from vector element 572 1.3 mrg ; vrepb, vreph, vrepf, vrepg 573 1.1 mrg (define_insn "*vec_splat<mode>" 574 1.3 mrg [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "=v") 575 1.3 mrg (vec_duplicate:V_128_NOSINGLE 576 1.1 mrg (vec_select:<non_vec> 577 1.3 mrg (match_operand:V_128_NOSINGLE 1 "register_operand" "v") 578 1.1 mrg (parallel 579 1.1 mrg [(match_operand:QI 2 "const_mask_operand" "C")]))))] 580 1.3 mrg "TARGET_VX && UINTVAL (operands[2]) < GET_MODE_NUNITS (<MODE>mode)" 581 1.1 mrg "vrep<bhfgq>\t%v0,%v1,%2" 582 1.1 mrg [(set_attr "op_type" "VRI")]) 583 1.1 mrg 584 1.3 mrg ; vlrepb, vlreph, vlrepf, vlrepg, vrepib, vrepih, vrepif, vrepig, vrepb, vreph, vrepf, vrepg 585 1.1 mrg (define_insn "*vec_splats<mode>" 586 1.3 mrg [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "=v,v,v,v") 587 1.3 mrg (vec_duplicate:V_128_NOSINGLE (match_operand:<non_vec> 1 "general_operand" " R,K,v,d")))] 588 1.1 mrg "TARGET_VX" 589 1.1 mrg "@ 590 1.1 mrg vlrep<bhfgq>\t%v0,%1 591 1.1 mrg vrepi<bhfgq>\t%v0,%h1 592 1.1 mrg vrep<bhfgq>\t%v0,%v1,0 593 1.1 mrg #" 594 1.1 mrg [(set_attr "op_type" "VRX,VRI,VRI,*")]) 595 1.1 mrg 596 1.5 mrg ; vlbrreph, vlbrrepf, vlbrrepg 597 1.5 mrg (define_insn "*vec_splats_bswap_vec<mode>" 598 1.5 mrg [(set (match_operand:V_HW_HSD 0 "register_operand" "=v") 599 1.5 mrg (bswap:V_HW_HSD 600 1.5 mrg (vec_duplicate:V_HW_HSD (match_operand:<non_vec> 1 "memory_operand" "R")))) 601 1.5 mrg (use (match_operand:V16QI 2 "permute_pattern_operand" "X"))] 602 1.5 mrg "TARGET_VXE2" 603 1.5 mrg "vlbrrep<bhfgq>\t%v0,%1" 604 1.5 mrg [(set_attr "op_type" "VRX")]) 605 1.5 mrg 606 1.5 mrg ; Why do we need both? Shouldn't there be a canonical form? 607 1.5 mrg ; vlbrreph, vlbrrepf, vlbrrepg 608 1.5 mrg (define_insn "*vec_splats_bswap_elem<mode>" 609 1.5 mrg [(set (match_operand:V_HW_HSD 0 "register_operand" "=v") 610 1.5 mrg (vec_duplicate:V_HW_HSD 611 1.5 mrg (bswap:<non_vec> (match_operand:<non_vec> 1 "memory_operand" "R"))))] 612 1.5 mrg "TARGET_VXE2" 613 1.5 mrg "vlbrrep<bhfgq>\t%v0,%1" 614 1.5 mrg [(set_attr "op_type" "VRX")]) 615 1.5 mrg 616 1.3 mrg ; A TFmode operand resides in FPR register pairs while V1TF is in a 617 1.3 mrg ; single vector register. 618 1.7 mrg (define_insn "*vec_tf_to_v1tf_fpr" 619 1.7 mrg [(set (match_operand:V1TF 0 "nonimmediate_operand" "=v,v,R,v,v") 620 1.7 mrg (vec_duplicate:V1TF (match_operand:TF 1 "general_operand" "f,R,f,G,d")))] 621 1.7 mrg "TARGET_VX && !TARGET_VXE" 622 1.7 mrg "@ 623 1.7 mrg vmrhg\t%v0,%1,%N1 624 1.7 mrg vl\t%v0,%1%A1 625 1.7 mrg vst\t%v1,%0%A0 626 1.7 mrg vzero\t%v0 627 1.7 mrg vlvgp\t%v0,%1,%N1" 628 1.7 mrg [(set_attr "op_type" "VRR,VRX,VRX,VRI,VRR")]) 629 1.7 mrg 630 1.7 mrg ; Both TFmode and V1TFmode operands reside in vector registers. 631 1.7 mrg (define_insn "*vec_tf_to_v1tf_vr" 632 1.3 mrg [(set (match_operand:V1TF 0 "nonimmediate_operand" "=v,v,R,v,v") 633 1.3 mrg (vec_duplicate:V1TF (match_operand:TF 1 "general_operand" "v,R,v,G,d")))] 634 1.7 mrg "TARGET_VXE" 635 1.3 mrg "@ 636 1.7 mrg vlr\t%v0,%1 637 1.5 mrg vl\t%v0,%1%A1 638 1.5 mrg vst\t%v1,%0%A0 639 1.3 mrg vzero\t%v0 640 1.3 mrg vlvgp\t%v0,%1,%N1" 641 1.3 mrg [(set_attr "op_type" "VRR,VRX,VRX,VRI,VRR")]) 642 1.3 mrg 643 1.7 mrg (define_insn_and_split "fprx2_to_tf" 644 1.7 mrg [(set (match_operand:TF 0 "nonimmediate_operand" "=v,AR") 645 1.7 mrg (subreg:TF (match_operand:FPRX2 1 "general_operand" "f,f") 0))] 646 1.7 mrg "TARGET_VXE" 647 1.7 mrg "@ 648 1.7 mrg vmrhg\t%v0,%1,%N1 649 1.7 mrg #" 650 1.7 mrg "!(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0]))" 651 1.7 mrg [(set (match_dup 2) (match_dup 3)) 652 1.7 mrg (set (match_dup 4) (match_dup 5))] 653 1.7 mrg { 654 1.7 mrg operands[2] = simplify_gen_subreg (DFmode, operands[0], TFmode, 0); 655 1.7 mrg operands[3] = simplify_gen_subreg (DFmode, operands[1], FPRX2mode, 0); 656 1.7 mrg operands[4] = simplify_gen_subreg (DFmode, operands[0], TFmode, 8); 657 1.7 mrg operands[5] = simplify_gen_subreg (DFmode, operands[1], FPRX2mode, 8); 658 1.7 mrg } 659 1.7 mrg [(set_attr "op_type" "VRR,*")]) 660 1.7 mrg 661 1.3 mrg (define_insn "*vec_ti_to_v1ti" 662 1.3 mrg [(set (match_operand:V1TI 0 "nonimmediate_operand" "=v,v,R, v, v,v") 663 1.3 mrg (vec_duplicate:V1TI (match_operand:TI 1 "general_operand" "v,R,v,j00,jm1,d")))] 664 1.3 mrg "TARGET_VX" 665 1.3 mrg "@ 666 1.3 mrg vlr\t%v0,%v1 667 1.5 mrg vl\t%v0,%1%A1 668 1.5 mrg vst\t%v1,%0%A0 669 1.3 mrg vzero\t%v0 670 1.3 mrg vone\t%v0 671 1.3 mrg vlvgp\t%v0,%1,%N1" 672 1.3 mrg [(set_attr "op_type" "VRR,VRX,VRX,VRI,VRI,VRR")]) 673 1.3 mrg 674 1.1 mrg ; vec_splats is supposed to replicate op1 into all elements of op0 675 1.1 mrg ; This splitter first sets the rightmost element of op0 to op1 and 676 1.1 mrg ; then does a vec_splat to replicate that element into all other 677 1.1 mrg ; elements. 678 1.1 mrg (define_split 679 1.3 mrg [(set (match_operand:V_128_NOSINGLE 0 "register_operand" "") 680 1.3 mrg (vec_duplicate:V_128_NOSINGLE (match_operand:<non_vec> 1 "register_operand" "")))] 681 1.1 mrg "TARGET_VX && GENERAL_REG_P (operands[1])" 682 1.1 mrg [(set (match_dup 0) 683 1.3 mrg (unspec:V_128_NOSINGLE [(match_dup 1) (match_dup 2) (match_dup 0)] UNSPEC_VEC_SET)) 684 1.1 mrg (set (match_dup 0) 685 1.3 mrg (vec_duplicate:V_128_NOSINGLE 686 1.1 mrg (vec_select:<non_vec> 687 1.1 mrg (match_dup 0) (parallel [(match_dup 2)]))))] 688 1.1 mrg { 689 1.1 mrg operands[2] = GEN_INT (GET_MODE_NUNITS (<MODE>mode) - 1); 690 1.1 mrg }) 691 1.1 mrg 692 1.6 mrg (define_predicate "vcond_comparison_operator" 693 1.6 mrg (match_operand 0 "comparison_operator") 694 1.6 mrg { 695 1.6 mrg if (!HONOR_NANS (GET_MODE (XEXP (op, 0))) 696 1.6 mrg && !HONOR_NANS (GET_MODE (XEXP (op, 1)))) 697 1.6 mrg return true; 698 1.6 mrg switch (GET_CODE (op)) 699 1.6 mrg { 700 1.6 mrg case LE: 701 1.6 mrg case LT: 702 1.6 mrg case GE: 703 1.6 mrg case GT: 704 1.6 mrg case LTGT: 705 1.6 mrg /* Signaling vector comparisons are supported only on z14+. */ 706 1.6 mrg return TARGET_VXE || TARGET_NONSIGNALING_VECTOR_COMPARE_OK; 707 1.6 mrg default: 708 1.6 mrg return true; 709 1.6 mrg } 710 1.6 mrg }) 711 1.6 mrg 712 1.1 mrg (define_expand "vcond<V_HW:mode><V_HW2:mode>" 713 1.1 mrg [(set (match_operand:V_HW 0 "register_operand" "") 714 1.1 mrg (if_then_else:V_HW 715 1.6 mrg (match_operator 3 "vcond_comparison_operator" 716 1.1 mrg [(match_operand:V_HW2 4 "register_operand" "") 717 1.3 mrg (match_operand:V_HW2 5 "nonmemory_operand" "")]) 718 1.1 mrg (match_operand:V_HW 1 "nonmemory_operand" "") 719 1.1 mrg (match_operand:V_HW 2 "nonmemory_operand" "")))] 720 1.1 mrg "TARGET_VX && GET_MODE_NUNITS (<V_HW:MODE>mode) == GET_MODE_NUNITS (<V_HW2:MODE>mode)" 721 1.1 mrg { 722 1.1 mrg s390_expand_vcond (operands[0], operands[1], operands[2], 723 1.1 mrg GET_CODE (operands[3]), operands[4], operands[5]); 724 1.1 mrg DONE; 725 1.1 mrg }) 726 1.1 mrg 727 1.1 mrg (define_expand "vcondu<V_HW:mode><V_HW2:mode>" 728 1.1 mrg [(set (match_operand:V_HW 0 "register_operand" "") 729 1.1 mrg (if_then_else:V_HW 730 1.1 mrg (match_operator 3 "comparison_operator" 731 1.1 mrg [(match_operand:V_HW2 4 "register_operand" "") 732 1.3 mrg (match_operand:V_HW2 5 "nonmemory_operand" "")]) 733 1.1 mrg (match_operand:V_HW 1 "nonmemory_operand" "") 734 1.1 mrg (match_operand:V_HW 2 "nonmemory_operand" "")))] 735 1.1 mrg "TARGET_VX && GET_MODE_NUNITS (<V_HW:MODE>mode) == GET_MODE_NUNITS (<V_HW2:MODE>mode)" 736 1.1 mrg { 737 1.1 mrg s390_expand_vcond (operands[0], operands[1], operands[2], 738 1.1 mrg GET_CODE (operands[3]), operands[4], operands[5]); 739 1.1 mrg DONE; 740 1.1 mrg }) 741 1.1 mrg 742 1.7 mrg (define_expand "vcond_mask_<mode><tointvec>" 743 1.7 mrg [(set (match_operand:V 0 "register_operand" "") 744 1.7 mrg (if_then_else:V 745 1.7 mrg (eq (match_operand:<TOINTVEC> 3 "register_operand" "") 746 1.7 mrg (match_dup 4)) 747 1.7 mrg (match_operand:V 2 "register_operand" "") 748 1.7 mrg (match_operand:V 1 "register_operand" "")))] 749 1.7 mrg "TARGET_VX" 750 1.7 mrg "operands[4] = CONST0_RTX (<TOINTVEC>mode);") 751 1.7 mrg 752 1.7 mrg 753 1.1 mrg ; We only have HW support for byte vectors. The middle-end is 754 1.1 mrg ; supposed to lower the mode if required. 755 1.1 mrg (define_insn "vec_permv16qi" 756 1.1 mrg [(set (match_operand:V16QI 0 "register_operand" "=v") 757 1.1 mrg (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v") 758 1.1 mrg (match_operand:V16QI 2 "register_operand" "v") 759 1.1 mrg (match_operand:V16QI 3 "register_operand" "v")] 760 1.1 mrg UNSPEC_VEC_PERM))] 761 1.1 mrg "TARGET_VX" 762 1.1 mrg "vperm\t%v0,%v1,%v2,%v3" 763 1.1 mrg [(set_attr "op_type" "VRR")]) 764 1.1 mrg 765 1.5 mrg (define_insn "*vec_perm<mode>" 766 1.5 mrg [(set (match_operand:VT_HW 0 "register_operand" "=v") 767 1.5 mrg (subreg:VT_HW (unspec:V16QI [(subreg:V16QI (match_operand:VT_HW 1 "register_operand" "v") 0) 768 1.5 mrg (subreg:V16QI (match_operand:VT_HW 2 "register_operand" "v") 0) 769 1.5 mrg (match_operand:V16QI 3 "register_operand" "v")] 770 1.5 mrg UNSPEC_VEC_PERM) 0))] 771 1.5 mrg "TARGET_VX" 772 1.5 mrg "vperm\t%v0,%v1,%v2,%v3" 773 1.5 mrg [(set_attr "op_type" "VRR")]) 774 1.5 mrg 775 1.5 mrg 776 1.7 mrg ; First DW of op1 and second DW of op2 777 1.7 mrg (define_insn "@vpdi1<mode>" 778 1.7 mrg [(set (match_operand:V_HW_2 0 "register_operand" "=v") 779 1.7 mrg (vec_select:V_HW_2 780 1.7 mrg (vec_concat:<vec_2x_nelts> 781 1.7 mrg (match_operand:V_HW_2 1 "register_operand" "v") 782 1.7 mrg (match_operand:V_HW_2 2 "register_operand" "v")) 783 1.7 mrg (parallel [(const_int 0) (const_int 3)])))] 784 1.7 mrg "TARGET_VX" 785 1.7 mrg "vpdi\t%v0,%v1,%v2,1" 786 1.7 mrg [(set_attr "op_type" "VRR")]) 787 1.7 mrg 788 1.7 mrg ; Second DW of op1 and first of op2 789 1.7 mrg (define_insn "@vpdi4<mode>" 790 1.7 mrg [(set (match_operand:V_HW_2 0 "register_operand" "=v") 791 1.7 mrg (vec_select:V_HW_2 792 1.7 mrg (vec_concat:<vec_2x_nelts> 793 1.7 mrg (match_operand:V_HW_2 1 "register_operand" "v") 794 1.7 mrg (match_operand:V_HW_2 2 "register_operand" "v")) 795 1.7 mrg (parallel [(const_int 1) (const_int 2)])))] 796 1.7 mrg "TARGET_VX" 797 1.7 mrg "vpdi\t%v0,%v1,%v2,4" 798 1.7 mrg [(set_attr "op_type" "VRR")]) 799 1.7 mrg 800 1.7 mrg 801 1.7 mrg (define_insn "*vmrhb" 802 1.7 mrg [(set (match_operand:V16QI 0 "register_operand" "=v") 803 1.7 mrg (vec_select:V16QI 804 1.7 mrg (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "v") 805 1.7 mrg (match_operand:V16QI 2 "register_operand" "v")) 806 1.7 mrg (parallel [(const_int 0) (const_int 16) 807 1.7 mrg (const_int 1) (const_int 17) 808 1.7 mrg (const_int 2) (const_int 18) 809 1.7 mrg (const_int 3) (const_int 19) 810 1.7 mrg (const_int 4) (const_int 20) 811 1.7 mrg (const_int 5) (const_int 21) 812 1.7 mrg (const_int 6) (const_int 22) 813 1.7 mrg (const_int 7) (const_int 23)])))] 814 1.7 mrg "TARGET_VX" 815 1.7 mrg "vmrhb\t%0,%1,%2"; 816 1.7 mrg [(set_attr "op_type" "VRR")]) 817 1.7 mrg 818 1.7 mrg (define_insn "*vmrlb" 819 1.7 mrg [(set (match_operand:V16QI 0 "register_operand" "=v") 820 1.7 mrg (vec_select:V16QI 821 1.7 mrg (vec_concat:V32QI (match_operand:V16QI 1 "register_operand" "v") 822 1.7 mrg (match_operand:V16QI 2 "register_operand" "v")) 823 1.7 mrg (parallel [(const_int 8) (const_int 24) 824 1.7 mrg (const_int 9) (const_int 25) 825 1.7 mrg (const_int 10) (const_int 26) 826 1.7 mrg (const_int 11) (const_int 27) 827 1.7 mrg (const_int 12) (const_int 28) 828 1.7 mrg (const_int 13) (const_int 29) 829 1.7 mrg (const_int 14) (const_int 30) 830 1.7 mrg (const_int 15) (const_int 31)])))] 831 1.7 mrg "TARGET_VX" 832 1.7 mrg "vmrlb\t%0,%1,%2"; 833 1.7 mrg [(set_attr "op_type" "VRR")]) 834 1.7 mrg 835 1.7 mrg (define_insn "*vmrhh" 836 1.7 mrg [(set (match_operand:V8HI 0 "register_operand" "=v") 837 1.7 mrg (vec_select:V8HI 838 1.7 mrg (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "v") 839 1.7 mrg (match_operand:V8HI 2 "register_operand" "v")) 840 1.7 mrg (parallel [(const_int 0) (const_int 8) 841 1.7 mrg (const_int 1) (const_int 9) 842 1.7 mrg (const_int 2) (const_int 10) 843 1.7 mrg (const_int 3) (const_int 11)])))] 844 1.7 mrg "TARGET_VX" 845 1.7 mrg "vmrhh\t%0,%1,%2"; 846 1.7 mrg [(set_attr "op_type" "VRR")]) 847 1.7 mrg 848 1.7 mrg (define_insn "*vmrlh" 849 1.7 mrg [(set (match_operand:V8HI 0 "register_operand" "=v") 850 1.7 mrg (vec_select:V8HI 851 1.7 mrg (vec_concat:V16HI (match_operand:V8HI 1 "register_operand" "v") 852 1.7 mrg (match_operand:V8HI 2 "register_operand" "v")) 853 1.7 mrg (parallel [(const_int 4) (const_int 12) 854 1.7 mrg (const_int 5) (const_int 13) 855 1.7 mrg (const_int 6) (const_int 14) 856 1.7 mrg (const_int 7) (const_int 15)])))] 857 1.7 mrg "TARGET_VX" 858 1.7 mrg "vmrlh\t%0,%1,%2"; 859 1.7 mrg [(set_attr "op_type" "VRR")]) 860 1.7 mrg 861 1.7 mrg (define_insn "*vmrhf" 862 1.7 mrg [(set (match_operand:V_HW_4 0 "register_operand" "=v") 863 1.7 mrg (vec_select:V_HW_4 864 1.7 mrg (vec_concat:<vec_2x_nelts> (match_operand:V_HW_4 1 "register_operand" "v") 865 1.7 mrg (match_operand:V_HW_4 2 "register_operand" "v")) 866 1.7 mrg (parallel [(const_int 0) (const_int 4) 867 1.7 mrg (const_int 1) (const_int 5)])))] 868 1.7 mrg "TARGET_VX" 869 1.7 mrg "vmrhf\t%0,%1,%2"; 870 1.7 mrg [(set_attr "op_type" "VRR")]) 871 1.7 mrg 872 1.7 mrg (define_insn "*vmrlf" 873 1.7 mrg [(set (match_operand:V_HW_4 0 "register_operand" "=v") 874 1.7 mrg (vec_select:V_HW_4 875 1.7 mrg (vec_concat:<vec_2x_nelts> (match_operand:V_HW_4 1 "register_operand" "v") 876 1.7 mrg (match_operand:V_HW_4 2 "register_operand" "v")) 877 1.7 mrg (parallel [(const_int 2) (const_int 6) 878 1.7 mrg (const_int 3) (const_int 7)])))] 879 1.7 mrg "TARGET_VX" 880 1.7 mrg "vmrlf\t%0,%1,%2"; 881 1.7 mrg [(set_attr "op_type" "VRR")]) 882 1.7 mrg 883 1.7 mrg (define_insn "*vmrhg" 884 1.7 mrg [(set (match_operand:V_HW_2 0 "register_operand" "=v") 885 1.7 mrg (vec_select:V_HW_2 886 1.7 mrg (vec_concat:<vec_2x_nelts> (match_operand:V_HW_2 1 "register_operand" "v") 887 1.7 mrg (match_operand:V_HW_2 2 "register_operand" "v")) 888 1.7 mrg (parallel [(const_int 0) (const_int 2)])))] 889 1.7 mrg "TARGET_VX" 890 1.7 mrg "vmrhg\t%0,%1,%2"; 891 1.7 mrg [(set_attr "op_type" "VRR")]) 892 1.7 mrg 893 1.7 mrg (define_insn "*vmrlg" 894 1.7 mrg [(set (match_operand:V_HW_2 0 "register_operand" "=v") 895 1.7 mrg (vec_select:V_HW_2 896 1.7 mrg (vec_concat:<vec_2x_nelts> (match_operand:V_HW_2 1 "register_operand" "v") 897 1.7 mrg (match_operand:V_HW_2 2 "register_operand" "v")) 898 1.7 mrg (parallel [(const_int 1) (const_int 3)])))] 899 1.7 mrg "TARGET_VX" 900 1.7 mrg "vmrlg\t%0,%1,%2"; 901 1.7 mrg [(set_attr "op_type" "VRR")]) 902 1.7 mrg 903 1.7 mrg (define_insn "tf_to_fprx2" 904 1.7 mrg [(set (match_operand:FPRX2 0 "register_operand" "=f,f ,f") 905 1.7 mrg (unspec:FPRX2 [(match_operand:TF 1 "general_operand" "v,AR,AT")] 906 1.7 mrg UNSPEC_TF_TO_FPRX2))] 907 1.7 mrg "TARGET_VXE" 908 1.7 mrg { 909 1.7 mrg char buf[64]; 910 1.7 mrg const char *reg_pair = reg_names[REGNO (operands[0]) + 1]; 911 1.7 mrg switch (which_alternative) 912 1.7 mrg { 913 1.7 mrg case 0: 914 1.7 mrg if (REGNO (operands[0]) == REGNO (operands[1])) 915 1.7 mrg { 916 1.7 mrg reg_pair += 2; // get rid of prefix %f 917 1.7 mrg snprintf (buf, sizeof (buf), "vpdi\t%%%%v%s,%%v1,%%%%v%s,5", reg_pair, reg_pair); 918 1.7 mrg output_asm_insn (buf, operands); 919 1.7 mrg return ""; 920 1.7 mrg } 921 1.7 mrg else 922 1.7 mrg { 923 1.7 mrg reg_pair += 2; // get rid of prefix %f 924 1.7 mrg snprintf (buf, sizeof (buf), "vlr\t%%v0,%%v1;vpdi\t%%%%v%s,%%v1,%%%%v%s,5", reg_pair, reg_pair); 925 1.7 mrg output_asm_insn (buf, operands); 926 1.7 mrg return ""; 927 1.7 mrg } 928 1.7 mrg case 1: 929 1.7 mrg { 930 1.7 mrg snprintf (buf, sizeof (buf), "ld\t%%f0,%%1;ld\t%%%s,8+%%1", reg_pair); 931 1.7 mrg output_asm_insn (buf, operands); 932 1.7 mrg return ""; 933 1.7 mrg } 934 1.7 mrg case 2: 935 1.7 mrg { 936 1.7 mrg snprintf (buf, sizeof (buf), "ldy\t%%f0,%%1;ldy\t%%%s,8+%%1", reg_pair); 937 1.7 mrg output_asm_insn (buf, operands); 938 1.7 mrg return ""; 939 1.7 mrg } 940 1.7 mrg default: gcc_unreachable (); 941 1.7 mrg } 942 1.7 mrg }) 943 1.7 mrg 944 1.1 mrg 945 1.1 mrg ;; 946 1.1 mrg ;; Vector integer arithmetic instructions 947 1.1 mrg ;; 948 1.1 mrg 949 1.1 mrg ; vab, vah, vaf, vag, vaq 950 1.1 mrg 951 1.1 mrg ; We use nonimmediate_operand instead of register_operand since it is 952 1.1 mrg ; better to have the reloads into VRs instead of splitting the 953 1.1 mrg ; operation into two DImode ADDs. 954 1.1 mrg (define_insn "<ti*>add<mode>3" 955 1.1 mrg [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") 956 1.6 mrg (plus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") 957 1.1 mrg (match_operand:VIT 2 "general_operand" "v")))] 958 1.1 mrg "TARGET_VX" 959 1.1 mrg "va<bhfgq>\t%v0,%v1,%v2" 960 1.1 mrg [(set_attr "op_type" "VRR")]) 961 1.1 mrg 962 1.1 mrg ; vsb, vsh, vsf, vsg, vsq 963 1.1 mrg (define_insn "<ti*>sub<mode>3" 964 1.1 mrg [(set (match_operand:VIT 0 "nonimmediate_operand" "=v") 965 1.1 mrg (minus:VIT (match_operand:VIT 1 "nonimmediate_operand" "v") 966 1.6 mrg (match_operand:VIT 2 "general_operand" "v")))] 967 1.1 mrg "TARGET_VX" 968 1.1 mrg "vs<bhfgq>\t%v0,%v1,%v2" 969 1.1 mrg [(set_attr "op_type" "VRR")]) 970 1.1 mrg 971 1.1 mrg ; vmlb, vmlhw, vmlf 972 1.1 mrg (define_insn "mul<mode>3" 973 1.1 mrg [(set (match_operand:VI_QHS 0 "register_operand" "=v") 974 1.6 mrg (mult:VI_QHS (match_operand:VI_QHS 1 "register_operand" "v") 975 1.1 mrg (match_operand:VI_QHS 2 "register_operand" "v")))] 976 1.1 mrg "TARGET_VX" 977 1.1 mrg "vml<bhfgq><w>\t%v0,%v1,%v2" 978 1.1 mrg [(set_attr "op_type" "VRR")]) 979 1.1 mrg 980 1.1 mrg ; vlcb, vlch, vlcf, vlcg 981 1.1 mrg (define_insn "neg<mode>2" 982 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 983 1.1 mrg (neg:VI (match_operand:VI 1 "register_operand" "v")))] 984 1.1 mrg "TARGET_VX" 985 1.1 mrg "vlc<bhfgq>\t%v0,%v1" 986 1.1 mrg [(set_attr "op_type" "VRR")]) 987 1.1 mrg 988 1.1 mrg ; vlpb, vlph, vlpf, vlpg 989 1.1 mrg (define_insn "abs<mode>2" 990 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 991 1.1 mrg (abs:VI (match_operand:VI 1 "register_operand" "v")))] 992 1.1 mrg "TARGET_VX" 993 1.1 mrg "vlp<bhfgq>\t%v0,%v1" 994 1.1 mrg [(set_attr "op_type" "VRR")]) 995 1.1 mrg 996 1.1 mrg 997 1.1 mrg ; Vector sum across 998 1.1 mrg 999 1.1 mrg ; Sum across DImode parts of the 1st operand and add the rightmost 1000 1.1 mrg ; element of 2nd operand 1001 1.1 mrg ; vsumgh, vsumgf 1002 1.1 mrg (define_insn "*vec_sum2<mode>" 1003 1.1 mrg [(set (match_operand:V2DI 0 "register_operand" "=v") 1004 1.1 mrg (unspec:V2DI [(match_operand:VI_HW_HS 1 "register_operand" "v") 1005 1.1 mrg (match_operand:VI_HW_HS 2 "register_operand" "v")] 1006 1.1 mrg UNSPEC_VEC_VSUMG))] 1007 1.1 mrg "TARGET_VX" 1008 1.1 mrg "vsumg<bhfgq>\t%v0,%v1,%v2" 1009 1.1 mrg [(set_attr "op_type" "VRR")]) 1010 1.1 mrg 1011 1.1 mrg ; vsumb, vsumh 1012 1.1 mrg (define_insn "*vec_sum4<mode>" 1013 1.1 mrg [(set (match_operand:V4SI 0 "register_operand" "=v") 1014 1.1 mrg (unspec:V4SI [(match_operand:VI_HW_QH 1 "register_operand" "v") 1015 1.1 mrg (match_operand:VI_HW_QH 2 "register_operand" "v")] 1016 1.1 mrg UNSPEC_VEC_VSUM))] 1017 1.1 mrg "TARGET_VX" 1018 1.1 mrg "vsum<bhfgq>\t%v0,%v1,%v2" 1019 1.1 mrg [(set_attr "op_type" "VRR")]) 1020 1.1 mrg 1021 1.1 mrg ;; 1022 1.1 mrg ;; Vector bit instructions (int + fp) 1023 1.1 mrg ;; 1024 1.1 mrg 1025 1.1 mrg ; Vector and 1026 1.1 mrg 1027 1.1 mrg (define_insn "and<mode>3" 1028 1.1 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1029 1.6 mrg (and:VT (match_operand:VT 1 "register_operand" "v") 1030 1.1 mrg (match_operand:VT 2 "register_operand" "v")))] 1031 1.1 mrg "TARGET_VX" 1032 1.1 mrg "vn\t%v0,%v1,%v2" 1033 1.1 mrg [(set_attr "op_type" "VRR")]) 1034 1.1 mrg 1035 1.3 mrg ; Vector not and 1036 1.3 mrg 1037 1.3 mrg (define_insn "notand<mode>3" 1038 1.3 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1039 1.6 mrg (ior:VT (not:VT (match_operand:VT 1 "register_operand" "v")) 1040 1.3 mrg (not:VT (match_operand:VT 2 "register_operand" "v"))))] 1041 1.3 mrg "TARGET_VXE" 1042 1.3 mrg "vnn\t%v0,%v1,%v2" 1043 1.3 mrg [(set_attr "op_type" "VRR")]) 1044 1.1 mrg 1045 1.1 mrg ; Vector or 1046 1.1 mrg 1047 1.1 mrg (define_insn "ior<mode>3" 1048 1.1 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1049 1.6 mrg (ior:VT (match_operand:VT 1 "register_operand" "v") 1050 1.1 mrg (match_operand:VT 2 "register_operand" "v")))] 1051 1.1 mrg "TARGET_VX" 1052 1.1 mrg "vo\t%v0,%v1,%v2" 1053 1.1 mrg [(set_attr "op_type" "VRR")]) 1054 1.1 mrg 1055 1.3 mrg ; Vector or with complement 1056 1.3 mrg 1057 1.3 mrg (define_insn "ior_not<mode>3" 1058 1.3 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1059 1.3 mrg (ior:VT (not:VT (match_operand:VT 2 "register_operand" "v")) 1060 1.6 mrg (match_operand:VT 1 "register_operand" "v")))] 1061 1.3 mrg "TARGET_VXE" 1062 1.3 mrg "voc\t%v0,%v1,%v2" 1063 1.3 mrg [(set_attr "op_type" "VRR")]) 1064 1.1 mrg 1065 1.1 mrg ; Vector xor 1066 1.1 mrg 1067 1.1 mrg (define_insn "xor<mode>3" 1068 1.1 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1069 1.6 mrg (xor:VT (match_operand:VT 1 "register_operand" "v") 1070 1.1 mrg (match_operand:VT 2 "register_operand" "v")))] 1071 1.1 mrg "TARGET_VX" 1072 1.1 mrg "vx\t%v0,%v1,%v2" 1073 1.1 mrg [(set_attr "op_type" "VRR")]) 1074 1.1 mrg 1075 1.3 mrg ; Vector not xor 1076 1.3 mrg 1077 1.3 mrg (define_insn "notxor<mode>3" 1078 1.3 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1079 1.6 mrg (not:VT (xor:VT (match_operand:VT 1 "register_operand" "v") 1080 1.3 mrg (match_operand:VT 2 "register_operand" "v"))))] 1081 1.3 mrg "TARGET_VXE" 1082 1.3 mrg "vnx\t%v0,%v1,%v2" 1083 1.3 mrg [(set_attr "op_type" "VRR")]) 1084 1.1 mrg 1085 1.3 mrg ; Bitwise inversion of a vector 1086 1.3 mrg (define_insn "one_cmpl<mode>2" 1087 1.1 mrg [(set (match_operand:VT 0 "register_operand" "=v") 1088 1.1 mrg (not:VT (match_operand:VT 1 "register_operand" "v")))] 1089 1.1 mrg "TARGET_VX" 1090 1.1 mrg "vnot\t%v0,%v1" 1091 1.1 mrg [(set_attr "op_type" "VRR")]) 1092 1.1 mrg 1093 1.1 mrg ; Vector population count 1094 1.1 mrg 1095 1.3 mrg (define_expand "popcount<mode>2" 1096 1.3 mrg [(set (match_operand:VI_HW 0 "register_operand" "=v") 1097 1.3 mrg (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")] 1098 1.3 mrg UNSPEC_POPCNT))] 1099 1.3 mrg "TARGET_VX" 1100 1.3 mrg { 1101 1.3 mrg if (TARGET_VXE) 1102 1.3 mrg emit_insn (gen_popcount<mode>2_vxe (operands[0], operands[1])); 1103 1.3 mrg else 1104 1.3 mrg emit_insn (gen_popcount<mode>2_vx (operands[0], operands[1])); 1105 1.3 mrg DONE; 1106 1.3 mrg }) 1107 1.3 mrg 1108 1.3 mrg ; vpopctb, vpopcth, vpopctf, vpopctg 1109 1.3 mrg (define_insn "popcount<mode>2_vxe" 1110 1.3 mrg [(set (match_operand:VI_HW 0 "register_operand" "=v") 1111 1.3 mrg (unspec:VI_HW [(match_operand:VI_HW 1 "register_operand" "v")] 1112 1.3 mrg UNSPEC_POPCNT))] 1113 1.3 mrg "TARGET_VXE" 1114 1.3 mrg "vpopct<bhfgq>\t%v0,%v1" 1115 1.3 mrg [(set_attr "op_type" "VRR")]) 1116 1.3 mrg 1117 1.3 mrg (define_insn "popcountv16qi2_vx" 1118 1.1 mrg [(set (match_operand:V16QI 0 "register_operand" "=v") 1119 1.1 mrg (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "v")] 1120 1.1 mrg UNSPEC_POPCNT))] 1121 1.3 mrg "TARGET_VX && !TARGET_VXE" 1122 1.1 mrg "vpopct\t%v0,%v1,0" 1123 1.1 mrg [(set_attr "op_type" "VRR")]) 1124 1.1 mrg 1125 1.1 mrg ; vpopct only counts bits in byte elements. Bigger element sizes need 1126 1.1 mrg ; to be emulated. Word and doubleword elements can use the sum across 1127 1.1 mrg ; instructions. For halfword sized elements we do a shift of a copy 1128 1.1 mrg ; of the result, add it to the result and extend it to halfword 1129 1.1 mrg ; element size (unpack). 1130 1.1 mrg 1131 1.3 mrg (define_expand "popcountv8hi2_vx" 1132 1.1 mrg [(set (match_dup 2) 1133 1.6 mrg (unspec:V16QI [(match_operand:V8HI 1 "register_operand" "v")] 1134 1.1 mrg UNSPEC_POPCNT)) 1135 1.1 mrg ; Make a copy of the result 1136 1.1 mrg (set (match_dup 3) (match_dup 2)) 1137 1.1 mrg ; Generate the shift count operand in a VR (8->byte 7) 1138 1.1 mrg (set (match_dup 4) (match_dup 5)) 1139 1.1 mrg (set (match_dup 4) (unspec:V16QI [(const_int 8) 1140 1.1 mrg (const_int 7) 1141 1.1 mrg (match_dup 4)] UNSPEC_VEC_SET)) 1142 1.1 mrg ; Vector shift right logical by one byte 1143 1.1 mrg (set (match_dup 3) 1144 1.1 mrg (unspec:V16QI [(match_dup 3) (match_dup 4)] UNSPEC_VEC_SRLB)) 1145 1.1 mrg ; Add the shifted and the original result 1146 1.1 mrg (set (match_dup 2) 1147 1.1 mrg (plus:V16QI (match_dup 2) (match_dup 3))) 1148 1.1 mrg ; Generate mask for the odd numbered byte elements 1149 1.1 mrg (set (match_dup 3) 1150 1.1 mrg (const_vector:V16QI [(const_int 0) (const_int 255) 1151 1.1 mrg (const_int 0) (const_int 255) 1152 1.1 mrg (const_int 0) (const_int 255) 1153 1.1 mrg (const_int 0) (const_int 255) 1154 1.1 mrg (const_int 0) (const_int 255) 1155 1.1 mrg (const_int 0) (const_int 255) 1156 1.1 mrg (const_int 0) (const_int 255) 1157 1.1 mrg (const_int 0) (const_int 255)])) 1158 1.1 mrg ; Zero out the even indexed bytes 1159 1.1 mrg (set (match_operand:V8HI 0 "register_operand" "=v") 1160 1.1 mrg (and:V8HI (subreg:V8HI (match_dup 2) 0) 1161 1.1 mrg (subreg:V8HI (match_dup 3) 0))) 1162 1.1 mrg ] 1163 1.3 mrg "TARGET_VX && !TARGET_VXE" 1164 1.1 mrg { 1165 1.6 mrg operands[1] = simplify_gen_subreg (V16QImode, operands[1], 1166 1.6 mrg V8HImode, 0); 1167 1.1 mrg operands[2] = gen_reg_rtx (V16QImode); 1168 1.1 mrg operands[3] = gen_reg_rtx (V16QImode); 1169 1.1 mrg operands[4] = gen_reg_rtx (V16QImode); 1170 1.1 mrg operands[5] = CONST0_RTX (V16QImode); 1171 1.1 mrg }) 1172 1.1 mrg 1173 1.3 mrg (define_expand "popcountv4si2_vx" 1174 1.1 mrg [(set (match_dup 2) 1175 1.6 mrg (unspec:V16QI [(match_operand:V4SI 1 "register_operand" "v")] 1176 1.1 mrg UNSPEC_POPCNT)) 1177 1.1 mrg (set (match_operand:V4SI 0 "register_operand" "=v") 1178 1.1 mrg (unspec:V4SI [(match_dup 2) (match_dup 3)] 1179 1.1 mrg UNSPEC_VEC_VSUM))] 1180 1.3 mrg "TARGET_VX && !TARGET_VXE" 1181 1.1 mrg { 1182 1.6 mrg operands[1] = simplify_gen_subreg (V16QImode, operands[1], V4SImode, 0); 1183 1.1 mrg operands[2] = gen_reg_rtx (V16QImode); 1184 1.1 mrg operands[3] = force_reg (V16QImode, CONST0_RTX (V16QImode)); 1185 1.1 mrg }) 1186 1.1 mrg 1187 1.3 mrg (define_expand "popcountv2di2_vx" 1188 1.1 mrg [(set (match_dup 2) 1189 1.6 mrg (unspec:V16QI [(match_operand:V2DI 1 "register_operand" "v")] 1190 1.1 mrg UNSPEC_POPCNT)) 1191 1.1 mrg (set (match_dup 3) 1192 1.1 mrg (unspec:V4SI [(match_dup 2) (match_dup 4)] 1193 1.1 mrg UNSPEC_VEC_VSUM)) 1194 1.1 mrg (set (match_operand:V2DI 0 "register_operand" "=v") 1195 1.1 mrg (unspec:V2DI [(match_dup 3) (match_dup 5)] 1196 1.1 mrg UNSPEC_VEC_VSUMG))] 1197 1.3 mrg "TARGET_VX && !TARGET_VXE" 1198 1.1 mrg { 1199 1.6 mrg operands[1] = simplify_gen_subreg (V16QImode, operands[1], V2DImode, 0); 1200 1.1 mrg operands[2] = gen_reg_rtx (V16QImode); 1201 1.1 mrg operands[3] = gen_reg_rtx (V4SImode); 1202 1.1 mrg operands[4] = force_reg (V16QImode, CONST0_RTX (V16QImode)); 1203 1.1 mrg operands[5] = force_reg (V4SImode, CONST0_RTX (V4SImode)); 1204 1.1 mrg }) 1205 1.1 mrg 1206 1.1 mrg ; Count leading zeros 1207 1.3 mrg ; vclzb, vclzh, vclzf, vclzg 1208 1.1 mrg (define_insn "clz<mode>2" 1209 1.1 mrg [(set (match_operand:V 0 "register_operand" "=v") 1210 1.1 mrg (clz:V (match_operand:V 1 "register_operand" "v")))] 1211 1.1 mrg "TARGET_VX" 1212 1.1 mrg "vclz<bhfgq>\t%v0,%v1" 1213 1.1 mrg [(set_attr "op_type" "VRR")]) 1214 1.1 mrg 1215 1.1 mrg ; Count trailing zeros 1216 1.3 mrg ; vctzb, vctzh, vctzf, vctzg 1217 1.1 mrg (define_insn "ctz<mode>2" 1218 1.1 mrg [(set (match_operand:V 0 "register_operand" "=v") 1219 1.1 mrg (ctz:V (match_operand:V 1 "register_operand" "v")))] 1220 1.1 mrg "TARGET_VX" 1221 1.1 mrg "vctz<bhfgq>\t%v0,%v1" 1222 1.1 mrg [(set_attr "op_type" "VRR")]) 1223 1.1 mrg 1224 1.1 mrg 1225 1.1 mrg 1226 1.1 mrg ; Each vector element rotated by the corresponding vector element 1227 1.1 mrg ; verllvb, verllvh, verllvf, verllvg 1228 1.1 mrg (define_insn "vrotl<mode>3" 1229 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1230 1.1 mrg (rotate:VI (match_operand:VI 1 "register_operand" "v") 1231 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1232 1.1 mrg "TARGET_VX" 1233 1.1 mrg "verllv<bhfgq>\t%v0,%v1,%v2" 1234 1.1 mrg [(set_attr "op_type" "VRR")]) 1235 1.1 mrg 1236 1.1 mrg 1237 1.3 mrg ; Vector rotate and shift by scalar instructions 1238 1.3 mrg 1239 1.3 mrg (define_code_iterator VEC_SHIFTS [ashift ashiftrt lshiftrt rotate]) 1240 1.3 mrg (define_code_attr vec_shifts_name [(ashift "ashl") (ashiftrt "ashr") 1241 1.3 mrg (lshiftrt "lshr") (rotate "rotl")]) 1242 1.3 mrg (define_code_attr vec_shifts_mnem [(ashift "vesl") (ashiftrt "vesra") 1243 1.3 mrg (lshiftrt "vesrl") (rotate "verll")]) 1244 1.1 mrg 1245 1.3 mrg ; Each vector element rotated by a scalar 1246 1.3 mrg (define_expand "<vec_shifts_name><mode>3" 1247 1.3 mrg [(set (match_operand:VI 0 "register_operand" "") 1248 1.3 mrg (VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "") 1249 1.6 mrg (match_operand:QI 2 "shift_count_operand" "")))] 1250 1.3 mrg "TARGET_VX") 1251 1.1 mrg 1252 1.3 mrg ; verllb, verllh, verllf, verllg 1253 1.3 mrg ; veslb, veslh, veslf, veslg 1254 1.1 mrg ; vesrab, vesrah, vesraf, vesrag 1255 1.1 mrg ; vesrlb, vesrlh, vesrlf, vesrlg 1256 1.6 mrg (define_insn "*<vec_shifts_name><mode>3" 1257 1.3 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1258 1.3 mrg (VEC_SHIFTS:VI (match_operand:VI 1 "register_operand" "v") 1259 1.6 mrg (match_operand:QI 2 "shift_count_operand_vec" "jsc")))] 1260 1.6 mrg "TARGET_VX 1261 1.6 mrg && s390_valid_shift_count (operands[2], 1262 1.6 mrg GET_MODE_BITSIZE (GET_MODE_INNER (<MODE>mode)) - 1) 1263 1.6 mrg " 1264 1.6 mrg "<vec_shifts_mnem><bhfgq>\t%v0,%v1,%Y2" 1265 1.1 mrg [(set_attr "op_type" "VRS")]) 1266 1.1 mrg 1267 1.6 mrg 1268 1.1 mrg ; Shift each element by corresponding vector element 1269 1.1 mrg 1270 1.1 mrg ; veslvb, veslvh, veslvf, veslvg 1271 1.1 mrg (define_insn "vashl<mode>3" 1272 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1273 1.1 mrg (ashift:VI (match_operand:VI 1 "register_operand" "v") 1274 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1275 1.1 mrg "TARGET_VX" 1276 1.1 mrg "veslv<bhfgq>\t%v0,%v1,%v2" 1277 1.1 mrg [(set_attr "op_type" "VRR")]) 1278 1.1 mrg 1279 1.1 mrg ; vesravb, vesravh, vesravf, vesravg 1280 1.1 mrg (define_insn "vashr<mode>3" 1281 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1282 1.1 mrg (ashiftrt:VI (match_operand:VI 1 "register_operand" "v") 1283 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1284 1.1 mrg "TARGET_VX" 1285 1.1 mrg "vesrav<bhfgq>\t%v0,%v1,%v2" 1286 1.1 mrg [(set_attr "op_type" "VRR")]) 1287 1.1 mrg 1288 1.1 mrg ; vesrlvb, vesrlvh, vesrlvf, vesrlvg 1289 1.1 mrg (define_insn "vlshr<mode>3" 1290 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1291 1.1 mrg (lshiftrt:VI (match_operand:VI 1 "register_operand" "v") 1292 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1293 1.1 mrg "TARGET_VX" 1294 1.1 mrg "vesrlv<bhfgq>\t%v0,%v1,%v2" 1295 1.1 mrg [(set_attr "op_type" "VRR")]) 1296 1.1 mrg 1297 1.1 mrg ; Vector shift right logical by byte 1298 1.1 mrg 1299 1.1 mrg ; Pattern used by e.g. popcount 1300 1.1 mrg (define_insn "*vec_srb<mode>" 1301 1.4 mrg [(set (match_operand:V_128 0 "register_operand" "=v") 1302 1.4 mrg (unspec:V_128 [(match_operand:V_128 1 "register_operand" "v") 1303 1.4 mrg (match_operand:V16QI 2 "register_operand" "v")] 1304 1.4 mrg UNSPEC_VEC_SRLB))] 1305 1.1 mrg "TARGET_VX" 1306 1.1 mrg "vsrlb\t%v0,%v1,%v2" 1307 1.1 mrg [(set_attr "op_type" "VRR")]) 1308 1.1 mrg 1309 1.1 mrg 1310 1.4 mrg ; Vector shift left by byte 1311 1.4 mrg 1312 1.4 mrg (define_insn "*vec_slb<mode>" 1313 1.4 mrg [(set (match_operand:V_128 0 "register_operand" "=v") 1314 1.4 mrg (unspec:V_128 [(match_operand:V_128 1 "register_operand" "v") 1315 1.4 mrg (match_operand:V16QI 2 "register_operand" "v")] 1316 1.4 mrg UNSPEC_VEC_SLB))] 1317 1.4 mrg "TARGET_VX" 1318 1.4 mrg "vslb\t%v0,%v1,%v2" 1319 1.4 mrg [(set_attr "op_type" "VRR")]) 1320 1.4 mrg 1321 1.4 mrg ; vec_shr is defined as shift towards element 0 1322 1.4 mrg ; this means it is a left shift on BE targets! 1323 1.4 mrg (define_expand "vec_shr_<mode>" 1324 1.4 mrg [(set (match_dup 3) 1325 1.4 mrg (unspec:V16QI [(match_operand:SI 2 "const_shift_by_byte_operand" "") 1326 1.4 mrg (const_int 7) 1327 1.4 mrg (match_dup 3)] 1328 1.4 mrg UNSPEC_VEC_SET)) 1329 1.4 mrg (set (match_operand:V_128 0 "register_operand" "") 1330 1.4 mrg (unspec:V_128 [(match_operand:V_128 1 "register_operand" "") 1331 1.4 mrg (match_dup 3)] 1332 1.4 mrg UNSPEC_VEC_SLB))] 1333 1.4 mrg "TARGET_VX" 1334 1.4 mrg { 1335 1.4 mrg operands[3] = gen_reg_rtx(V16QImode); 1336 1.4 mrg }) 1337 1.4 mrg 1338 1.1 mrg ; vmnb, vmnh, vmnf, vmng 1339 1.1 mrg (define_insn "smin<mode>3" 1340 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1341 1.6 mrg (smin:VI (match_operand:VI 1 "register_operand" "v") 1342 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1343 1.1 mrg "TARGET_VX" 1344 1.1 mrg "vmn<bhfgq>\t%v0,%v1,%v2" 1345 1.1 mrg [(set_attr "op_type" "VRR")]) 1346 1.1 mrg 1347 1.1 mrg ; vmxb, vmxh, vmxf, vmxg 1348 1.1 mrg (define_insn "smax<mode>3" 1349 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1350 1.6 mrg (smax:VI (match_operand:VI 1 "register_operand" "v") 1351 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1352 1.1 mrg "TARGET_VX" 1353 1.1 mrg "vmx<bhfgq>\t%v0,%v1,%v2" 1354 1.1 mrg [(set_attr "op_type" "VRR")]) 1355 1.1 mrg 1356 1.1 mrg ; vmnlb, vmnlh, vmnlf, vmnlg 1357 1.1 mrg (define_insn "umin<mode>3" 1358 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1359 1.6 mrg (umin:VI (match_operand:VI 1 "register_operand" "v") 1360 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1361 1.1 mrg "TARGET_VX" 1362 1.1 mrg "vmnl<bhfgq>\t%v0,%v1,%v2" 1363 1.1 mrg [(set_attr "op_type" "VRR")]) 1364 1.1 mrg 1365 1.1 mrg ; vmxlb, vmxlh, vmxlf, vmxlg 1366 1.1 mrg (define_insn "umax<mode>3" 1367 1.1 mrg [(set (match_operand:VI 0 "register_operand" "=v") 1368 1.6 mrg (umax:VI (match_operand:VI 1 "register_operand" "v") 1369 1.1 mrg (match_operand:VI 2 "register_operand" "v")))] 1370 1.1 mrg "TARGET_VX" 1371 1.1 mrg "vmxl<bhfgq>\t%v0,%v1,%v2" 1372 1.1 mrg [(set_attr "op_type" "VRR")]) 1373 1.1 mrg 1374 1.1 mrg ; vmeb, vmeh, vmef 1375 1.1 mrg (define_insn "vec_widen_smult_even_<mode>" 1376 1.1 mrg [(set (match_operand:<vec_double> 0 "register_operand" "=v") 1377 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v") 1378 1.1 mrg (match_operand:VI_QHS 2 "register_operand" "v")] 1379 1.1 mrg UNSPEC_VEC_SMULT_EVEN))] 1380 1.1 mrg "TARGET_VX" 1381 1.1 mrg "vme<bhfgq>\t%v0,%v1,%v2" 1382 1.1 mrg [(set_attr "op_type" "VRR")]) 1383 1.1 mrg 1384 1.1 mrg ; vmleb, vmleh, vmlef 1385 1.1 mrg (define_insn "vec_widen_umult_even_<mode>" 1386 1.1 mrg [(set (match_operand:<vec_double> 0 "register_operand" "=v") 1387 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v") 1388 1.1 mrg (match_operand:VI_QHS 2 "register_operand" "v")] 1389 1.1 mrg UNSPEC_VEC_UMULT_EVEN))] 1390 1.1 mrg "TARGET_VX" 1391 1.1 mrg "vmle<bhfgq>\t%v0,%v1,%v2" 1392 1.1 mrg [(set_attr "op_type" "VRR")]) 1393 1.1 mrg 1394 1.1 mrg ; vmob, vmoh, vmof 1395 1.1 mrg (define_insn "vec_widen_smult_odd_<mode>" 1396 1.1 mrg [(set (match_operand:<vec_double> 0 "register_operand" "=v") 1397 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v") 1398 1.1 mrg (match_operand:VI_QHS 2 "register_operand" "v")] 1399 1.1 mrg UNSPEC_VEC_SMULT_ODD))] 1400 1.1 mrg "TARGET_VX" 1401 1.1 mrg "vmo<bhfgq>\t%v0,%v1,%v2" 1402 1.1 mrg [(set_attr "op_type" "VRR")]) 1403 1.1 mrg 1404 1.1 mrg ; vmlob, vmloh, vmlof 1405 1.1 mrg (define_insn "vec_widen_umult_odd_<mode>" 1406 1.1 mrg [(set (match_operand:<vec_double> 0 "register_operand" "=v") 1407 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "v") 1408 1.1 mrg (match_operand:VI_QHS 2 "register_operand" "v")] 1409 1.1 mrg UNSPEC_VEC_UMULT_ODD))] 1410 1.1 mrg "TARGET_VX" 1411 1.1 mrg "vmlo<bhfgq>\t%v0,%v1,%v2" 1412 1.1 mrg [(set_attr "op_type" "VRR")]) 1413 1.1 mrg 1414 1.4 mrg 1415 1.4 mrg ; Widening hi/lo multiplications 1416 1.4 mrg 1417 1.4 mrg ; The S/390 instructions vml and vmh return the low or high parts of 1418 1.4 mrg ; the double sized result elements in the corresponding elements of 1419 1.4 mrg ; the target register. That's NOT what the vec_widen_umult_lo/hi 1420 1.4 mrg ; patterns are expected to do. 1421 1.4 mrg 1422 1.4 mrg ; We emulate the widening lo/hi multiplies with the even/odd versions 1423 1.4 mrg ; followed by a vector merge 1424 1.4 mrg 1425 1.4 mrg 1426 1.4 mrg (define_expand "vec_widen_umult_lo_<mode>" 1427 1.4 mrg [(set (match_dup 3) 1428 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "") 1429 1.6 mrg (match_operand:VI_QHS 2 "register_operand" "")] 1430 1.4 mrg UNSPEC_VEC_UMULT_EVEN)) 1431 1.4 mrg (set (match_dup 4) 1432 1.4 mrg (unspec:<vec_double> [(match_dup 1) (match_dup 2)] 1433 1.4 mrg UNSPEC_VEC_UMULT_ODD)) 1434 1.6 mrg (set (match_operand:<vec_double> 0 "register_operand" "") 1435 1.7 mrg (vec_select:<vec_double> 1436 1.7 mrg (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4)) 1437 1.7 mrg (match_dup 5)))] 1438 1.4 mrg "TARGET_VX" 1439 1.4 mrg { 1440 1.4 mrg operands[3] = gen_reg_rtx (<vec_double>mode); 1441 1.4 mrg operands[4] = gen_reg_rtx (<vec_double>mode); 1442 1.7 mrg operands[5] = s390_expand_merge_perm_const (<vec_double>mode, false); 1443 1.4 mrg }) 1444 1.4 mrg 1445 1.4 mrg (define_expand "vec_widen_umult_hi_<mode>" 1446 1.4 mrg [(set (match_dup 3) 1447 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "") 1448 1.6 mrg (match_operand:VI_QHS 2 "register_operand" "")] 1449 1.4 mrg UNSPEC_VEC_UMULT_EVEN)) 1450 1.4 mrg (set (match_dup 4) 1451 1.4 mrg (unspec:<vec_double> [(match_dup 1) (match_dup 2)] 1452 1.4 mrg UNSPEC_VEC_UMULT_ODD)) 1453 1.6 mrg (set (match_operand:<vec_double> 0 "register_operand" "") 1454 1.7 mrg (vec_select:<vec_double> 1455 1.7 mrg (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4)) 1456 1.7 mrg (match_dup 5)))] 1457 1.4 mrg "TARGET_VX" 1458 1.4 mrg { 1459 1.4 mrg operands[3] = gen_reg_rtx (<vec_double>mode); 1460 1.4 mrg operands[4] = gen_reg_rtx (<vec_double>mode); 1461 1.7 mrg operands[5] = s390_expand_merge_perm_const (<vec_double>mode, true); 1462 1.4 mrg }) 1463 1.4 mrg 1464 1.4 mrg (define_expand "vec_widen_smult_lo_<mode>" 1465 1.4 mrg [(set (match_dup 3) 1466 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "") 1467 1.6 mrg (match_operand:VI_QHS 2 "register_operand" "")] 1468 1.4 mrg UNSPEC_VEC_SMULT_EVEN)) 1469 1.4 mrg (set (match_dup 4) 1470 1.4 mrg (unspec:<vec_double> [(match_dup 1) (match_dup 2)] 1471 1.4 mrg UNSPEC_VEC_SMULT_ODD)) 1472 1.6 mrg (set (match_operand:<vec_double> 0 "register_operand" "") 1473 1.7 mrg (vec_select:<vec_double> 1474 1.7 mrg (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4)) 1475 1.7 mrg (match_dup 5)))] 1476 1.4 mrg "TARGET_VX" 1477 1.4 mrg { 1478 1.4 mrg operands[3] = gen_reg_rtx (<vec_double>mode); 1479 1.4 mrg operands[4] = gen_reg_rtx (<vec_double>mode); 1480 1.7 mrg operands[5] = s390_expand_merge_perm_const (<vec_double>mode, false); 1481 1.4 mrg }) 1482 1.4 mrg 1483 1.4 mrg (define_expand "vec_widen_smult_hi_<mode>" 1484 1.4 mrg [(set (match_dup 3) 1485 1.6 mrg (unspec:<vec_double> [(match_operand:VI_QHS 1 "register_operand" "") 1486 1.6 mrg (match_operand:VI_QHS 2 "register_operand" "")] 1487 1.4 mrg UNSPEC_VEC_SMULT_EVEN)) 1488 1.4 mrg (set (match_dup 4) 1489 1.4 mrg (unspec:<vec_double> [(match_dup 1) (match_dup 2)] 1490 1.4 mrg UNSPEC_VEC_SMULT_ODD)) 1491 1.6 mrg (set (match_operand:<vec_double> 0 "register_operand" "") 1492 1.7 mrg (vec_select:<vec_double> 1493 1.7 mrg (vec_concat:<vec_2x_wide> (match_dup 3) (match_dup 4)) 1494 1.7 mrg (match_dup 5)))] 1495 1.4 mrg "TARGET_VX" 1496 1.4 mrg { 1497 1.4 mrg operands[3] = gen_reg_rtx (<vec_double>mode); 1498 1.4 mrg operands[4] = gen_reg_rtx (<vec_double>mode); 1499 1.7 mrg operands[5] = s390_expand_merge_perm_const (<vec_double>mode, true); 1500 1.4 mrg }) 1501 1.1 mrg 1502 1.1 mrg ; vec_widen_ushiftl_hi 1503 1.1 mrg ; vec_widen_ushiftl_lo 1504 1.1 mrg ; vec_widen_sshiftl_hi 1505 1.1 mrg ; vec_widen_sshiftl_lo 1506 1.1 mrg 1507 1.1 mrg ;; 1508 1.1 mrg ;; Vector floating point arithmetic instructions 1509 1.1 mrg ;; 1510 1.1 mrg 1511 1.3 mrg ; vfasb, vfadb, wfasb, wfadb, wfaxb 1512 1.7 mrg (define_insn "add<mode>3<tf_vr>" 1513 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1514 1.6 mrg (plus:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1515 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v")))] 1516 1.1 mrg "TARGET_VX" 1517 1.3 mrg "<vw>fa<sdx>b\t%v0,%v1,%v2" 1518 1.1 mrg [(set_attr "op_type" "VRR")]) 1519 1.1 mrg 1520 1.7 mrg (define_expand "addtf3" 1521 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1522 1.7 mrg (match_operand:TF 1 "nonimmediate_operand" "") 1523 1.7 mrg (match_operand:TF 2 "general_operand" "")] 1524 1.7 mrg "HAVE_TF (addtf3)" 1525 1.7 mrg { EXPAND_TF (addtf3, 3); }) 1526 1.7 mrg 1527 1.3 mrg ; vfssb, vfsdb, wfssb, wfsdb, wfsxb 1528 1.7 mrg (define_insn "sub<mode>3<tf_vr>" 1529 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1530 1.6 mrg (minus:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1531 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v")))] 1532 1.1 mrg "TARGET_VX" 1533 1.3 mrg "<vw>fs<sdx>b\t%v0,%v1,%v2" 1534 1.1 mrg [(set_attr "op_type" "VRR")]) 1535 1.1 mrg 1536 1.7 mrg (define_expand "subtf3" 1537 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1538 1.7 mrg (match_operand:TF 1 "register_operand" "") 1539 1.7 mrg (match_operand:TF 2 "general_operand" "")] 1540 1.7 mrg "HAVE_TF (subtf3)" 1541 1.7 mrg { EXPAND_TF (subtf3, 3); }) 1542 1.7 mrg 1543 1.3 mrg ; vfmsb, vfmdb, wfmsb, wfmdb, wfmxb 1544 1.7 mrg (define_insn "mul<mode>3<tf_vr>" 1545 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1546 1.6 mrg (mult:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1547 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v")))] 1548 1.1 mrg "TARGET_VX" 1549 1.3 mrg "<vw>fm<sdx>b\t%v0,%v1,%v2" 1550 1.1 mrg [(set_attr "op_type" "VRR")]) 1551 1.1 mrg 1552 1.7 mrg (define_expand "multf3" 1553 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1554 1.7 mrg (match_operand:TF 1 "nonimmediate_operand" "") 1555 1.7 mrg (match_operand:TF 2 "general_operand" "")] 1556 1.7 mrg "HAVE_TF (multf3)" 1557 1.7 mrg { EXPAND_TF (multf3, 3); }) 1558 1.7 mrg 1559 1.3 mrg ; vfdsb, vfddb, wfdsb, wfddb, wfdxb 1560 1.7 mrg (define_insn "div<mode>3<tf_vr>" 1561 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1562 1.3 mrg (div:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1563 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v")))] 1564 1.1 mrg "TARGET_VX" 1565 1.3 mrg "<vw>fd<sdx>b\t%v0,%v1,%v2" 1566 1.1 mrg [(set_attr "op_type" "VRR")]) 1567 1.1 mrg 1568 1.7 mrg (define_expand "divtf3" 1569 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1570 1.7 mrg (match_operand:TF 1 "register_operand" "") 1571 1.7 mrg (match_operand:TF 2 "general_operand" "")] 1572 1.7 mrg "HAVE_TF (divtf3)" 1573 1.7 mrg { EXPAND_TF (divtf3, 3); }) 1574 1.7 mrg 1575 1.3 mrg ; vfsqsb, vfsqdb, wfsqsb, wfsqdb, wfsqxb 1576 1.7 mrg (define_insn "sqrt<mode>2<tf_vr>" 1577 1.7 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1578 1.3 mrg (sqrt:VF_HW (match_operand:VF_HW 1 "register_operand" "v")))] 1579 1.1 mrg "TARGET_VX" 1580 1.3 mrg "<vw>fsq<sdx>b\t%v0,%v1" 1581 1.1 mrg [(set_attr "op_type" "VRR")]) 1582 1.1 mrg 1583 1.7 mrg (define_expand "sqrttf2" 1584 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1585 1.7 mrg (match_operand:TF 1 "general_operand" "")] 1586 1.7 mrg "HAVE_TF (sqrttf2)" 1587 1.7 mrg { EXPAND_TF (sqrttf2, 2); }) 1588 1.7 mrg 1589 1.3 mrg ; vfmasb, vfmadb, wfmasb, wfmadb, wfmaxb 1590 1.3 mrg (define_insn "fma<mode>4" 1591 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1592 1.6 mrg (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1593 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v") 1594 1.3 mrg (match_operand:VF_HW 3 "register_operand" "v")))] 1595 1.7 mrg "TARGET_VX && s390_fma_allowed_p (<MODE>mode)" 1596 1.3 mrg "<vw>fma<sdx>b\t%v0,%v1,%v2,%v3" 1597 1.1 mrg [(set_attr "op_type" "VRR")]) 1598 1.1 mrg 1599 1.3 mrg ; vfmssb, vfmsdb, wfmssb, wfmsdb, wfmsxb 1600 1.3 mrg (define_insn "fms<mode>4" 1601 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1602 1.6 mrg (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1603 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v") 1604 1.3 mrg (neg:VF_HW (match_operand:VF_HW 3 "register_operand" "v"))))] 1605 1.7 mrg "TARGET_VX && s390_fma_allowed_p (<MODE>mode)" 1606 1.3 mrg "<vw>fms<sdx>b\t%v0,%v1,%v2,%v3" 1607 1.3 mrg [(set_attr "op_type" "VRR")]) 1608 1.3 mrg 1609 1.3 mrg ; vfnmasb, vfnmadb, wfnmasb, wfnmadb, wfnmaxb 1610 1.3 mrg (define_insn "neg_fma<mode>4" 1611 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1612 1.3 mrg (neg:VF_HW 1613 1.6 mrg (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1614 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v") 1615 1.3 mrg (match_operand:VF_HW 3 "register_operand" "v"))))] 1616 1.7 mrg "TARGET_VXE && s390_fma_allowed_p (<MODE>mode)" 1617 1.3 mrg "<vw>fnma<sdx>b\t%v0,%v1,%v2,%v3" 1618 1.1 mrg [(set_attr "op_type" "VRR")]) 1619 1.1 mrg 1620 1.3 mrg ; vfnmssb, vfnmsdb, wfnmssb, wfnmsdb, wfnmsxb 1621 1.3 mrg (define_insn "neg_fms<mode>4" 1622 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1623 1.3 mrg (neg:VF_HW 1624 1.6 mrg (fma:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1625 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v") 1626 1.3 mrg (neg:VF_HW (match_operand:VF_HW 3 "register_operand" "v")))))] 1627 1.7 mrg "TARGET_VXE && s390_fma_allowed_p (<MODE>mode)" 1628 1.3 mrg "<vw>fnms<sdx>b\t%v0,%v1,%v2,%v3" 1629 1.3 mrg [(set_attr "op_type" "VRR")]) 1630 1.3 mrg 1631 1.3 mrg ; vflcsb, vflcdb, wflcsb, wflcdb, wflcxb 1632 1.7 mrg (define_insn "neg<mode>2<tf_vr>" 1633 1.3 mrg [(set (match_operand:VFT 0 "register_operand" "=v") 1634 1.3 mrg (neg:VFT (match_operand:VFT 1 "register_operand" "v")))] 1635 1.1 mrg "TARGET_VX" 1636 1.3 mrg "<vw>flc<sdx>b\t%v0,%v1" 1637 1.1 mrg [(set_attr "op_type" "VRR")]) 1638 1.1 mrg 1639 1.7 mrg (define_expand "negtf2" 1640 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1641 1.7 mrg (match_operand:TF 1 "register_operand" "")] 1642 1.7 mrg "HAVE_TF (negtf2)" 1643 1.7 mrg { EXPAND_TF (negtf2, 2); }) 1644 1.7 mrg 1645 1.3 mrg ; vflpsb, vflpdb, wflpsb, wflpdb, wflpxb 1646 1.7 mrg (define_insn "abs<mode>2<tf_vr>" 1647 1.3 mrg [(set (match_operand:VFT 0 "register_operand" "=v") 1648 1.3 mrg (abs:VFT (match_operand:VFT 1 "register_operand" "v")))] 1649 1.1 mrg "TARGET_VX" 1650 1.3 mrg "<vw>flp<sdx>b\t%v0,%v1" 1651 1.1 mrg [(set_attr "op_type" "VRR")]) 1652 1.1 mrg 1653 1.7 mrg (define_expand "abstf2" 1654 1.7 mrg [(match_operand:TF 0 "register_operand" "") 1655 1.7 mrg (match_operand:TF 1 "register_operand" "")] 1656 1.7 mrg "HAVE_TF (abstf2)" 1657 1.7 mrg { EXPAND_TF (abstf2, 2); }) 1658 1.7 mrg 1659 1.3 mrg ; vflnsb, vflndb, wflnsb, wflndb, wflnxb 1660 1.3 mrg (define_insn "negabs<mode>2" 1661 1.3 mrg [(set (match_operand:VFT 0 "register_operand" "=v") 1662 1.3 mrg (neg:VFT (abs:VFT (match_operand:VFT 1 "register_operand" "v"))))] 1663 1.1 mrg "TARGET_VX" 1664 1.3 mrg "<vw>fln<sdx>b\t%v0,%v1" 1665 1.3 mrg [(set_attr "op_type" "VRR")]) 1666 1.3 mrg 1667 1.3 mrg (define_expand "smax<mode>3" 1668 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand") 1669 1.3 mrg (smax:VF_HW (match_operand:VF_HW 1 "register_operand") 1670 1.3 mrg (match_operand:VF_HW 2 "register_operand")))] 1671 1.3 mrg "TARGET_VX") 1672 1.3 mrg 1673 1.3 mrg ; vfmaxsb, vfmaxdb, wfmaxsb, wfmaxdb, wfmaxxb 1674 1.3 mrg (define_insn "*smax<mode>3_vxe" 1675 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1676 1.6 mrg (smax:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1677 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v")))] 1678 1.3 mrg "TARGET_VXE" 1679 1.3 mrg "<vw>fmax<sdx>b\t%v0,%v1,%v2,4" 1680 1.1 mrg [(set_attr "op_type" "VRR")]) 1681 1.1 mrg 1682 1.1 mrg ; Emulate with compare + select 1683 1.3 mrg (define_insn_and_split "*smaxv2df3_vx" 1684 1.1 mrg [(set (match_operand:V2DF 0 "register_operand" "=v") 1685 1.6 mrg (smax:V2DF (match_operand:V2DF 1 "register_operand" "v") 1686 1.1 mrg (match_operand:V2DF 2 "register_operand" "v")))] 1687 1.3 mrg "TARGET_VX && !TARGET_VXE" 1688 1.1 mrg "#" 1689 1.3 mrg "&& 1" 1690 1.1 mrg [(set (match_dup 3) 1691 1.6 mrg (not:V2DI 1692 1.6 mrg (unge:V2DI (match_dup 2) (match_dup 1)))) 1693 1.1 mrg (set (match_dup 0) 1694 1.1 mrg (if_then_else:V2DF 1695 1.1 mrg (eq (match_dup 3) (match_dup 4)) 1696 1.1 mrg (match_dup 2) 1697 1.1 mrg (match_dup 1)))] 1698 1.1 mrg { 1699 1.1 mrg operands[3] = gen_reg_rtx (V2DImode); 1700 1.1 mrg operands[4] = CONST0_RTX (V2DImode); 1701 1.1 mrg }) 1702 1.1 mrg 1703 1.3 mrg (define_expand "smin<mode>3" 1704 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand") 1705 1.3 mrg (smin:VF_HW (match_operand:VF_HW 1 "register_operand") 1706 1.3 mrg (match_operand:VF_HW 2 "register_operand")))] 1707 1.3 mrg "TARGET_VX") 1708 1.3 mrg 1709 1.3 mrg ; vfminsb, vfmindb, wfminsb, wfmindb, wfminxb 1710 1.3 mrg (define_insn "*smin<mode>3_vxe" 1711 1.3 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 1712 1.6 mrg (smin:VF_HW (match_operand:VF_HW 1 "register_operand" "v") 1713 1.3 mrg (match_operand:VF_HW 2 "register_operand" "v")))] 1714 1.3 mrg "TARGET_VXE" 1715 1.3 mrg "<vw>fmin<sdx>b\t%v0,%v1,%v2,4" 1716 1.3 mrg [(set_attr "op_type" "VRR")]) 1717 1.3 mrg 1718 1.1 mrg ; Emulate with compare + select 1719 1.3 mrg (define_insn_and_split "*sminv2df3_vx" 1720 1.1 mrg [(set (match_operand:V2DF 0 "register_operand" "=v") 1721 1.6 mrg (smin:V2DF (match_operand:V2DF 1 "register_operand" "v") 1722 1.1 mrg (match_operand:V2DF 2 "register_operand" "v")))] 1723 1.3 mrg "TARGET_VX && !TARGET_VXE" 1724 1.1 mrg "#" 1725 1.3 mrg "&& 1" 1726 1.1 mrg [(set (match_dup 3) 1727 1.6 mrg (not:V2DI 1728 1.6 mrg (unge:V2DI (match_dup 2) (match_dup 1)))) 1729 1.1 mrg (set (match_dup 0) 1730 1.1 mrg (if_then_else:V2DF 1731 1.1 mrg (eq (match_dup 3) (match_dup 4)) 1732 1.1 mrg (match_dup 1) 1733 1.1 mrg (match_dup 2)))] 1734 1.1 mrg { 1735 1.1 mrg operands[3] = gen_reg_rtx (V2DImode); 1736 1.1 mrg operands[4] = CONST0_RTX (V2DImode); 1737 1.1 mrg }) 1738 1.1 mrg 1739 1.5 mrg ; Vector copysign, implement using vector select 1740 1.5 mrg (define_expand "copysign<mode>3" 1741 1.7 mrg [(set (match_operand:VFT 0 "register_operand" "") 1742 1.7 mrg (ior:VFT 1743 1.7 mrg (and:VFT (match_operand:VFT 2 "register_operand" "") 1744 1.7 mrg (match_dup 3)) 1745 1.7 mrg (and:VFT (not:VFT (match_dup 3)) 1746 1.7 mrg (match_operand:VFT 1 "register_operand" ""))))] 1747 1.5 mrg "TARGET_VX" 1748 1.5 mrg { 1749 1.7 mrg rtx mask = s390_build_signbit_mask (<MODE>mode); 1750 1.7 mrg operands[3] = force_reg (<MODE>mode, mask); 1751 1.7 mrg }) 1752 1.5 mrg 1753 1.7 mrg ;; 1754 1.7 mrg ;; Compares 1755 1.7 mrg ;; 1756 1.5 mrg 1757 1.7 mrg (define_expand "vec_cmp<mode><tointvec>" 1758 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "") 1759 1.7 mrg (match_operator:<TOINTVEC> 1 "vcond_comparison_operator" 1760 1.7 mrg [(match_operand:V_HW 2 "register_operand" "") 1761 1.7 mrg (match_operand:V_HW 3 "nonmemory_operand" "")]))] 1762 1.7 mrg "TARGET_VX" 1763 1.7 mrg { 1764 1.7 mrg s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], operands[3]); 1765 1.7 mrg DONE; 1766 1.7 mrg }) 1767 1.5 mrg 1768 1.7 mrg (define_expand "vec_cmpu<VI_HW:mode><VI_HW:mode>" 1769 1.7 mrg [(set (match_operand:VI_HW 0 "register_operand" "") 1770 1.7 mrg (match_operator:VI_HW 1 "" 1771 1.7 mrg [(match_operand:VI_HW 2 "register_operand" "") 1772 1.7 mrg (match_operand:VI_HW 3 "register_operand" "")]))] 1773 1.7 mrg "TARGET_VX" 1774 1.7 mrg { 1775 1.7 mrg s390_expand_vec_compare (operands[0], GET_CODE(operands[1]), operands[2], operands[3]); 1776 1.7 mrg DONE; 1777 1.5 mrg }) 1778 1.1 mrg 1779 1.7 mrg (define_insn "*vec_cmp<VICMP_HW_OP:code><VI:mode><VI:mode>_nocc" 1780 1.1 mrg [(set (match_operand:VI 2 "register_operand" "=v") 1781 1.1 mrg (VICMP_HW_OP:VI (match_operand:VI 0 "register_operand" "v") 1782 1.1 mrg (match_operand:VI 1 "register_operand" "v")))] 1783 1.1 mrg "TARGET_VX" 1784 1.1 mrg "vc<VICMP_HW_OP:insn_cmp_op><VI:bhfgq>\t%v2,%v0,%v1" 1785 1.1 mrg [(set_attr "op_type" "VRR")]) 1786 1.1 mrg 1787 1.1 mrg 1788 1.1 mrg ;; 1789 1.1 mrg ;; Floating point compares 1790 1.1 mrg ;; 1791 1.1 mrg 1792 1.6 mrg ; vfcesb, vfcedb, wfcexb: non-signaling "==" comparison (a == b) 1793 1.6 mrg (define_insn "*vec_cmpeq<mode>_quiet_nocc" 1794 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1795 1.7 mrg (eq:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1796 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))] 1797 1.6 mrg "TARGET_VX" 1798 1.6 mrg "<vw>fce<sdx>b\t%v0,%v1,%v2" 1799 1.6 mrg [(set_attr "op_type" "VRR")]) 1800 1.6 mrg 1801 1.6 mrg ; vfchsb, vfchdb, wfchxb: non-signaling > comparison (!(b u>= a)) 1802 1.6 mrg (define_insn "vec_cmpgt<mode>_quiet_nocc" 1803 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1804 1.7 mrg (not:<TOINTVEC> 1805 1.7 mrg (unge:<TOINTVEC> (match_operand:VFT 2 "register_operand" "v") 1806 1.6 mrg (match_operand:VFT 1 "register_operand" "v"))))] 1807 1.6 mrg "TARGET_VX" 1808 1.6 mrg "<vw>fch<sdx>b\t%v0,%v1,%v2" 1809 1.6 mrg [(set_attr "op_type" "VRR")]) 1810 1.6 mrg 1811 1.6 mrg (define_expand "vec_cmplt<mode>_quiet_nocc" 1812 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1813 1.7 mrg (not:<TOINTVEC> 1814 1.7 mrg (unge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1815 1.6 mrg (match_operand:VFT 2 "register_operand" "v"))))] 1816 1.6 mrg "TARGET_VX") 1817 1.6 mrg 1818 1.6 mrg ; vfchesb, vfchedb, wfchexb: non-signaling >= comparison (!(a u< b)) 1819 1.6 mrg (define_insn "vec_cmpge<mode>_quiet_nocc" 1820 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1821 1.7 mrg (not:<TOINTVEC> 1822 1.7 mrg (unlt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1823 1.6 mrg (match_operand:VFT 2 "register_operand" "v"))))] 1824 1.6 mrg "TARGET_VX" 1825 1.6 mrg "<vw>fche<sdx>b\t%v0,%v1,%v2" 1826 1.6 mrg [(set_attr "op_type" "VRR")]) 1827 1.6 mrg 1828 1.6 mrg (define_expand "vec_cmple<mode>_quiet_nocc" 1829 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1830 1.7 mrg (not:<TOINTVEC> 1831 1.7 mrg (unlt:<TOINTVEC> (match_operand:VFT 2 "register_operand" "v") 1832 1.6 mrg (match_operand:VFT 1 "register_operand" "v"))))] 1833 1.6 mrg "TARGET_VX") 1834 1.6 mrg 1835 1.6 mrg ; vfkesb, vfkedb, wfkexb: signaling == comparison ((a >= b) & (b >= a)) 1836 1.6 mrg (define_insn "*vec_cmpeq<mode>_signaling_nocc" 1837 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1838 1.7 mrg (and:<TOINTVEC> 1839 1.7 mrg (ge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1840 1.6 mrg (match_operand:VFT 2 "register_operand" "v")) 1841 1.7 mrg (ge:<TOINTVEC> (match_dup 2) 1842 1.6 mrg (match_dup 1))))] 1843 1.6 mrg "TARGET_VXE" 1844 1.6 mrg "<vw>fke<sdx>b\t%v0,%v1,%v2" 1845 1.6 mrg [(set_attr "op_type" "VRR")]) 1846 1.6 mrg 1847 1.6 mrg ; vfkhsb, vfkhdb, wfkhxb: signaling > comparison (a > b) 1848 1.6 mrg (define_insn "*vec_cmpgt<mode>_signaling_nocc" 1849 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1850 1.7 mrg (gt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1851 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))] 1852 1.6 mrg "TARGET_VXE" 1853 1.6 mrg "<vw>fkh<sdx>b\t%v0,%v1,%v2" 1854 1.6 mrg [(set_attr "op_type" "VRR")]) 1855 1.6 mrg 1856 1.6 mrg (define_insn "*vec_cmpgt<mode>_signaling_finite_nocc" 1857 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1858 1.7 mrg (gt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1859 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))] 1860 1.6 mrg "TARGET_NONSIGNALING_VECTOR_COMPARE_OK" 1861 1.6 mrg "<vw>fch<sdx>b\t%v0,%v1,%v2" 1862 1.6 mrg [(set_attr "op_type" "VRR")]) 1863 1.6 mrg 1864 1.6 mrg ; vfkhesb, vfkhedb, wfkhexb: signaling >= comparison (a >= b) 1865 1.6 mrg (define_insn "*vec_cmpge<mode>_signaling_nocc" 1866 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1867 1.7 mrg (ge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1868 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))] 1869 1.6 mrg "TARGET_VXE" 1870 1.6 mrg "<vw>fkhe<sdx>b\t%v0,%v1,%v2" 1871 1.6 mrg [(set_attr "op_type" "VRR")]) 1872 1.6 mrg 1873 1.6 mrg (define_insn "*vec_cmpge<mode>_signaling_finite_nocc" 1874 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1875 1.7 mrg (ge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1876 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))] 1877 1.6 mrg "TARGET_NONSIGNALING_VECTOR_COMPARE_OK" 1878 1.6 mrg "<vw>fche<sdx>b\t%v0,%v1,%v2" 1879 1.1 mrg [(set_attr "op_type" "VRR")]) 1880 1.1 mrg 1881 1.1 mrg ; Expanders for not directly supported comparisons 1882 1.6 mrg ; Signaling comparisons must be expressed via signaling rtxes only, 1883 1.6 mrg ; and quiet comparisons must be expressed via quiet rtxes only. 1884 1.6 mrg 1885 1.6 mrg ; UNGT a u> b -> !!(b u< a) 1886 1.6 mrg (define_expand "vec_cmpungt<mode>" 1887 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1888 1.7 mrg (not:<TOINTVEC> 1889 1.7 mrg (unlt:<TOINTVEC> (match_operand:VFT 2 "register_operand" "v") 1890 1.6 mrg (match_operand:VFT 1 "register_operand" "v")))) 1891 1.6 mrg (set (match_dup 0) 1892 1.7 mrg (not:<TOINTVEC> (match_dup 0)))] 1893 1.6 mrg "TARGET_VX") 1894 1.6 mrg 1895 1.6 mrg ; UNGE a u>= b -> !!(a u>= b) 1896 1.6 mrg (define_expand "vec_cmpunge<mode>" 1897 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1898 1.7 mrg (not:<TOINTVEC> 1899 1.7 mrg (unge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1900 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))) 1901 1.6 mrg (set (match_dup 0) 1902 1.7 mrg (not:<TOINTVEC> (match_dup 0)))] 1903 1.6 mrg "TARGET_VX") 1904 1.1 mrg 1905 1.6 mrg ; UNEQ a u== b -> !(!(a u>= b) | !(b u>= a)) 1906 1.3 mrg (define_expand "vec_cmpuneq<mode>" 1907 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1908 1.7 mrg (not:<TOINTVEC> 1909 1.7 mrg (unge:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1910 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))) 1911 1.6 mrg (set (match_dup 3) 1912 1.7 mrg (not:<TOINTVEC> 1913 1.7 mrg (unge:<TOINTVEC> (match_dup 2) 1914 1.6 mrg (match_dup 1)))) 1915 1.6 mrg (set (match_dup 0) 1916 1.7 mrg (ior:<TOINTVEC> (match_dup 0) 1917 1.6 mrg (match_dup 3))) 1918 1.6 mrg (set (match_dup 0) 1919 1.7 mrg (not:<TOINTVEC> (match_dup 0)))] 1920 1.1 mrg "TARGET_VX" 1921 1.1 mrg { 1922 1.7 mrg operands[3] = gen_reg_rtx (<TOINTVEC>mode); 1923 1.1 mrg }) 1924 1.1 mrg 1925 1.1 mrg ; LTGT a <> b -> a > b | b > a 1926 1.3 mrg (define_expand "vec_cmpltgt<mode>" 1927 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1928 1.7 mrg (gt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1929 1.3 mrg (match_operand:VFT 2 "register_operand" "v"))) 1930 1.7 mrg (set (match_dup 3) (gt:<TOINTVEC> (match_dup 2) (match_dup 1))) 1931 1.7 mrg (set (match_dup 0) (ior:<TOINTVEC> (match_dup 0) (match_dup 3)))] 1932 1.6 mrg "TARGET_VXE" 1933 1.1 mrg { 1934 1.7 mrg operands[3] = gen_reg_rtx (<TOINTVEC>mode); 1935 1.1 mrg }) 1936 1.1 mrg 1937 1.6 mrg ; ORDERED (a, b): !(a u< b) | !(a u>= b) 1938 1.6 mrg (define_expand "vec_cmpordered<mode>" 1939 1.7 mrg [(set (match_operand:<TOINTVEC> 0 "register_operand" "=v") 1940 1.7 mrg (not:<TOINTVEC> 1941 1.7 mrg (unlt:<TOINTVEC> (match_operand:VFT 1 "register_operand" "v") 1942 1.6 mrg (match_operand:VFT 2 "register_operand" "v")))) 1943 1.6 mrg (set (match_dup 3) 1944 1.7 mrg (not:<TOINTVEC> 1945 1.7 mrg (unge:<TOINTVEC> (match_dup 1) 1946 1.6 mrg (match_dup 2)))) 1947 1.6 mrg (set (match_dup 0) 1948 1.7 mrg (ior:<TOINTVEC> (match_dup 0) 1949 1.6 mrg (match_dup 3)))] 1950 1.1 mrg "TARGET_VX" 1951 1.1 mrg { 1952 1.7 mrg operands[3] = gen_reg_rtx (<TOINTVEC>mode); 1953 1.1 mrg }) 1954 1.1 mrg 1955 1.6 mrg ; UNORDERED (a, b): !ORDERED (a, b) 1956 1.6 mrg (define_expand "vec_cmpunordered<mode>" 1957 1.7 mrg [(match_operand:<TOINTVEC> 0 "register_operand" "=v") 1958 1.6 mrg (match_operand:VFT 1 "register_operand" "v") 1959 1.6 mrg (match_operand:VFT 2 "register_operand" "v")] 1960 1.4 mrg "TARGET_VX" 1961 1.4 mrg { 1962 1.6 mrg emit_insn (gen_vec_cmpordered<mode> (operands[0], operands[1], operands[2])); 1963 1.6 mrg emit_insn (gen_rtx_SET (operands[0], 1964 1.7 mrg gen_rtx_NOT (<TOINTVEC>mode, operands[0]))); 1965 1.4 mrg DONE; 1966 1.4 mrg }) 1967 1.4 mrg 1968 1.6 mrg (define_code_iterator VEC_CMP_EXPAND 1969 1.6 mrg [ungt unge uneq ltgt ordered unordered]) 1970 1.1 mrg 1971 1.6 mrg (define_expand "vec_cmp<code>" 1972 1.4 mrg [(match_operand 0 "register_operand" "") 1973 1.6 mrg (VEC_CMP_EXPAND (match_operand 1 "register_operand" "") 1974 1.6 mrg (match_operand 2 "register_operand" ""))] 1975 1.4 mrg "TARGET_VX" 1976 1.4 mrg { 1977 1.4 mrg if (GET_MODE (operands[1]) == V4SFmode) 1978 1.6 mrg emit_insn (gen_vec_cmp<code>v4sf (operands[0], operands[1], operands[2])); 1979 1.4 mrg else if (GET_MODE (operands[1]) == V2DFmode) 1980 1.6 mrg emit_insn (gen_vec_cmp<code>v2df (operands[0], operands[1], operands[2])); 1981 1.4 mrg else 1982 1.4 mrg gcc_unreachable (); 1983 1.4 mrg 1984 1.4 mrg DONE; 1985 1.4 mrg }) 1986 1.4 mrg 1987 1.3 mrg (define_insn "*vec_load_pair<mode>" 1988 1.7 mrg [(set (match_operand:V_HW_2 0 "register_operand" "=v,v") 1989 1.7 mrg (vec_concat:V_HW_2 (match_operand:<non_vec> 1 "register_operand" "d,v") 1990 1.7 mrg (match_operand:<non_vec> 2 "register_operand" "d,v")))] 1991 1.1 mrg "TARGET_VX" 1992 1.3 mrg "@ 1993 1.3 mrg vlvgp\t%v0,%1,%2 1994 1.3 mrg vmrhg\t%v0,%v1,%v2" 1995 1.3 mrg [(set_attr "op_type" "VRR,VRR")]) 1996 1.1 mrg 1997 1.1 mrg (define_insn "vllv16qi" 1998 1.1 mrg [(set (match_operand:V16QI 0 "register_operand" "=v") 1999 1.1 mrg (unspec:V16QI [(match_operand:SI 1 "register_operand" "d") 2000 1.1 mrg (match_operand:BLK 2 "memory_operand" "Q")] 2001 1.1 mrg UNSPEC_VEC_LOAD_LEN))] 2002 1.1 mrg "TARGET_VX" 2003 1.1 mrg "vll\t%v0,%1,%2" 2004 1.1 mrg [(set_attr "op_type" "VRS")]) 2005 1.1 mrg 2006 1.7 mrg ; vfeebs, vfeehs, vfeefs 2007 1.7 mrg ; vfeezbs, vfeezhs, vfeezfs 2008 1.7 mrg (define_insn "@vec_vfees<mode>" 2009 1.7 mrg [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") 2010 1.7 mrg (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") 2011 1.7 mrg (match_operand:VI_HW_QHS 2 "register_operand" "v") 2012 1.7 mrg (match_operand:QI 3 "const_mask_operand" "C")] 2013 1.7 mrg UNSPEC_VEC_VFEE)) 2014 1.7 mrg (set (reg:CCRAW CC_REGNUM) 2015 1.7 mrg (unspec:CCRAW [(match_dup 1) 2016 1.7 mrg (match_dup 2) 2017 1.7 mrg (match_dup 3)] 2018 1.7 mrg UNSPEC_VEC_VFEECC))] 2019 1.7 mrg "TARGET_VX" 2020 1.7 mrg { 2021 1.7 mrg unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]); 2022 1.7 mrg 2023 1.7 mrg gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); 2024 1.7 mrg flags &= ~VSTRING_FLAG_CS; 2025 1.7 mrg 2026 1.7 mrg if (flags == VSTRING_FLAG_ZS) 2027 1.7 mrg return "vfeez<bhfgq>s\t%v0,%v1,%v2"; 2028 1.7 mrg return "vfee<bhfgq>s\t%v0,%v1,%v2"; 2029 1.7 mrg } 2030 1.7 mrg [(set_attr "op_type" "VRR")]) 2031 1.7 mrg 2032 1.1 mrg ; vfenebs, vfenehs, vfenefs 2033 1.1 mrg ; vfenezbs, vfenezhs, vfenezfs 2034 1.1 mrg (define_insn "vec_vfenes<mode>" 2035 1.1 mrg [(set (match_operand:VI_HW_QHS 0 "register_operand" "=v") 2036 1.1 mrg (unspec:VI_HW_QHS [(match_operand:VI_HW_QHS 1 "register_operand" "v") 2037 1.1 mrg (match_operand:VI_HW_QHS 2 "register_operand" "v") 2038 1.1 mrg (match_operand:QI 3 "const_mask_operand" "C")] 2039 1.1 mrg UNSPEC_VEC_VFENE)) 2040 1.1 mrg (set (reg:CCRAW CC_REGNUM) 2041 1.1 mrg (unspec:CCRAW [(match_dup 1) 2042 1.1 mrg (match_dup 2) 2043 1.1 mrg (match_dup 3)] 2044 1.1 mrg UNSPEC_VEC_VFENECC))] 2045 1.1 mrg "TARGET_VX" 2046 1.1 mrg { 2047 1.3 mrg unsigned HOST_WIDE_INT flags = UINTVAL (operands[3]); 2048 1.1 mrg 2049 1.1 mrg gcc_assert (!(flags & ~(VSTRING_FLAG_ZS | VSTRING_FLAG_CS))); 2050 1.1 mrg flags &= ~VSTRING_FLAG_CS; 2051 1.1 mrg 2052 1.1 mrg if (flags == VSTRING_FLAG_ZS) 2053 1.1 mrg return "vfenez<bhfgq>s\t%v0,%v1,%v2"; 2054 1.1 mrg return "vfene<bhfgq>s\t%v0,%v1,%v2"; 2055 1.1 mrg } 2056 1.1 mrg [(set_attr "op_type" "VRR")]) 2057 1.1 mrg 2058 1.1 mrg 2059 1.1 mrg ; Vector select 2060 1.1 mrg 2061 1.1 mrg ; The following splitters simplify vec_sel for constant 0 or -1 2062 1.1 mrg ; selection sources. This is required to generate efficient code for 2063 1.1 mrg ; vcond. 2064 1.1 mrg 2065 1.1 mrg ; a = b == c; 2066 1.1 mrg (define_split 2067 1.1 mrg [(set (match_operand:V 0 "register_operand" "") 2068 1.1 mrg (if_then_else:V 2069 1.7 mrg (eq (match_operand:<TOINTVEC> 3 "register_operand" "") 2070 1.1 mrg (match_operand:V 4 "const0_operand" "")) 2071 1.1 mrg (match_operand:V 1 "const0_operand" "") 2072 1.1 mrg (match_operand:V 2 "all_ones_operand" "")))] 2073 1.1 mrg "TARGET_VX" 2074 1.1 mrg [(set (match_dup 0) (match_dup 3))] 2075 1.1 mrg { 2076 1.1 mrg PUT_MODE (operands[3], <V:MODE>mode); 2077 1.1 mrg }) 2078 1.1 mrg 2079 1.1 mrg ; a = ~(b == c) 2080 1.1 mrg (define_split 2081 1.1 mrg [(set (match_operand:V 0 "register_operand" "") 2082 1.1 mrg (if_then_else:V 2083 1.7 mrg (eq (match_operand:<TOINTVEC> 3 "register_operand" "") 2084 1.1 mrg (match_operand:V 4 "const0_operand" "")) 2085 1.1 mrg (match_operand:V 1 "all_ones_operand" "") 2086 1.1 mrg (match_operand:V 2 "const0_operand" "")))] 2087 1.1 mrg "TARGET_VX" 2088 1.1 mrg [(set (match_dup 0) (not:V (match_dup 3)))] 2089 1.1 mrg { 2090 1.1 mrg PUT_MODE (operands[3], <V:MODE>mode); 2091 1.1 mrg }) 2092 1.1 mrg 2093 1.1 mrg ; a = b != c 2094 1.1 mrg (define_split 2095 1.1 mrg [(set (match_operand:V 0 "register_operand" "") 2096 1.1 mrg (if_then_else:V 2097 1.7 mrg (ne (match_operand:<TOINTVEC> 3 "register_operand" "") 2098 1.1 mrg (match_operand:V 4 "const0_operand" "")) 2099 1.1 mrg (match_operand:V 1 "all_ones_operand" "") 2100 1.1 mrg (match_operand:V 2 "const0_operand" "")))] 2101 1.1 mrg "TARGET_VX" 2102 1.1 mrg [(set (match_dup 0) (match_dup 3))] 2103 1.1 mrg { 2104 1.1 mrg PUT_MODE (operands[3], <V:MODE>mode); 2105 1.1 mrg }) 2106 1.1 mrg 2107 1.1 mrg ; a = ~(b != c) 2108 1.1 mrg (define_split 2109 1.1 mrg [(set (match_operand:V 0 "register_operand" "") 2110 1.1 mrg (if_then_else:V 2111 1.7 mrg (ne (match_operand:<TOINTVEC> 3 "register_operand" "") 2112 1.1 mrg (match_operand:V 4 "const0_operand" "")) 2113 1.1 mrg (match_operand:V 1 "const0_operand" "") 2114 1.1 mrg (match_operand:V 2 "all_ones_operand" "")))] 2115 1.1 mrg "TARGET_VX" 2116 1.1 mrg [(set (match_dup 0) (not:V (match_dup 3)))] 2117 1.1 mrg { 2118 1.1 mrg PUT_MODE (operands[3], <V:MODE>mode); 2119 1.1 mrg }) 2120 1.1 mrg 2121 1.1 mrg ; op0 = op3 == 0 ? op1 : op2 2122 1.1 mrg (define_insn "*vec_sel0<mode>" 2123 1.1 mrg [(set (match_operand:V 0 "register_operand" "=v") 2124 1.1 mrg (if_then_else:V 2125 1.7 mrg (eq (match_operand:<TOINTVEC> 3 "register_operand" "v") 2126 1.7 mrg (match_operand:<TOINTVEC> 4 "const0_operand" "")) 2127 1.1 mrg (match_operand:V 1 "register_operand" "v") 2128 1.1 mrg (match_operand:V 2 "register_operand" "v")))] 2129 1.1 mrg "TARGET_VX" 2130 1.1 mrg "vsel\t%v0,%2,%1,%3" 2131 1.1 mrg [(set_attr "op_type" "VRR")]) 2132 1.1 mrg 2133 1.1 mrg ; op0 = !op3 == 0 ? op1 : op2 2134 1.1 mrg (define_insn "*vec_sel0<mode>" 2135 1.1 mrg [(set (match_operand:V 0 "register_operand" "=v") 2136 1.1 mrg (if_then_else:V 2137 1.7 mrg (eq (not:<TOINTVEC> (match_operand:<TOINTVEC> 3 "register_operand" "v")) 2138 1.7 mrg (match_operand:<TOINTVEC> 4 "const0_operand" "")) 2139 1.1 mrg (match_operand:V 1 "register_operand" "v") 2140 1.1 mrg (match_operand:V 2 "register_operand" "v")))] 2141 1.1 mrg "TARGET_VX" 2142 1.1 mrg "vsel\t%v0,%1,%2,%3" 2143 1.1 mrg [(set_attr "op_type" "VRR")]) 2144 1.1 mrg 2145 1.1 mrg ; op0 = op3 == -1 ? op1 : op2 2146 1.1 mrg (define_insn "*vec_sel1<mode>" 2147 1.1 mrg [(set (match_operand:V 0 "register_operand" "=v") 2148 1.1 mrg (if_then_else:V 2149 1.7 mrg (eq (match_operand:<TOINTVEC> 3 "register_operand" "v") 2150 1.7 mrg (match_operand:<TOINTVEC> 4 "all_ones_operand" "")) 2151 1.1 mrg (match_operand:V 1 "register_operand" "v") 2152 1.1 mrg (match_operand:V 2 "register_operand" "v")))] 2153 1.1 mrg "TARGET_VX" 2154 1.1 mrg "vsel\t%v0,%1,%2,%3" 2155 1.1 mrg [(set_attr "op_type" "VRR")]) 2156 1.1 mrg 2157 1.1 mrg ; op0 = !op3 == -1 ? op1 : op2 2158 1.1 mrg (define_insn "*vec_sel1<mode>" 2159 1.1 mrg [(set (match_operand:V 0 "register_operand" "=v") 2160 1.1 mrg (if_then_else:V 2161 1.7 mrg (eq (not:<TOINTVEC> (match_operand:<TOINTVEC> 3 "register_operand" "v")) 2162 1.7 mrg (match_operand:<TOINTVEC> 4 "all_ones_operand" "")) 2163 1.1 mrg (match_operand:V 1 "register_operand" "v") 2164 1.1 mrg (match_operand:V 2 "register_operand" "v")))] 2165 1.1 mrg "TARGET_VX" 2166 1.1 mrg "vsel\t%v0,%2,%1,%3" 2167 1.1 mrg [(set_attr "op_type" "VRR")]) 2168 1.1 mrg 2169 1.3 mrg ; vec_pack_trunc 2170 1.3 mrg 2171 1.3 mrg ; vpkh, vpkf, vpkg 2172 1.3 mrg (define_insn "vec_pack_trunc_<mode>" 2173 1.3 mrg [(set (match_operand:<vec_half> 0 "register_operand" "=v") 2174 1.3 mrg (vec_concat:<vec_half> 2175 1.3 mrg (truncate:<vec_halfhalf> 2176 1.3 mrg (match_operand:VI_HW_HSD 1 "register_operand" "v")) 2177 1.3 mrg (truncate:<vec_halfhalf> 2178 1.3 mrg (match_operand:VI_HW_HSD 2 "register_operand" "v"))))] 2179 1.3 mrg "TARGET_VX" 2180 1.3 mrg "vpk<bhfgq>\t%0,%1,%2" 2181 1.3 mrg [(set_attr "op_type" "VRR")]) 2182 1.3 mrg 2183 1.3 mrg ; vpksh, vpksf, vpksg 2184 1.3 mrg (define_insn "vec_pack_ssat_<mode>" 2185 1.3 mrg [(set (match_operand:<vec_half> 0 "register_operand" "=v") 2186 1.3 mrg (vec_concat:<vec_half> 2187 1.3 mrg (ss_truncate:<vec_halfhalf> 2188 1.3 mrg (match_operand:VI_HW_HSD 1 "register_operand" "v")) 2189 1.3 mrg (ss_truncate:<vec_halfhalf> 2190 1.3 mrg (match_operand:VI_HW_HSD 2 "register_operand" "v"))))] 2191 1.3 mrg "TARGET_VX" 2192 1.3 mrg "vpks<bhfgq>\t%0,%1,%2" 2193 1.3 mrg [(set_attr "op_type" "VRR")]) 2194 1.3 mrg 2195 1.3 mrg ; vpklsh, vpklsf, vpklsg 2196 1.3 mrg (define_insn "vec_pack_usat_<mode>" 2197 1.3 mrg [(set (match_operand:<vec_half> 0 "register_operand" "=v") 2198 1.3 mrg (vec_concat:<vec_half> 2199 1.3 mrg (us_truncate:<vec_halfhalf> 2200 1.3 mrg (match_operand:VI_HW_HSD 1 "register_operand" "v")) 2201 1.3 mrg (us_truncate:<vec_halfhalf> 2202 1.3 mrg (match_operand:VI_HW_HSD 2 "register_operand" "v"))))] 2203 1.3 mrg "TARGET_VX" 2204 1.3 mrg "vpkls<bhfgq>\t%0,%1,%2" 2205 1.3 mrg [(set_attr "op_type" "VRR")]) 2206 1.3 mrg 2207 1.3 mrg ;; vector unpack v16qi 2208 1.1 mrg 2209 1.3 mrg ; signed 2210 1.3 mrg 2211 1.3 mrg (define_insn "vec_unpacks_hi_v16qi" 2212 1.3 mrg [(set (match_operand:V8HI 0 "register_operand" "=v") 2213 1.3 mrg (sign_extend:V8HI 2214 1.3 mrg (vec_select:V8QI 2215 1.3 mrg (match_operand:V16QI 1 "register_operand" "v") 2216 1.3 mrg (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3) 2217 1.3 mrg (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] 2218 1.3 mrg "TARGET_VX" 2219 1.3 mrg "vuphb\t%0,%1" 2220 1.3 mrg [(set_attr "op_type" "VRR")]) 2221 1.3 mrg 2222 1.4 mrg (define_insn "vec_unpacks_lo_v16qi" 2223 1.3 mrg [(set (match_operand:V8HI 0 "register_operand" "=v") 2224 1.3 mrg (sign_extend:V8HI 2225 1.3 mrg (vec_select:V8QI 2226 1.3 mrg (match_operand:V16QI 1 "register_operand" "v") 2227 1.3 mrg (parallel [(const_int 8) (const_int 9) (const_int 10)(const_int 11) 2228 1.3 mrg (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))))] 2229 1.3 mrg "TARGET_VX" 2230 1.3 mrg "vuplb\t%0,%1" 2231 1.3 mrg [(set_attr "op_type" "VRR")]) 2232 1.3 mrg 2233 1.3 mrg ; unsigned 2234 1.3 mrg 2235 1.3 mrg (define_insn "vec_unpacku_hi_v16qi" 2236 1.3 mrg [(set (match_operand:V8HI 0 "register_operand" "=v") 2237 1.3 mrg (zero_extend:V8HI 2238 1.3 mrg (vec_select:V8QI 2239 1.3 mrg (match_operand:V16QI 1 "register_operand" "v") 2240 1.3 mrg (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3) 2241 1.3 mrg (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] 2242 1.3 mrg "TARGET_VX" 2243 1.3 mrg "vuplhb\t%0,%1" 2244 1.3 mrg [(set_attr "op_type" "VRR")]) 2245 1.3 mrg 2246 1.4 mrg (define_insn "vec_unpacku_lo_v16qi" 2247 1.3 mrg [(set (match_operand:V8HI 0 "register_operand" "=v") 2248 1.3 mrg (zero_extend:V8HI 2249 1.3 mrg (vec_select:V8QI 2250 1.3 mrg (match_operand:V16QI 1 "register_operand" "v") 2251 1.3 mrg (parallel [(const_int 8) (const_int 9) (const_int 10)(const_int 11) 2252 1.3 mrg (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))))] 2253 1.3 mrg "TARGET_VX" 2254 1.3 mrg "vupllb\t%0,%1" 2255 1.3 mrg [(set_attr "op_type" "VRR")]) 2256 1.3 mrg 2257 1.3 mrg ;; vector unpack v8hi 2258 1.3 mrg 2259 1.3 mrg ; signed 2260 1.3 mrg 2261 1.3 mrg (define_insn "vec_unpacks_hi_v8hi" 2262 1.3 mrg [(set (match_operand:V4SI 0 "register_operand" "=v") 2263 1.3 mrg (sign_extend:V4SI 2264 1.3 mrg (vec_select:V4HI 2265 1.3 mrg (match_operand:V8HI 1 "register_operand" "v") 2266 1.3 mrg (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))))] 2267 1.3 mrg "TARGET_VX" 2268 1.3 mrg "vuphh\t%0,%1" 2269 1.3 mrg [(set_attr "op_type" "VRR")]) 2270 1.3 mrg 2271 1.3 mrg (define_insn "vec_unpacks_lo_v8hi" 2272 1.3 mrg [(set (match_operand:V4SI 0 "register_operand" "=v") 2273 1.3 mrg (sign_extend:V4SI 2274 1.3 mrg (vec_select:V4HI 2275 1.3 mrg (match_operand:V8HI 1 "register_operand" "v") 2276 1.3 mrg (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] 2277 1.3 mrg "TARGET_VX" 2278 1.3 mrg "vuplhw\t%0,%1" 2279 1.3 mrg [(set_attr "op_type" "VRR")]) 2280 1.3 mrg 2281 1.3 mrg ; unsigned 2282 1.3 mrg 2283 1.3 mrg (define_insn "vec_unpacku_hi_v8hi" 2284 1.3 mrg [(set (match_operand:V4SI 0 "register_operand" "=v") 2285 1.3 mrg (zero_extend:V4SI 2286 1.3 mrg (vec_select:V4HI 2287 1.3 mrg (match_operand:V8HI 1 "register_operand" "v") 2288 1.3 mrg (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))))] 2289 1.3 mrg "TARGET_VX" 2290 1.3 mrg "vuplhh\t%0,%1" 2291 1.3 mrg [(set_attr "op_type" "VRR")]) 2292 1.3 mrg 2293 1.3 mrg (define_insn "vec_unpacku_lo_v8hi" 2294 1.3 mrg [(set (match_operand:V4SI 0 "register_operand" "=v") 2295 1.3 mrg (zero_extend:V4SI 2296 1.3 mrg (vec_select:V4HI 2297 1.3 mrg (match_operand:V8HI 1 "register_operand" "v") 2298 1.3 mrg (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))))] 2299 1.3 mrg "TARGET_VX" 2300 1.3 mrg "vupllh\t%0,%1" 2301 1.3 mrg [(set_attr "op_type" "VRR")]) 2302 1.3 mrg 2303 1.3 mrg ;; vector unpack v4si 2304 1.3 mrg 2305 1.3 mrg ; signed 2306 1.3 mrg 2307 1.3 mrg (define_insn "vec_unpacks_hi_v4si" 2308 1.3 mrg [(set (match_operand:V2DI 0 "register_operand" "=v") 2309 1.3 mrg (sign_extend:V2DI 2310 1.3 mrg (vec_select:V2SI 2311 1.3 mrg (match_operand:V4SI 1 "register_operand" "v") 2312 1.3 mrg (parallel [(const_int 0)(const_int 1)]))))] 2313 1.3 mrg "TARGET_VX" 2314 1.3 mrg "vuphf\t%0,%1" 2315 1.3 mrg [(set_attr "op_type" "VRR")]) 2316 1.3 mrg 2317 1.3 mrg (define_insn "vec_unpacks_lo_v4si" 2318 1.3 mrg [(set (match_operand:V2DI 0 "register_operand" "=v") 2319 1.3 mrg (sign_extend:V2DI 2320 1.3 mrg (vec_select:V2SI 2321 1.3 mrg (match_operand:V4SI 1 "register_operand" "v") 2322 1.3 mrg (parallel [(const_int 2)(const_int 3)]))))] 2323 1.3 mrg "TARGET_VX" 2324 1.3 mrg "vuplf\t%0,%1" 2325 1.3 mrg [(set_attr "op_type" "VRR")]) 2326 1.3 mrg 2327 1.3 mrg ; unsigned 2328 1.3 mrg 2329 1.3 mrg (define_insn "vec_unpacku_hi_v4si" 2330 1.3 mrg [(set (match_operand:V2DI 0 "register_operand" "=v") 2331 1.3 mrg (zero_extend:V2DI 2332 1.3 mrg (vec_select:V2SI 2333 1.3 mrg (match_operand:V4SI 1 "register_operand" "v") 2334 1.3 mrg (parallel [(const_int 0)(const_int 1)]))))] 2335 1.3 mrg "TARGET_VX" 2336 1.3 mrg "vuplhf\t%0,%1" 2337 1.3 mrg [(set_attr "op_type" "VRR")]) 2338 1.3 mrg 2339 1.3 mrg (define_insn "vec_unpacku_lo_v4si" 2340 1.3 mrg [(set (match_operand:V2DI 0 "register_operand" "=v") 2341 1.3 mrg (zero_extend:V2DI 2342 1.3 mrg (vec_select:V2SI 2343 1.3 mrg (match_operand:V4SI 1 "register_operand" "v") 2344 1.3 mrg (parallel [(const_int 2)(const_int 3)]))))] 2345 1.3 mrg "TARGET_VX" 2346 1.3 mrg "vupllf\t%0,%1" 2347 1.3 mrg [(set_attr "op_type" "VRR")]) 2348 1.3 mrg 2349 1.3 mrg ;; vector load lengthened 2350 1.3 mrg 2351 1.4 mrg ; vflls float -> double 2352 1.3 mrg (define_insn "*vec_extendv4sf" 2353 1.3 mrg [(set (match_operand:V2DF 0 "register_operand" "=v") 2354 1.3 mrg (float_extend:V2DF 2355 1.3 mrg (vec_select:V2SF 2356 1.3 mrg (match_operand:V4SF 1 "register_operand" "v") 2357 1.3 mrg (parallel [(const_int 0) (const_int 2)]))))] 2358 1.3 mrg "TARGET_VX" 2359 1.3 mrg "vldeb\t%v0,%v1" 2360 1.3 mrg [(set_attr "op_type" "VRR")]) 2361 1.3 mrg 2362 1.4 mrg (define_expand "vec_unpacks_lo_v4sf" 2363 1.4 mrg [(set (match_dup 2) 2364 1.7 mrg (vec_select:V4SF 2365 1.7 mrg (vec_concat:V8SF (match_operand:V4SF 1 "register_operand" "") (match_dup 1)) 2366 1.7 mrg (match_dup 3))) 2367 1.7 mrg (set (match_operand:V2DF 0 "register_operand" "") 2368 1.4 mrg (float_extend:V2DF 2369 1.4 mrg (vec_select:V2SF 2370 1.4 mrg (match_dup 2) 2371 1.4 mrg (parallel [(const_int 0) (const_int 2)]))))] 2372 1.4 mrg "TARGET_VX" 2373 1.7 mrg { 2374 1.7 mrg operands[2] = gen_reg_rtx(V4SFmode); 2375 1.7 mrg operands[3] = s390_expand_merge_perm_const (V4SFmode, false); 2376 1.7 mrg }) 2377 1.4 mrg 2378 1.4 mrg (define_expand "vec_unpacks_hi_v4sf" 2379 1.4 mrg [(set (match_dup 2) 2380 1.7 mrg (vec_select:V4SF 2381 1.7 mrg (vec_concat:V8SF (match_operand:V4SF 1 "register_operand" "") (match_dup 1)) 2382 1.7 mrg (match_dup 3))) 2383 1.7 mrg (set (match_operand:V2DF 0 "register_operand" "") 2384 1.4 mrg (float_extend:V2DF 2385 1.4 mrg (vec_select:V2SF 2386 1.4 mrg (match_dup 2) 2387 1.4 mrg (parallel [(const_int 0) (const_int 2)]))))] 2388 1.4 mrg "TARGET_VX" 2389 1.7 mrg { 2390 1.7 mrg operands[2] = gen_reg_rtx(V4SFmode); 2391 1.7 mrg operands[3] = s390_expand_merge_perm_const (V4SFmode, true); 2392 1.7 mrg }) 2393 1.4 mrg 2394 1.4 mrg 2395 1.4 mrg ; double -> long double 2396 1.3 mrg (define_insn "*vec_extendv2df" 2397 1.3 mrg [(set (match_operand:V1TF 0 "register_operand" "=v") 2398 1.3 mrg (float_extend:V1TF 2399 1.3 mrg (vec_select:V1DF 2400 1.3 mrg (match_operand:V2DF 1 "register_operand" "v") 2401 1.3 mrg (parallel [(const_int 0)]))))] 2402 1.3 mrg "TARGET_VXE" 2403 1.3 mrg "wflld\t%v0,%v1" 2404 1.3 mrg [(set_attr "op_type" "VRR")]) 2405 1.1 mrg 2406 1.4 mrg (define_expand "vec_unpacks_lo_v2df" 2407 1.4 mrg [(set (match_dup 2) 2408 1.7 mrg (vec_select:V2DF 2409 1.7 mrg (vec_concat:V4DF (match_operand:V2DF 1 "register_operand" "") (match_dup 1)) 2410 1.7 mrg (match_dup 3))) 2411 1.7 mrg (set (match_operand:V1TF 0 "register_operand" "") 2412 1.4 mrg (float_extend:V1TF 2413 1.4 mrg (vec_select:V1DF 2414 1.4 mrg (match_dup 2) 2415 1.4 mrg (parallel [(const_int 0)]))))] 2416 1.4 mrg "TARGET_VXE" 2417 1.7 mrg { 2418 1.7 mrg operands[2] = gen_reg_rtx (V2DFmode); 2419 1.7 mrg operands[3] = s390_expand_merge_perm_const (V2DFmode, false); 2420 1.7 mrg }) 2421 1.4 mrg 2422 1.4 mrg (define_expand "vec_unpacks_hi_v2df" 2423 1.4 mrg [(set (match_dup 2) 2424 1.7 mrg (vec_select:V2DF 2425 1.7 mrg (vec_concat:V4DF (match_operand:V2DF 1 "register_operand" "") (match_dup 1)) 2426 1.7 mrg (match_dup 3))) 2427 1.7 mrg (set (match_operand:V1TF 0 "register_operand" "") 2428 1.4 mrg (float_extend:V1TF 2429 1.4 mrg (vec_select:V1DF 2430 1.4 mrg (match_dup 2) 2431 1.4 mrg (parallel [(const_int 0)]))))] 2432 1.4 mrg "TARGET_VXE" 2433 1.7 mrg { 2434 1.7 mrg operands[2] = gen_reg_rtx (V2DFmode); 2435 1.7 mrg operands[3] = s390_expand_merge_perm_const (V2DFmode, true); 2436 1.7 mrg }) 2437 1.4 mrg 2438 1.4 mrg 2439 1.4 mrg ; 2 x v2df -> 1 x v4sf 2440 1.4 mrg (define_expand "vec_pack_trunc_v2df" 2441 1.4 mrg [(set (match_dup 3) 2442 1.4 mrg (unspec:V4SF [(match_operand:V2DF 1 "register_operand" "") 2443 1.4 mrg (const_int VEC_INEXACT) 2444 1.4 mrg (const_int VEC_RND_CURRENT)] 2445 1.4 mrg UNSPEC_VEC_VFLR)) 2446 1.4 mrg (set (match_dup 4) 2447 1.4 mrg (unspec:V4SF [(match_operand:V2DF 2 "register_operand" "") 2448 1.4 mrg (const_int VEC_INEXACT) 2449 1.4 mrg (const_int VEC_RND_CURRENT)] 2450 1.4 mrg UNSPEC_VEC_VFLR)) 2451 1.4 mrg (set (match_dup 6) 2452 1.4 mrg (unspec:V16QI [(subreg:V16QI (match_dup 3) 0) 2453 1.4 mrg (subreg:V16QI (match_dup 4) 0) 2454 1.4 mrg (match_dup 5)] 2455 1.4 mrg UNSPEC_VEC_PERM)) 2456 1.4 mrg (set (match_operand:V4SF 0 "register_operand" "") 2457 1.4 mrg (subreg:V4SF (match_dup 6) 0))] 2458 1.4 mrg "TARGET_VX" 2459 1.4 mrg { 2460 1.4 mrg rtx constv, perm[16]; 2461 1.4 mrg int i; 2462 1.4 mrg 2463 1.4 mrg for (i = 0; i < 4; ++i) 2464 1.4 mrg { 2465 1.4 mrg perm[i] = GEN_INT (i); 2466 1.4 mrg perm[i + 4] = GEN_INT (i + 8); 2467 1.4 mrg perm[i + 8] = GEN_INT (i + 16); 2468 1.4 mrg perm[i + 12] = GEN_INT (i + 24); 2469 1.4 mrg } 2470 1.4 mrg constv = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm)); 2471 1.4 mrg 2472 1.4 mrg operands[3] = gen_reg_rtx (V4SFmode); 2473 1.4 mrg operands[4] = gen_reg_rtx (V4SFmode); 2474 1.4 mrg operands[5] = force_reg (V16QImode, constv); 2475 1.4 mrg operands[6] = gen_reg_rtx (V16QImode); 2476 1.4 mrg }) 2477 1.4 mrg 2478 1.5 mrg ; 2479 1.5 mrg ; BFP <-> integer conversions 2480 1.5 mrg ; 2481 1.5 mrg 2482 1.5 mrg ; signed integer to floating point 2483 1.5 mrg 2484 1.5 mrg ; op2: inexact exception not suppressed (IEEE 754 2008) 2485 1.5 mrg ; op3: according to current rounding mode 2486 1.5 mrg ; vcdgb, vcefb 2487 1.5 mrg (define_insn "float<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2" 2488 1.5 mrg [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "=v") 2489 1.5 mrg (float:VX_VEC_CONV_BFP (match_operand:VX_VEC_CONV_INT 1 "register_operand" "v")))] 2490 1.5 mrg "TARGET_VX 2491 1.5 mrg && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)" 2492 1.5 mrg "vc<VX_VEC_CONV_BFP:xde><VX_VEC_CONV_INT:bhfgq>b\t%v0,%v1,0,0" 2493 1.5 mrg [(set_attr "op_type" "VRR")]) 2494 1.5 mrg 2495 1.7 mrg ; There is no instruction for loading a signed integer into an extended BFP 2496 1.7 mrg ; operand in a VR, therefore we need to load it into a FPR pair first. 2497 1.7 mrg (define_expand "float<mode>tf2_vr" 2498 1.7 mrg [(set (match_dup 2) 2499 1.7 mrg (float:FPRX2 (match_operand:DSI 1 "register_operand" ""))) 2500 1.7 mrg (set (match_operand:TF 0 "register_operand" "") 2501 1.7 mrg (subreg:TF (match_dup 2) 0))] 2502 1.7 mrg "TARGET_VXE" 2503 1.7 mrg { 2504 1.7 mrg operands[2] = gen_reg_rtx (FPRX2mode); 2505 1.7 mrg }) 2506 1.7 mrg 2507 1.7 mrg (define_expand "float<mode>tf2" 2508 1.7 mrg [(match_operand:TF 0 "register_operand" "") 2509 1.7 mrg (match_operand:DSI 1 "register_operand" "")] 2510 1.7 mrg "HAVE_TF (float<mode>tf2)" 2511 1.7 mrg { EXPAND_TF (float<mode>tf2, 2); }) 2512 1.7 mrg 2513 1.5 mrg ; unsigned integer to floating point 2514 1.5 mrg 2515 1.5 mrg ; op2: inexact exception not suppressed (IEEE 754 2008) 2516 1.5 mrg ; op3: according to current rounding mode 2517 1.5 mrg ; vcdlgb, vcelfb 2518 1.5 mrg (define_insn "floatuns<VX_VEC_CONV_INT:mode><VX_VEC_CONV_BFP:mode>2" 2519 1.5 mrg [(set (match_operand:VX_VEC_CONV_BFP 0 "register_operand" "=v") 2520 1.5 mrg (unsigned_float:VX_VEC_CONV_BFP (match_operand:VX_VEC_CONV_INT 1 "register_operand" "v")))] 2521 1.5 mrg "TARGET_VX 2522 1.5 mrg && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)" 2523 1.5 mrg "vc<VX_VEC_CONV_BFP:xde>l<VX_VEC_CONV_INT:bhfgq>b\t%v0,%v1,0,0" 2524 1.5 mrg [(set_attr "op_type" "VRR")]) 2525 1.5 mrg 2526 1.7 mrg ; There is no instruction for loading an unsigned integer into an extended BFP 2527 1.7 mrg ; operand in a VR, therefore load it into a FPR pair first. 2528 1.7 mrg (define_expand "floatuns<mode>tf2_vr" 2529 1.7 mrg [(set (match_dup 2) 2530 1.7 mrg (unsigned_float:FPRX2 (match_operand:GPR 1 "register_operand" ""))) 2531 1.7 mrg (set (match_operand:TF 0 "register_operand" "") 2532 1.7 mrg (subreg:TF (match_dup 2) 0))] 2533 1.7 mrg "TARGET_VXE" 2534 1.7 mrg { 2535 1.7 mrg operands[2] = gen_reg_rtx (FPRX2mode); 2536 1.7 mrg }) 2537 1.7 mrg 2538 1.7 mrg (define_expand "floatuns<mode>tf2" 2539 1.7 mrg [(match_operand:TF 0 "register_operand" "") 2540 1.7 mrg (match_operand:GPR 1 "register_operand" "")] 2541 1.7 mrg "HAVE_TF (floatuns<mode>tf2)" 2542 1.7 mrg { EXPAND_TF (floatuns<mode>tf2, 2); }) 2543 1.7 mrg 2544 1.5 mrg ; floating point to signed integer 2545 1.5 mrg 2546 1.5 mrg ; op2: inexact exception not suppressed (IEEE 754 2008) 2547 1.5 mrg ; op3: rounding mode 5 (round towards 0 C11 6.3.1.4) 2548 1.5 mrg ; vcgdb, vcfeb 2549 1.5 mrg (define_insn "fix_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2" 2550 1.5 mrg [(set (match_operand:VX_VEC_CONV_INT 0 "register_operand" "=v") 2551 1.5 mrg (fix:VX_VEC_CONV_INT (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "v")))] 2552 1.5 mrg "TARGET_VX 2553 1.5 mrg && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)" 2554 1.5 mrg "vc<VX_VEC_CONV_INT:bhfgq><VX_VEC_CONV_BFP:xde>b\t%v0,%v1,0,5" 2555 1.5 mrg [(set_attr "op_type" "VRR")]) 2556 1.5 mrg 2557 1.7 mrg ; There is no instruction for rounding an extended BFP operand in a VR into 2558 1.7 mrg ; a signed integer, therefore copy it into a FPR pair first. 2559 1.7 mrg (define_expand "fix_trunctf<mode>2_vr" 2560 1.7 mrg [(set (match_dup 2) 2561 1.7 mrg (unspec:FPRX2 [(match_operand:TF 1 "register_operand")] UNSPEC_TF_TO_FPRX2)) 2562 1.7 mrg (parallel [(set (match_operand:GPR 0 "register_operand" "") 2563 1.7 mrg (fix:GPR (match_dup 2))) 2564 1.7 mrg (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) 2565 1.7 mrg (clobber (reg:CC CC_REGNUM))])] 2566 1.7 mrg "TARGET_VXE" 2567 1.7 mrg { 2568 1.7 mrg operands[2] = gen_reg_rtx (FPRX2mode); 2569 1.7 mrg }) 2570 1.7 mrg 2571 1.7 mrg (define_expand "fix_trunctf<mode>2" 2572 1.7 mrg [(match_operand:GPR 0 "register_operand" "") 2573 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2574 1.7 mrg "HAVE_TF (fix_trunctf<mode>2)" 2575 1.7 mrg { EXPAND_TF (fix_trunctf<mode>2, 2); }) 2576 1.7 mrg 2577 1.5 mrg ; floating point to unsigned integer 2578 1.5 mrg 2579 1.5 mrg ; op2: inexact exception not suppressed (IEEE 754 2008) 2580 1.5 mrg ; op3: rounding mode 5 (round towards 0 C11 6.3.1.4) 2581 1.5 mrg ; vclgdb, vclfeb 2582 1.5 mrg (define_insn "fixuns_trunc<VX_VEC_CONV_BFP:mode><VX_VEC_CONV_INT:mode>2" 2583 1.5 mrg [(set (match_operand:VX_VEC_CONV_INT 0 "register_operand" "=v") 2584 1.5 mrg (unsigned_fix:VX_VEC_CONV_INT (match_operand:VX_VEC_CONV_BFP 1 "register_operand" "v")))] 2585 1.5 mrg "TARGET_VX 2586 1.5 mrg && GET_MODE_UNIT_SIZE (<VX_VEC_CONV_INT:MODE>mode) == GET_MODE_UNIT_SIZE (<VX_VEC_CONV_BFP:MODE>mode)" 2587 1.5 mrg "vcl<VX_VEC_CONV_INT:bhfgq><VX_VEC_CONV_BFP:xde>b\t%v0,%v1,0,5" 2588 1.5 mrg [(set_attr "op_type" "VRR")]) 2589 1.5 mrg 2590 1.7 mrg ; There is no instruction for rounding an extended BFP operand in a VR into 2591 1.7 mrg ; an unsigned integer, therefore copy it into a FPR pair first. 2592 1.7 mrg (define_expand "fixuns_trunctf<mode>2_vr" 2593 1.7 mrg [(set (match_dup 2) 2594 1.7 mrg (unspec:FPRX2 [(match_operand:TF 1 "register_operand")] UNSPEC_TF_TO_FPRX2)) 2595 1.7 mrg (parallel [(set (match_operand:GPR 0 "register_operand" "") 2596 1.7 mrg (unsigned_fix:GPR (match_dup 2))) 2597 1.7 mrg (unspec:GPR [(const_int BFP_RND_TOWARD_0)] UNSPEC_ROUND) 2598 1.7 mrg (clobber (reg:CC CC_REGNUM))])] 2599 1.7 mrg "TARGET_VXE" 2600 1.7 mrg { 2601 1.7 mrg operands[2] = gen_reg_rtx (FPRX2mode); 2602 1.7 mrg }) 2603 1.7 mrg 2604 1.7 mrg (define_expand "fixuns_trunctf<mode>2" 2605 1.7 mrg [(match_operand:GPR 0 "register_operand" "") 2606 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2607 1.7 mrg "HAVE_TF (fixuns_trunctf<mode>2)" 2608 1.7 mrg { EXPAND_TF (fixuns_trunctf<mode>2, 2); }) 2609 1.7 mrg 2610 1.7 mrg ; load fp integer 2611 1.7 mrg 2612 1.7 mrg ; vfisb, wfisb, vfidb, wfidb, wfixb; suppress inexact exceptions 2613 1.7 mrg (define_insn "<FPINT:fpint_name><VF_HW:mode>2<VF_HW:tf_vr>" 2614 1.7 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 2615 1.7 mrg (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "v")] 2616 1.7 mrg FPINT))] 2617 1.7 mrg "TARGET_VX" 2618 1.7 mrg "<vw>fi<VF_HW:sdx>b\t%v0,%v1,4,<FPINT:fpint_roundingmode>" 2619 1.7 mrg [(set_attr "op_type" "VRR")]) 2620 1.7 mrg 2621 1.7 mrg (define_expand "<FPINT:fpint_name>tf2" 2622 1.7 mrg [(match_operand:TF 0 "register_operand" "") 2623 1.7 mrg (match_operand:TF 1 "register_operand" "") 2624 1.7 mrg ; recognize FPINT as an iterator 2625 1.7 mrg (unspec:TF [(match_dup 1)] FPINT)] 2626 1.7 mrg "HAVE_TF (<FPINT:fpint_name>tf2)" 2627 1.7 mrg { EXPAND_TF (<FPINT:fpint_name>tf2, 2); }) 2628 1.7 mrg 2629 1.7 mrg ; vfisb, wfisb, vfidb, wfidb, wfixb; raise inexact exceptions 2630 1.7 mrg (define_insn "rint<mode>2<tf_vr>" 2631 1.7 mrg [(set (match_operand:VF_HW 0 "register_operand" "=v") 2632 1.7 mrg (unspec:VF_HW [(match_operand:VF_HW 1 "register_operand" "v")] 2633 1.7 mrg UNSPEC_FPINT_RINT))] 2634 1.7 mrg "TARGET_VX" 2635 1.7 mrg "<vw>fi<sdx>b\t%v0,%v1,0,0" 2636 1.7 mrg [(set_attr "op_type" "VRR")]) 2637 1.7 mrg 2638 1.7 mrg (define_expand "rinttf2" 2639 1.7 mrg [(match_operand:TF 0 "register_operand" "") 2640 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2641 1.7 mrg "HAVE_TF (rinttf2)" 2642 1.7 mrg { EXPAND_TF (rinttf2, 2); }) 2643 1.7 mrg 2644 1.7 mrg ; load rounded 2645 1.7 mrg 2646 1.7 mrg ; wflrx 2647 1.7 mrg (define_insn "*trunctfdf2_vr" 2648 1.7 mrg [(set (match_operand:DF 0 "register_operand" "=f") 2649 1.7 mrg (float_truncate:DF (match_operand:TF 1 "register_operand" "v"))) 2650 1.7 mrg (unspec:DF [(match_operand 2 "const_int_operand" "")] 2651 1.7 mrg UNSPEC_ROUND)] 2652 1.7 mrg "TARGET_VXE" 2653 1.7 mrg "wflrx\t%v0,%v1,0,%2" 2654 1.7 mrg [(set_attr "op_type" "VRR")]) 2655 1.7 mrg 2656 1.7 mrg (define_expand "trunctfdf2_vr" 2657 1.7 mrg [(parallel [ 2658 1.7 mrg (set (match_operand:DF 0 "register_operand" "") 2659 1.7 mrg (float_truncate:DF (match_operand:TF 1 "register_operand" ""))) 2660 1.7 mrg (unspec:DF [(const_int BFP_RND_CURRENT)] UNSPEC_ROUND)])] 2661 1.7 mrg "TARGET_VXE") 2662 1.7 mrg 2663 1.7 mrg (define_expand "trunctfdf2" 2664 1.7 mrg [(match_operand:DF 0 "register_operand" "") 2665 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2666 1.7 mrg "HAVE_TF (trunctfdf2)" 2667 1.7 mrg { EXPAND_TF (trunctfdf2, 2); }) 2668 1.7 mrg 2669 1.7 mrg ; wflrx + (ledbr|wledb) 2670 1.7 mrg (define_expand "trunctfsf2_vr" 2671 1.7 mrg [(parallel [ 2672 1.7 mrg (set (match_dup 2) 2673 1.7 mrg (float_truncate:DF (match_operand:TF 1 "register_operand" ""))) 2674 1.7 mrg (unspec:DF [(const_int BFP_RND_PREP_FOR_SHORT_PREC)] UNSPEC_ROUND)]) 2675 1.7 mrg (set (match_operand:SF 0 "register_operand" "") 2676 1.7 mrg (float_truncate:SF (match_dup 2)))] 2677 1.7 mrg "TARGET_VXE" 2678 1.7 mrg { 2679 1.7 mrg operands[2] = gen_reg_rtx(DFmode); 2680 1.7 mrg }) 2681 1.7 mrg 2682 1.7 mrg (define_expand "trunctfsf2" 2683 1.7 mrg [(match_operand:SF 0 "register_operand" "") 2684 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2685 1.7 mrg "HAVE_TF (trunctfsf2)" 2686 1.7 mrg { EXPAND_TF (trunctfsf2, 2); }) 2687 1.7 mrg 2688 1.7 mrg (define_expand "trunctf<DFP_ALL:mode>2_vr" 2689 1.7 mrg [(match_operand:DFP_ALL 0 "nonimmediate_operand" "") 2690 1.7 mrg (match_operand:TF 1 "nonimmediate_operand" "")] 2691 1.7 mrg "TARGET_HARD_DFP 2692 1.7 mrg && GET_MODE_SIZE (TFmode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode) 2693 1.7 mrg && TARGET_VXE" 2694 1.7 mrg { 2695 1.7 mrg rtx fprx2 = gen_reg_rtx (FPRX2mode); 2696 1.7 mrg emit_insn (gen_tf_to_fprx2 (fprx2, operands[1])); 2697 1.7 mrg emit_insn (gen_truncfprx2<DFP_ALL:mode>2 (operands[0], fprx2)); 2698 1.7 mrg DONE; 2699 1.7 mrg }) 2700 1.7 mrg 2701 1.7 mrg (define_expand "trunctf<DFP_ALL:mode>2" 2702 1.7 mrg [(match_operand:DFP_ALL 0 "nonimmediate_operand" "") 2703 1.7 mrg (match_operand:TF 1 "nonimmediate_operand" "")] 2704 1.7 mrg "HAVE_TF (trunctf<DFP_ALL:mode>2)" 2705 1.7 mrg { EXPAND_TF (trunctf<DFP_ALL:mode>2, 2); }) 2706 1.7 mrg 2707 1.7 mrg (define_expand "trunctdtf2_vr" 2708 1.7 mrg [(match_operand:TF 0 "nonimmediate_operand" "") 2709 1.7 mrg (match_operand:TD 1 "nonimmediate_operand" "")] 2710 1.7 mrg "TARGET_HARD_DFP && TARGET_VXE" 2711 1.7 mrg { 2712 1.7 mrg rtx fprx2 = gen_reg_rtx (FPRX2mode); 2713 1.7 mrg emit_insn (gen_trunctdfprx22 (fprx2, operands[1])); 2714 1.7 mrg emit_insn (gen_fprx2_to_tf (operands[0], fprx2)); 2715 1.7 mrg DONE; 2716 1.7 mrg }) 2717 1.7 mrg 2718 1.7 mrg (define_expand "trunctdtf2" 2719 1.7 mrg [(match_operand:TF 0 "nonimmediate_operand" "") 2720 1.7 mrg (match_operand:TD 1 "nonimmediate_operand" "")] 2721 1.7 mrg "HAVE_TF (trunctdtf2)" 2722 1.7 mrg { EXPAND_TF (trunctdtf2, 2); }) 2723 1.7 mrg 2724 1.7 mrg ; load lengthened 2725 1.7 mrg 2726 1.7 mrg (define_insn "extenddftf2_vr" 2727 1.7 mrg [(set (match_operand:TF 0 "register_operand" "=v") 2728 1.7 mrg (float_extend:TF (match_operand:DF 1 "register_operand" "f")))] 2729 1.7 mrg "TARGET_VXE" 2730 1.7 mrg "wflld\t%v0,%v1" 2731 1.7 mrg [(set_attr "op_type" "VRR")]) 2732 1.7 mrg 2733 1.7 mrg (define_expand "extenddftf2" 2734 1.7 mrg [(match_operand:TF 0 "register_operand" "") 2735 1.7 mrg (match_operand:DF 1 "nonimmediate_operand" "")] 2736 1.7 mrg "HAVE_TF (extenddftf2)" 2737 1.7 mrg { EXPAND_TF (extenddftf2, 2); }) 2738 1.7 mrg 2739 1.7 mrg (define_expand "extendsftf2_vr" 2740 1.7 mrg [(set (match_dup 2) 2741 1.7 mrg (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" ""))) 2742 1.7 mrg (set (match_operand:TF 0 "register_operand" "") 2743 1.7 mrg (float_extend:TF (match_dup 2)))] 2744 1.7 mrg "TARGET_VXE" 2745 1.7 mrg { 2746 1.7 mrg operands[2] = gen_reg_rtx(DFmode); 2747 1.7 mrg }) 2748 1.7 mrg 2749 1.7 mrg (define_expand "extendsftf2" 2750 1.7 mrg [(match_operand:TF 0 "register_operand" "") 2751 1.7 mrg (match_operand:SF 1 "nonimmediate_operand" "")] 2752 1.7 mrg "HAVE_TF (extendsftf2)" 2753 1.7 mrg { EXPAND_TF (extendsftf2, 2); }) 2754 1.7 mrg 2755 1.7 mrg (define_expand "extend<DFP_ALL:mode>tf2_vr" 2756 1.7 mrg [(match_operand:TF 0 "nonimmediate_operand" "") 2757 1.7 mrg (match_operand:DFP_ALL 1 "nonimmediate_operand" "")] 2758 1.7 mrg "TARGET_HARD_DFP 2759 1.7 mrg && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (TFmode) 2760 1.7 mrg && TARGET_VXE" 2761 1.7 mrg { 2762 1.7 mrg rtx fprx2 = gen_reg_rtx (FPRX2mode); 2763 1.7 mrg emit_insn (gen_extend<DFP_ALL:mode>fprx22 (fprx2, operands[1])); 2764 1.7 mrg emit_insn (gen_fprx2_to_tf (operands[0], fprx2)); 2765 1.7 mrg DONE; 2766 1.7 mrg }) 2767 1.7 mrg 2768 1.7 mrg (define_expand "extend<DFP_ALL:mode>tf2" 2769 1.7 mrg [(match_operand:TF 0 "nonimmediate_operand" "") 2770 1.7 mrg (match_operand:DFP_ALL 1 "nonimmediate_operand" "")] 2771 1.7 mrg "HAVE_TF (extend<DFP_ALL:mode>tf2)" 2772 1.7 mrg { EXPAND_TF (extend<DFP_ALL:mode>tf2, 2); }) 2773 1.7 mrg 2774 1.7 mrg (define_expand "extendtftd2_vr" 2775 1.7 mrg [(match_operand:TD 0 "nonimmediate_operand" "") 2776 1.7 mrg (match_operand:TF 1 "nonimmediate_operand" "")] 2777 1.7 mrg "TARGET_HARD_DFP && TARGET_VXE" 2778 1.7 mrg { 2779 1.7 mrg rtx fprx2 = gen_reg_rtx (FPRX2mode); 2780 1.7 mrg emit_insn (gen_tf_to_fprx2 (fprx2, operands[1])); 2781 1.7 mrg emit_insn (gen_extendfprx2td2 (operands[0], fprx2)); 2782 1.7 mrg DONE; 2783 1.7 mrg }) 2784 1.7 mrg 2785 1.7 mrg (define_expand "extendtftd2" 2786 1.7 mrg [(match_operand:TD 0 "nonimmediate_operand" "") 2787 1.7 mrg (match_operand:TF 1 "nonimmediate_operand" "")] 2788 1.7 mrg "HAVE_TF (extendtftd2)" 2789 1.7 mrg { EXPAND_TF (extendtftd2, 2); }) 2790 1.7 mrg 2791 1.7 mrg ; test data class 2792 1.7 mrg 2793 1.7 mrg (define_expand "signbittf2_vr" 2794 1.7 mrg [(parallel 2795 1.7 mrg [(set (reg:CCRAW CC_REGNUM) 2796 1.7 mrg (unspec:CCRAW [(match_operand:TF 1 "register_operand" "") 2797 1.7 mrg (match_dup 2)] 2798 1.7 mrg UNSPEC_VEC_VFTCICC)) 2799 1.7 mrg (clobber (scratch:V1TI))]) 2800 1.7 mrg (set (match_operand:SI 0 "register_operand" "") 2801 1.7 mrg (const_int 0)) 2802 1.7 mrg (set (match_dup 0) 2803 1.7 mrg (if_then_else:SI (eq (reg:CCRAW CC_REGNUM) (const_int 8)) 2804 1.7 mrg (const_int 1) 2805 1.7 mrg (match_dup 0)))] 2806 1.7 mrg "TARGET_VXE" 2807 1.7 mrg { 2808 1.7 mrg operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); 2809 1.7 mrg }) 2810 1.7 mrg 2811 1.7 mrg (define_expand "signbittf2" 2812 1.7 mrg [(match_operand:SI 0 "register_operand" "") 2813 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2814 1.7 mrg "HAVE_TF (signbittf2)" 2815 1.7 mrg { EXPAND_TF (signbittf2, 2); }) 2816 1.7 mrg 2817 1.7 mrg (define_expand "isinftf2_vr" 2818 1.7 mrg [(parallel 2819 1.7 mrg [(set (reg:CCRAW CC_REGNUM) 2820 1.7 mrg (unspec:CCRAW [(match_operand:TF 1 "register_operand" "") 2821 1.7 mrg (match_dup 2)] 2822 1.7 mrg UNSPEC_VEC_VFTCICC)) 2823 1.7 mrg (clobber (scratch:V1TI))]) 2824 1.7 mrg (set (match_operand:SI 0 "register_operand" "") 2825 1.7 mrg (const_int 0)) 2826 1.7 mrg (set (match_dup 0) 2827 1.7 mrg (if_then_else:SI (eq (reg:CCRAW CC_REGNUM) (const_int 8)) 2828 1.7 mrg (const_int 1) 2829 1.7 mrg (match_dup 0)))] 2830 1.7 mrg "TARGET_VXE" 2831 1.7 mrg { 2832 1.7 mrg operands[2] = GEN_INT (S390_TDC_INFINITY); 2833 1.7 mrg }) 2834 1.7 mrg 2835 1.7 mrg (define_expand "isinftf2" 2836 1.7 mrg [(match_operand:SI 0 "register_operand" "") 2837 1.7 mrg (match_operand:TF 1 "register_operand" "")] 2838 1.7 mrg "HAVE_TF (isinftf2)" 2839 1.7 mrg { EXPAND_TF (isinftf2, 2); }) 2840 1.7 mrg 2841 1.5 mrg ; 2842 1.5 mrg ; Vector byte swap patterns 2843 1.5 mrg ; 2844 1.5 mrg 2845 1.5 mrg ; FIXME: The bswap rtl standard name currently does not appear to be 2846 1.5 mrg ; used for vector modes. 2847 1.5 mrg (define_expand "bswap<mode>" 2848 1.5 mrg [(parallel 2849 1.5 mrg [(set (match_operand:VT_HW_HSDT 0 "nonimmediate_operand" "") 2850 1.5 mrg (bswap:VT_HW_HSDT (match_operand:VT_HW_HSDT 1 "nonimmediate_operand" ""))) 2851 1.5 mrg (use (match_dup 2))])] 2852 1.5 mrg "TARGET_VX" 2853 1.5 mrg { 2854 1.5 mrg static char p[4][16] = 2855 1.5 mrg { { 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 }, /* H */ 2856 1.5 mrg { 3, 2, 1, 0, 7, 6, 5, 4, 11, 10, 9, 8, 15, 14, 13, 12 }, /* S */ 2857 1.5 mrg { 7, 6, 5, 4, 3, 2, 1, 0, 15, 14, 13, 12, 11, 10, 9, 8 }, /* D */ 2858 1.5 mrg { 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 } }; /* T */ 2859 1.5 mrg char *perm; 2860 1.5 mrg rtx perm_rtx[16]; 2861 1.5 mrg 2862 1.5 mrg switch (GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode))) 2863 1.5 mrg { 2864 1.5 mrg case 2: perm = p[0]; break; 2865 1.5 mrg case 4: perm = p[1]; break; 2866 1.5 mrg case 8: perm = p[2]; break; 2867 1.5 mrg case 16: perm = p[3]; break; 2868 1.5 mrg default: gcc_unreachable (); 2869 1.5 mrg } 2870 1.5 mrg for (int i = 0; i < 16; i++) 2871 1.5 mrg perm_rtx[i] = GEN_INT (perm[i]); 2872 1.5 mrg 2873 1.5 mrg operands[2] = gen_rtx_CONST_VECTOR (V16QImode, gen_rtvec_v (16, perm_rtx)); 2874 1.5 mrg 2875 1.5 mrg /* Without vxe2 we do not have byte swap instructions dealing 2876 1.5 mrg directly with memory operands. So instead of waiting until 2877 1.5 mrg reload to fix that up switch over to vector permute right 2878 1.5 mrg now. */ 2879 1.5 mrg if (!TARGET_VXE2) 2880 1.5 mrg { 2881 1.5 mrg rtx in = force_reg (V16QImode, simplify_gen_subreg (V16QImode, operands[1], <MODE>mode, 0)); 2882 1.5 mrg rtx permute = force_reg (V16QImode, force_const_mem (V16QImode, operands[2])); 2883 1.5 mrg rtx out = gen_reg_rtx (V16QImode); 2884 1.5 mrg 2885 1.5 mrg emit_insn (gen_vec_permv16qi (out, in, in, permute)); 2886 1.5 mrg emit_move_insn (operands[0], simplify_gen_subreg (<MODE>mode, out, V16QImode, 0)); 2887 1.5 mrg DONE; 2888 1.5 mrg } 2889 1.5 mrg }) 2890 1.5 mrg 2891 1.5 mrg ; Switching late to the reg-reg variant requires the vector permute 2892 1.5 mrg ; pattern to be pushed into literal pool and allocating a vector 2893 1.5 mrg ; register to load it into. We rely on both being provided by LRA 2894 1.5 mrg ; when fixing up the v constraint for operand 2. 2895 1.5 mrg 2896 1.5 mrg ; permute_pattern_operand: general_operand would reject the permute 2897 1.5 mrg ; pattern constants since these are not accepted by 2898 1.5 mrg ; s390_legimitate_constant_p 2899 1.5 mrg 2900 1.5 mrg ; ^R: Prevent these alternatives from being chosen if it would require 2901 1.5 mrg ; pushing the operand into memory first 2902 1.5 mrg 2903 1.5 mrg ; vlbrh, vlbrf, vlbrg, vlbrq, vstbrh, vstbrf, vstbrg, vstbrq 2904 1.5 mrg (define_insn_and_split "*bswap<mode>" 2905 1.5 mrg [(set (match_operand:VT_HW_HSDT 0 "nonimmediate_operand" "=v, v,^R") 2906 1.5 mrg (bswap:VT_HW_HSDT (match_operand:VT_HW_HSDT 1 "nonimmediate_operand" "v,^R, v"))) 2907 1.5 mrg (use (match_operand:V16QI 2 "permute_pattern_operand" "v, X, X"))] 2908 1.5 mrg "TARGET_VXE2" 2909 1.5 mrg "@ 2910 1.5 mrg # 2911 1.5 mrg vlbr<bhfgq>\t%v0,%v1 2912 1.5 mrg vstbr<bhfgq>\t%v1,%v0" 2913 1.5 mrg "&& reload_completed 2914 1.5 mrg && !memory_operand (operands[0], <MODE>mode) 2915 1.5 mrg && !memory_operand (operands[1], <MODE>mode)" 2916 1.5 mrg [(set (match_dup 0) 2917 1.5 mrg (subreg:VT_HW_HSDT 2918 1.5 mrg (unspec:V16QI [(subreg:V16QI (match_dup 1) 0) 2919 1.5 mrg (subreg:V16QI (match_dup 1) 0) 2920 1.5 mrg (match_dup 2)] 2921 1.5 mrg UNSPEC_VEC_PERM) 0))] 2922 1.5 mrg "" 2923 1.5 mrg [(set_attr "op_type" "*,VRX,VRX")]) 2924 1.5 mrg 2925 1.1 mrg ; reduc_smin 2926 1.1 mrg ; reduc_smax 2927 1.1 mrg ; reduc_umin 2928 1.1 mrg ; reduc_umax 2929 1.1 mrg 2930 1.3 mrg ; vec_pack_sfix_trunc: convert + pack ? 2931 1.1 mrg ; vec_pack_ufix_trunc 2932 1.1 mrg ; vec_unpacks_float_hi 2933 1.1 mrg ; vec_unpacks_float_lo 2934 1.1 mrg ; vec_unpacku_float_hi 2935 1.1 mrg ; vec_unpacku_float_lo 2936
Indexes created Wed Apr 15 00:22:22 UTC 2026