1 1.1 mrg ;; Scheduling description for Niagara. 2 1.12 mrg ;; Copyright (C) 2006-2022 Free Software Foundation, Inc. 3 1.1 mrg ;; 4 1.1 mrg ;; This file is part of GCC. 5 1.1 mrg ;; 6 1.1 mrg ;; GCC is free software; you can redistribute it and/or modify 7 1.1 mrg ;; it under the terms of the GNU General Public License as published by 8 1.1 mrg ;; the Free Software Foundation; either version 3, or (at your option) 9 1.1 mrg ;; any later version. 10 1.1 mrg ;; 11 1.1 mrg ;; GCC is distributed in the hope that it will be useful, 12 1.1 mrg ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13 1.1 mrg ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 1.1 mrg ;; GNU General Public License for more details. 15 1.1 mrg ;; 16 1.1 mrg ;; You should have received a copy of the GNU General Public License 17 1.1 mrg ;; along with GCC; see the file COPYING3. If not see 18 1.1 mrg ;; <http://www.gnu.org/licenses/>. 19 1.1 mrg 20 1.1 mrg ;; Niagara is a single-issue processor. 21 1.1 mrg 22 1.1 mrg (define_automaton "niagara_0") 23 1.1 mrg 24 1.1 mrg (define_cpu_unit "niag_pipe" "niagara_0") 25 1.1 mrg 26 1.1 mrg (define_insn_reservation "niag_5cycle" 5 27 1.1 mrg (and (eq_attr "cpu" "niagara") 28 1.1 mrg (eq_attr "type" "multi,flushw,iflush,trap")) 29 1.1 mrg "niag_pipe*5") 30 1.1 mrg 31 1.1 mrg (define_insn_reservation "niag_4cycle" 4 32 1.1 mrg (and (eq_attr "cpu" "niagara") 33 1.1 mrg (eq_attr "type" "savew")) 34 1.1 mrg "niag_pipe*4") 35 1.1 mrg 36 1.1 mrg /* Most basic operations are single-cycle. */ 37 1.1 mrg (define_insn_reservation "niag_ialu" 1 38 1.1 mrg (and (eq_attr "cpu" "niagara") 39 1.1 mrg (eq_attr "type" "ialu,shift,compare,cmove")) 40 1.1 mrg "niag_pipe") 41 1.1 mrg 42 1.1 mrg (define_insn_reservation "niag_imul" 11 43 1.1 mrg (and (eq_attr "cpu" "niagara") 44 1.1 mrg (eq_attr "type" "imul")) 45 1.1 mrg "niag_pipe*11") 46 1.1 mrg 47 1.1 mrg (define_insn_reservation "niag_idiv" 72 48 1.1 mrg (and (eq_attr "cpu" "niagara") 49 1.1 mrg (eq_attr "type" "idiv")) 50 1.1 mrg "niag_pipe*72") 51 1.1 mrg 52 1.1 mrg (define_insn_reservation "niag_branch" 3 53 1.1 mrg (and (eq_attr "cpu" "niagara") 54 1.1 mrg (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch")) 55 1.1 mrg "niag_pipe*3") 56 1.1 mrg 57 1.1 mrg (define_insn_reservation "niag_3cycle_load" 3 58 1.1 mrg (and (eq_attr "cpu" "niagara") 59 1.1 mrg (eq_attr "type" "load")) 60 1.1 mrg "niag_pipe*3") 61 1.1 mrg 62 1.1 mrg (define_insn_reservation "niag_9cycle_load" 9 63 1.1 mrg (and (eq_attr "cpu" "niagara") 64 1.1 mrg (eq_attr "type" "fpload")) 65 1.1 mrg "niag_pipe*9") 66 1.1 mrg 67 1.1 mrg (define_insn_reservation "niag_1cycle_store" 1 68 1.1 mrg (and (eq_attr "cpu" "niagara") 69 1.1 mrg (eq_attr "type" "store")) 70 1.1 mrg "niag_pipe") 71 1.1 mrg 72 1.1 mrg (define_insn_reservation "niag_8cycle_store" 8 73 1.1 mrg (and (eq_attr "cpu" "niagara") 74 1.1 mrg (eq_attr "type" "fpstore")) 75 1.1 mrg "niag_pipe*8") 76 1.1 mrg 77 1.1 mrg /* Things incorrectly modelled here: 78 1.1 mrg * FPADD{s,d}: 26 cycles 79 1.1 mrg * FPSUB{s,d}: 26 cycles 80 1.1 mrg * FABSD: 26 cycles 81 1.1 mrg * F{s,d}TO{s,d}: 26 cycles 82 1.1 mrg * F{s,d}TO{i,x}: 26 cycles 83 1.1 mrg * FSMULD: 29 cycles 84 1.1 mrg */ 85 1.1 mrg (define_insn_reservation "niag_fmov" 8 86 1.1 mrg (and (eq_attr "cpu" "niagara") 87 1.1 mrg (eq_attr "type" "fpmove,fpcmove,fpcrmove")) 88 1.1 mrg "niag_pipe*8") 89 1.1 mrg 90 1.1 mrg (define_insn_reservation "niag_fpcmp" 26 91 1.1 mrg (and (eq_attr "cpu" "niagara") 92 1.1 mrg (eq_attr "type" "fpcmp")) 93 1.1 mrg "niag_pipe*26") 94 1.1 mrg 95 1.1 mrg (define_insn_reservation "niag_fmult" 29 96 1.1 mrg (and (eq_attr "cpu" "niagara") 97 1.1 mrg (eq_attr "type" "fpmul")) 98 1.1 mrg "niag_pipe*29") 99 1.1 mrg 100 1.1 mrg (define_insn_reservation "niag_fdivs" 54 101 1.1 mrg (and (eq_attr "cpu" "niagara") 102 1.1 mrg (eq_attr "type" "fpdivs")) 103 1.1 mrg "niag_pipe*54") 104 1.1 mrg 105 1.1 mrg (define_insn_reservation "niag_fdivd" 83 106 1.1 mrg (and (eq_attr "cpu" "niagara") 107 1.1 mrg (eq_attr "type" "fpdivd")) 108 1.1 mrg "niag_pipe*83") 109 1.1 mrg 110 1.1 mrg /* Things incorrectly modelled here: 111 1.1 mrg * FPADD{16,32}: 10 cycles 112 1.1 mrg * FPSUB{16,32}: 10 cycles 113 1.1 mrg * FALIGNDATA: 10 cycles 114 1.1 mrg */ 115 1.1 mrg (define_insn_reservation "niag_vis" 8 116 1.1 mrg (and (eq_attr "cpu" "niagara") 117 1.8 mrg (eq_attr "type" "fga,visl,viscmp,vismv,fgm_pack,fgm_mul,pdist,edge,edgen,gsr,array,bmask")) 118 1.1 mrg "niag_pipe*8") 119
Indexes created Wed Sep 09 00:24:13 UTC 2026