vax.md revision 1.20
1 ;; Machine description for GNU compiler, VAX Version 2 ;; Copyright (C) 1987-2022 Free Software Foundation, Inc. 3 4 ;; This file is part of GCC. 5 6 ;; GCC is free software; you can redistribute it and/or modify 7 ;; it under the terms of the GNU General Public License as published by 8 ;; the Free Software Foundation; either version 3, or (at your option) 9 ;; any later version. 10 11 ;; GCC is distributed in the hope that it will be useful, 12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 ;; GNU General Public License for more details. 15 16 ;; You should have received a copy of the GNU General Public License 17 ;; along with GCC; see the file COPYING3. If not see 18 ;; <http://www.gnu.org/licenses/>. 19 20 21 ;;- Instruction patterns. When multiple patterns apply, 22 ;;- the first one in the file is chosen. 23 ;;- 24 ;;- See file "rtl.def" for documentation on define_insn, match_*, et al. 25 26 ;; UNSPEC_VOLATILE usage: 27 28 (define_c_enum "unspecv" [ 29 VUNSPEC_BLOCKAGE ; 'blockage' insn to prevent scheduling across an 30 ; insn in the code. 31 VUNSPEC_SYNC_ISTREAM ; sequence of insns to sync the I-stream 32 VUNSPEC_PEM ; 'procedure_entry_mask' insn. 33 34 VUNSPEC_EH_RETURN 35 ]) 36 37 ;; UNSPEC usage: 38 39 (define_c_enum "unspec" [ 40 UNSPEC_SETMEM_FILL ; 'fill' operand to 'setmem' insn. 41 ]) 42 43 (define_constants 44 [(VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer 45 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer 46 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer 47 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter 48 (VAX_PSL_REGNUM 16) ; Register 16 contains the processor status 49 ; and condition codes in particular 50 ] 51 ) 52 53 ;; Integer modes supported on VAX, with a mapping from machine mode 54 ;; to mnemonic suffix. DImode is always a special case. 55 (define_mode_iterator VAXint [QI HI SI]) 56 (define_mode_iterator VAXintQH [QI HI]) 57 (define_mode_iterator VAXintQHSD [QI HI SI DI]) 58 (define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")]) 59 60 ;; Similar for float modes supported on VAX. 61 (define_mode_iterator VAXfp [SF DF]) 62 (define_mode_attr fsfx [(SF "f") (DF "%#")]) 63 64 ;; Some output patterns want integer immediates with a prefix... 65 (define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")]) 66 67 (define_mode_iterator VAXcc [CC CCN CCNZ CCZ]) 68 (define_mode_iterator VAXccnz [CCN CCNZ CCZ]) 69 70 (define_code_iterator any_extract [sign_extract zero_extract]) 71 72 ;; 73 (include "constraints.md") 74 (include "predicates.md") 75 76 ;; Make instructions that set the N, N+Z, and Z condition codes respectively. 77 (define_subst "subst_<mode>" 78 [(set (match_operand 0 "") 79 (match_operand 1 "")) 80 (clobber (reg:CC VAX_PSL_REGNUM))] 81 "" 82 [(set (reg:VAXccnz VAX_PSL_REGNUM) 83 (compare:VAXccnz (match_dup 1) 84 (const_int 0))) 85 (set (match_dup 0) 86 (match_dup 1))]) 87 88 (define_subst "subst_f<VAXccnz:mode>" 89 [(set (match_operand:VAXfp 0 "") 90 (match_operand:VAXfp 1 "")) 91 (clobber (reg:CC VAX_PSL_REGNUM))] 92 "" 93 [(set (reg:VAXccnz VAX_PSL_REGNUM) 94 (compare:VAXccnz (match_dup 1) 95 (const_double_zero:VAXfp))) 96 (set (match_dup 0) 97 (match_dup 1))]) 98 99 ;; Select all from the attributes below that apply to a given insn that 100 ;; has a clobber on CC for the comparison elimination pass to use it in 101 ;; place of a subsequent comparison instruction matching the mode used 102 ;; by a comparison operator in branch. 103 ;; 104 ;; For example a branch doing `eq' in SImode will use `*cmpsi_ccz', so 105 ;; to eliminate it a `*movsi_ccz', etc. pattern will be required via the 106 ;; `ccz' substitution. Analogously for the other CC modes. 107 ;; 108 ;; The general `cc' mode, which sets all of the C, N, V and Z condition 109 ;; codes, has to be handled specially as it makes no sense for the usual 110 ;; comparison against zero, so no substitution has been defined for it. 111 (define_subst_attr "ccn" "subst_ccn" "" "_ccn") 112 (define_subst_attr "ccnz" "subst_ccnz" "" "_ccnz") 113 (define_subst_attr "ccz" "subst_ccz" "" "_ccz") 114 (define_subst_attr "fccn" "subst_fccn" "" "_ccn") 115 (define_subst_attr "fccnz" "subst_fccnz" "" "_ccnz") 116 (define_subst_attr "fccz" "subst_fccz" "" "_ccz") 117 118 (define_insn "*cmp<VAXint:mode>_<VAXcc:mode>" 119 [(set (reg:VAXcc VAX_PSL_REGNUM) 120 (compare:VAXcc (match_operand:VAXint 0 "general_operand" "nrmT,nrmT") 121 (match_operand:VAXint 1 "general_operand" "I,nrmT")))] 122 "reload_completed" 123 "@ 124 tst<VAXint:isfx> %0 125 cmp<VAXint:isfx> %0,%1") 126 127 ;; We don't have a CMPQ instruction, but we can set the N and Z condition 128 ;; codes with MOVQ, and also this comparison can be folded into a preceding 129 ;; operation by the post-reload comparison elimination pass. 130 (define_insn "*cmpdi_<VAXccnz:mode>" 131 [(set (reg:VAXccnz VAX_PSL_REGNUM) 132 (compare:VAXccnz (match_operand:DI 0 "general_operand" "r,nmT") 133 (match_operand:DI 1 "const_zero_operand" "I,I"))) 134 (clobber (match_scratch:DI 2 "=X,r"))] 135 "reload_completed" 136 "@ 137 movq %0,%0 138 movq %0,%2") 139 140 (define_insn "*cmp<VAXfp:mode>_<VAXccnz:mode>" 141 [(set (reg:VAXccnz VAX_PSL_REGNUM) 142 (compare:VAXccnz (match_operand:VAXfp 0 "general_operand" "gF,gF") 143 (match_operand:VAXfp 1 "general_operand" "G,gF")))] 144 "reload_completed" 145 "@ 146 tst<VAXfp:fsfx> %0 147 cmp<VAXfp:fsfx> %0,%1") 148 149 (define_insn "*bit<VAXint:mode>_<VAXccnz:mode>" 150 [(set (reg:VAXccnz VAX_PSL_REGNUM) 151 (compare:VAXccnz 152 (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT") 153 (match_operand:VAXint 1 "general_operand" "nrmT")) 154 (const_int 0)))] 155 "reload_completed" 156 "bit<VAXint:isfx> %0,%1") 157 158 ;; The VAX has no sCOND insns. It does have add/subtract with carry 159 ;; which could be used to implement the sltu and sgeu patterns. However, 160 ;; to do this properly requires a complete rewrite of the compare insns 161 ;; to keep them together with the sltu/sgeu insns until after the 162 ;; reload pass is complete. The previous implementation didn't do this 163 ;; and has been deleted. 164 165 167 (define_insn_and_split "mov<mode>" 168 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 169 (match_operand:VAXfp 1 "general_operand" "G,gF"))] 170 "" 171 "#" 172 "reload_completed" 173 [(parallel 174 [(set (match_dup 0) 175 (match_dup 1)) 176 (clobber (reg:CC VAX_PSL_REGNUM))])] 177 "") 178 179 (define_insn "*mov<mode><fccn><fccnz><fccz>" 180 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 181 (match_operand:VAXfp 1 "general_operand" "G,gF")) 182 (clobber (reg:CC VAX_PSL_REGNUM))] 183 "reload_completed" 184 "@ 185 clr<VAXfp:fsfx> %0 186 mov<VAXfp:fsfx> %1,%0") 187 188 ;; Some VAXen don't support this instruction. 189 ;;(define_insn_and_split "movti" 190 ;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g") 191 ;; (match_operand:TI 1 "general_operand" "g"))] 192 ;; "" 193 ;; "#" 194 ;; "reload_completed" 195 ;; [(parallel 196 ;; [(set (match_dup 0) 197 ;; (match_dup 1)) 198 ;; (clobber (reg:CC VAX_PSL_REGNUM))])] 199 ;; "") 200 ;; 201 ;;(define_insn "*movti<ccn><ccnz><ccz>" 202 ;; [(set (match_operand:TI 0 "nonimmediate_operand" "=g") 203 ;; (match_operand:TI 1 "general_operand" "g")) 204 ;; (clobber (reg:CC VAX_PSL_REGNUM))] 205 ;; "reload_completed" 206 ;; "movo %1,%0") 207 208 (define_insn_and_split "movdi" 209 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 210 (match_operand:DI 1 "general_operand" "g"))] 211 "" 212 "#" 213 "reload_completed" 214 [(parallel 215 [(set (match_dup 0) 216 (match_dup 1)) 217 (clobber (reg:CC VAX_PSL_REGNUM))])] 218 "") 219 220 ;; In some cases `vax_output_int_move' splits a `DImode' move into a pair 221 ;; of `SImode' moves, in which case the flags aren't usefully set. Have 222 ;; separate patterns then, for the cases where the move may and may not be 223 ;; split each. We use the outer condition only so in some cases we will 224 ;; fail to notice the move does not actually get split, but this is OK. 225 (define_insn "*movdi_maybe_split" 226 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 227 (match_operand:DI 1 "general_operand" "g")) 228 (clobber (reg:CC VAX_PSL_REGNUM))] 229 "reload_completed && vax_maybe_split_dimode_move (operands)" 230 "* return vax_output_int_move (insn, operands, DImode);") 231 232 (define_insn "*movdi_unsplit<ccn><ccnz><ccz>" 233 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 234 (match_operand:DI 1 "general_operand" "g")) 235 (clobber (reg:CC VAX_PSL_REGNUM))] 236 "reload_completed && !vax_maybe_split_dimode_move (operands)" 237 "* return vax_output_int_move (insn, operands, DImode);") 238 239 ;; The VAX move instructions have space-time tradeoffs. On a MicroVAX 240 ;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl 241 ;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles 242 ;; if the constant is smaller than 4 bytes, 3 cycles for a longword 243 ;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster 244 ;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt 245 ;; instructions take 4 cycles. inc takes 3 cycles. The machine description 246 ;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl 247 ;; instead of movl). 248 249 ;; Cycle counts for other models may vary (on a VAX 750 they are similar, 250 ;; but on a VAX 9000 most move and add instructions with one constant 251 ;; operand take 1 cycle). 252 253 ;; Loads of constants between 64 and 128 used to be done with 254 ;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space. 255 256 (define_expand "movsi" 257 [(set (match_operand:SI 0 "nonimmediate_operand" "") 258 (match_operand:SI 1 "general_operand" ""))] 259 "" 260 " 261 { 262 #ifdef NO_EXTERNAL_INDIRECT_ADDRESS 263 if (flag_pic 264 && GET_CODE (operands[1]) == CONST 265 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF 266 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0))) 267 { 268 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0); 269 rtx const_int = XEXP (XEXP (operands[1], 0), 1); 270 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 271 emit_move_insn (temp, symbol_ref); 272 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int)); 273 DONE; 274 } 275 #endif 276 }") 277 278 ;; Split a store of the upper half of a 64 bit value in memory into 279 ;; two operations. 280 (define_split 281 [(set (match_operand:SI 0 "nonimmediate_operand" "") 282 (subreg:SI 283 (match_operand:DI 1 "indexed_memory_operand" "") 284 4 285 ) 286 ) 287 (clobber (match_scratch:DI 2 "")) 288 ] 289 "" 290 [ 291 (set (match_dup 2) 292 (match_dup 1) 293 ) 294 (set (match_dup 0) 295 (subreg:SI (match_dup 2) 4) 296 ) 297 ] 298 ) 299 300 (define_insn_and_split "movsi_2" 301 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 302 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))] 303 "" 304 "#" 305 "reload_completed" 306 [(parallel 307 [(set (match_dup 0) 308 (match_dup 1)) 309 (clobber (reg:CC VAX_PSL_REGNUM))])] 310 "") 311 312 (define_insn "*movsi_2<ccn><ccnz><ccz>" 313 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 314 (match_operand:SI 1 "nonsymbolic_operand" "nrmT")) 315 (clobber (reg:CC VAX_PSL_REGNUM))] 316 "reload_completed" 317 "* return vax_output_int_move (insn, operands, SImode);") 318 319 (define_insn_and_split "mov<mode>" 320 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g") 321 (match_operand:VAXintQH 1 "general_operand" "g"))] 322 "" 323 "#" 324 "reload_completed" 325 [(parallel 326 [(set (match_dup 0) 327 (match_dup 1)) 328 (clobber (reg:CC VAX_PSL_REGNUM))])] 329 "") 330 331 (define_insn "*mov<mode><ccn><ccnz><ccz>" 332 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g") 333 (match_operand:VAXintQH 1 "general_operand" "g")) 334 (clobber (reg:CC VAX_PSL_REGNUM))] 335 "reload_completed" 336 "* return vax_output_int_move (insn, operands, <MODE>mode);") 337 338 (define_insn_and_split "movstricthi" 339 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) 340 (match_operand:HI 1 "general_operand" "g"))] 341 "" 342 "#" 343 "reload_completed" 344 [(parallel 345 [(set (strict_low_part (match_dup 0)) 346 (match_dup 1)) 347 (clobber (reg:CC VAX_PSL_REGNUM))])] 348 "") 349 350 (define_insn "*movstricthi<ccn><ccnz><ccz>" 351 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+r")) 352 (match_operand:HI 1 "general_operand" "g")) 353 (clobber (reg:CC VAX_PSL_REGNUM))] 354 "reload_completed" 355 "* 356 { 357 if (CONST_INT_P (operands[1])) 358 { 359 int i = INTVAL (operands[1]); 360 if (i == 0) 361 return \"clrw %0\"; 362 else if ((unsigned int)i < 64) 363 return \"movw %1,%0\"; 364 else if ((unsigned int)~i < 64) 365 return \"mcomw %H1,%0\"; 366 else if ((unsigned int)i < 256) 367 return \"movzbw %1,%0\"; 368 } 369 return \"movw %1,%0\"; 370 }") 371 372 (define_insn_and_split "movstrictqi" 373 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) 374 (match_operand:QI 1 "general_operand" "g"))] 375 "" 376 "#" 377 "reload_completed" 378 [(parallel 379 [(set (strict_low_part (match_dup 0)) 380 (match_dup 1)) 381 (clobber (reg:CC VAX_PSL_REGNUM))])] 382 "") 383 384 (define_insn "*movstrictqi<ccn><ccnz><ccz>" 385 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+r")) 386 (match_operand:QI 1 "general_operand" "g")) 387 (clobber (reg:CC VAX_PSL_REGNUM))] 388 "reload_completed" 389 "* 390 { 391 if (CONST_INT_P (operands[1])) 392 { 393 int i = INTVAL (operands[1]); 394 if (i == 0) 395 return \"clrb %0\"; 396 else if ((unsigned int)~i < 64) 397 return \"mcomb %B1,%0\"; 398 } 399 return \"movb %1,%0\"; 400 }") 401 402 ;; This is here to accept 4 arguments and pass the first 3 along 403 ;; to the movmemhi1 pattern that really does the work. 404 (define_expand "cpymemhi" 405 [(set (match_operand:BLK 0 "memory_operand" "") 406 (match_operand:BLK 1 "memory_operand" "")) 407 (use (match_operand:HI 2 "general_operand" "")) 408 (match_operand 3 "" "")] 409 "" 410 " 411 { 412 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2])); 413 DONE; 414 }") 415 416 (define_expand "movmemhi" 417 [(set (match_operand:BLK 0 "memory_operand" "") 418 (match_operand:BLK 1 "memory_operand" "")) 419 (use (match_operand:HI 2 "general_operand" "")) 420 (match_operand 3 "" "")] 421 "" 422 " 423 { 424 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2])); 425 DONE; 426 }") 427 428 ;; The definition of this insn does not really explain what it does, 429 ;; but it should suffice 430 ;; that anything generated as this insn will be recognized as one 431 ;; and that it won't successfully combine with anything. 432 433 (define_insn_and_split "movmemhi1" 434 [(set (match_operand:BLK 0 "memory_operand" "=o") 435 (match_operand:BLK 1 "memory_operand" "o")) 436 (use (match_operand:HI 2 "general_operand" "g")) 437 (clobber (reg:SI 0)) 438 (clobber (reg:SI 1)) 439 (clobber (reg:SI 2)) 440 (clobber (reg:SI 3)) 441 (clobber (reg:SI 4)) 442 (clobber (reg:SI 5))] 443 "" 444 "#" 445 "reload_completed" 446 [(parallel 447 [(set (match_dup 0) 448 (match_dup 1)) 449 (use (match_dup 2)) 450 (clobber (reg:SI 0)) 451 (clobber (reg:SI 1)) 452 (clobber (reg:SI 2)) 453 (clobber (reg:SI 3)) 454 (clobber (reg:SI 4)) 455 (clobber (reg:SI 5)) 456 (clobber (reg:CC VAX_PSL_REGNUM))])] 457 "") 458 459 (define_insn "*movmemhi1" 460 [(set (match_operand:BLK 0 "memory_operand" "=o") 461 (match_operand:BLK 1 "memory_operand" "o")) 462 (use (match_operand:HI 2 "general_operand" "g")) 463 (clobber (reg:SI 0)) 464 (clobber (reg:SI 1)) 465 (clobber (reg:SI 2)) 466 (clobber (reg:SI 3)) 467 (clobber (reg:SI 4)) 468 (clobber (reg:SI 5)) 469 (clobber (reg:CC VAX_PSL_REGNUM))] 470 "reload_completed" 471 "movc3 %2,%1,%0") 472 473 ;; This is here to accept 4 arguments and pass the first 3 along 474 ;; to the setmemhi1 pattern that really does the work. 475 (define_expand "setmemhi" 476 [(set (match_operand:BLK 0 "memory_operand" "") 477 (match_operand:QI 2 "general_operand" "")) 478 (use (match_operand:HI 1 "general_operand" "")) 479 (match_operand 3 "" "")] 480 "" 481 " 482 { 483 emit_insn (gen_setmemhi1 (operands[0], operands[1], operands[2])); 484 DONE; 485 }") 486 487 ;; The srcaddr operand of MOVC5 is not dereferenced if srclen is zero, so we 488 ;; set it to (%ap) somewhat arbitrarily chosen for the shortest encoding. 489 (define_insn_and_split "setmemhi1" 490 [(set (match_operand:BLK 0 "memory_operand" "=o") 491 (unspec:BLK [(use (match_operand:QI 2 "general_operand" "g"))] 492 UNSPEC_SETMEM_FILL)) 493 (use (match_operand:HI 1 "general_operand" "g")) 494 (clobber (reg:SI 0)) 495 (clobber (reg:SI 1)) 496 (clobber (reg:SI 2)) 497 (clobber (reg:SI 3)) 498 (clobber (reg:SI 4)) 499 (clobber (reg:SI 5))] 500 "" 501 "#" 502 "reload_completed" 503 [(parallel 504 [(set (match_dup 0) 505 (unspec:BLK [(use (match_dup 2))] UNSPEC_SETMEM_FILL)) 506 (use (match_dup 1)) 507 (clobber (reg:SI 0)) 508 (clobber (reg:SI 1)) 509 (clobber (reg:SI 2)) 510 (clobber (reg:SI 3)) 511 (clobber (reg:SI 4)) 512 (clobber (reg:SI 5)) 513 (clobber (reg:CC VAX_PSL_REGNUM))])] 514 "") 515 516 (define_insn "*setmemhi1" 517 [(set (match_operand:BLK 0 "memory_operand" "=o") 518 (unspec:BLK [(use (match_operand:QI 2 "general_operand" "g"))] 519 UNSPEC_SETMEM_FILL)) 520 (use (match_operand:HI 1 "general_operand" "g")) 521 (clobber (reg:SI 0)) 522 (clobber (reg:SI 1)) 523 (clobber (reg:SI 2)) 524 (clobber (reg:SI 3)) 525 (clobber (reg:SI 4)) 526 (clobber (reg:SI 5)) 527 (clobber (reg:CC VAX_PSL_REGNUM))] 528 "reload_completed" 529 "movc5 $0,(%%ap),%2,%1,%0") 530 532 ;; Extension and truncation insns. 533 534 (define_insn_and_split "truncsiqi2" 535 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 536 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))] 537 "" 538 "#" 539 "reload_completed" 540 [(parallel 541 [(set (match_dup 0) 542 (truncate:QI (match_dup 1))) 543 (clobber (reg:CC VAX_PSL_REGNUM))])] 544 "") 545 546 (define_insn "*truncsiqi2<ccn><ccnz><ccz>" 547 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 548 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT"))) 549 (clobber (reg:CC VAX_PSL_REGNUM))] 550 "reload_completed" 551 "cvtlb %1,%0") 552 553 (define_insn_and_split "truncsihi2" 554 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 555 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))] 556 "" 557 "#" 558 "reload_completed" 559 [(parallel 560 [(set (match_dup 0) 561 (truncate:HI (match_dup 1))) 562 (clobber (reg:CC VAX_PSL_REGNUM))])] 563 "") 564 565 (define_insn "*truncsihi2<ccn><ccnz><ccz>" 566 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 567 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT"))) 568 (clobber (reg:CC VAX_PSL_REGNUM))] 569 "reload_completed" 570 "cvtlw %1,%0") 571 572 (define_insn_and_split "trunchiqi2" 573 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 574 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))] 575 "" 576 "#" 577 "reload_completed" 578 [(parallel 579 [(set (match_dup 0) 580 (truncate:QI (match_dup 1))) 581 (clobber (reg:CC VAX_PSL_REGNUM))])] 582 "") 583 584 (define_insn "*trunchiqi2<ccn><ccnz><ccz>" 585 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 586 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g"))) 587 (clobber (reg:CC VAX_PSL_REGNUM))] 588 "reload_completed" 589 "cvtwb %1,%0") 590 591 (define_insn_and_split "extendhisi2" 592 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 593 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 594 "" 595 "#" 596 "reload_completed" 597 [(parallel 598 [(set (match_dup 0) 599 (sign_extend:SI (match_dup 1))) 600 (clobber (reg:CC VAX_PSL_REGNUM))])] 601 "") 602 603 (define_insn "*extendhisi2<ccn><ccnz><ccz>" 604 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 605 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g"))) 606 (clobber (reg:CC VAX_PSL_REGNUM))] 607 "reload_completed" 608 "cvtwl %1,%0") 609 610 (define_insn_and_split "extendqihi2" 611 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 612 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 613 "" 614 "#" 615 "reload_completed" 616 [(parallel 617 [(set (match_dup 0) 618 (sign_extend:HI (match_dup 1))) 619 (clobber (reg:CC VAX_PSL_REGNUM))])] 620 "") 621 622 (define_insn "*extendqihi2<ccn><ccnz><ccz>" 623 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 624 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g"))) 625 (clobber (reg:CC VAX_PSL_REGNUM))] 626 "reload_completed" 627 "cvtbw %1,%0") 628 629 (define_insn_and_split "extendqisi2" 630 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 631 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 632 "" 633 "#" 634 "reload_completed" 635 [(parallel 636 [(set (match_dup 0) 637 (sign_extend:SI (match_dup 1))) 638 (clobber (reg:CC VAX_PSL_REGNUM))])] 639 "") 640 641 (define_insn "*extendqisi2<ccn><ccnz><ccz>" 642 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 643 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) 644 (clobber (reg:CC VAX_PSL_REGNUM))] 645 "reload_completed" 646 "cvtbl %1,%0") 647 648 (define_insn_and_split "extendsfdf2" 649 [(set (match_operand:DF 0 "nonimmediate_operand" "=g") 650 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))] 651 "" 652 "#" 653 "reload_completed" 654 [(parallel 655 [(set (match_dup 0) 656 (float_extend:DF (match_dup 1))) 657 (clobber (reg:CC VAX_PSL_REGNUM))])] 658 "") 659 660 (define_insn "*extendsfdf2<fccn><fccnz><fccz>" 661 [(set (match_operand:DF 0 "nonimmediate_operand" "=g") 662 (float_extend:DF (match_operand:SF 1 "general_operand" "gF"))) 663 (clobber (reg:CC VAX_PSL_REGNUM))] 664 "reload_completed" 665 "cvtf%# %1,%0") 666 667 (define_insn_and_split "truncdfsf2" 668 [(set (match_operand:SF 0 "nonimmediate_operand" "=g") 669 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))] 670 "" 671 "#" 672 "reload_completed" 673 [(parallel 674 [(set (match_dup 0) 675 (float_truncate:SF (match_dup 1))) 676 (clobber (reg:CC VAX_PSL_REGNUM))])] 677 "") 678 679 (define_insn "*truncdfsf2<fccn><fccnz><fccz>" 680 [(set (match_operand:SF 0 "nonimmediate_operand" "=g") 681 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF"))) 682 (clobber (reg:CC VAX_PSL_REGNUM))] 683 "reload_completed" 684 "cvt%#f %1,%0") 685 686 (define_insn_and_split "zero_extendhisi2" 687 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 688 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 689 "" 690 "#" 691 "reload_completed" 692 [(parallel 693 [(set (match_dup 0) 694 (zero_extend:SI (match_dup 1))) 695 (clobber (reg:CC VAX_PSL_REGNUM))])] 696 "") 697 698 (define_insn "*zero_extendhisi2<ccn><ccnz><ccz>" 699 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 700 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g"))) 701 (clobber (reg:CC VAX_PSL_REGNUM))] 702 "reload_completed" 703 "movzwl %1,%0") 704 705 (define_insn_and_split "zero_extendqihi2" 706 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 707 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 708 "" 709 "#" 710 "reload_completed" 711 [(parallel 712 [(set (match_dup 0) 713 (zero_extend:HI (match_dup 1))) 714 (clobber (reg:CC VAX_PSL_REGNUM))])] 715 "") 716 717 (define_insn "*zero_extendqihi2<ccn><ccnz><ccz>" 718 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 719 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g"))) 720 (clobber (reg:CC VAX_PSL_REGNUM))] 721 "reload_completed" 722 "movzbw %1,%0") 723 724 (define_insn_and_split "zero_extendqisi2" 725 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 726 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 727 "" 728 "#" 729 "reload_completed" 730 [(parallel 731 [(set (match_dup 0) 732 (zero_extend:SI (match_dup 1))) 733 (clobber (reg:CC VAX_PSL_REGNUM))])] 734 "") 735 736 (define_insn "*zero_extendqisi2<ccn><ccnz><ccz>" 737 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 738 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g"))) 739 (clobber (reg:CC VAX_PSL_REGNUM))] 740 "reload_completed" 741 "movzbl %1,%0") 742 744 ;; Fix-to-float conversion insns. 745 746 (define_insn_and_split "float<VAXint:mode><VAXfp:mode>2" 747 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 748 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))] 749 "" 750 "#" 751 "reload_completed" 752 [(parallel 753 [(set (match_dup 0) 754 (float:VAXfp (match_dup 1))) 755 (clobber (reg:CC VAX_PSL_REGNUM))])] 756 "") 757 758 (define_insn "*float<VAXint:mode><VAXfp:mode>2<fccn><fccnz><fccz>" 759 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 760 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g"))) 761 (clobber (reg:CC VAX_PSL_REGNUM))] 762 "reload_completed" 763 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0") 764 765 ;; Float-to-fix conversion insns. 766 767 (define_insn_and_split "fix_trunc<VAXfp:mode><VAXint:mode>2" 768 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 769 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))] 770 "" 771 "#" 772 "reload_completed" 773 [(parallel 774 [(set (match_dup 0) 775 (fix:VAXint (match_dup 1))) 776 (clobber (reg:CC VAX_PSL_REGNUM))])] 777 "") 778 779 (define_insn "*fix_trunc<VAXfp:mode><VAXint:mode>2<ccn><ccnz><ccz>" 780 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 781 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF"))) 782 (clobber (reg:CC VAX_PSL_REGNUM))] 783 "reload_completed" 784 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0") 785 786 (define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2" 787 [(set (match_operand:VAXint 0 "nonimmediate_operand" "") 788 (fix:VAXint (match_operand:VAXfp 1 "general_operand")))] 789 "") 790 792 ;;- All kinds of add instructions. 793 794 (define_insn_and_split "add<mode>3" 795 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 796 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 797 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))] 798 "" 799 "#" 800 "reload_completed" 801 [(parallel 802 [(set (match_dup 0) 803 (plus:VAXfp (match_dup 1) 804 (match_dup 2))) 805 (clobber (reg:CC VAX_PSL_REGNUM))])] 806 "") 807 808 (define_insn "*add<mode>3<fccn><fccnz><fccz>" 809 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 810 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 811 (match_operand:VAXfp 2 "general_operand" "gF,0,gF"))) 812 (clobber (reg:CC VAX_PSL_REGNUM))] 813 "reload_completed" 814 "@ 815 add<VAXfp:fsfx>2 %2,%0 816 add<VAXfp:fsfx>2 %1,%0 817 add<VAXfp:fsfx>3 %1,%2,%0") 818 819 (define_insn_and_split "add<mode>3" 820 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 821 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT") 822 (match_operand:VAXint 2 "general_operand" "nrmT")))] 823 "" 824 "#" 825 "reload_completed" 826 [(parallel 827 [(set (match_dup 0) 828 (plus:VAXint (match_dup 1) 829 (match_dup 2))) 830 (clobber (reg:CC VAX_PSL_REGNUM))])] 831 "") 832 833 (define_insn "*add<mode>3<ccn><ccnz><ccz>" 834 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 835 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT") 836 (match_operand:VAXint 2 "general_operand" "nrmT"))) 837 (clobber (reg:CC VAX_PSL_REGNUM))] 838 "reload_completed" 839 "* return vax_output_int_add (insn, operands, <MODE>mode);") 840 841 (define_expand "adddi3" 842 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 843 (plus:DI (match_operand:DI 1 "general_operand" "g") 844 (match_operand:DI 2 "general_operand" "g")))] 845 "!reload_in_progress" 846 "vax_expand_addsub_di_operands (operands, PLUS); DONE;") 847 848 (define_insn_and_split "adcdi3" 849 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr") 850 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0") 851 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))] 852 "TARGET_QMATH" 853 "#" 854 "&& reload_completed" 855 [(parallel 856 [(set (match_dup 0) 857 (plus:DI (match_dup 1) 858 (match_dup 2))) 859 (clobber (reg:CC VAX_PSL_REGNUM))])] 860 "") 861 862 (define_insn "*adcdi3<ccn>" 863 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr") 864 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0") 865 (match_operand:DI 2 "general_addsub_di_operand" "nRr"))) 866 (clobber (reg:CC VAX_PSL_REGNUM))] 867 "TARGET_QMATH && reload_completed" 868 "* return vax_output_int_add (insn, operands, DImode);") 869 870 ;; The add-with-carry (adwc) instruction only accepts two operands. 871 (define_insn_and_split "adddi3_old" 872 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>") 873 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 874 (match_operand:DI 2 "general_operand" "Fsro,Fs")))] 875 "!TARGET_QMATH" 876 "#" 877 "&& reload_completed" 878 [(parallel 879 [(set (match_dup 0) 880 (plus:DI (match_dup 1) 881 (match_dup 2))) 882 (clobber (reg:CC VAX_PSL_REGNUM))])] 883 "") 884 885 (define_insn "*adddi3_old<ccn>" 886 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>") 887 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 888 (match_operand:DI 2 "general_operand" "Fsro,Fs"))) 889 (clobber (reg:CC VAX_PSL_REGNUM))] 890 "!TARGET_QMATH && reload_completed" 891 "* return vax_output_int_add (insn, operands, DImode);") 892 894 ;;- All kinds of subtract instructions. 895 896 (define_insn_and_split "sub<mode>3" 897 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 898 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 899 (match_operand:VAXfp 2 "general_operand" "gF,gF")))] 900 "" 901 "#" 902 "reload_completed" 903 [(parallel 904 [(set (match_dup 0) 905 (minus:VAXfp (match_dup 1) 906 (match_dup 2))) 907 (clobber (reg:CC VAX_PSL_REGNUM))])] 908 "") 909 910 (define_insn "*sub<mode>3<fccn><fccnz><fccz>" 911 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 912 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 913 (match_operand:VAXfp 2 "general_operand" "gF,gF"))) 914 (clobber (reg:CC VAX_PSL_REGNUM))] 915 "reload_completed" 916 "@ 917 sub<VAXfp:fsfx>2 %2,%0 918 sub<VAXfp:fsfx>3 %2,%1,%0") 919 920 (define_insn_and_split "sub<mode>3" 921 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 922 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 923 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))] 924 "" 925 "#" 926 "reload_completed" 927 [(parallel 928 [(set (match_dup 0) 929 (minus:VAXint (match_dup 1) 930 (match_dup 2))) 931 (clobber (reg:CC VAX_PSL_REGNUM))])] 932 "") 933 934 (define_insn "*sub<mode>3<ccn><ccnz><ccz>" 935 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 936 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 937 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT"))) 938 (clobber (reg:CC VAX_PSL_REGNUM))] 939 "reload_completed" 940 "@ 941 sub<VAXint:isfx>2 %2,%0 942 sub<VAXint:isfx>3 %2,%1,%0") 943 944 (define_insn "*sub<mode>3_cc" 945 [(set (reg:CC VAX_PSL_REGNUM) 946 (compare:CC (match_operand:VAXint 1 "general_operand" "0,nrmT") 947 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT"))) 948 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 949 (minus:VAXint (match_dup 1) 950 (match_dup 2)))] 951 "reload_completed" 952 "@ 953 sub<VAXint:isfx>2 %2,%0 954 sub<VAXint:isfx>3 %2,%1,%0") 955 956 (define_expand "subdi3" 957 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 958 (minus:DI (match_operand:DI 1 "general_operand" "g") 959 (match_operand:DI 2 "general_operand" "g")))] 960 "!reload_in_progress" 961 "vax_expand_addsub_di_operands (operands, MINUS); DONE;") 962 963 (define_insn_and_split "sbcdi3" 964 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=&Rr,&Rr") 965 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I") 966 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))] 967 "TARGET_QMATH" 968 "#" 969 "&& reload_completed" 970 [(parallel 971 [(set (match_dup 0) 972 (minus:DI (match_dup 1) 973 (match_dup 2))) 974 (clobber (reg:CC VAX_PSL_REGNUM))])] 975 "") 976 977 (define_insn "*sbcdi3<ccn>" 978 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=&Rr,&Rr") 979 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I") 980 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr"))) 981 (clobber (reg:CC VAX_PSL_REGNUM))] 982 "TARGET_QMATH && reload_completed" 983 "* return vax_output_int_subtract (insn, operands, DImode);") 984 985 ;; The subtract-with-carry (sbwc) instruction only takes two operands. 986 (define_insn_and_split "subdi3_old" 987 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>") 988 (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 989 (match_operand:DI 2 "general_operand" "Fsor,Fs")))] 990 "!TARGET_QMATH" 991 "#" 992 "&& reload_completed" 993 [(parallel 994 [(set (match_dup 0) 995 (minus:DI (match_dup 1) 996 (match_dup 2))) 997 (clobber (reg:CC VAX_PSL_REGNUM))])] 998 "") 999 1000 (define_insn "*subdi3_old<ccn>" 1001 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>") 1002 (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 1003 (match_operand:DI 2 "general_operand" "Fsor,Fs"))) 1004 (clobber (reg:CC VAX_PSL_REGNUM))] 1005 "!TARGET_QMATH && reload_completed" 1006 "* return vax_output_int_subtract (insn, operands, DImode);") 1007 1009 ;;- Multiply instructions. 1010 1011 (define_insn_and_split "mul<mode>3" 1012 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 1013 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 1014 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))] 1015 "" 1016 "#" 1017 "reload_completed" 1018 [(parallel 1019 [(set (match_dup 0) 1020 (mult:VAXfp (match_dup 1) 1021 (match_dup 2))) 1022 (clobber (reg:CC VAX_PSL_REGNUM))])] 1023 "") 1024 1025 (define_insn "*mul<mode>3<fccn><fccnz><fccz>" 1026 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 1027 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 1028 (match_operand:VAXfp 2 "general_operand" "gF,0,gF"))) 1029 (clobber (reg:CC VAX_PSL_REGNUM))] 1030 "reload_completed" 1031 "@ 1032 mul<VAXfp:fsfx>2 %2,%0 1033 mul<VAXfp:fsfx>2 %1,%0 1034 mul<VAXfp:fsfx>3 %1,%2,%0") 1035 1036 (define_insn_and_split "mul<mode>3" 1037 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1038 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1039 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 1040 "" 1041 "#" 1042 "reload_completed" 1043 [(parallel 1044 [(set (match_dup 0) 1045 (mult:VAXint (match_dup 1) 1046 (match_dup 2))) 1047 (clobber (reg:CC VAX_PSL_REGNUM))])] 1048 "") 1049 1050 (define_insn "*mul<mode>3<ccn><ccnz><ccz>" 1051 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1052 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1053 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT"))) 1054 (clobber (reg:CC VAX_PSL_REGNUM))] 1055 "reload_completed" 1056 "@ 1057 mul<VAXint:isfx>2 %2,%0 1058 mul<VAXint:isfx>2 %1,%0 1059 mul<VAXint:isfx>3 %1,%2,%0") 1060 1061 (define_insn_and_split "mulsidi3" 1062 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1063 (mult:DI 1064 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1065 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))))] 1066 "" 1067 "#" 1068 "reload_completed" 1069 [(parallel 1070 [(set (match_dup 0) 1071 (mult:DI 1072 (sign_extend:DI (match_dup 1)) 1073 (sign_extend:DI (match_dup 2)))) 1074 (clobber (reg:CC VAX_PSL_REGNUM))])] 1075 "") 1076 1077 (define_insn "*mulsidi3<ccn><ccnz><ccz>" 1078 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1079 (mult:DI 1080 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1081 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT")))) 1082 (clobber (reg:CC VAX_PSL_REGNUM))] 1083 "reload_completed" 1084 "emul %1,%2,$0,%0") 1085 1086 (define_insn_and_split "*maddsidi4" 1087 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1088 (plus:DI 1089 (mult:DI 1090 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1091 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1092 (sign_extend:DI (match_operand:SI 3 "general_operand" "g"))))] 1093 "" 1094 "#" 1095 "reload_completed" 1096 [(parallel 1097 [(set (match_dup 0) 1098 (plus:DI 1099 (mult:DI 1100 (sign_extend:DI (match_dup 1)) 1101 (sign_extend:DI (match_dup 2))) 1102 (sign_extend:DI (match_dup 3)))) 1103 (clobber (reg:CC VAX_PSL_REGNUM))])] 1104 "") 1105 1106 (define_insn "*maddsidi4_2<ccn><ccnz><ccz>" 1107 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1108 (plus:DI 1109 (mult:DI 1110 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1111 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1112 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g")))) 1113 (clobber (reg:CC VAX_PSL_REGNUM))] 1114 "reload_completed" 1115 "emul %1,%2,%3,%0") 1116 1117 ;; 'F' constraint means type CONST_DOUBLE 1118 (define_insn_and_split "*maddsidi4_const" 1119 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1120 (plus:DI 1121 (mult:DI 1122 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1123 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1124 (match_operand:DI 3 "immediate_operand" "F")))] 1125 "GET_CODE (operands[3]) == CONST_DOUBLE 1126 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)" 1127 "#" 1128 "&& reload_completed" 1129 [(parallel 1130 [(set (match_dup 0) 1131 (plus:DI 1132 (mult:DI 1133 (sign_extend:DI (match_dup 1)) 1134 (sign_extend:DI (match_dup 2))) 1135 (match_dup 3))) 1136 (clobber (reg:CC VAX_PSL_REGNUM))])] 1137 "") 1138 1139 (define_insn "*maddsidi4_const_2<ccn><ccnz><ccz>" 1140 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1141 (plus:DI 1142 (mult:DI 1143 (sign_extend:DI (match_operand:SI 1 "general_operand" "nrmT")) 1144 (sign_extend:DI (match_operand:SI 2 "general_operand" "nrmT"))) 1145 (match_operand:DI 3 "immediate_operand" "F"))) 1146 (clobber (reg:CC VAX_PSL_REGNUM))] 1147 "GET_CODE (operands[3]) == CONST_DOUBLE 1148 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31) 1149 && reload_completed" 1150 "* 1151 { 1152 if (CONST_DOUBLE_HIGH (operands[3])) 1153 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3])); 1154 return \"emul %1,%2,%3,%0\"; 1155 }") 1156 1158 ;;- Divide instructions. 1159 1160 (define_insn_and_split "div<mode>3" 1161 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 1162 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 1163 (match_operand:VAXfp 2 "general_operand" "gF,gF")))] 1164 "" 1165 "#" 1166 "reload_completed" 1167 [(parallel 1168 [(set (match_dup 0) 1169 (div:VAXfp (match_dup 1) 1170 (match_dup 2))) 1171 (clobber (reg:CC VAX_PSL_REGNUM))])] 1172 "") 1173 1174 (define_insn "*div<mode>3<fccn><fccnz><fccz>" 1175 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 1176 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 1177 (match_operand:VAXfp 2 "general_operand" "gF,gF"))) 1178 (clobber (reg:CC VAX_PSL_REGNUM))] 1179 "reload_completed" 1180 "@ 1181 div<VAXfp:fsfx>2 %2,%0 1182 div<VAXfp:fsfx>3 %2,%1,%0") 1183 1184 (define_insn_and_split "div<mode>3" 1185 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1186 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1187 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))] 1188 "" 1189 "#" 1190 "reload_completed" 1191 [(parallel 1192 [(set (match_dup 0) 1193 (div:VAXint (match_dup 1) 1194 (match_dup 2))) 1195 (clobber (reg:CC VAX_PSL_REGNUM))])] 1196 "") 1197 1198 (define_insn "*div<mode>3<ccn><ccnz><ccz>" 1199 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1200 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1201 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT"))) 1202 (clobber (reg:CC VAX_PSL_REGNUM))] 1203 "reload_completed" 1204 "@ 1205 div<VAXint:isfx>2 %2,%0 1206 div<VAXint:isfx>3 %2,%1,%0") 1207 1208 ;; This is left out because it is very slow; 1209 ;; we are better off programming around the "lack" of this insn. 1210 ;;(define_insn_and_split "divmoddisi4" 1211 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1212 ;; (div:SI (match_operand:DI 1 "general_operand" "g") 1213 ;; (match_operand:SI 2 "general_operand" "g"))) 1214 ;; (set (match_operand:SI 3 "nonimmediate_operand" "=g") 1215 ;; (mod:SI (match_dup 1) 1216 ;; (match_dup 2)))] 1217 ;; "" 1218 ;; "#" 1219 ;; "reload_completed" 1220 ;; [(parallel 1221 ;; [(set (match_dup 0) 1222 ;; (div:SI (match_dup 1) 1223 ;; (match_dup 2))) 1224 ;; (set (match_dup 3) 1225 ;; (mod:SI (match_dup 1) 1226 ;; (match_dup 2))) 1227 ;; (clobber (reg:CC VAX_PSL_REGNUM))])] 1228 ;; "") 1229 ;; 1230 ;;(define_insn "*divmoddisi4<ccn><ccnz><ccz>" 1231 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1232 ;; (div:SI (match_operand:DI 1 "general_operand" "g") 1233 ;; (match_operand:SI 2 "general_operand" "g"))) 1234 ;; (set (match_operand:SI 3 "nonimmediate_operand" "=g") 1235 ;; (mod:SI (match_dup 1) 1236 ;; (match_dup 2))) 1237 ;; (clobber (reg:CC VAX_PSL_REGNUM))] 1238 ;; "reload_completed" 1239 ;; "ediv %2,%1,%0,%3") 1240 1242 ;; Bit-and on the VAX is done with a clear-bits insn. 1243 (define_expand "and<mode>3" 1244 [(set (match_operand:VAXint 0 "nonimmediate_operand" "") 1245 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "")) 1246 (match_operand:VAXint 2 "general_operand" "")))] 1247 "" 1248 " 1249 { 1250 rtx op1 = operands[1]; 1251 1252 /* If there is a constant argument, complement that one. */ 1253 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) 1254 { 1255 operands[1] = operands[2]; 1256 operands[2] = op1; 1257 op1 = operands[1]; 1258 } 1259 1260 if (CONST_INT_P (op1)) 1261 operands[1] = GEN_INT (~INTVAL (op1)); 1262 else 1263 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1); 1264 }") 1265 1266 (define_insn_and_split "*and<mode>3" 1267 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1268 (and:VAXint (not:VAXint 1269 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT")) 1270 (match_operand:VAXint 2 "general_operand" "0,nrmT")))] 1271 "" 1272 "#" 1273 "reload_completed" 1274 [(parallel 1275 [(set (match_dup 0) 1276 (and:VAXint (not:VAXint 1277 (match_dup 1)) 1278 (match_dup 2))) 1279 (clobber (reg:CC VAX_PSL_REGNUM))])] 1280 "") 1281 1282 (define_insn "*and<mode>3_2<ccn><ccnz><ccz>" 1283 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1284 (and:VAXint (not:VAXint 1285 (match_operand:VAXint 1 "general_operand" "nrmT,nrmT")) 1286 (match_operand:VAXint 2 "general_operand" "0,nrmT"))) 1287 (clobber (reg:CC VAX_PSL_REGNUM))] 1288 "reload_completed" 1289 "@ 1290 bic<VAXint:isfx>2 %1,%0 1291 bic<VAXint:isfx>3 %1,%2,%0") 1292 1293 ;; The following used to be needed because constant propagation can 1294 ;; create them starting from the bic insn patterns above. This is no 1295 ;; longer a problem. However, having these patterns allows optimization 1296 ;; opportunities in combine.cc. 1297 1298 (define_insn_and_split "*and<mode>3_const_int" 1299 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1300 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1301 (match_operand:VAXint 2 "const_int_operand" "n,n")))] 1302 "" 1303 "#" 1304 "reload_completed" 1305 [(parallel 1306 [(set (match_dup 0) 1307 (and:VAXint (match_dup 1) 1308 (match_dup 2))) 1309 (clobber (reg:CC VAX_PSL_REGNUM))])] 1310 "") 1311 1312 (define_insn "*and<mode>3_2_const_int<ccn><ccnz><ccz>" 1313 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1314 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 1315 (match_operand:VAXint 2 "const_int_operand" "n,n"))) 1316 (clobber (reg:CC VAX_PSL_REGNUM))] 1317 "reload_completed" 1318 "@ 1319 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0 1320 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0") 1321 1322 ;; We have no direct AND operation and consequently the RTL sequence 1323 ;; the "and<mode>3" pattern produces does not match the instruction 1324 ;; the "*bit<mode>" pattern does for the purpose of the compare 1325 ;; elimination pass. Try to get rid of the extra operation by hand 1326 ;; and where the sequence is used to set the condition codes only 1327 ;; convert MCOM/BIC => BIT. 1328 (define_peephole2 1329 [(parallel 1330 [(set (match_operand:VAXint 0 "register_operand") 1331 (not:VAXint (match_operand:VAXint 1 "general_operand"))) 1332 (clobber (reg:CC VAX_PSL_REGNUM))]) 1333 (parallel 1334 [(set (reg:VAXccnz VAX_PSL_REGNUM) 1335 (compare:VAXccnz 1336 (and:VAXint (not:VAXint (match_dup 0)) 1337 (match_operand:VAXint 3 "general_operand")) 1338 (const_int 0))) 1339 (set (match_operand:VAXint 2 "register_operand") 1340 (and:VAXint (not:VAXint (match_dup 0)) 1341 (match_dup 3)))])] 1342 "peep2_reg_dead_p (2, operands[0]) && peep2_reg_dead_p (2, operands[2])" 1343 [(set (reg:VAXccnz VAX_PSL_REGNUM) 1344 (compare:VAXccnz 1345 (and:VAXint (match_dup 1) 1346 (match_dup 3)) 1347 (const_int 0)))] 1348 "") 1349 1351 ;;- Bit set instructions. 1352 1353 (define_insn_and_split "ior<mode>3" 1354 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1355 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1356 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 1357 "" 1358 "#" 1359 "reload_completed" 1360 [(parallel 1361 [(set (match_dup 0) 1362 (ior:VAXint (match_dup 1) 1363 (match_dup 2))) 1364 (clobber (reg:CC VAX_PSL_REGNUM))])] 1365 "") 1366 1367 (define_insn "*ior<mode>3<ccn><ccnz><ccz>" 1368 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1369 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1370 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT"))) 1371 (clobber (reg:CC VAX_PSL_REGNUM))] 1372 "reload_completed" 1373 "@ 1374 bis<VAXint:isfx>2 %2,%0 1375 bis<VAXint:isfx>2 %1,%0 1376 bis<VAXint:isfx>3 %2,%1,%0") 1377 1378 ;;- xor instructions. 1379 1380 (define_insn_and_split "xor<mode>3" 1381 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1382 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1383 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 1384 "" 1385 "#" 1386 "reload_completed" 1387 [(parallel 1388 [(set (match_dup 0) 1389 (xor:VAXint (match_dup 1) 1390 (match_dup 2))) 1391 (clobber (reg:CC VAX_PSL_REGNUM))])] 1392 "") 1393 1394 (define_insn "*xor<mode>3<ccn><ccnz><ccz>" 1395 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 1396 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 1397 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT"))) 1398 (clobber (reg:CC VAX_PSL_REGNUM))] 1399 "reload_completed" 1400 "@ 1401 xor<VAXint:isfx>2 %2,%0 1402 xor<VAXint:isfx>2 %1,%0 1403 xor<VAXint:isfx>3 %2,%1,%0") 1404 1406 (define_insn_and_split "neg<mode>2" 1407 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 1408 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))] 1409 "" 1410 "#" 1411 "reload_completed" 1412 [(parallel 1413 [(set (match_dup 0) 1414 (neg:VAXfp (match_dup 1))) 1415 (clobber (reg:CC VAX_PSL_REGNUM))])] 1416 "") 1417 1418 (define_insn "*neg<mode>2<fccn><fccnz><fccz>" 1419 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 1420 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF"))) 1421 (clobber (reg:CC VAX_PSL_REGNUM))] 1422 "reload_completed" 1423 "mneg<VAXfp:fsfx> %1,%0") 1424 1425 (define_insn_and_split "neg<mode>2" 1426 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1427 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))] 1428 "" 1429 "#" 1430 "reload_completed" 1431 [(parallel 1432 [(set (match_dup 0) 1433 (neg:VAXint (match_dup 1))) 1434 (clobber (reg:CC VAX_PSL_REGNUM))])] 1435 "") 1436 1437 (define_insn "*neg<mode>2<ccn><ccnz><ccz>" 1438 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1439 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT"))) 1440 (clobber (reg:CC VAX_PSL_REGNUM))] 1441 "reload_completed" 1442 "mneg<VAXint:isfx> %1,%0") 1443 1444 (define_insn "*neg<mode>2_cc" 1445 [(set (reg:CC VAX_PSL_REGNUM) 1446 (compare:CC (const_int 0) 1447 (neg:VAXint 1448 (match_operand:VAXint 1 "general_operand" "0,nrmT")))) 1449 (set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 1450 (neg:VAXint (match_dup 1)))] 1451 "reload_completed" 1452 "mneg<VAXint:isfx> %1,%0") 1453 1454 (define_insn_and_split "one_cmpl<mode>2" 1455 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1456 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))] 1457 "" 1458 "#" 1459 "reload_completed" 1460 [(parallel 1461 [(set (match_dup 0) 1462 (not:VAXint (match_dup 1))) 1463 (clobber (reg:CC VAX_PSL_REGNUM))])] 1464 "") 1465 1466 (define_insn "*one_cmpl<mode>2<ccn><ccnz><ccz>" 1467 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 1468 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT"))) 1469 (clobber (reg:CC VAX_PSL_REGNUM))] 1470 "reload_completed" 1471 "mcom<VAXint:isfx> %1,%0") 1472 1474 ;; Arithmetic right shift on the VAX works by negating the shift count, 1475 ;; then emitting a right shift with the shift count negated. This means 1476 ;; that all actual shift counts in the RTL will be positive. This 1477 ;; prevents converting shifts to ZERO_EXTRACTs with negative positions, 1478 ;; which isn't valid. 1479 (define_expand "ashrsi3" 1480 [(set (match_operand:SI 0 "general_operand" "=g") 1481 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1482 (match_operand:QI 2 "general_operand" "g")))] 1483 "" 1484 " 1485 { 1486 if (! CONST_INT_P(operands[2])) 1487 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 1488 }") 1489 1490 (define_insn_and_split "*ashlnegsi3_const_int" 1491 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1492 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1493 (match_operand:QI 2 "const_int_operand" "n")))] 1494 "" 1495 "#" 1496 "reload_completed" 1497 [(parallel 1498 [(set (match_dup 0) 1499 (ashiftrt:SI (match_dup 1) 1500 (match_dup 2))) 1501 (clobber (reg:CC VAX_PSL_REGNUM))])] 1502 "") 1503 1504 (define_insn "*ashlnegsi3_const_int_2<ccn><ccnz><ccz>" 1505 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1506 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1507 (match_operand:QI 2 "const_int_operand" "n"))) 1508 (clobber (reg:CC VAX_PSL_REGNUM))] 1509 "reload_completed" 1510 "ashl $%n2,%1,%0") 1511 1512 (define_insn_and_split "*ashlnegsi3" 1513 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1514 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1515 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1516 "" 1517 "#" 1518 "reload_completed" 1519 [(parallel 1520 [(set (match_dup 0) 1521 (ashiftrt:SI (match_dup 1) 1522 (neg:QI (match_dup 2)))) 1523 (clobber (reg:CC VAX_PSL_REGNUM))])] 1524 "") 1525 1526 (define_insn "*ashlnegsi3_2<ccn><ccnz><ccz>" 1527 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1528 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1529 (neg:QI (match_operand:QI 2 "general_operand" "g")))) 1530 (clobber (reg:CC VAX_PSL_REGNUM))] 1531 "reload_completed" 1532 "ashl %2,%1,%0") 1533 1534 (define_insn_and_split "ashlsi3" 1535 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1536 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 1537 (match_operand:QI 2 "general_operand" "g")))] 1538 "" 1539 "#" 1540 "reload_completed" 1541 [(parallel 1542 [(set (match_dup 0) 1543 (ashift:SI (match_dup 1) 1544 (match_dup 2))) 1545 (clobber (reg:CC VAX_PSL_REGNUM))])] 1546 "") 1547 1548 (define_insn "*ashlsi3<ccn><ccnz><ccz>" 1549 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1550 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 1551 (match_operand:QI 2 "general_operand" "g"))) 1552 (clobber (reg:CC VAX_PSL_REGNUM))] 1553 "reload_completed" 1554 "* 1555 { 1556 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) 1557 return \"addl2 %0,%0\"; 1558 if (REG_P (operands[1]) && CONST_INT_P (operands[2])) 1559 { 1560 int i = INTVAL (operands[2]); 1561 if (i == 1) 1562 return \"addl3 %1,%1,%0\"; 1563 if (i == 2 && !optimize_size) 1564 { 1565 if (push_operand (operands[0], SImode)) 1566 return \"pushal 0[%1]\"; 1567 return \"moval 0[%1],%0\"; 1568 } 1569 if (i == 3 && !optimize_size) 1570 { 1571 if (push_operand (operands[0], SImode)) 1572 return \"pushaq 0[%1]\"; 1573 return \"movaq 0[%1],%0\"; 1574 } 1575 } 1576 return \"ashl %2,%1,%0\"; 1577 }") 1578 1579 ;; Arithmetic right shift on the VAX works by negating the shift count. 1580 (define_expand "ashrdi3" 1581 [(set (match_operand:DI 0 "general_operand" "=g") 1582 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1583 (match_operand:QI 2 "general_operand" "g")))] 1584 "" 1585 " 1586 { 1587 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 1588 }") 1589 1590 (define_insn_and_split "ashldi3" 1591 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1592 (ashift:DI (match_operand:DI 1 "general_operand" "g") 1593 (match_operand:QI 2 "general_operand" "g")))] 1594 "" 1595 "#" 1596 "reload_completed" 1597 [(parallel 1598 [(set (match_dup 0) 1599 (ashift:DI (match_dup 1) 1600 (match_dup 2))) 1601 (clobber (reg:CC VAX_PSL_REGNUM))])] 1602 "") 1603 1604 (define_insn "*ashldi3<ccn><ccnz><ccz>" 1605 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1606 (ashift:DI (match_operand:DI 1 "general_operand" "g") 1607 (match_operand:QI 2 "general_operand" "g"))) 1608 (clobber (reg:CC VAX_PSL_REGNUM))] 1609 "reload_completed" 1610 "ashq %2,%D1,%0") 1611 1612 (define_insn_and_split "*ashlnegdi3" 1613 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1614 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1615 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1616 "" 1617 "#" 1618 "reload_completed" 1619 [(parallel 1620 [(set (match_dup 0) 1621 (ashiftrt:DI (match_dup 1) 1622 (neg:QI (match_dup 2)))) 1623 (clobber (reg:CC VAX_PSL_REGNUM))])] 1624 "") 1625 1626 (define_insn "*ashlnegdi3_2<ccn><ccnz><ccz>" 1627 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 1628 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 1629 (neg:QI (match_operand:QI 2 "general_operand" "g")))) 1630 (clobber (reg:CC VAX_PSL_REGNUM))] 1631 "reload_completed" 1632 "ashq %2,%D1,%0") 1633 1634 ;; We used to have expand_shift handle logical right shifts by using extzv, 1635 ;; but this make it very difficult to do lshrdi3. Since the VAX is the 1636 ;; only machine with this kludge, it's better to just do this with a 1637 ;; define_expand and remove that case from expand_shift. 1638 1639 (define_expand "lshrsi3" 1640 [(set (match_dup 3) 1641 (minus:QI (const_int 32) 1642 (match_dup 4))) 1643 (set (match_operand:SI 0 "nonimmediate_operand" "=g") 1644 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 1645 (match_dup 3) 1646 (match_operand:SI 2 "register_operand" "g")))] 1647 "" 1648 " 1649 { 1650 operands[3] = gen_reg_rtx (QImode); 1651 operands[4] = gen_lowpart (QImode, operands[2]); 1652 }") 1653 1654 ;; Rotate right on the VAX works by negating the shift count. 1655 (define_expand "rotrsi3" 1656 [(set (match_operand:SI 0 "general_operand" "=g") 1657 (rotatert:SI (match_operand:SI 1 "general_operand" "g") 1658 (match_operand:QI 2 "general_operand" "g")))] 1659 "" 1660 " 1661 { 1662 if (! CONST_INT_P (operands[2])) 1663 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 1664 }") 1665 1666 (define_insn_and_split "rotlsi3" 1667 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1668 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT") 1669 (match_operand:QI 2 "general_operand" "g")))] 1670 "" 1671 "#" 1672 "reload_completed" 1673 [(parallel 1674 [(set (match_dup 0) 1675 (rotate:SI (match_dup 1) 1676 (match_dup 2))) 1677 (clobber (reg:CC VAX_PSL_REGNUM))])] 1678 "") 1679 1680 (define_insn "*rotlsi3<ccn><ccnz><ccz>" 1681 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1682 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT") 1683 (match_operand:QI 2 "general_operand" "g"))) 1684 (clobber (reg:CC VAX_PSL_REGNUM))] 1685 "reload_completed" 1686 "rotl %2,%1,%0") 1687 1688 (define_insn_and_split "*rotrsi3_const_int" 1689 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1690 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1691 (match_operand:QI 2 "const_int_operand" "n")))] 1692 "" 1693 "#" 1694 "reload_completed" 1695 [(parallel 1696 [(set (match_dup 0) 1697 (rotatert:SI (match_dup 1) 1698 (match_dup 2))) 1699 (clobber (reg:CC VAX_PSL_REGNUM))])] 1700 "") 1701 1702 (define_insn "*rotrsi3_const_int_2<ccn><ccnz><ccz>" 1703 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1704 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1705 (match_operand:QI 2 "const_int_operand" "n"))) 1706 (clobber (reg:CC VAX_PSL_REGNUM))] 1707 "reload_completed" 1708 "rotl %R2,%1,%0") 1709 1710 (define_insn_and_split "*rotrnegsi3" 1711 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1712 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1713 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 1714 "" 1715 "#" 1716 "reload_completed" 1717 [(parallel 1718 [(set (match_dup 0) 1719 (rotatert:SI (match_dup 1) 1720 (neg:QI (match_dup 2)))) 1721 (clobber (reg:CC VAX_PSL_REGNUM))])] 1722 "") 1723 1724 (define_insn "*rotrnegsi3_2<ccn><ccnz><ccz>" 1725 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1726 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 1727 (neg:QI (match_operand:QI 2 "general_operand" "g")))) 1728 (clobber (reg:CC VAX_PSL_REGNUM))] 1729 "reload_completed" 1730 "rotl %2,%1,%0") 1731 1732 ;; This insn is probably slower than a multiply and an add. 1733 ;;(define_insn_and_split "*amulsi4" 1734 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1735 ;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 1736 ;; (match_operand:SI 2 "general_operand" "g")) 1737 ;; (match_operand:SI 3 "general_operand" "g")))] 1738 ;; "" 1739 ;; "#" 1740 ;; "reload_completed" 1741 ;; [(parallel 1742 ;; [(set (match_dup 0) 1743 ;; (mult:SI (plus:SI (match_dup 1) 1744 ;; (match_dup 2)) 1745 ;; (match_dup 3))) 1746 ;; (clobber (reg:CC VAX_PSL_REGNUM))])] 1747 ;; "") 1748 ;; 1749 ;;(define_insn "*amulsi4_2<ccn><ccnz><ccz>" 1750 ;; [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1751 ;; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 1752 ;; (match_operand:SI 2 "general_operand" "g")) 1753 ;; (match_operand:SI 3 "general_operand" "g"))) 1754 ;; (clobber (reg:CC VAX_PSL_REGNUM))] 1755 ;; "reload_completed" 1756 ;; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0") 1757 1759 ;; Special cases of bit-field insns which we should 1760 ;; recognize in preference to the general case. 1761 ;; These handle aligned 8-bit and 16-bit fields 1762 ;; that can be done with move or convert instructions. 1763 1764 (define_insn_and_split "*insv_aligned" 1765 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 1766 (match_operand:QI 1 "const_int_operand" "n") 1767 (match_operand:SI 2 "const_int_operand" "n")) 1768 (match_operand:SI 3 "general_operand" "g"))] 1769 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 1770 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 1771 && (!MEM_P (operands[0]) 1772 || ((!flag_pic 1773 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0), 1774 true, true)) 1775 && !mode_dependent_address_p (XEXP (operands[0], 0), 1776 MEM_ADDR_SPACE (operands[0])))) 1777 && (!(REG_P (operands[0]) 1778 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0])))) 1779 || INTVAL (operands[2]) == 0)" 1780 "#" 1781 "&& reload_completed" 1782 [(parallel 1783 [(set (zero_extract:SI (match_dup 0) 1784 (match_dup 1) 1785 (match_dup 2)) 1786 (match_dup 3)) 1787 (clobber (reg:CC VAX_PSL_REGNUM))])] 1788 "") 1789 1790 (define_insn "*insv_aligned_2<ccn><ccnz><ccz>" 1791 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 1792 (match_operand:QI 1 "const_int_operand" "n") 1793 (match_operand:SI 2 "const_int_operand" "n")) 1794 (match_operand:SI 3 "general_operand" "g")) 1795 (clobber (reg:CC VAX_PSL_REGNUM))] 1796 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 1797 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 1798 && (!MEM_P (operands[0]) 1799 || ((!flag_pic 1800 || vax_acceptable_pic_operand_p (XEXP (operands[0], 0), 1801 true, true)) 1802 && !mode_dependent_address_p (XEXP (operands[0], 0), 1803 MEM_ADDR_SPACE (operands[0])))) 1804 && (!(REG_P (operands[0]) 1805 || (SUBREG_P (operands[0]) && REG_P (SUBREG_REG (operands[0])))) 1806 || INTVAL (operands[2]) == 0) 1807 && reload_completed" 1808 "* 1809 { 1810 if (!REG_P (operands[0])) 1811 operands[0] 1812 = adjust_address (operands[0], 1813 INTVAL (operands[1]) == 8 ? QImode : HImode, 1814 INTVAL (operands[2]) / 8); 1815 else 1816 gcc_assert (INTVAL (operands[2]) == 0); 1817 1818 if (INTVAL (operands[1]) == 8) 1819 return \"movb %3,%0\"; 1820 return \"movw %3,%0\"; 1821 }") 1822 1823 (define_insn_and_split "*extzv_aligned" 1824 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1825 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1826 (match_operand:QI 2 "const_int_operand" "n") 1827 (match_operand:SI 3 "const_int_operand" "n")))] 1828 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1829 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1830 && (!MEM_P (operands[1]) 1831 || ((!flag_pic 1832 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1833 true, true)) 1834 && !mode_dependent_address_p (XEXP (operands[1], 0), 1835 MEM_ADDR_SPACE (operands[1])))) 1836 && (!(REG_P (operands[1]) 1837 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1838 || INTVAL (operands[3]) == 0)" 1839 "#" 1840 "&& reload_completed" 1841 [(parallel 1842 [(set (match_dup 0) 1843 (zero_extract:SI (match_dup 1) 1844 (match_dup 2) 1845 (match_dup 3))) 1846 (clobber (reg:CC VAX_PSL_REGNUM))])] 1847 "") 1848 1849 (define_insn "*extzv_aligned_2<ccn><ccnz><ccz>" 1850 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1851 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1852 (match_operand:QI 2 "const_int_operand" "n") 1853 (match_operand:SI 3 "const_int_operand" "n"))) 1854 (clobber (reg:CC VAX_PSL_REGNUM))] 1855 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1856 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1857 && (!MEM_P (operands[1]) 1858 || ((!flag_pic 1859 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1860 true, true)) 1861 && !mode_dependent_address_p (XEXP (operands[1], 0), 1862 MEM_ADDR_SPACE (operands[1])))) 1863 && (!(REG_P (operands[1]) 1864 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1865 || INTVAL (operands[3]) == 0) 1866 && reload_completed" 1867 "* 1868 { 1869 if (!REG_P (operands[1])) 1870 operands[1] 1871 = adjust_address (operands[1], 1872 INTVAL (operands[2]) == 8 ? QImode : HImode, 1873 INTVAL (operands[3]) / 8); 1874 else 1875 gcc_assert (INTVAL (operands[3]) == 0); 1876 1877 if (INTVAL (operands[2]) == 8) 1878 return \"movzbl %1,%0\"; 1879 return \"movzwl %1,%0\"; 1880 }") 1881 1882 (define_insn_and_split "*extv_aligned" 1883 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1884 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1885 (match_operand:QI 2 "const_int_operand" "n") 1886 (match_operand:SI 3 "const_int_operand" "n")))] 1887 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1888 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1889 && (!MEM_P (operands[1]) 1890 || ((!flag_pic 1891 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1892 true, true)) 1893 && !mode_dependent_address_p (XEXP (operands[1], 0), 1894 MEM_ADDR_SPACE (operands[1])))) 1895 && (!(REG_P (operands[1]) 1896 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1897 || INTVAL (operands[3]) == 0)" 1898 "#" 1899 "&& reload_completed" 1900 [(parallel 1901 [(set (match_dup 0) 1902 (sign_extract:SI (match_dup 1) 1903 (match_dup 2) 1904 (match_dup 3))) 1905 (clobber (reg:CC VAX_PSL_REGNUM))])] 1906 "") 1907 1908 (define_insn "*extv_aligned_2<ccn><ccnz><ccz>" 1909 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1910 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1911 (match_operand:QI 2 "const_int_operand" "n") 1912 (match_operand:SI 3 "const_int_operand" "n"))) 1913 (clobber (reg:CC VAX_PSL_REGNUM))] 1914 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1915 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 1916 && (!MEM_P (operands[1]) 1917 || ((!flag_pic 1918 || vax_acceptable_pic_operand_p (XEXP (operands[1], 0), 1919 true, true)) 1920 && !mode_dependent_address_p (XEXP (operands[1], 0), 1921 MEM_ADDR_SPACE (operands[1])))) 1922 && (!(REG_P (operands[1]) 1923 || (SUBREG_P (operands[1]) && REG_P (SUBREG_REG (operands[1])))) 1924 || INTVAL (operands[3]) == 0) 1925 && reload_completed" 1926 "* 1927 { 1928 if (!REG_P (operands[1])) 1929 operands[1] 1930 = adjust_address (operands[1], 1931 INTVAL (operands[2]) == 8 ? QImode : HImode, 1932 INTVAL (operands[3]) / 8); 1933 else 1934 gcc_assert (INTVAL (operands[3]) == 0); 1935 1936 if (INTVAL (operands[2]) == 8) 1937 return \"cvtbl %1,%0\"; 1938 return \"cvtwl %1,%0\"; 1939 }") 1940 1942 ;; Register and non-offsettable-memory SImode cases of bit-field insns. 1943 1944 (define_insn "*cmpv_<mode>" 1945 [(set (reg:VAXcc VAX_PSL_REGNUM) 1946 (compare:VAXcc 1947 (sign_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro") 1948 (match_operand:QI 1 "general_operand" "g") 1949 (match_operand:SI 2 "general_operand" "nrmT")) 1950 (match_operand:SI 3 "general_operand" "nrmT")))] 1951 "reload_completed" 1952 "cmpv %2,%1,%0,%3") 1953 1954 (define_insn "*cmpzv_<mode>" 1955 [(set (reg:VAXcc VAX_PSL_REGNUM) 1956 (compare:VAXcc 1957 (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "ro") 1958 (match_operand:QI 1 "general_operand" "g") 1959 (match_operand:SI 2 "general_operand" "nrmT")) 1960 (match_operand:SI 3 "general_operand" "nrmT")))] 1961 "reload_completed" 1962 "cmpzv %2,%1,%0,%3") 1963 1964 ;; When the field position and size are constant and the destination 1965 ;; is a register, extv and extzv are much slower than a rotate followed 1966 ;; by a bicl or sign extension. Because we might end up choosing ext[z]v 1967 ;; anyway, we can't allow immediate values for the primary source operand. 1968 1969 (define_insn_and_split "*extv_non_const" 1970 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1971 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1972 (match_operand:QI 2 "general_operand" "g") 1973 (match_operand:SI 3 "general_operand" "nrmT")))] 1974 "" 1975 "#" 1976 "reload_completed" 1977 [(parallel 1978 [(set (match_dup 0) 1979 (sign_extract:SI (match_dup 1) 1980 (match_dup 2) 1981 (match_dup 3))) 1982 (clobber (reg:CC VAX_PSL_REGNUM))])] 1983 "") 1984 1985 (define_insn "*extv_non_const_2<ccn><ccnz><ccz>" 1986 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1987 (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 1988 (match_operand:QI 2 "general_operand" "g") 1989 (match_operand:SI 3 "general_operand" "nrmT"))) 1990 (clobber (reg:CC VAX_PSL_REGNUM))] 1991 "reload_completed" 1992 "* 1993 { 1994 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2]) 1995 || ! REG_P (operands[0]) 1996 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)) 1997 return \"extv %3,%2,%1,%0\"; 1998 if (INTVAL (operands[2]) == 8) 1999 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 2000 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 2001 }") 2002 2003 (define_insn_and_split "*extzv_non_const" 2004 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2005 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 2006 (match_operand:QI 2 "general_operand" "g") 2007 (match_operand:SI 3 "general_operand" "nrmT")))] 2008 "" 2009 "#" 2010 "reload_completed" 2011 [(parallel 2012 [(set (match_dup 0) 2013 (zero_extract:SI (match_dup 1) 2014 (match_dup 2) 2015 (match_dup 3))) 2016 (clobber (reg:CC VAX_PSL_REGNUM))])] 2017 "") 2018 2019 (define_insn "*extzv_non_const_2<ccn><ccnz><ccz>" 2020 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2021 (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "ro") 2022 (match_operand:QI 2 "general_operand" "g") 2023 (match_operand:SI 3 "general_operand" "nrmT"))) 2024 (clobber (reg:CC VAX_PSL_REGNUM))] 2025 "reload_completed" 2026 "* 2027 { 2028 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2]) 2029 || ! REG_P (operands[0])) 2030 return \"extzv %3,%2,%1,%0\"; 2031 if (INTVAL (operands[2]) == 8) 2032 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 2033 if (INTVAL (operands[2]) == 16) 2034 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 2035 if (INTVAL (operands[3]) & 31) 2036 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 2037 if (rtx_equal_p (operands[0], operands[1])) 2038 { 2039 if (INTVAL (operands[2]) == 32) 2040 return \"\"; /* no-op */ 2041 else 2042 return \"bicl2 %M2,%0\"; 2043 } 2044 if (INTVAL (operands[2]) == 32) 2045 return \"movl %1,%0\"; 2046 return \"bicl3 %M2,%1,%0\"; 2047 }") 2048 2049 ;; Non-register cases. 2050 ;; nonimmediate_operand is used to make sure that mode-ambiguous cases 2051 ;; don't match these (and therefore match the cases above instead). 2052 2053 (define_insn "*cmpv_2_<mode>" 2054 [(set (reg:VAXcc VAX_PSL_REGNUM) 2055 (compare:VAXcc 2056 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m") 2057 (match_operand:QI 1 "general_operand" "g") 2058 (match_operand:SI 2 "general_operand" "nrmT")) 2059 (match_operand:SI 3 "general_operand" "nrmT")))] 2060 "reload_completed" 2061 "cmpv %2,%1,%0,%3") 2062 2063 (define_insn "*cmpzv_2_<mode>" 2064 [(set (reg:VAXcc VAX_PSL_REGNUM) 2065 (compare:VAXcc 2066 (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") 2067 (match_operand:QI 1 "general_operand" "g") 2068 (match_operand:SI 2 "general_operand" "nrmT")) 2069 (match_operand:SI 3 "general_operand" "nrmT")))] 2070 "reload_completed" 2071 "cmpzv %2,%1,%0,%3") 2072 2073 (define_expand "extv" 2074 [(set (match_operand:SI 0 "general_operand" "") 2075 (sign_extract:SI (match_operand:SI 1 "general_operand" "") 2076 (match_operand:QI 2 "general_operand" "") 2077 (match_operand:SI 3 "general_operand" "")))] 2078 "" 2079 "") 2080 2081 (define_insn_and_split "*extv" 2082 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2083 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") 2084 (match_operand:QI 2 "general_operand" "g") 2085 (match_operand:SI 3 "general_operand" "nrmT")))] 2086 "" 2087 "#" 2088 "reload_completed" 2089 [(parallel 2090 [(set (match_dup 0) 2091 (sign_extract:SI (match_dup 1) 2092 (match_dup 2) 2093 (match_dup 3))) 2094 (clobber (reg:CC VAX_PSL_REGNUM))])] 2095 "") 2096 2097 (define_insn "*extv_2<ccn><ccnz><ccz>" 2098 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2099 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") 2100 (match_operand:QI 2 "general_operand" "g") 2101 (match_operand:SI 3 "general_operand" "nrmT"))) 2102 (clobber (reg:CC VAX_PSL_REGNUM))] 2103 "reload_completed" 2104 "* 2105 { 2106 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2]) 2107 || !CONST_INT_P (operands[3]) 2108 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16) 2109 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 2110 || side_effects_p (operands[1]) 2111 || (MEM_P (operands[1]) 2112 && mode_dependent_address_p (XEXP (operands[1], 0), 2113 MEM_ADDR_SPACE (operands[1])))) 2114 return \"extv %3,%2,%1,%0\"; 2115 if (INTVAL (operands[2]) == 8) 2116 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 2117 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 2118 }") 2119 2120 (define_expand "extzv" 2121 [(set (match_operand:SI 0 "general_operand" "") 2122 (zero_extract:SI (match_operand:SI 1 "general_operand" "") 2123 (match_operand:QI 2 "general_operand" "") 2124 (match_operand:SI 3 "general_operand" "")))] 2125 "" 2126 "") 2127 2128 (define_insn_and_split "*extzv" 2129 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2130 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") 2131 (match_operand:QI 2 "general_operand" "g") 2132 (match_operand:SI 3 "general_operand" "nrmT")))] 2133 "" 2134 "#" 2135 "reload_completed" 2136 [(parallel 2137 [(set (match_dup 0) 2138 (zero_extract:SI (match_dup 1) 2139 (match_dup 2) 2140 (match_dup 3))) 2141 (clobber (reg:CC VAX_PSL_REGNUM))])] 2142 "") 2143 2144 (define_insn "*extzv_2<ccn><ccnz><ccz>" 2145 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 2146 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") 2147 (match_operand:QI 2 "general_operand" "g") 2148 (match_operand:SI 3 "general_operand" "nrmT"))) 2149 (clobber (reg:CC VAX_PSL_REGNUM))] 2150 "reload_completed" 2151 "* 2152 { 2153 if (!REG_P (operands[0]) || !CONST_INT_P (operands[2]) 2154 || !CONST_INT_P (operands[3]) 2155 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 2156 || side_effects_p (operands[1]) 2157 || (MEM_P (operands[1]) 2158 && mode_dependent_address_p (XEXP (operands[1], 0), 2159 MEM_ADDR_SPACE (operands[1])))) 2160 return \"extzv %3,%2,%1,%0\"; 2161 if (INTVAL (operands[2]) == 8) 2162 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 2163 if (INTVAL (operands[2]) == 16) 2164 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 2165 if (MEM_P (operands[1]) 2166 && GET_CODE (XEXP (operands[1], 0)) == PLUS 2167 && REG_P (XEXP (XEXP (operands[1], 0), 0)) 2168 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)) 2169 && CONST_INT_P (operands[2]) 2170 && CONST_INT_P (operands[3])) 2171 { 2172 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 2173 HOST_WIDE_INT l = INTVAL (operands[2]); 2174 HOST_WIDE_INT v = INTVAL (operands[3]); 2175 if ((o & 3) && (o & 3) * 8 + v + l <= 32) 2176 { 2177 rtx tmp; 2178 tmp = XEXP (XEXP (operands[1], 0), 0); 2179 if (o & ~3) 2180 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3)); 2181 operands[1] = gen_rtx_MEM (QImode, tmp); 2182 operands[3] = GEN_INT (v + (o & 3) * 8); 2183 } 2184 if (optimize_size) 2185 return \"extzv %3,%2,%1,%0\"; 2186 } 2187 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 2188 }") 2189 2190 ;; Combine EXTV/CMPL and EXTZV/CMPL sequences where the output of 2191 ;; extraction is used for the comparison only into CMPV and CMPZV 2192 ;; respectively. 2193 (define_peephole2 2194 [(parallel 2195 [(set (match_operand:SI 0 "register_operand") 2196 (any_extract:SI (match_operand 1 "general_operand") 2197 (match_operand:QI 2 "general_operand") 2198 (match_operand:SI 3 "general_operand"))) 2199 (clobber (reg:CC VAX_PSL_REGNUM))]) 2200 (set (reg:VAXcc VAX_PSL_REGNUM) 2201 (compare:VAXcc (match_dup 0) 2202 (match_operand:SI 4 "general_operand")))] 2203 "peep2_reg_dead_p (2, operands[0])" 2204 [(set (reg:VAXcc VAX_PSL_REGNUM) 2205 (compare:VAXcc 2206 (any_extract:SI (match_dup 1) 2207 (match_dup 2) 2208 (match_dup 3)) 2209 (match_dup 4)))] 2210 "") 2211 2212 (define_expand "insv" 2213 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") 2214 (match_operand:QI 1 "general_operand" "") 2215 (match_operand:SI 2 "general_operand" "")) 2216 (match_operand:SI 3 "general_operand" ""))] 2217 "" 2218 "") 2219 2220 ;; This one actually doesn't change CC. 2221 (define_insn "*insv" 2222 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") 2223 (match_operand:QI 1 "general_operand" "g") 2224 (match_operand:SI 2 "general_operand" "nrmT")) 2225 (match_operand:SI 3 "general_operand" "nrmT"))] 2226 "" 2227 "* 2228 { 2229 if (MEM_P (operands[0]) 2230 && GET_CODE (XEXP (operands[0], 0)) == PLUS 2231 && REG_P (XEXP (XEXP (operands[0], 0), 0)) 2232 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)) 2233 && CONST_INT_P (operands[1]) 2234 && CONST_INT_P (operands[2])) 2235 { 2236 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 2237 HOST_WIDE_INT v = INTVAL (operands[2]); 2238 HOST_WIDE_INT l = INTVAL (operands[1]); 2239 if ((o & 3) && (o & 3) * 8 + v + l <= 32) 2240 { 2241 rtx tmp; 2242 tmp = XEXP (XEXP (operands[0], 0), 0); 2243 if (o & ~3) 2244 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3)); 2245 operands[0] = gen_rtx_MEM (QImode, tmp); 2246 operands[2] = GEN_INT (v + (o & 3) * 8); 2247 } 2248 } 2249 return \"insv %3,%2,%1,%0\"; 2250 }") 2251 2252 ;; This one actually doesn't change CC. 2253 (define_insn "*insv_2" 2254 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+ro") 2255 (match_operand:QI 1 "general_operand" "g") 2256 (match_operand:SI 2 "general_operand" "nrmT")) 2257 (match_operand:SI 3 "general_operand" "nrmT"))] 2258 "" 2259 "insv %3,%2,%1,%0") 2260 2262 ;; Unconditional jump 2263 (define_insn "jump" 2264 [(set (pc) 2265 (label_ref (match_operand 0 "" "")))] 2266 "" 2267 "jbr %l0") 2268 2269 ;; Conditional jumps 2270 2271 (define_expand "cbranch<mode>4" 2272 [(set (pc) 2273 (if_then_else 2274 (match_operator 0 "ordered_comparison_operator" 2275 [(match_operand:VAXint 1 "general_operand" "") 2276 (match_operand:VAXint 2 "general_operand" "")]) 2277 (label_ref (match_operand 3 "" "")) 2278 (pc)))] 2279 "" 2280 "") 2281 2282 (define_insn_and_split "*cbranch<VAXint:mode>4_<VAXcc:mode>" 2283 [(set (pc) 2284 (if_then_else 2285 (match_operator 0 "vax_<VAXcc:mode>_comparison_operator" 2286 [(match_operand:VAXint 1 "general_operand" "nrmT") 2287 (match_operand:VAXint 2 "general_operand" "nrmT")]) 2288 (label_ref (match_operand 3 "" "")) 2289 (pc)))] 2290 "" 2291 "#" 2292 "reload_completed" 2293 [(set (reg:VAXcc VAX_PSL_REGNUM) 2294 (compare:VAXcc (match_dup 1) (match_dup 2))) 2295 (set (pc) 2296 (if_then_else 2297 (match_op_dup 0 [(reg:VAXcc VAX_PSL_REGNUM) 2298 (const_int 0)]) 2299 (label_ref (match_operand 3 "" "")) 2300 (pc)))] 2301 "") 2302 2303 (define_expand "cbranch<mode>4" 2304 [(set (pc) 2305 (if_then_else 2306 (match_operator 0 "ordered_comparison_operator" 2307 [(match_operand:VAXfp 1 "general_operand" "") 2308 (match_operand:VAXfp 2 "general_operand" "")]) 2309 (label_ref (match_operand 3 "" "")) 2310 (pc)))] 2311 "" 2312 "") 2313 2314 (define_insn_and_split "*cbranch<VAXfp:mode>4_<VAXccnz:mode>" 2315 [(set (pc) 2316 (if_then_else 2317 (match_operator 0 "vax_<VAXccnz:mode>_comparison_operator" 2318 [(match_operand:VAXfp 1 "general_operand" "gF") 2319 (match_operand:VAXfp 2 "general_operand" "gF")]) 2320 (label_ref (match_operand 3 "" "")) 2321 (pc)))] 2322 "" 2323 "#" 2324 "reload_completed" 2325 [(set (reg:VAXccnz VAX_PSL_REGNUM) 2326 (compare:VAXccnz (match_dup 1) (match_dup 2))) 2327 (set (pc) 2328 (if_then_else 2329 (match_op_dup 0 [(reg:VAXccnz VAX_PSL_REGNUM) 2330 (const_int 0)]) 2331 (label_ref (match_operand 3 "" "")) 2332 (pc)))] 2333 "") 2334 2335 (define_insn "*branch_<mode>" 2336 [(set (pc) 2337 (if_then_else (match_operator 0 "vax_<mode>_comparison_operator" 2338 [(reg:VAXcc VAX_PSL_REGNUM) 2339 (const_int 0)]) 2340 (label_ref (match_operand 1 "" "")) 2341 (pc)))] 2342 "reload_completed" 2343 "j%k0 %l1") 2344 2345 ;; Recognize reversed jumps. 2346 (define_insn "*branch_<mode>_reversed" 2347 [(set (pc) 2348 (if_then_else (match_operator 0 "vax_<mode>_comparison_operator" 2349 [(reg:VAXcc VAX_PSL_REGNUM) 2350 (const_int 0)]) 2351 (pc) 2352 (label_ref (match_operand 1 "" ""))))] 2353 "reload_completed" 2354 "j%K0 %l1") ; %K0 negates condition 2355 2357 ;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand 2358 ;; of jlbs and jlbc insns are SImode in the hardware. However, if it is 2359 ;; memory, we use QImode in the insn. So we can't use those instructions 2360 ;; for mode-dependent addresses. 2361 2362 (define_insn "" 2363 [(set (pc) 2364 (if_then_else 2365 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 2366 (const_int 1) 2367 (match_operand:SI 1 "general_operand" "I,nrmT")) 2368 (const_int 0)) 2369 (label_ref (match_operand 2 "" "")) 2370 (pc)))] 2371 "" 2372 "@ 2373 jlbs %0,%l2 2374 jbs %1,%0,%l2") 2375 2376 (define_insn "" 2377 [(set (pc) 2378 (if_then_else 2379 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 2380 (const_int 1) 2381 (match_operand:SI 1 "general_operand" "I,nrmT")) 2382 (const_int 0)) 2383 (label_ref (match_operand 2 "" "")) 2384 (pc)))] 2385 "" 2386 "@ 2387 jlbc %0,%l2 2388 jbc %1,%0,%l2") 2389 2390 (define_insn "" 2391 [(set (pc) 2392 (if_then_else 2393 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 2394 (const_int 1) 2395 (match_operand:SI 1 "general_operand" "I,nrmT")) 2396 (const_int 0)) 2397 (label_ref (match_operand 2 "" "")) 2398 (pc)))] 2399 "" 2400 "@ 2401 jlbs %0,%l2 2402 jbs %1,%0,%l2") 2403 2404 (define_insn "" 2405 [(set (pc) 2406 (if_then_else 2407 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 2408 (const_int 1) 2409 (match_operand:SI 1 "general_operand" "I,nrmT")) 2410 (const_int 0)) 2411 (label_ref (match_operand 2 "" "")) 2412 (pc)))] 2413 "" 2414 "@ 2415 jlbc %0,%l2 2416 jbc %1,%0,%l2") 2417 2419 ;; Subtract-and-jump and Add-and-jump insns. 2420 ;; These are not used when output is for the Unix assembler 2421 ;; because it does not know how to modify them to reach far. 2422 2423 ;; Normal sob insns. 2424 2425 (define_insn_and_split "*jsobgtr" 2426 [(set (pc) 2427 (if_then_else 2428 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2429 (const_int -1)) 2430 (const_int 0)) 2431 (label_ref (match_operand 1 "" "")) 2432 (pc))) 2433 (set (match_dup 0) 2434 (plus:SI (match_dup 0) 2435 (const_int -1)))] 2436 "!TARGET_UNIX_ASM" 2437 "#" 2438 "&& reload_completed" 2439 [(parallel 2440 [(set (pc) 2441 (if_then_else 2442 (gt (plus:SI (match_dup 0) 2443 (const_int -1)) 2444 (const_int 0)) 2445 (label_ref (match_dup 1)) 2446 (pc))) 2447 (set (match_dup 0) 2448 (plus:SI (match_dup 0) 2449 (const_int -1))) 2450 (clobber (reg:CC VAX_PSL_REGNUM))])] 2451 "") 2452 2453 (define_insn "*jsobgtr_2" 2454 [(set (pc) 2455 (if_then_else 2456 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2457 (const_int -1)) 2458 (const_int 0)) 2459 (label_ref (match_operand 1 "" "")) 2460 (pc))) 2461 (set (match_dup 0) 2462 (plus:SI (match_dup 0) 2463 (const_int -1))) 2464 (clobber (reg:CC VAX_PSL_REGNUM))] 2465 "!TARGET_UNIX_ASM && reload_completed" 2466 "jsobgtr %0,%l1") 2467 2468 (define_insn_and_split "*jsobgeq" 2469 [(set (pc) 2470 (if_then_else 2471 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2472 (const_int -1)) 2473 (const_int 0)) 2474 (label_ref (match_operand 1 "" "")) 2475 (pc))) 2476 (set (match_dup 0) 2477 (plus:SI (match_dup 0) 2478 (const_int -1)))] 2479 "!TARGET_UNIX_ASM" 2480 "#" 2481 "&& reload_completed" 2482 [(parallel 2483 [(set (pc) 2484 (if_then_else 2485 (ge (plus:SI (match_dup 0) 2486 (const_int -1)) 2487 (const_int 0)) 2488 (label_ref (match_dup 1)) 2489 (pc))) 2490 (set (match_dup 0) 2491 (plus:SI (match_dup 0) 2492 (const_int -1))) 2493 (clobber (reg:CC VAX_PSL_REGNUM))])] 2494 "") 2495 2496 (define_insn "*jsobgeq_2" 2497 [(set (pc) 2498 (if_then_else 2499 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2500 (const_int -1)) 2501 (const_int 0)) 2502 (label_ref (match_operand 1 "" "")) 2503 (pc))) 2504 (set (match_dup 0) 2505 (plus:SI (match_dup 0) 2506 (const_int -1))) 2507 (clobber (reg:CC VAX_PSL_REGNUM))] 2508 "!TARGET_UNIX_ASM && reload_completed" 2509 "jsobgeq %0,%l1") 2510 2511 ;; Normal aob insns. Define a version for when operands[1] is a constant. 2512 (define_insn_and_split "*jaoblss" 2513 [(set (pc) 2514 (if_then_else 2515 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2516 (const_int 1)) 2517 (match_operand:SI 1 "general_operand" "nrmT")) 2518 (label_ref (match_operand 2 "" "")) 2519 (pc))) 2520 (set (match_dup 0) 2521 (plus:SI (match_dup 0) 2522 (const_int 1)))] 2523 "!TARGET_UNIX_ASM" 2524 "#" 2525 "&& reload_completed" 2526 [(parallel 2527 [(set (pc) 2528 (if_then_else 2529 (lt (plus:SI (match_dup 0) 2530 (const_int 1)) 2531 (match_dup 1)) 2532 (label_ref (match_dup 2)) 2533 (pc))) 2534 (set (match_dup 0) 2535 (plus:SI (match_dup 0) 2536 (const_int 1))) 2537 (clobber (reg:CC VAX_PSL_REGNUM))])] 2538 "") 2539 2540 (define_insn "*jaoblss_2" 2541 [(set (pc) 2542 (if_then_else 2543 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2544 (const_int 1)) 2545 (match_operand:SI 1 "general_operand" "nrmT")) 2546 (label_ref (match_operand 2 "" "")) 2547 (pc))) 2548 (set (match_dup 0) 2549 (plus:SI (match_dup 0) 2550 (const_int 1))) 2551 (clobber (reg:CC VAX_PSL_REGNUM))] 2552 "!TARGET_UNIX_ASM && reload_completed" 2553 "jaoblss %1,%0,%l2") 2554 2555 (define_insn_and_split "*jaoblss_const" 2556 [(set (pc) 2557 (if_then_else 2558 (lt (match_operand:SI 0 "nonimmediate_operand" "+g") 2559 (match_operand:SI 1 "general_operand" "nrmT")) 2560 (label_ref (match_operand 2 "" "")) 2561 (pc))) 2562 (set (match_dup 0) 2563 (plus:SI (match_dup 0) 2564 (const_int 1)))] 2565 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])" 2566 "#" 2567 "&& reload_completed" 2568 [(parallel 2569 [(set (pc) 2570 (if_then_else 2571 (lt (match_dup 0) 2572 (match_dup 1)) 2573 (label_ref (match_dup 2)) 2574 (pc))) 2575 (set (match_dup 0) 2576 (plus:SI (match_dup 0) 2577 (const_int 1))) 2578 (clobber (reg:CC VAX_PSL_REGNUM))])] 2579 "") 2580 2581 (define_insn "*jaoblss_const_2" 2582 [(set (pc) 2583 (if_then_else 2584 (lt (match_operand:SI 0 "nonimmediate_operand" "+g") 2585 (match_operand:SI 1 "general_operand" "nrmT")) 2586 (label_ref (match_operand 2 "" "")) 2587 (pc))) 2588 (set (match_dup 0) 2589 (plus:SI (match_dup 0) 2590 (const_int 1))) 2591 (clobber (reg:CC VAX_PSL_REGNUM))] 2592 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed" 2593 "jaoblss %P1,%0,%l2") 2594 2595 (define_insn_and_split "*jaobleq" 2596 [(set (pc) 2597 (if_then_else 2598 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2599 (const_int 1)) 2600 (match_operand:SI 1 "general_operand" "nrmT")) 2601 (label_ref (match_operand 2 "" "")) 2602 (pc))) 2603 (set (match_dup 0) 2604 (plus:SI (match_dup 0) 2605 (const_int 1)))] 2606 "!TARGET_UNIX_ASM" 2607 "#" 2608 "&& reload_completed" 2609 [(parallel 2610 [(set (pc) 2611 (if_then_else 2612 (le (plus:SI (match_dup 0) 2613 (const_int 1)) 2614 (match_dup 1)) 2615 (label_ref (match_dup 2)) 2616 (pc))) 2617 (set (match_dup 0) 2618 (plus:SI (match_dup 0) 2619 (const_int 1))) 2620 (clobber (reg:CC VAX_PSL_REGNUM))])] 2621 "") 2622 2623 (define_insn "*jaobleq_2" 2624 [(set (pc) 2625 (if_then_else 2626 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 2627 (const_int 1)) 2628 (match_operand:SI 1 "general_operand" "nrmT")) 2629 (label_ref (match_operand 2 "" "")) 2630 (pc))) 2631 (set (match_dup 0) 2632 (plus:SI (match_dup 0) 2633 (const_int 1))) 2634 (clobber (reg:CC VAX_PSL_REGNUM))] 2635 "!TARGET_UNIX_ASM && reload_completed" 2636 "jaobleq %1,%0,%l2") 2637 2638 (define_insn_and_split "*jaobleq_const" 2639 [(set (pc) 2640 (if_then_else 2641 (le (match_operand:SI 0 "nonimmediate_operand" "+g") 2642 (match_operand:SI 1 "general_operand" "nrmT")) 2643 (label_ref (match_operand 2 "" "")) 2644 (pc))) 2645 (set (match_dup 0) 2646 (plus:SI (match_dup 0) 2647 (const_int 1)))] 2648 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])" 2649 "#" 2650 "&& reload_completed" 2651 [(parallel 2652 [(set (pc) 2653 (if_then_else 2654 (le (match_dup 0) 2655 (match_dup 1)) 2656 (label_ref (match_dup 2)) 2657 (pc))) 2658 (set (match_dup 0) 2659 (plus:SI (match_dup 0) 2660 (const_int 1))) 2661 (clobber (reg:CC VAX_PSL_REGNUM))])] 2662 "") 2663 2664 (define_insn "*jaobleq_const_2" 2665 [(set (pc) 2666 (if_then_else 2667 (le (match_operand:SI 0 "nonimmediate_operand" "+g") 2668 (match_operand:SI 1 "general_operand" "nrmT")) 2669 (label_ref (match_operand 2 "" "")) 2670 (pc))) 2671 (set (match_dup 0) 2672 (plus:SI (match_dup 0) 2673 (const_int 1))) 2674 (clobber (reg:CC VAX_PSL_REGNUM))] 2675 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1]) && reload_completed" 2676 "jaobleq %P1,%0,%l2") 2677 2678 ;; Something like a sob insn, but compares against -1. 2679 ;; This finds `while (foo--)' which was changed to `while (--foo != -1)'. 2680 2681 (define_insn_and_split "*jsobneq_minus_one" 2682 [(set (pc) 2683 (if_then_else 2684 (ne (match_operand:SI 0 "nonimmediate_operand" "+g") 2685 (const_int 0)) 2686 (label_ref (match_operand 1 "" "")) 2687 (pc))) 2688 (set (match_dup 0) 2689 (plus:SI (match_dup 0) 2690 (const_int -1)))] 2691 "" 2692 "#" 2693 "reload_completed" 2694 [(parallel 2695 [(set (pc) 2696 (if_then_else 2697 (ne (match_dup 0) 2698 (const_int 0)) 2699 (label_ref (match_dup 1)) 2700 (pc))) 2701 (set (match_dup 0) 2702 (plus:SI (match_dup 0) 2703 (const_int -1))) 2704 (clobber (reg:CC VAX_PSL_REGNUM))])] 2705 "") 2706 2707 (define_insn "*jsobneq_minus_one_2" 2708 [(set (pc) 2709 (if_then_else 2710 (ne (match_operand:SI 0 "nonimmediate_operand" "+g") 2711 (const_int 0)) 2712 (label_ref (match_operand 1 "" "")) 2713 (pc))) 2714 (set (match_dup 0) 2715 (plus:SI (match_dup 0) 2716 (const_int -1))) 2717 (clobber (reg:CC VAX_PSL_REGNUM))] 2718 "reload_completed" 2719 "decl %0\;jgequ %l1") 2720 2722 (define_expand "call_pop" 2723 [(parallel [(call (match_operand:QI 0 "memory_operand" "") 2724 (match_operand:SI 1 "const_int_operand" "")) 2725 (set (reg:SI VAX_SP_REGNUM) 2726 (plus:SI (reg:SI VAX_SP_REGNUM) 2727 (match_operand:SI 3 "immediate_operand" "")))])] 2728 "" 2729 { 2730 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0); 2731 2732 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size 2733 during EH unwinding. We must include the argument count pushed by 2734 the calls instruction. */ 2735 operands[1] = GEN_INT (INTVAL (operands[3]) + 4); 2736 }) 2737 2738 (define_insn "*call_pop" 2739 [(call (match_operand:QI 0 "memory_operand" "m") 2740 (match_operand:SI 1 "const_int_operand" "n")) 2741 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM) 2742 (match_operand:SI 2 "immediate_operand" "i")))] 2743 "" 2744 { 2745 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4); 2746 return "calls %1,%0"; 2747 }) 2748 2749 (define_expand "call_value_pop" 2750 [(parallel [(set (match_operand 0 "" "") 2751 (call (match_operand:QI 1 "memory_operand" "") 2752 (match_operand:SI 2 "const_int_operand" ""))) 2753 (set (reg:SI VAX_SP_REGNUM) 2754 (plus:SI (reg:SI VAX_SP_REGNUM) 2755 (match_operand:SI 4 "immediate_operand" "")))])] 2756 "" 2757 { 2758 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0); 2759 2760 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 2761 during EH unwinding. We must include the argument count pushed by 2762 the calls instruction. */ 2763 operands[2] = GEN_INT (INTVAL (operands[4]) + 4); 2764 }) 2765 2766 (define_insn "*call_value_pop" 2767 [(set (match_operand 0 "" "") 2768 (call (match_operand:QI 1 "memory_operand" "m") 2769 (match_operand:SI 2 "const_int_operand" "n"))) 2770 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM) 2771 (match_operand:SI 3 "immediate_operand" "i")))] 2772 "" 2773 "* 2774 { 2775 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4); 2776 return \"calls %2,%1\"; 2777 }") 2778 2779 (define_expand "call" 2780 [(call (match_operand:QI 0 "memory_operand" "") 2781 (match_operand:SI 1 "const_int_operand" ""))] 2782 "" 2783 " 2784 { 2785 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size 2786 during EH unwinding. We must include the argument count pushed by 2787 the calls instruction. */ 2788 operands[1] = GEN_INT (INTVAL (operands[1]) + 4); 2789 }") 2790 2791 (define_insn "*call" 2792 [(call (match_operand:QI 0 "memory_operand" "m") 2793 (match_operand:SI 1 "const_int_operand" ""))] 2794 "" 2795 "calls $0,%0") 2796 2797 (define_expand "call_value" 2798 [(set (match_operand 0 "" "") 2799 (call (match_operand:QI 1 "memory_operand" "") 2800 (match_operand:SI 2 "const_int_operand" "")))] 2801 "" 2802 " 2803 { 2804 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 2805 during EH unwinding. We must include the argument count pushed by 2806 the calls instruction. */ 2807 operands[2] = GEN_INT (INTVAL (operands[2]) + 4); 2808 }") 2809 2810 (define_insn "*call_value" 2811 [(set (match_operand 0 "" "") 2812 (call (match_operand:QI 1 "memory_operand" "m") 2813 (match_operand:SI 2 "const_int_operand" "")))] 2814 "" 2815 "calls $0,%1") 2816 2817 ;; Call subroutine returning any type. 2818 2819 (define_expand "untyped_call" 2820 [(parallel [(call (match_operand 0 "" "") 2821 (const_int 0)) 2822 (match_operand 1 "" "") 2823 (match_operand 2 "" "")])] 2824 "" 2825 " 2826 { 2827 int i; 2828 2829 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx)); 2830 2831 for (i = 0; i < XVECLEN (operands[2], 0); i++) 2832 { 2833 rtx set = XVECEXP (operands[2], 0, i); 2834 emit_move_insn (SET_DEST (set), SET_SRC (set)); 2835 } 2836 2837 /* The optimizer does not know that the call sets the function value 2838 registers we stored in the result block. We avoid problems by 2839 claiming that all hard registers are used and clobbered at this 2840 point. */ 2841 emit_insn (gen_blockage ()); 2842 2843 DONE; 2844 }") 2845 2846 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2847 ;; all of memory. This blocks insns from being moved across this point. 2848 2849 (define_insn "blockage" 2850 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)] 2851 "" 2852 "") 2853 2854 (define_insn "procedure_entry_mask" 2855 [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)] 2856 "" 2857 ".word %x0") 2858 2859 (define_insn "return" 2860 [(return)] 2861 "" 2862 "ret") 2863 2864 (define_expand "prologue" 2865 [(const_int 0)] 2866 "" 2867 { 2868 vax_expand_prologue (); 2869 DONE; 2870 }) 2871 2872 (define_expand "epilogue" 2873 [(return)] 2874 "" 2875 " 2876 { 2877 emit_jump_insn (gen_return ()); 2878 DONE; 2879 }") 2880 2881 ;; Exception handling 2882 ;; This is used when compiling the stack unwinding routines. 2883 (define_expand "eh_return" 2884 [(use (match_operand 0 "general_operand"))] 2885 "" 2886 { 2887 if (GET_MODE (operands[0]) != word_mode) 2888 operands[0] = convert_to_mode (word_mode, operands[0], 0); 2889 emit_insn (gen_eh_set_retaddr (operands[0])); 2890 DONE; 2891 }) 2892 2893 (define_insn_and_split "eh_set_retaddr" 2894 [(unspec [(match_operand:SI 0 "general_operand")] VUNSPEC_EH_RETURN) 2895 (clobber (match_scratch:SI 1 "=&r")) 2896 ] 2897 "" 2898 "#" 2899 "reload_completed" 2900 [(const_int 0)] 2901 { 2902 rtx tmp = RETURN_ADDR_RTX(0, frame_pointer_rtx); 2903 MEM_VOLATILE_P(tmp) = 1; 2904 tmp = gen_rtx_SET(tmp, operands[0]); 2905 emit_insn(tmp); 2906 DONE; 2907 }) 2908 2909 2910 2911 (define_insn "nop" 2912 [(const_int 0)] 2913 "" 2914 "nop") 2915 2916 ;; This had a wider constraint once, and it had trouble. 2917 ;; If you are tempted to try `g', please don't--it's not worth 2918 ;; the risk we will reopen the same bug. 2919 (define_insn "indirect_jump" 2920 [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 2921 "" 2922 "jmp (%0)") 2923 2924 ;; This is here to accept 5 arguments (as passed by expand_end_case) 2925 ;; and pass the first 4 along to the casesi1 pattern that really does 2926 ;; the actual casesi work. We emit a jump here to the default label 2927 ;; _before_ the casesi so that we can be sure that the casesi never 2928 ;; drops through. 2929 ;; This is suboptimal perhaps, but so is much of the rest of this 2930 ;; machine description. For what it's worth, HPPA uses the same trick. 2931 ;; 2932 ;; operand 0 is index 2933 ;; operand 1 is the minimum bound (a const_int) 2934 ;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int) 2935 ;; operand 3 is CODE_LABEL for the table; 2936 ;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default). 2937 ;; 2938 ;; We emit: 2939 ;; i = index - minimum_bound 2940 ;; if (i > (maximum_bound - minimum_bound + 1) goto default; 2941 ;; casesi (i, 0, table); 2942 ;; 2943 (define_expand "casesi" 2944 [(match_operand:SI 0 "general_operand" "") 2945 (match_operand:SI 1 "general_operand" "") 2946 (match_operand:SI 2 "general_operand" "") 2947 (match_operand 3 "" "") 2948 (match_operand 4 "" "")] 2949 "" 2950 { 2951 rtx test; 2952 2953 /* i = index - minimum_bound; 2954 But only if the lower bound is not already zero. */ 2955 if (operands[1] != const0_rtx) 2956 { 2957 rtx index = gen_reg_rtx (SImode); 2958 emit_insn (gen_addsi3 (index, 2959 operands[0], 2960 gen_int_mode (-INTVAL (operands[1]), SImode))); 2961 operands[0] = index; 2962 } 2963 2964 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */ 2965 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]); 2966 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4])); 2967 2968 /* casesi (i, 0, table); */ 2969 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3])); 2970 DONE; 2971 }) 2972 2973 ;; This insn is a bit of a lier. It actually falls through if no case 2974 ;; matches. But, we prevent that from ever happening by emitting a jump 2975 ;; before this, see the define_expand above. 2976 (define_insn_and_split "casesi1" 2977 [(match_operand:SI 1 "const_int_operand" "n") 2978 (set (pc) 2979 (plus:SI (sign_extend:SI 2980 (mem:HI (plus:SI 2981 (mult:SI 2982 (match_operand:SI 0 "general_operand" "nrmT") 2983 (const_int 2)) 2984 (pc)))) 2985 (label_ref:SI (match_operand 2 "" ""))))] 2986 "" 2987 "#" 2988 "reload_completed" 2989 [(parallel 2990 [(use (match_dup 1)) 2991 (set (pc) 2992 (plus:SI (sign_extend:SI 2993 (mem:HI (plus:SI 2994 (mult:SI 2995 (match_dup 0) 2996 (const_int 2)) 2997 (pc)))) 2998 (label_ref:SI (match_dup 2)))) 2999 (clobber (reg:CC VAX_PSL_REGNUM)) 3000 (use (label_ref:SI (match_dup 2))) 3001 ])] 3002 "") 3003 3004 (define_insn "*casesi1" 3005 [(use (match_operand:SI 1 "const_int_operand" "n")) 3006 (set (pc) 3007 (plus:SI (sign_extend:SI 3008 (mem:HI (plus:SI 3009 (mult:SI 3010 (match_operand:SI 0 "general_operand" "nrmT") 3011 (const_int 2)) 3012 (pc)))) 3013 (label_ref:SI (match_operand 2 "" "")))) 3014 (clobber (reg:CC VAX_PSL_REGNUM)) 3015 (use (label_ref:SI (match_dup 2))) 3016 ] 3017 "reload_completed" 3018 "casel %0,$0,%1") 3019 3021 (define_insn_and_split "*pushsym" 3022 [(set (match_operand:SI 0 "push_operand" "=g") 3023 (match_operand:SI 1 "pic_symbolic_operand" "A"))] 3024 "" 3025 "#" 3026 "reload_completed" 3027 [(parallel 3028 [(set (match_dup 0) 3029 (match_dup 1)) 3030 (clobber (reg:CC VAX_PSL_REGNUM))])] 3031 "") 3032 3033 (define_insn "*pushsym_2<ccn><ccnz><ccz>" 3034 [(set (match_operand:SI 0 "push_operand" "=g") 3035 (match_operand:SI 1 "pic_symbolic_operand" "A")) 3036 (clobber (reg:CC VAX_PSL_REGNUM))] 3037 "reload_completed" 3038 "pushab %a1") 3039 3040 (define_insn_and_split "*movsym" 3041 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3042 (match_operand:SI 1 "pic_symbolic_operand" "A"))] 3043 "" 3044 "#" 3045 "reload_completed" 3046 [(parallel 3047 [(set (match_dup 0) 3048 (match_dup 1)) 3049 (clobber (reg:CC VAX_PSL_REGNUM))])] 3050 "") 3051 3052 (define_insn "*movsym_2<ccn><ccnz><ccz>" 3053 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3054 (match_operand:SI 1 "pic_symbolic_operand" "A")) 3055 (clobber (reg:CC VAX_PSL_REGNUM))] 3056 "reload_completed" 3057 "movab %a1,%0") 3058 3059 (define_insn_and_split "*pushsymreg" 3060 [(set (match_operand:SI 0 "push_operand" "=g") 3061 (plus:SI (match_operand:SI 1 "register_operand" "%r") 3062 (match_operand:SI 2 "pic_symbolic_operand" "A")))] 3063 "flag_pic" 3064 "#" 3065 "&& reload_completed" 3066 [(parallel 3067 [(set (match_dup 0) 3068 (plus:SI (match_dup 1) 3069 (match_dup 2))) 3070 (clobber (reg:CC VAX_PSL_REGNUM))])] 3071 "") 3072 3073 (define_insn "*pushsymreg_2<ccn><ccnz><ccz>" 3074 [(set (match_operand:SI 0 "push_operand" "=g") 3075 (plus:SI (match_operand:SI 1 "register_operand" "%r") 3076 (match_operand:SI 2 "pic_symbolic_operand" "A"))) 3077 (clobber (reg:CC VAX_PSL_REGNUM))] 3078 "flag_pic && reload_completed" 3079 "pushab %a2[%1]") 3080 3081 (define_insn_and_split "*movsymreg" 3082 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3083 (plus:SI (match_operand:SI 1 "register_operand" "%r") 3084 (match_operand:SI 2 "pic_symbolic_operand" "A")))] 3085 "flag_pic" 3086 "#" 3087 "&& reload_completed" 3088 [(parallel 3089 [(set (match_dup 0) 3090 (plus:SI (match_dup 1) 3091 (match_dup 2))) 3092 (clobber (reg:CC VAX_PSL_REGNUM))])] 3093 "") 3094 3095 (define_insn "*movsymreg_2<ccn><ccnz><ccz>" 3096 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3097 (plus:SI (match_operand:SI 1 "register_operand" "%r") 3098 (match_operand:SI 2 "pic_symbolic_operand" "A"))) 3099 (clobber (reg:CC VAX_PSL_REGNUM))] 3100 "flag_pic && reload_completed" 3101 "movab %a2[%1],%0") 3102 3104 ;;- load or push effective address 3105 ;; These come after the move and add/sub patterns 3106 ;; because we don't want pushl $1 turned into pushad 1. 3107 ;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3. 3108 3109 ;; It does not work to use constraints to distinguish pushes from moves, 3110 ;; because < matches any autodecrement, not just a push. 3111 3112 (define_insn_and_split "pushaddr<mode>" 3113 [(set (match_operand:SI 0 "push_operand" "=g") 3114 (match_operand:VAXintQHSD 1 "address_operand" "p"))] 3115 "" 3116 "#" 3117 "reload_completed" 3118 [(parallel 3119 [(set (match_dup 0) 3120 (match_dup 1)) 3121 (clobber (reg:CC VAX_PSL_REGNUM))])] 3122 "") 3123 3124 (define_insn "*pushaddr<mode><ccn><ccnz><ccz>" 3125 [(set (match_operand:SI 0 "push_operand" "=g") 3126 (match_operand:VAXintQHSD 1 "address_operand" "p")) 3127 (clobber (reg:CC VAX_PSL_REGNUM))] 3128 "reload_completed" 3129 "pusha<VAXintQHSD:isfx> %a1") 3130 3131 (define_insn_and_split "movaddr<mode>" 3132 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3133 (match_operand:VAXintQHSD 1 "address_operand" "p"))] 3134 "" 3135 "#" 3136 "reload_completed" 3137 [(parallel 3138 [(set (match_dup 0) 3139 (match_dup 1)) 3140 (clobber (reg:CC VAX_PSL_REGNUM))])] 3141 "") 3142 3143 (define_insn "*movaddr<mode><ccn><ccnz><ccz>" 3144 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3145 (match_operand:VAXintQHSD 1 "address_operand" "p")) 3146 (clobber (reg:CC VAX_PSL_REGNUM))] 3147 "reload_completed" 3148 "mova<VAXintQHSD:isfx> %a1,%0") 3149 3150 (define_insn_and_split "pushaddr<mode>" 3151 [(set (match_operand:SI 0 "push_operand" "=g") 3152 (match_operand:VAXfp 1 "address_operand" "p"))] 3153 "" 3154 "#" 3155 "reload_completed" 3156 [(parallel 3157 [(set (match_dup 0) 3158 (match_dup 1)) 3159 (clobber (reg:CC VAX_PSL_REGNUM))])] 3160 "") 3161 3162 (define_insn "*pushaddr<mode><ccn><ccnz><ccz>" 3163 [(set (match_operand:SI 0 "push_operand" "=g") 3164 (match_operand:VAXfp 1 "address_operand" "p")) 3165 (clobber (reg:CC VAX_PSL_REGNUM))] 3166 "reload_completed" 3167 "pusha<VAXfp:fsfx> %a1") 3168 3169 (define_insn_and_split "movaddr<mode>" 3170 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3171 (match_operand:VAXfp 1 "address_operand" "p"))] 3172 "" 3173 "#" 3174 "reload_completed" 3175 [(parallel 3176 [(set (match_dup 0) 3177 (match_dup 1)) 3178 (clobber (reg:CC VAX_PSL_REGNUM))])] 3179 "") 3180 3181 (define_insn "*movaddr<mode>" 3182 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 3183 (match_operand:VAXfp 1 "address_operand" "p")) 3184 (clobber (reg:CC VAX_PSL_REGNUM))] 3185 "reload_completed" 3186 "mova<VAXfp:fsfx> %a1,%0") 3187 3189 ;; These used to be peepholes, but it is more straightforward to do them 3190 ;; as single insns. However, we must force the output to be a register 3191 ;; if it is not an offsettable address so that we know that we can assign 3192 ;; to it twice. 3193 3194 ;; If we had a good way of evaluating the relative costs, these could be 3195 ;; machine-independent. 3196 3197 ;; Optimize extzv ...,z; andl2 ...,z 3198 ;; or ashl ...,z; andl2 ...,z 3199 ;; with other operands constant. This is what the combiner converts the 3200 ;; above sequences to before attempting to recognize the new insn. 3201 3202 (define_insn_and_split "*andashlnegsi4" 3203 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3204 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 3205 (match_operand:QI 2 "const_int_operand" "n")) 3206 (match_operand:SI 3 "const_int_operand" "n")))] 3207 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0" 3208 "#" 3209 "&& reload_completed" 3210 [(parallel 3211 [(set (match_dup 0) 3212 (and:SI (ashiftrt:SI (match_dup 1) 3213 (match_dup 2)) 3214 (match_dup 3))) 3215 (clobber (reg:CC VAX_PSL_REGNUM))])] 3216 "") 3217 3218 (define_insn "*andashlnegsi4_2<ccn><ccnz><ccz>" 3219 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3220 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 3221 (match_operand:QI 2 "const_int_operand" "n")) 3222 (match_operand:SI 3 "const_int_operand" "n"))) 3223 (clobber (reg:CC VAX_PSL_REGNUM))] 3224 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0 3225 && reload_completed" 3226 "* 3227 { 3228 unsigned long mask1 = INTVAL (operands[3]); 3229 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1; 3230 3231 if ((mask1 & mask2) != mask1) 3232 operands[3] = GEN_INT (mask1 & mask2); 3233 3234 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\"; 3235 }") 3236 3237 ;; left-shift and mask 3238 ;; The only case where `ashl' is better is if the mask only turns off 3239 ;; bits that the ashl would anyways, in which case it should have been 3240 ;; optimized away. 3241 3242 (define_insn_and_split "*andashlsi4" 3243 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3244 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 3245 (match_operand:QI 2 "const_int_operand" "n")) 3246 (match_operand:SI 3 "const_int_operand" "n")))] 3247 "" 3248 "#" 3249 "reload_completed" 3250 [(parallel 3251 [(set (match_dup 0) 3252 (and:SI (ashift:SI (match_dup 1) 3253 (match_dup 2)) 3254 (match_dup 3))) 3255 (clobber (reg:CC VAX_PSL_REGNUM))])] 3256 "") 3257 3258 (define_insn "*andashlsi4_2<ccn><ccnz><ccz>" 3259 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 3260 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 3261 (match_operand:QI 2 "const_int_operand" "n")) 3262 (match_operand:SI 3 "const_int_operand" "n"))) 3263 (clobber (reg:CC VAX_PSL_REGNUM))] 3264 "reload_completed" 3265 "* 3266 { 3267 operands[3] 3268 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1)); 3269 return \"rotl %2,%1,%0\;bicl2 %N3,%0\"; 3270 }") 3271 3272 ;; Instruction sequence to sync the VAX instruction stream. 3273 (define_insn "sync_istream" 3274 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)] 3275 "" 3276 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei") 3277 3278 (define_expand "nonlocal_goto" 3279 [(use (match_operand 0 "general_operand" "")) 3280 (use (match_operand 1 "general_operand" "")) 3281 (use (match_operand 2 "general_operand" "")) 3282 (use (match_operand 3 "general_operand" ""))] 3283 "" 3284 { 3285 rtx lab = operands[1]; 3286 rtx stack = operands[2]; 3287 rtx fp = operands[3]; 3288 3289 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); 3290 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); 3291 3292 emit_move_insn (hard_frame_pointer_rtx, fp); 3293 emit_stack_restore (SAVE_NONLOCAL, stack); 3294 3295 emit_use (hard_frame_pointer_rtx); 3296 emit_use (stack_pointer_rtx); 3297 3298 /* We'll convert this to direct jump via a peephole optimization. */ 3299 emit_indirect_jump (copy_to_reg (lab)); 3300 emit_barrier (); 3301 DONE; 3302 }) 3303 3304 (include "builtins.md") 3305
Indexes created Thu Sep 10 00:26:39 UTC 2026