xtensa.cc revision 1.1.1.1
1 /* Subroutines for insn-output.cc for Tensilica's Xtensa architecture. 2 Copyright (C) 2001-2022 Free Software Foundation, Inc. 3 Contributed by Bob Wilson (bwilson (at) tensilica.com) at Tensilica. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #define IN_TARGET_CODE 1 22 23 #include "config.h" 24 #include "system.h" 25 #include "coretypes.h" 26 #include "backend.h" 27 #include "target.h" 28 #include "rtl.h" 29 #include "tree.h" 30 #include "gimple.h" 31 #include "cfghooks.h" 32 #include "df.h" 33 #include "memmodel.h" 34 #include "tm_p.h" 35 #include "stringpool.h" 36 #include "attribs.h" 37 #include "optabs.h" 38 #include "regs.h" 39 #include "emit-rtl.h" 40 #include "recog.h" 41 #include "diagnostic-core.h" 42 #include "cfgrtl.h" 43 #include "output.h" 44 #include "fold-const.h" 45 #include "stor-layout.h" 46 #include "calls.h" 47 #include "varasm.h" 48 #include "alias.h" 49 #include "explow.h" 50 #include "expr.h" 51 #include "reload.h" 52 #include "langhooks.h" 53 #include "gimplify.h" 54 #include "builtins.h" 55 #include "dumpfile.h" 56 #include "hw-doloop.h" 57 #include "rtl-iter.h" 58 59 /* This file should be included last. */ 60 #include "target-def.h" 61 62 /* Enumeration for all of the relational tests, so that we can build 63 arrays indexed by the test type, and not worry about the order 64 of EQ, NE, etc. */ 65 66 enum internal_test 67 { 68 ITEST_EQ, 69 ITEST_NE, 70 ITEST_GT, 71 ITEST_GE, 72 ITEST_LT, 73 ITEST_LE, 74 ITEST_GTU, 75 ITEST_GEU, 76 ITEST_LTU, 77 ITEST_LEU, 78 ITEST_MAX 79 }; 80 81 /* Array giving truth value on whether or not a given hard register 82 can support a given mode. */ 83 static char xtensa_hard_regno_mode_ok_p 84 [(int) MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER]; 85 86 /* Largest block move to handle in-line. */ 87 #define LARGEST_MOVE_RATIO 15 88 89 /* Define the structure for the machine field in struct function. */ 90 struct GTY(()) machine_function 91 { 92 int accesses_prev_frame; 93 bool need_a7_copy; 94 bool vararg_a7; 95 rtx vararg_a7_copy; 96 rtx_insn *set_frame_ptr_insn; 97 /* Current frame size calculated by compute_frame_size. */ 98 unsigned current_frame_size; 99 /* Callee-save area size in the current frame calculated by 100 compute_frame_size. */ 101 int callee_save_size; 102 bool frame_laid_out; 103 bool epilogue_done; 104 }; 105 106 /* Vector, indexed by hard register number, which contains 1 for a 107 register that is allowable in a candidate for leaf function 108 treatment. */ 109 110 const char xtensa_leaf_regs[FIRST_PSEUDO_REGISTER] = 111 { 112 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 113 1, 1, 1, 114 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 115 1 116 }; 117 118 static void xtensa_option_override (void); 119 static enum internal_test map_test_to_internal_test (enum rtx_code); 120 static rtx gen_int_relational (enum rtx_code, rtx, rtx, int *); 121 static rtx gen_float_relational (enum rtx_code, rtx, rtx); 122 static rtx gen_conditional_move (enum rtx_code, machine_mode, rtx, rtx); 123 static rtx fixup_subreg_mem (rtx); 124 static struct machine_function * xtensa_init_machine_status (void); 125 static rtx xtensa_legitimize_tls_address (rtx); 126 static rtx xtensa_legitimize_address (rtx, rtx, machine_mode); 127 static bool xtensa_mode_dependent_address_p (const_rtx, addr_space_t); 128 static bool xtensa_return_in_msb (const_tree); 129 static void printx (FILE *, signed int); 130 static rtx xtensa_builtin_saveregs (void); 131 static bool xtensa_legitimate_address_p (machine_mode, rtx, bool); 132 static unsigned int xtensa_multibss_section_type_flags (tree, const char *, 133 int) ATTRIBUTE_UNUSED; 134 static section *xtensa_select_rtx_section (machine_mode, rtx, 135 unsigned HOST_WIDE_INT); 136 static bool xtensa_rtx_costs (rtx, machine_mode, int, int, int *, bool); 137 static int xtensa_register_move_cost (machine_mode, reg_class_t, 138 reg_class_t); 139 static int xtensa_memory_move_cost (machine_mode, reg_class_t, bool); 140 static tree xtensa_build_builtin_va_list (void); 141 static bool xtensa_return_in_memory (const_tree, const_tree); 142 static tree xtensa_gimplify_va_arg_expr (tree, tree, gimple_seq *, 143 gimple_seq *); 144 static void xtensa_function_arg_advance (cumulative_args_t, 145 const function_arg_info &); 146 static rtx xtensa_function_arg (cumulative_args_t, const function_arg_info &); 147 static rtx xtensa_function_incoming_arg (cumulative_args_t, 148 const function_arg_info &); 149 static rtx xtensa_function_value (const_tree, const_tree, bool); 150 static rtx xtensa_libcall_value (machine_mode, const_rtx); 151 static bool xtensa_function_value_regno_p (const unsigned int); 152 static unsigned int xtensa_function_arg_boundary (machine_mode, 153 const_tree); 154 static void xtensa_init_builtins (void); 155 static tree xtensa_fold_builtin (tree, int, tree *, bool); 156 static rtx xtensa_expand_builtin (tree, rtx, rtx, machine_mode, int); 157 static void xtensa_va_start (tree, rtx); 158 static bool xtensa_frame_pointer_required (void); 159 static rtx xtensa_static_chain (const_tree, bool); 160 static void xtensa_asm_trampoline_template (FILE *); 161 static void xtensa_trampoline_init (rtx, tree, rtx); 162 static bool xtensa_output_addr_const_extra (FILE *, rtx); 163 static bool xtensa_cannot_force_const_mem (machine_mode, rtx); 164 165 static reg_class_t xtensa_preferred_reload_class (rtx, reg_class_t); 166 static reg_class_t xtensa_preferred_output_reload_class (rtx, reg_class_t); 167 static reg_class_t xtensa_secondary_reload (bool, rtx, reg_class_t, 168 machine_mode, 169 struct secondary_reload_info *); 170 171 static bool constantpool_address_p (const_rtx addr); 172 static bool xtensa_legitimate_constant_p (machine_mode, rtx); 173 static void xtensa_reorg (void); 174 static bool xtensa_can_use_doloop_p (const widest_int &, const widest_int &, 175 unsigned int, bool); 176 static const char *xtensa_invalid_within_doloop (const rtx_insn *); 177 178 static bool xtensa_member_type_forces_blk (const_tree, 179 machine_mode mode); 180 181 static void xtensa_conditional_register_usage (void); 182 static unsigned int xtensa_hard_regno_nregs (unsigned int, machine_mode); 183 static bool xtensa_hard_regno_mode_ok (unsigned int, machine_mode); 184 static bool xtensa_modes_tieable_p (machine_mode, machine_mode); 185 static HOST_WIDE_INT xtensa_constant_alignment (const_tree, HOST_WIDE_INT); 186 static bool xtensa_can_eliminate (const int from ATTRIBUTE_UNUSED, 187 const int to); 188 static HOST_WIDE_INT xtensa_starting_frame_offset (void); 189 static unsigned HOST_WIDE_INT xtensa_asan_shadow_offset (void); 190 191 static rtx xtensa_delegitimize_address (rtx); 192 193 194 196 /* These hooks specify assembly directives for creating certain kinds 197 of integer object. */ 198 199 #undef TARGET_ASM_ALIGNED_SI_OP 200 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 201 202 #undef TARGET_ASM_SELECT_RTX_SECTION 203 #define TARGET_ASM_SELECT_RTX_SECTION xtensa_select_rtx_section 204 205 #undef TARGET_LEGITIMIZE_ADDRESS 206 #define TARGET_LEGITIMIZE_ADDRESS xtensa_legitimize_address 207 #undef TARGET_MODE_DEPENDENT_ADDRESS_P 208 #define TARGET_MODE_DEPENDENT_ADDRESS_P xtensa_mode_dependent_address_p 209 210 #undef TARGET_REGISTER_MOVE_COST 211 #define TARGET_REGISTER_MOVE_COST xtensa_register_move_cost 212 #undef TARGET_MEMORY_MOVE_COST 213 #define TARGET_MEMORY_MOVE_COST xtensa_memory_move_cost 214 #undef TARGET_RTX_COSTS 215 #define TARGET_RTX_COSTS xtensa_rtx_costs 216 #undef TARGET_ADDRESS_COST 217 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 218 219 #undef TARGET_MEMBER_TYPE_FORCES_BLK 220 #define TARGET_MEMBER_TYPE_FORCES_BLK xtensa_member_type_forces_blk 221 222 #undef TARGET_BUILD_BUILTIN_VA_LIST 223 #define TARGET_BUILD_BUILTIN_VA_LIST xtensa_build_builtin_va_list 224 225 #undef TARGET_EXPAND_BUILTIN_VA_START 226 #define TARGET_EXPAND_BUILTIN_VA_START xtensa_va_start 227 228 #undef TARGET_PROMOTE_FUNCTION_MODE 229 #define TARGET_PROMOTE_FUNCTION_MODE default_promote_function_mode_always_promote 230 #undef TARGET_PROMOTE_PROTOTYPES 231 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true 232 233 #undef TARGET_RETURN_IN_MEMORY 234 #define TARGET_RETURN_IN_MEMORY xtensa_return_in_memory 235 #undef TARGET_FUNCTION_VALUE 236 #define TARGET_FUNCTION_VALUE xtensa_function_value 237 #undef TARGET_LIBCALL_VALUE 238 #define TARGET_LIBCALL_VALUE xtensa_libcall_value 239 #undef TARGET_FUNCTION_VALUE_REGNO_P 240 #define TARGET_FUNCTION_VALUE_REGNO_P xtensa_function_value_regno_p 241 242 #undef TARGET_SPLIT_COMPLEX_ARG 243 #define TARGET_SPLIT_COMPLEX_ARG hook_bool_const_tree_true 244 #undef TARGET_MUST_PASS_IN_STACK 245 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 246 #undef TARGET_FUNCTION_ARG_ADVANCE 247 #define TARGET_FUNCTION_ARG_ADVANCE xtensa_function_arg_advance 248 #undef TARGET_FUNCTION_ARG 249 #define TARGET_FUNCTION_ARG xtensa_function_arg 250 #undef TARGET_FUNCTION_INCOMING_ARG 251 #define TARGET_FUNCTION_INCOMING_ARG xtensa_function_incoming_arg 252 #undef TARGET_FUNCTION_ARG_BOUNDARY 253 #define TARGET_FUNCTION_ARG_BOUNDARY xtensa_function_arg_boundary 254 255 #undef TARGET_EXPAND_BUILTIN_SAVEREGS 256 #define TARGET_EXPAND_BUILTIN_SAVEREGS xtensa_builtin_saveregs 257 #undef TARGET_GIMPLIFY_VA_ARG_EXPR 258 #define TARGET_GIMPLIFY_VA_ARG_EXPR xtensa_gimplify_va_arg_expr 259 260 #undef TARGET_RETURN_IN_MSB 261 #define TARGET_RETURN_IN_MSB xtensa_return_in_msb 262 263 #undef TARGET_INIT_BUILTINS 264 #define TARGET_INIT_BUILTINS xtensa_init_builtins 265 #undef TARGET_FOLD_BUILTIN 266 #define TARGET_FOLD_BUILTIN xtensa_fold_builtin 267 #undef TARGET_EXPAND_BUILTIN 268 #define TARGET_EXPAND_BUILTIN xtensa_expand_builtin 269 270 #undef TARGET_PREFERRED_RELOAD_CLASS 271 #define TARGET_PREFERRED_RELOAD_CLASS xtensa_preferred_reload_class 272 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS 273 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS xtensa_preferred_output_reload_class 274 275 #undef TARGET_SECONDARY_RELOAD 276 #define TARGET_SECONDARY_RELOAD xtensa_secondary_reload 277 278 #undef TARGET_HAVE_TLS 279 #define TARGET_HAVE_TLS HAVE_AS_TLS 280 281 #undef TARGET_CANNOT_FORCE_CONST_MEM 282 #define TARGET_CANNOT_FORCE_CONST_MEM xtensa_cannot_force_const_mem 283 284 #undef TARGET_LRA_P 285 #define TARGET_LRA_P hook_bool_void_false 286 287 #undef TARGET_LEGITIMATE_ADDRESS_P 288 #define TARGET_LEGITIMATE_ADDRESS_P xtensa_legitimate_address_p 289 290 #undef TARGET_FRAME_POINTER_REQUIRED 291 #define TARGET_FRAME_POINTER_REQUIRED xtensa_frame_pointer_required 292 293 #undef TARGET_STATIC_CHAIN 294 #define TARGET_STATIC_CHAIN xtensa_static_chain 295 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE 296 #define TARGET_ASM_TRAMPOLINE_TEMPLATE xtensa_asm_trampoline_template 297 #undef TARGET_TRAMPOLINE_INIT 298 #define TARGET_TRAMPOLINE_INIT xtensa_trampoline_init 299 300 #undef TARGET_OPTION_OVERRIDE 301 #define TARGET_OPTION_OVERRIDE xtensa_option_override 302 303 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 304 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA xtensa_output_addr_const_extra 305 306 #undef TARGET_LEGITIMATE_CONSTANT_P 307 #define TARGET_LEGITIMATE_CONSTANT_P xtensa_legitimate_constant_p 308 309 #undef TARGET_MACHINE_DEPENDENT_REORG 310 #define TARGET_MACHINE_DEPENDENT_REORG xtensa_reorg 311 312 #undef TARGET_CAN_USE_DOLOOP_P 313 #define TARGET_CAN_USE_DOLOOP_P xtensa_can_use_doloop_p 314 315 #undef TARGET_INVALID_WITHIN_DOLOOP 316 #define TARGET_INVALID_WITHIN_DOLOOP xtensa_invalid_within_doloop 317 318 #undef TARGET_CONDITIONAL_REGISTER_USAGE 319 #define TARGET_CONDITIONAL_REGISTER_USAGE xtensa_conditional_register_usage 320 321 #undef TARGET_HARD_REGNO_NREGS 322 #define TARGET_HARD_REGNO_NREGS xtensa_hard_regno_nregs 323 #undef TARGET_HARD_REGNO_MODE_OK 324 #define TARGET_HARD_REGNO_MODE_OK xtensa_hard_regno_mode_ok 325 326 #undef TARGET_MODES_TIEABLE_P 327 #define TARGET_MODES_TIEABLE_P xtensa_modes_tieable_p 328 329 #undef TARGET_CONSTANT_ALIGNMENT 330 #define TARGET_CONSTANT_ALIGNMENT xtensa_constant_alignment 331 332 #undef TARGET_CAN_ELIMINATE 333 #define TARGET_CAN_ELIMINATE xtensa_can_eliminate 334 335 #undef TARGET_STARTING_FRAME_OFFSET 336 #define TARGET_STARTING_FRAME_OFFSET xtensa_starting_frame_offset 337 338 #undef TARGET_ASAN_SHADOW_OFFSET 339 #define TARGET_ASAN_SHADOW_OFFSET xtensa_asan_shadow_offset 340 341 #undef TARGET_HAVE_SPECULATION_SAFE_VALUE 342 #define TARGET_HAVE_SPECULATION_SAFE_VALUE speculation_safe_value_not_needed 343 344 #undef TARGET_DELEGITIMIZE_ADDRESS 345 #define TARGET_DELEGITIMIZE_ADDRESS xtensa_delegitimize_address 346 347 struct gcc_target targetm = TARGET_INITIALIZER; 348 349 350 /* Functions to test Xtensa immediate operand validity. */ 352 353 bool 354 xtensa_simm8 (HOST_WIDE_INT v) 355 { 356 return v >= -128 && v <= 127; 357 } 358 359 360 bool 361 xtensa_simm8x256 (HOST_WIDE_INT v) 362 { 363 return (v & 255) == 0 && (v >= -32768 && v <= 32512); 364 } 365 366 367 bool 368 xtensa_simm12b (HOST_WIDE_INT v) 369 { 370 return v >= -2048 && v <= 2047; 371 } 372 373 374 static bool 375 xtensa_uimm8 (HOST_WIDE_INT v) 376 { 377 return v >= 0 && v <= 255; 378 } 379 380 381 static bool 382 xtensa_uimm8x2 (HOST_WIDE_INT v) 383 { 384 return (v & 1) == 0 && (v >= 0 && v <= 510); 385 } 386 387 388 static bool 389 xtensa_uimm8x4 (HOST_WIDE_INT v) 390 { 391 return (v & 3) == 0 && (v >= 0 && v <= 1020); 392 } 393 394 395 static bool 396 xtensa_b4const (HOST_WIDE_INT v) 397 { 398 switch (v) 399 { 400 case -1: 401 case 1: 402 case 2: 403 case 3: 404 case 4: 405 case 5: 406 case 6: 407 case 7: 408 case 8: 409 case 10: 410 case 12: 411 case 16: 412 case 32: 413 case 64: 414 case 128: 415 case 256: 416 return true; 417 } 418 return false; 419 } 420 421 422 bool 423 xtensa_b4const_or_zero (HOST_WIDE_INT v) 424 { 425 if (v == 0) 426 return true; 427 return xtensa_b4const (v); 428 } 429 430 431 bool 432 xtensa_b4constu (HOST_WIDE_INT v) 433 { 434 switch (v) 435 { 436 case 32768: 437 case 65536: 438 case 2: 439 case 3: 440 case 4: 441 case 5: 442 case 6: 443 case 7: 444 case 8: 445 case 10: 446 case 12: 447 case 16: 448 case 32: 449 case 64: 450 case 128: 451 case 256: 452 return true; 453 } 454 return false; 455 } 456 457 458 bool 459 xtensa_mask_immediate (HOST_WIDE_INT v) 460 { 461 #define MAX_MASK_SIZE 16 462 int mask_size; 463 464 for (mask_size = 1; mask_size <= MAX_MASK_SIZE; mask_size++) 465 { 466 if ((v & 1) == 0) 467 return false; 468 v = v >> 1; 469 if (v == 0) 470 return true; 471 } 472 473 return false; 474 } 475 476 477 /* This is just like the standard true_regnum() function except that it 478 works even when reg_renumber is not initialized. */ 479 480 int 481 xt_true_regnum (rtx x) 482 { 483 if (GET_CODE (x) == REG) 484 { 485 if (reg_renumber 486 && REGNO (x) >= FIRST_PSEUDO_REGISTER 487 && reg_renumber[REGNO (x)] >= 0) 488 return reg_renumber[REGNO (x)]; 489 return REGNO (x); 490 } 491 if (GET_CODE (x) == SUBREG) 492 { 493 int base = xt_true_regnum (SUBREG_REG (x)); 494 if (base >= 0 && base < FIRST_PSEUDO_REGISTER) 495 return base + subreg_regno_offset (REGNO (SUBREG_REG (x)), 496 GET_MODE (SUBREG_REG (x)), 497 SUBREG_BYTE (x), GET_MODE (x)); 498 } 499 return -1; 500 } 501 502 503 int 504 xtensa_valid_move (machine_mode mode, rtx *operands) 505 { 506 /* Either the destination or source must be a register, and the 507 MAC16 accumulator doesn't count. */ 508 509 if (register_operand (operands[0], mode)) 510 { 511 int dst_regnum = xt_true_regnum (operands[0]); 512 513 if (xtensa_tls_referenced_p (operands[1])) 514 return FALSE; 515 516 /* The stack pointer can only be assigned with a MOVSP opcode. */ 517 if (dst_regnum == STACK_POINTER_REGNUM) 518 return !TARGET_WINDOWED_ABI 519 || (mode == SImode 520 && register_operand (operands[1], mode) 521 && !ACC_REG_P (xt_true_regnum (operands[1]))); 522 523 if (!ACC_REG_P (dst_regnum)) 524 return true; 525 } 526 if (register_operand (operands[1], mode)) 527 { 528 int src_regnum = xt_true_regnum (operands[1]); 529 if (!ACC_REG_P (src_regnum)) 530 return true; 531 } 532 return FALSE; 533 } 534 535 536 int 537 smalloffset_mem_p (rtx op) 538 { 539 if (GET_CODE (op) == MEM) 540 { 541 rtx addr = XEXP (op, 0); 542 if (GET_CODE (addr) == REG) 543 return BASE_REG_P (addr, 0); 544 if (GET_CODE (addr) == PLUS) 545 { 546 rtx offset = XEXP (addr, 0); 547 HOST_WIDE_INT val; 548 if (GET_CODE (offset) != CONST_INT) 549 offset = XEXP (addr, 1); 550 if (GET_CODE (offset) != CONST_INT) 551 return FALSE; 552 553 val = INTVAL (offset); 554 return (val & 3) == 0 && (val >= 0 && val <= 60); 555 } 556 } 557 return FALSE; 558 } 559 560 561 static bool 562 constantpool_address_p (const_rtx addr) 563 { 564 const_rtx sym = addr; 565 566 if (GET_CODE (addr) == CONST) 567 { 568 rtx offset; 569 570 /* Only handle (PLUS (SYM, OFFSET)) form. */ 571 addr = XEXP (addr, 0); 572 if (GET_CODE (addr) != PLUS) 573 return false; 574 575 /* Make sure the address is word aligned. */ 576 offset = XEXP (addr, 1); 577 if ((!CONST_INT_P (offset)) 578 || ((INTVAL (offset) & 3) != 0)) 579 return false; 580 581 sym = XEXP (addr, 0); 582 } 583 584 if ((GET_CODE (sym) == SYMBOL_REF) 585 && CONSTANT_POOL_ADDRESS_P (sym)) 586 return true; 587 return false; 588 } 589 590 591 int 592 constantpool_mem_p (rtx op) 593 { 594 if (GET_CODE (op) == SUBREG) 595 op = SUBREG_REG (op); 596 if (GET_CODE (op) == MEM) 597 return constantpool_address_p (XEXP (op, 0)); 598 return FALSE; 599 } 600 601 602 /* Return TRUE if X is a thread-local symbol. */ 603 604 static bool 605 xtensa_tls_symbol_p (rtx x) 606 { 607 if (! targetm.have_tls) 608 return false; 609 610 return GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0; 611 } 612 613 614 void 615 xtensa_extend_reg (rtx dst, rtx src) 616 { 617 rtx temp = gen_reg_rtx (SImode); 618 rtx shift = GEN_INT (BITS_PER_WORD - GET_MODE_BITSIZE (GET_MODE (src))); 619 620 /* Generate paradoxical subregs as needed so that the modes match. */ 621 src = simplify_gen_subreg (SImode, src, GET_MODE (src), 0); 622 dst = simplify_gen_subreg (SImode, dst, GET_MODE (dst), 0); 623 624 emit_insn (gen_ashlsi3 (temp, src, shift)); 625 emit_insn (gen_ashrsi3 (dst, temp, shift)); 626 } 627 628 629 bool 630 xtensa_mem_offset (unsigned v, machine_mode mode) 631 { 632 switch (mode) 633 { 634 case E_BLKmode: 635 /* Handle the worst case for block moves. See xtensa_expand_block_move 636 where we emit an optimized block move operation if the block can be 637 moved in < "move_ratio" pieces. The worst case is when the block is 638 aligned but has a size of (3 mod 4) (does this happen?) so that the 639 last piece requires a byte load/store. */ 640 return (xtensa_uimm8 (v) 641 && xtensa_uimm8 (v + MOVE_MAX * LARGEST_MOVE_RATIO)); 642 643 case E_QImode: 644 return xtensa_uimm8 (v); 645 646 case E_HImode: 647 return xtensa_uimm8x2 (v); 648 649 case E_DImode: 650 case E_DFmode: 651 return (xtensa_uimm8x4 (v) && xtensa_uimm8x4 (v + 4)); 652 653 default: 654 break; 655 } 656 657 return xtensa_uimm8x4 (v); 658 } 659 660 661 /* Make normal rtx_code into something we can index from an array. */ 662 663 static enum internal_test 664 map_test_to_internal_test (enum rtx_code test_code) 665 { 666 enum internal_test test = ITEST_MAX; 667 668 switch (test_code) 669 { 670 default: break; 671 case EQ: test = ITEST_EQ; break; 672 case NE: test = ITEST_NE; break; 673 case GT: test = ITEST_GT; break; 674 case GE: test = ITEST_GE; break; 675 case LT: test = ITEST_LT; break; 676 case LE: test = ITEST_LE; break; 677 case GTU: test = ITEST_GTU; break; 678 case GEU: test = ITEST_GEU; break; 679 case LTU: test = ITEST_LTU; break; 680 case LEU: test = ITEST_LEU; break; 681 } 682 683 return test; 684 } 685 686 687 /* Generate the code to compare two integer values. The return value is 688 the comparison expression. */ 689 690 static rtx 691 gen_int_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ 692 rtx cmp0, /* first operand to compare */ 693 rtx cmp1, /* second operand to compare */ 694 int *p_invert /* whether branch needs to reverse test */) 695 { 696 struct cmp_info 697 { 698 enum rtx_code test_code; /* test code to use in insn */ 699 bool (*const_range_p) (HOST_WIDE_INT); /* range check function */ 700 int const_add; /* constant to add (convert LE -> LT) */ 701 int reverse_regs; /* reverse registers in test */ 702 int invert_const; /* != 0 if invert value if cmp1 is constant */ 703 int invert_reg; /* != 0 if invert value if cmp1 is register */ 704 int unsignedp; /* != 0 for unsigned comparisons. */ 705 }; 706 707 static struct cmp_info info[ (int)ITEST_MAX ] = { 708 709 { EQ, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* EQ */ 710 { NE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* NE */ 711 712 { LT, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* GT */ 713 { GE, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* GE */ 714 { LT, xtensa_b4const_or_zero, 0, 0, 0, 0, 0 }, /* LT */ 715 { GE, xtensa_b4const_or_zero, 1, 1, 1, 0, 0 }, /* LE */ 716 717 { LTU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* GTU */ 718 { GEU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* GEU */ 719 { LTU, xtensa_b4constu, 0, 0, 0, 0, 1 }, /* LTU */ 720 { GEU, xtensa_b4constu, 1, 1, 1, 0, 1 }, /* LEU */ 721 }; 722 723 enum internal_test test; 724 machine_mode mode; 725 struct cmp_info *p_info; 726 727 test = map_test_to_internal_test (test_code); 728 gcc_assert (test != ITEST_MAX); 729 730 p_info = &info[ (int)test ]; 731 732 mode = GET_MODE (cmp0); 733 if (mode == VOIDmode) 734 mode = GET_MODE (cmp1); 735 736 /* Make sure we can handle any constants given to us. */ 737 if (GET_CODE (cmp1) == CONST_INT) 738 { 739 HOST_WIDE_INT value = INTVAL (cmp1); 740 unsigned HOST_WIDE_INT uvalue = (unsigned HOST_WIDE_INT)value; 741 742 /* if the immediate overflows or does not fit in the immediate field, 743 spill it to a register */ 744 745 if ((p_info->unsignedp ? 746 (uvalue + p_info->const_add > uvalue) : 747 (value + p_info->const_add > value)) != (p_info->const_add > 0)) 748 { 749 cmp1 = force_reg (mode, cmp1); 750 } 751 else if (!(p_info->const_range_p) (value + p_info->const_add)) 752 { 753 cmp1 = force_reg (mode, cmp1); 754 } 755 } 756 else if ((GET_CODE (cmp1) != REG) && (GET_CODE (cmp1) != SUBREG)) 757 { 758 cmp1 = force_reg (mode, cmp1); 759 } 760 761 /* See if we need to invert the result. */ 762 *p_invert = ((GET_CODE (cmp1) == CONST_INT) 763 ? p_info->invert_const 764 : p_info->invert_reg); 765 766 /* Comparison to constants, may involve adding 1 to change a LT into LE. 767 Comparison between two registers, may involve switching operands. */ 768 if (GET_CODE (cmp1) == CONST_INT) 769 { 770 if (p_info->const_add != 0) 771 cmp1 = GEN_INT (INTVAL (cmp1) + p_info->const_add); 772 773 } 774 else if (p_info->reverse_regs) 775 { 776 rtx temp = cmp0; 777 cmp0 = cmp1; 778 cmp1 = temp; 779 } 780 781 return gen_rtx_fmt_ee (p_info->test_code, VOIDmode, cmp0, cmp1); 782 } 783 784 785 /* Generate the code to compare two float values. The return value is 786 the comparison expression. */ 787 788 static rtx 789 gen_float_relational (enum rtx_code test_code, /* relational test (EQ, etc) */ 790 rtx cmp0, /* first operand to compare */ 791 rtx cmp1 /* second operand to compare */) 792 { 793 rtx (*gen_fn) (rtx, rtx, rtx); 794 rtx brtmp; 795 int reverse_regs, invert; 796 797 switch (test_code) 798 { 799 case EQ: reverse_regs = 0; invert = 0; gen_fn = gen_seq_sf; break; 800 case NE: reverse_regs = 0; invert = 1; gen_fn = gen_seq_sf; break; 801 case LE: reverse_regs = 0; invert = 0; gen_fn = gen_sle_sf; break; 802 case GT: reverse_regs = 1; invert = 0; gen_fn = gen_slt_sf; break; 803 case LT: reverse_regs = 0; invert = 0; gen_fn = gen_slt_sf; break; 804 case GE: reverse_regs = 1; invert = 0; gen_fn = gen_sle_sf; break; 805 case UNEQ: reverse_regs = 0; invert = 0; gen_fn = gen_suneq_sf; break; 806 case LTGT: reverse_regs = 0; invert = 1; gen_fn = gen_suneq_sf; break; 807 case UNLE: reverse_regs = 0; invert = 0; gen_fn = gen_sunle_sf; break; 808 case UNGT: reverse_regs = 1; invert = 0; gen_fn = gen_sunlt_sf; break; 809 case UNLT: reverse_regs = 0; invert = 0; gen_fn = gen_sunlt_sf; break; 810 case UNGE: reverse_regs = 1; invert = 0; gen_fn = gen_sunle_sf; break; 811 case UNORDERED: 812 reverse_regs = 0; invert = 0; gen_fn = gen_sunordered_sf; break; 813 case ORDERED: 814 reverse_regs = 0; invert = 1; gen_fn = gen_sunordered_sf; break; 815 default: 816 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); 817 reverse_regs = 0; invert = 0; gen_fn = 0; /* avoid compiler warnings */ 818 } 819 820 if (reverse_regs) 821 { 822 rtx temp = cmp0; 823 cmp0 = cmp1; 824 cmp1 = temp; 825 } 826 827 brtmp = gen_rtx_REG (CCmode, FPCC_REGNUM); 828 emit_insn (gen_fn (brtmp, cmp0, cmp1)); 829 830 return gen_rtx_fmt_ee (invert ? EQ : NE, VOIDmode, brtmp, const0_rtx); 831 } 832 833 834 void 835 xtensa_expand_conditional_branch (rtx *operands, machine_mode mode) 836 { 837 enum rtx_code test_code = GET_CODE (operands[0]); 838 rtx cmp0 = operands[1]; 839 rtx cmp1 = operands[2]; 840 rtx cmp; 841 int invert; 842 rtx label1, label2; 843 844 switch (mode) 845 { 846 case E_DFmode: 847 default: 848 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, cmp0, cmp1)); 849 850 case E_SImode: 851 invert = FALSE; 852 cmp = gen_int_relational (test_code, cmp0, cmp1, &invert); 853 break; 854 855 case E_SFmode: 856 if (!TARGET_HARD_FLOAT) 857 fatal_insn ("bad test", gen_rtx_fmt_ee (test_code, VOIDmode, 858 cmp0, cmp1)); 859 invert = FALSE; 860 cmp = gen_float_relational (test_code, cmp0, cmp1); 861 break; 862 } 863 864 /* Generate the branch. */ 865 866 label1 = gen_rtx_LABEL_REF (VOIDmode, operands[3]); 867 label2 = pc_rtx; 868 869 if (invert) 870 { 871 label2 = label1; 872 label1 = pc_rtx; 873 } 874 875 emit_jump_insn (gen_rtx_SET (pc_rtx, 876 gen_rtx_IF_THEN_ELSE (VOIDmode, cmp, 877 label1, 878 label2))); 879 } 880 881 882 static rtx 883 gen_conditional_move (enum rtx_code code, machine_mode mode, 884 rtx op0, rtx op1) 885 { 886 if (mode == SImode) 887 { 888 rtx cmp; 889 890 /* Jump optimization calls get_condition() which canonicalizes 891 comparisons like (GE x <const>) to (GT x <const-1>). 892 Transform those comparisons back to GE, since that is the 893 comparison supported in Xtensa. We shouldn't have to 894 transform <LE x const> comparisons, because neither 895 xtensa_expand_conditional_branch() nor get_condition() will 896 produce them. */ 897 898 if ((code == GT) && (op1 == constm1_rtx)) 899 { 900 code = GE; 901 op1 = const0_rtx; 902 } 903 cmp = gen_rtx_fmt_ee (code, VOIDmode, pc_rtx, const0_rtx); 904 905 if (boolean_operator (cmp, VOIDmode)) 906 { 907 /* Swap the operands to make const0 second. */ 908 if (op0 == const0_rtx) 909 { 910 op0 = op1; 911 op1 = const0_rtx; 912 } 913 914 /* If not comparing against zero, emit a comparison (subtract). */ 915 if (op1 != const0_rtx) 916 { 917 op0 = expand_binop (SImode, sub_optab, op0, op1, 918 0, 0, OPTAB_LIB_WIDEN); 919 op1 = const0_rtx; 920 } 921 } 922 else if (branch_operator (cmp, VOIDmode)) 923 { 924 /* Swap the operands to make const0 second. */ 925 if (op0 == const0_rtx) 926 { 927 op0 = op1; 928 op1 = const0_rtx; 929 930 switch (code) 931 { 932 case LT: code = GE; break; 933 case GE: code = LT; break; 934 default: gcc_unreachable (); 935 } 936 } 937 938 if (op1 != const0_rtx) 939 return 0; 940 } 941 else 942 return 0; 943 944 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 945 } 946 947 if (TARGET_HARD_FLOAT && mode == SFmode) 948 return gen_float_relational (code, op0, op1); 949 950 return 0; 951 } 952 953 954 int 955 xtensa_expand_conditional_move (rtx *operands, int isflt) 956 { 957 rtx dest = operands[0]; 958 rtx cmp = operands[1]; 959 machine_mode cmp_mode = GET_MODE (XEXP (cmp, 0)); 960 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); 961 962 if (!(cmp = gen_conditional_move (GET_CODE (cmp), cmp_mode, 963 XEXP (cmp, 0), XEXP (cmp, 1)))) 964 return 0; 965 966 if (isflt) 967 gen_fn = (cmp_mode == SImode 968 ? gen_movsfcc_internal0 969 : gen_movsfcc_internal1); 970 else 971 gen_fn = (cmp_mode == SImode 972 ? gen_movsicc_internal0 973 : gen_movsicc_internal1); 974 975 emit_insn (gen_fn (dest, XEXP (cmp, 0), operands[2], operands[3], cmp)); 976 return 1; 977 } 978 979 980 int 981 xtensa_expand_scc (rtx operands[4], machine_mode cmp_mode) 982 { 983 rtx dest = operands[0]; 984 rtx cmp; 985 rtx one_tmp, zero_tmp; 986 rtx (*gen_fn) (rtx, rtx, rtx, rtx, rtx); 987 988 if (!(cmp = gen_conditional_move (GET_CODE (operands[1]), cmp_mode, 989 operands[2], operands[3]))) 990 return 0; 991 992 one_tmp = gen_reg_rtx (SImode); 993 zero_tmp = gen_reg_rtx (SImode); 994 emit_insn (gen_movsi (one_tmp, const_true_rtx)); 995 emit_insn (gen_movsi (zero_tmp, const0_rtx)); 996 997 gen_fn = (cmp_mode == SImode 998 ? gen_movsicc_internal0 999 : gen_movsicc_internal1); 1000 emit_insn (gen_fn (dest, XEXP (cmp, 0), one_tmp, zero_tmp, cmp)); 1001 return 1; 1002 } 1003 1004 1005 /* Split OP[1] into OP[2,3] and likewise for OP[0] into OP[0,1]. MODE is 1006 for the output, i.e., the input operands are twice as big as MODE. */ 1007 1008 void 1009 xtensa_split_operand_pair (rtx operands[4], machine_mode mode) 1010 { 1011 switch (GET_CODE (operands[1])) 1012 { 1013 case REG: 1014 operands[3] = gen_rtx_REG (mode, REGNO (operands[1]) + 1); 1015 operands[2] = gen_rtx_REG (mode, REGNO (operands[1])); 1016 break; 1017 1018 case MEM: 1019 operands[3] = adjust_address (operands[1], mode, GET_MODE_SIZE (mode)); 1020 operands[2] = adjust_address (operands[1], mode, 0); 1021 break; 1022 1023 case CONST_INT: 1024 case CONST_DOUBLE: 1025 split_double (operands[1], &operands[2], &operands[3]); 1026 break; 1027 1028 default: 1029 gcc_unreachable (); 1030 } 1031 1032 switch (GET_CODE (operands[0])) 1033 { 1034 case REG: 1035 operands[1] = gen_rtx_REG (mode, REGNO (operands[0]) + 1); 1036 operands[0] = gen_rtx_REG (mode, REGNO (operands[0])); 1037 break; 1038 1039 case MEM: 1040 operands[1] = adjust_address (operands[0], mode, GET_MODE_SIZE (mode)); 1041 operands[0] = adjust_address (operands[0], mode, 0); 1042 break; 1043 1044 default: 1045 gcc_unreachable (); 1046 } 1047 } 1048 1049 1050 /* Emit insns to move operands[1] into operands[0]. 1051 Return 1 if we have written out everything that needs to be done to 1052 do the move. Otherwise, return 0 and the caller will emit the move 1053 normally. */ 1054 1055 int 1056 xtensa_emit_move_sequence (rtx *operands, machine_mode mode) 1057 { 1058 rtx src = operands[1]; 1059 1060 if (CONSTANT_P (src) 1061 && (GET_CODE (src) != CONST_INT || ! xtensa_simm12b (INTVAL (src)))) 1062 { 1063 rtx dst = operands[0]; 1064 1065 if (xtensa_tls_referenced_p (src)) 1066 { 1067 rtx addend = NULL; 1068 1069 if (GET_CODE (src) == CONST && GET_CODE (XEXP (src, 0)) == PLUS) 1070 { 1071 addend = XEXP (XEXP (src, 0), 1); 1072 src = XEXP (XEXP (src, 0), 0); 1073 } 1074 1075 src = xtensa_legitimize_tls_address (src); 1076 if (addend) 1077 { 1078 src = gen_rtx_PLUS (mode, src, addend); 1079 src = force_operand (src, dst); 1080 } 1081 emit_move_insn (dst, src); 1082 return 1; 1083 } 1084 1085 if (! TARGET_AUTO_LITPOOLS && ! TARGET_CONST16) 1086 { 1087 /* Try to emit MOVI + SLLI sequence, that is smaller 1088 than L32R + literal. */ 1089 if (optimize_size && mode == SImode && CONST_INT_P (src) 1090 && register_operand (dst, mode)) 1091 { 1092 HOST_WIDE_INT srcval = INTVAL (src); 1093 int shift = ctz_hwi (srcval); 1094 1095 if (xtensa_simm12b (srcval >> shift)) 1096 { 1097 emit_move_insn (dst, GEN_INT (srcval >> shift)); 1098 emit_insn (gen_ashlsi3_internal (dst, dst, GEN_INT (shift))); 1099 return 1; 1100 } 1101 } 1102 1103 src = force_const_mem (SImode, src); 1104 operands[1] = src; 1105 } 1106 1107 /* PC-relative loads are always SImode, and CONST16 is only 1108 supported in the movsi pattern, so add a SUBREG for any other 1109 (smaller) mode. */ 1110 1111 if (mode != SImode) 1112 { 1113 if (register_operand (dst, mode)) 1114 { 1115 emit_move_insn (simplify_gen_subreg (SImode, dst, mode, 0), src); 1116 return 1; 1117 } 1118 else 1119 { 1120 src = force_reg (SImode, src); 1121 src = gen_lowpart_SUBREG (mode, src); 1122 operands[1] = src; 1123 } 1124 } 1125 } 1126 1127 if (!(reload_in_progress | reload_completed) 1128 && !xtensa_valid_move (mode, operands)) 1129 operands[1] = force_reg (mode, operands[1]); 1130 1131 operands[1] = xtensa_copy_incoming_a7 (operands[1]); 1132 1133 /* During reload we don't want to emit (subreg:X (mem:Y)) since that 1134 instruction won't be recognized after reload, so we remove the 1135 subreg and adjust mem accordingly. */ 1136 if (reload_in_progress) 1137 { 1138 operands[0] = fixup_subreg_mem (operands[0]); 1139 operands[1] = fixup_subreg_mem (operands[1]); 1140 } 1141 return 0; 1142 } 1143 1144 1145 static rtx 1146 fixup_subreg_mem (rtx x) 1147 { 1148 if (GET_CODE (x) == SUBREG 1149 && GET_CODE (SUBREG_REG (x)) == REG 1150 && REGNO (SUBREG_REG (x)) >= FIRST_PSEUDO_REGISTER) 1151 { 1152 rtx temp = 1153 gen_rtx_SUBREG (GET_MODE (x), 1154 reg_equiv_mem (REGNO (SUBREG_REG (x))), 1155 SUBREG_BYTE (x)); 1156 x = alter_subreg (&temp, true); 1157 } 1158 return x; 1159 } 1160 1161 1162 /* Check if an incoming argument in a7 is expected to be used soon and 1163 if OPND is a register or register pair that includes a7. If so, 1164 create a new pseudo and copy a7 into that pseudo at the very 1165 beginning of the function, followed by the special "set_frame_ptr" 1166 unspec_volatile insn. The return value is either the original 1167 operand, if it is not a7, or the new pseudo containing a copy of 1168 the incoming argument. This is necessary because the register 1169 allocator will ignore conflicts with a7 and may either assign some 1170 other pseudo to a7 or use a7 as the hard_frame_pointer, clobbering 1171 the incoming argument in a7. By copying the argument out of a7 as 1172 the very first thing, and then immediately following that with an 1173 unspec_volatile to keep the scheduler away, we should avoid any 1174 problems. Putting the set_frame_ptr insn at the beginning, with 1175 only the a7 copy before it, also makes it easier for the prologue 1176 expander to initialize the frame pointer after the a7 copy and to 1177 fix up the a7 copy to use the stack pointer instead of the frame 1178 pointer. */ 1179 1180 rtx 1181 xtensa_copy_incoming_a7 (rtx opnd) 1182 { 1183 rtx entry_insns = 0; 1184 rtx reg, tmp; 1185 machine_mode mode; 1186 1187 if (!cfun->machine->need_a7_copy) 1188 return opnd; 1189 1190 /* This function should never be called again once a7 has been copied. */ 1191 gcc_assert (!cfun->machine->set_frame_ptr_insn); 1192 1193 mode = GET_MODE (opnd); 1194 1195 /* The operand using a7 may come in a later instruction, so just return 1196 the original operand if it doesn't use a7. */ 1197 reg = opnd; 1198 if (GET_CODE (reg) == SUBREG) 1199 { 1200 gcc_assert (SUBREG_BYTE (reg) == 0); 1201 reg = SUBREG_REG (reg); 1202 } 1203 if (GET_CODE (reg) != REG 1204 || REGNO (reg) > A7_REG 1205 || REGNO (reg) + hard_regno_nregs (A7_REG, mode) <= A7_REG) 1206 return opnd; 1207 1208 /* 1-word args will always be in a7; 2-word args in a6/a7. */ 1209 gcc_assert (REGNO (reg) + hard_regno_nregs (A7_REG, mode) - 1 == A7_REG); 1210 1211 cfun->machine->need_a7_copy = false; 1212 1213 /* Copy a7 to a new pseudo at the function entry. Use gen_raw_REG to 1214 create the REG for a7 so that hard_frame_pointer_rtx is not used. */ 1215 1216 start_sequence (); 1217 tmp = gen_reg_rtx (mode); 1218 1219 switch (mode) 1220 { 1221 case E_DFmode: 1222 case E_DImode: 1223 /* Copy the value out of A7 here but keep the first word in A6 until 1224 after the set_frame_ptr insn. Otherwise, the register allocator 1225 may decide to put "subreg (tmp, 0)" in A7 and clobber the incoming 1226 value. */ 1227 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 4), 1228 gen_raw_REG (SImode, A7_REG))); 1229 break; 1230 case E_SFmode: 1231 emit_insn (gen_movsf_internal (tmp, gen_raw_REG (mode, A7_REG))); 1232 break; 1233 case E_SImode: 1234 emit_insn (gen_movsi_internal (tmp, gen_raw_REG (mode, A7_REG))); 1235 break; 1236 case E_HImode: 1237 emit_insn (gen_movhi_internal (tmp, gen_raw_REG (mode, A7_REG))); 1238 break; 1239 case E_QImode: 1240 emit_insn (gen_movqi_internal (tmp, gen_raw_REG (mode, A7_REG))); 1241 break; 1242 default: 1243 gcc_unreachable (); 1244 } 1245 1246 cfun->machine->set_frame_ptr_insn = emit_insn (gen_set_frame_ptr ()); 1247 1248 /* For DF and DI mode arguments, copy the incoming value in A6 now. */ 1249 if (mode == DFmode || mode == DImode) 1250 emit_insn (gen_movsi_internal (gen_rtx_SUBREG (SImode, tmp, 0), 1251 gen_rtx_REG (SImode, A7_REG - 1))); 1252 entry_insns = get_insns (); 1253 end_sequence (); 1254 1255 if (cfun->machine->vararg_a7) 1256 { 1257 /* This is called from within builtin_saveregs, which will insert the 1258 saveregs code at the function entry, ahead of anything placed at 1259 the function entry now. Instead, save the sequence to be inserted 1260 at the beginning of the saveregs code. */ 1261 cfun->machine->vararg_a7_copy = entry_insns; 1262 } 1263 else 1264 { 1265 /* Put entry_insns after the NOTE that starts the function. If 1266 this is inside a start_sequence, make the outer-level insn 1267 chain current, so the code is placed at the start of the 1268 function. */ 1269 push_topmost_sequence (); 1270 /* Do not use entry_of_function() here. This is called from within 1271 expand_function_start, when the CFG still holds GIMPLE. */ 1272 emit_insn_after (entry_insns, get_insns ()); 1273 pop_topmost_sequence (); 1274 } 1275 1276 return tmp; 1277 } 1278 1279 1280 /* Try to expand a block move operation to a sequence of RTL move 1281 instructions. If not optimizing, or if the block size is not a 1282 constant, or if the block is too large, the expansion fails and GCC 1283 falls back to calling memcpy(). 1284 1285 operands[0] is the destination 1286 operands[1] is the source 1287 operands[2] is the length 1288 operands[3] is the alignment */ 1289 1290 int 1291 xtensa_expand_block_move (rtx *operands) 1292 { 1293 static const machine_mode mode_from_align[] = 1294 { 1295 VOIDmode, QImode, HImode, VOIDmode, SImode, 1296 }; 1297 1298 rtx dst_mem = operands[0]; 1299 rtx src_mem = operands[1]; 1300 HOST_WIDE_INT bytes, align; 1301 int num_pieces, move_ratio; 1302 rtx temp[2]; 1303 machine_mode mode[2]; 1304 int amount[2]; 1305 bool active[2]; 1306 int phase = 0; 1307 int next; 1308 int offset_ld = 0; 1309 int offset_st = 0; 1310 rtx x; 1311 1312 /* If this is not a fixed size move, just call memcpy. */ 1313 if (!optimize || (GET_CODE (operands[2]) != CONST_INT)) 1314 return 0; 1315 1316 bytes = INTVAL (operands[2]); 1317 align = INTVAL (operands[3]); 1318 1319 /* Anything to move? */ 1320 if (bytes <= 0) 1321 return 0; 1322 1323 if (align > MOVE_MAX) 1324 align = MOVE_MAX; 1325 1326 /* Decide whether to expand inline based on the optimization level. */ 1327 move_ratio = 4; 1328 if (optimize > 2) 1329 move_ratio = LARGEST_MOVE_RATIO; 1330 num_pieces = (bytes / align) + (bytes % align); /* Close enough anyway. */ 1331 if (num_pieces > move_ratio) 1332 return 0; 1333 1334 x = XEXP (dst_mem, 0); 1335 if (!REG_P (x)) 1336 { 1337 x = force_reg (Pmode, x); 1338 dst_mem = replace_equiv_address (dst_mem, x); 1339 } 1340 1341 x = XEXP (src_mem, 0); 1342 if (!REG_P (x)) 1343 { 1344 x = force_reg (Pmode, x); 1345 src_mem = replace_equiv_address (src_mem, x); 1346 } 1347 1348 active[0] = active[1] = false; 1349 1350 do 1351 { 1352 next = phase; 1353 phase ^= 1; 1354 1355 if (bytes > 0) 1356 { 1357 int next_amount; 1358 1359 next_amount = (bytes >= 4 ? 4 : (bytes >= 2 ? 2 : 1)); 1360 next_amount = MIN (next_amount, align); 1361 1362 amount[next] = next_amount; 1363 mode[next] = mode_from_align[next_amount]; 1364 temp[next] = gen_reg_rtx (mode[next]); 1365 1366 x = adjust_address (src_mem, mode[next], offset_ld); 1367 emit_insn (gen_rtx_SET (temp[next], x)); 1368 1369 offset_ld += next_amount; 1370 bytes -= next_amount; 1371 active[next] = true; 1372 } 1373 1374 if (active[phase]) 1375 { 1376 active[phase] = false; 1377 1378 x = adjust_address (dst_mem, mode[phase], offset_st); 1379 emit_insn (gen_rtx_SET (x, temp[phase])); 1380 1381 offset_st += amount[phase]; 1382 } 1383 } 1384 while (active[next]); 1385 1386 return 1; 1387 } 1388 1389 1390 void 1391 xtensa_expand_nonlocal_goto (rtx *operands) 1392 { 1393 rtx goto_handler = operands[1]; 1394 rtx containing_fp = operands[3]; 1395 1396 /* Generate a call to "__xtensa_nonlocal_goto" (in libgcc); the code 1397 is too big to generate in-line. */ 1398 1399 if (GET_CODE (containing_fp) != REG) 1400 containing_fp = force_reg (Pmode, containing_fp); 1401 1402 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_nonlocal_goto"), 1403 LCT_NORMAL, VOIDmode, 1404 containing_fp, Pmode, 1405 goto_handler, Pmode); 1406 } 1407 1408 1409 static struct machine_function * 1410 xtensa_init_machine_status (void) 1411 { 1412 return ggc_cleared_alloc<machine_function> (); 1413 } 1414 1415 1416 /* Shift VAL of mode MODE left by COUNT bits. */ 1417 1418 static inline rtx 1419 xtensa_expand_mask_and_shift (rtx val, machine_mode mode, rtx count) 1420 { 1421 val = expand_simple_binop (SImode, AND, val, GEN_INT (GET_MODE_MASK (mode)), 1422 NULL_RTX, 1, OPTAB_DIRECT); 1423 return expand_simple_binop (SImode, ASHIFT, val, count, 1424 NULL_RTX, 1, OPTAB_DIRECT); 1425 } 1426 1427 1428 /* Structure to hold the initial parameters for a compare_and_swap operation 1429 in HImode and QImode. */ 1430 1431 struct alignment_context 1432 { 1433 rtx memsi; /* SI aligned memory location. */ 1434 rtx shift; /* Bit offset with regard to lsb. */ 1435 rtx modemask; /* Mask of the HQImode shifted by SHIFT bits. */ 1436 rtx modemaski; /* ~modemask */ 1437 }; 1438 1439 1440 /* Initialize structure AC for word access to HI and QI mode memory. */ 1441 1442 static void 1443 init_alignment_context (struct alignment_context *ac, rtx mem) 1444 { 1445 machine_mode mode = GET_MODE (mem); 1446 rtx byteoffset = NULL_RTX; 1447 bool aligned = (MEM_ALIGN (mem) >= GET_MODE_BITSIZE (SImode)); 1448 1449 if (aligned) 1450 ac->memsi = adjust_address (mem, SImode, 0); /* Memory is aligned. */ 1451 else 1452 { 1453 /* Alignment is unknown. */ 1454 rtx addr, align; 1455 1456 /* Force the address into a register. */ 1457 addr = force_reg (Pmode, XEXP (mem, 0)); 1458 1459 /* Align it to SImode. */ 1460 align = expand_simple_binop (Pmode, AND, addr, 1461 GEN_INT (-GET_MODE_SIZE (SImode)), 1462 NULL_RTX, 1, OPTAB_DIRECT); 1463 /* Generate MEM. */ 1464 ac->memsi = gen_rtx_MEM (SImode, align); 1465 MEM_VOLATILE_P (ac->memsi) = MEM_VOLATILE_P (mem); 1466 set_mem_alias_set (ac->memsi, ALIAS_SET_MEMORY_BARRIER); 1467 set_mem_align (ac->memsi, GET_MODE_BITSIZE (SImode)); 1468 1469 byteoffset = expand_simple_binop (Pmode, AND, addr, 1470 GEN_INT (GET_MODE_SIZE (SImode) - 1), 1471 NULL_RTX, 1, OPTAB_DIRECT); 1472 } 1473 1474 /* Calculate shiftcount. */ 1475 if (TARGET_BIG_ENDIAN) 1476 { 1477 ac->shift = GEN_INT (GET_MODE_SIZE (SImode) - GET_MODE_SIZE (mode)); 1478 if (!aligned) 1479 ac->shift = expand_simple_binop (SImode, MINUS, ac->shift, byteoffset, 1480 NULL_RTX, 1, OPTAB_DIRECT); 1481 } 1482 else 1483 { 1484 if (aligned) 1485 ac->shift = NULL_RTX; 1486 else 1487 ac->shift = byteoffset; 1488 } 1489 1490 if (ac->shift != NULL_RTX) 1491 { 1492 /* Shift is the byte count, but we need the bitcount. */ 1493 gcc_assert (exact_log2 (BITS_PER_UNIT) >= 0); 1494 ac->shift = expand_simple_binop (SImode, ASHIFT, ac->shift, 1495 GEN_INT (exact_log2 (BITS_PER_UNIT)), 1496 NULL_RTX, 1, OPTAB_DIRECT); 1497 ac->modemask = expand_simple_binop (SImode, ASHIFT, 1498 GEN_INT (GET_MODE_MASK (mode)), 1499 ac->shift, 1500 NULL_RTX, 1, OPTAB_DIRECT); 1501 } 1502 else 1503 ac->modemask = GEN_INT (GET_MODE_MASK (mode)); 1504 1505 ac->modemaski = expand_simple_unop (SImode, NOT, ac->modemask, NULL_RTX, 1); 1506 } 1507 1508 1509 /* Expand an atomic compare and swap operation for HImode and QImode. 1510 MEM is the memory location, CMP the old value to compare MEM with 1511 and NEW_RTX the value to set if CMP == MEM. */ 1512 1513 void 1514 xtensa_expand_compare_and_swap (rtx target, rtx mem, rtx cmp, rtx new_rtx) 1515 { 1516 machine_mode mode = GET_MODE (mem); 1517 struct alignment_context ac; 1518 rtx tmp, cmpv, newv, val; 1519 rtx oldval = gen_reg_rtx (SImode); 1520 rtx res = gen_reg_rtx (SImode); 1521 rtx_code_label *csloop = gen_label_rtx (); 1522 rtx_code_label *csend = gen_label_rtx (); 1523 1524 init_alignment_context (&ac, mem); 1525 1526 if (ac.shift != NULL_RTX) 1527 { 1528 cmp = xtensa_expand_mask_and_shift (cmp, mode, ac.shift); 1529 new_rtx = xtensa_expand_mask_and_shift (new_rtx, mode, ac.shift); 1530 } 1531 1532 /* Load the surrounding word into VAL with the MEM value masked out. */ 1533 val = force_reg (SImode, expand_simple_binop (SImode, AND, ac.memsi, 1534 ac.modemaski, NULL_RTX, 1, 1535 OPTAB_DIRECT)); 1536 emit_label (csloop); 1537 1538 /* Patch CMP and NEW_RTX into VAL at correct position. */ 1539 cmpv = force_reg (SImode, expand_simple_binop (SImode, IOR, cmp, val, 1540 NULL_RTX, 1, OPTAB_DIRECT)); 1541 newv = force_reg (SImode, expand_simple_binop (SImode, IOR, new_rtx, val, 1542 NULL_RTX, 1, OPTAB_DIRECT)); 1543 1544 /* Jump to end if we're done. */ 1545 emit_insn (gen_sync_compare_and_swapsi (res, ac.memsi, cmpv, newv)); 1546 emit_cmp_and_jump_insns (res, cmpv, EQ, const0_rtx, SImode, true, csend); 1547 1548 /* Check for changes outside mode. */ 1549 emit_move_insn (oldval, val); 1550 tmp = expand_simple_binop (SImode, AND, res, ac.modemaski, 1551 val, 1, OPTAB_DIRECT); 1552 if (tmp != val) 1553 emit_move_insn (val, tmp); 1554 1555 /* Loop internal if so. */ 1556 emit_cmp_and_jump_insns (oldval, val, NE, const0_rtx, SImode, true, csloop); 1557 1558 emit_label (csend); 1559 1560 /* Return the correct part of the bitfield. */ 1561 convert_move (target, 1562 (ac.shift == NULL_RTX ? res 1563 : expand_simple_binop (SImode, LSHIFTRT, res, ac.shift, 1564 NULL_RTX, 1, OPTAB_DIRECT)), 1565 1); 1566 } 1567 1568 1569 /* Expand an atomic operation CODE of mode MODE (either HImode or QImode -- 1570 the default expansion works fine for SImode). MEM is the memory location 1571 and VAL the value to play with. If AFTER is true then store the value 1572 MEM holds after the operation, if AFTER is false then store the value MEM 1573 holds before the operation. If TARGET is zero then discard that value, else 1574 store it to TARGET. */ 1575 1576 void 1577 xtensa_expand_atomic (enum rtx_code code, rtx target, rtx mem, rtx val, 1578 bool after) 1579 { 1580 machine_mode mode = GET_MODE (mem); 1581 struct alignment_context ac; 1582 rtx_code_label *csloop = gen_label_rtx (); 1583 rtx cmp, tmp; 1584 rtx old = gen_reg_rtx (SImode); 1585 rtx new_rtx = gen_reg_rtx (SImode); 1586 rtx orig = NULL_RTX; 1587 1588 init_alignment_context (&ac, mem); 1589 1590 /* Prepare values before the compare-and-swap loop. */ 1591 if (ac.shift != NULL_RTX) 1592 val = xtensa_expand_mask_and_shift (val, mode, ac.shift); 1593 switch (code) 1594 { 1595 case PLUS: 1596 case MINUS: 1597 orig = gen_reg_rtx (SImode); 1598 convert_move (orig, val, 1); 1599 break; 1600 1601 case SET: 1602 case IOR: 1603 case XOR: 1604 break; 1605 1606 case MULT: /* NAND */ 1607 case AND: 1608 /* val = "11..1<val>11..1" */ 1609 val = expand_simple_binop (SImode, XOR, val, ac.modemaski, 1610 NULL_RTX, 1, OPTAB_DIRECT); 1611 break; 1612 1613 default: 1614 gcc_unreachable (); 1615 } 1616 1617 /* Load full word. Subsequent loads are performed by S32C1I. */ 1618 cmp = force_reg (SImode, ac.memsi); 1619 1620 emit_label (csloop); 1621 emit_move_insn (old, cmp); 1622 1623 switch (code) 1624 { 1625 case PLUS: 1626 case MINUS: 1627 val = expand_simple_binop (SImode, code, old, orig, 1628 NULL_RTX, 1, OPTAB_DIRECT); 1629 val = expand_simple_binop (SImode, AND, val, ac.modemask, 1630 NULL_RTX, 1, OPTAB_DIRECT); 1631 /* FALLTHRU */ 1632 case SET: 1633 tmp = expand_simple_binop (SImode, AND, old, ac.modemaski, 1634 NULL_RTX, 1, OPTAB_DIRECT); 1635 tmp = expand_simple_binop (SImode, IOR, tmp, val, 1636 new_rtx, 1, OPTAB_DIRECT); 1637 break; 1638 1639 case AND: 1640 case IOR: 1641 case XOR: 1642 tmp = expand_simple_binop (SImode, code, old, val, 1643 new_rtx, 1, OPTAB_DIRECT); 1644 break; 1645 1646 case MULT: /* NAND */ 1647 tmp = expand_simple_binop (SImode, AND, old, val, 1648 NULL_RTX, 1, OPTAB_DIRECT); 1649 tmp = expand_simple_binop (SImode, XOR, tmp, ac.modemask, 1650 new_rtx, 1, OPTAB_DIRECT); 1651 break; 1652 1653 default: 1654 gcc_unreachable (); 1655 } 1656 1657 if (tmp != new_rtx) 1658 emit_move_insn (new_rtx, tmp); 1659 emit_insn (gen_sync_compare_and_swapsi (cmp, ac.memsi, old, new_rtx)); 1660 emit_cmp_and_jump_insns (cmp, old, NE, const0_rtx, SImode, true, csloop); 1661 1662 if (target) 1663 { 1664 tmp = (after ? new_rtx : cmp); 1665 convert_move (target, 1666 (ac.shift == NULL_RTX ? tmp 1667 : expand_simple_binop (SImode, LSHIFTRT, tmp, ac.shift, 1668 NULL_RTX, 1, OPTAB_DIRECT)), 1669 1); 1670 } 1671 } 1672 1673 1674 void 1675 xtensa_setup_frame_addresses (void) 1676 { 1677 /* Set flag to cause TARGET_FRAME_POINTER_REQUIRED to return true. */ 1678 cfun->machine->accesses_prev_frame = 1; 1679 1680 if (TARGET_WINDOWED_ABI) 1681 emit_library_call 1682 (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_libgcc_window_spill"), 1683 LCT_NORMAL, VOIDmode); 1684 } 1685 1686 1687 /* Emit the assembly for the end of a zero-cost loop. Normally we just emit 1688 a comment showing where the end of the loop is. However, if there is a 1689 label or a branch at the end of the loop then we need to place a nop 1690 there. If the loop ends with a label we need the nop so that branches 1691 targeting that label will target the nop (and thus remain in the loop), 1692 instead of targeting the instruction after the loop (and thus exiting 1693 the loop). If the loop ends with a branch, we need the nop in case the 1694 branch is targeting a location inside the loop. When the branch 1695 executes it will cause the loop count to be decremented even if it is 1696 taken (because it is the last instruction in the loop), so we need to 1697 nop after the branch to prevent the loop count from being decremented 1698 when the branch is taken. */ 1699 1700 void 1701 xtensa_emit_loop_end (rtx_insn *insn, rtx *operands) 1702 { 1703 char done = 0; 1704 1705 for (insn = PREV_INSN (insn); insn && !done; insn = PREV_INSN (insn)) 1706 { 1707 switch (GET_CODE (insn)) 1708 { 1709 case NOTE: 1710 case BARRIER: 1711 break; 1712 1713 case CODE_LABEL: 1714 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); 1715 done = 1; 1716 break; 1717 1718 default: 1719 { 1720 rtx body = PATTERN (insn); 1721 1722 if (JUMP_P (body)) 1723 { 1724 output_asm_insn (TARGET_DENSITY ? "nop.n" : "nop", operands); 1725 done = 1; 1726 } 1727 else if ((GET_CODE (body) != USE) 1728 && (GET_CODE (body) != CLOBBER)) 1729 done = 1; 1730 } 1731 break; 1732 } 1733 } 1734 1735 output_asm_insn ("%1_LEND:", operands); 1736 } 1737 1738 1739 char * 1740 xtensa_emit_branch (bool inverted, bool immed, rtx *operands) 1741 { 1742 static char result[64]; 1743 enum rtx_code code; 1744 const char *op; 1745 1746 code = GET_CODE (operands[3]); 1747 switch (code) 1748 { 1749 case EQ: op = inverted ? "ne" : "eq"; break; 1750 case NE: op = inverted ? "eq" : "ne"; break; 1751 case LT: op = inverted ? "ge" : "lt"; break; 1752 case GE: op = inverted ? "lt" : "ge"; break; 1753 case LTU: op = inverted ? "geu" : "ltu"; break; 1754 case GEU: op = inverted ? "ltu" : "geu"; break; 1755 default: gcc_unreachable (); 1756 } 1757 1758 if (immed) 1759 { 1760 if (INTVAL (operands[1]) == 0) 1761 sprintf (result, "b%sz%s\t%%0, %%2", op, 1762 (TARGET_DENSITY && (code == EQ || code == NE)) ? ".n" : ""); 1763 else 1764 sprintf (result, "b%si\t%%0, %%d1, %%2", op); 1765 } 1766 else 1767 sprintf (result, "b%s\t%%0, %%1, %%2", op); 1768 1769 return result; 1770 } 1771 1772 1773 char * 1774 xtensa_emit_bit_branch (bool inverted, bool immed, rtx *operands) 1775 { 1776 static char result[64]; 1777 const char *op; 1778 1779 switch (GET_CODE (operands[3])) 1780 { 1781 case EQ: op = inverted ? "bs" : "bc"; break; 1782 case NE: op = inverted ? "bc" : "bs"; break; 1783 default: gcc_unreachable (); 1784 } 1785 1786 if (immed) 1787 { 1788 unsigned bitnum = INTVAL (operands[1]) & 0x1f; 1789 operands[1] = GEN_INT (bitnum); 1790 sprintf (result, "b%si\t%%0, %%d1, %%2", op); 1791 } 1792 else 1793 sprintf (result, "b%s\t%%0, %%1, %%2", op); 1794 1795 return result; 1796 } 1797 1798 1799 char * 1800 xtensa_emit_movcc (bool inverted, bool isfp, bool isbool, rtx *operands) 1801 { 1802 static char result[64]; 1803 enum rtx_code code; 1804 const char *op; 1805 1806 code = GET_CODE (operands[4]); 1807 if (isbool) 1808 { 1809 switch (code) 1810 { 1811 case EQ: op = inverted ? "t" : "f"; break; 1812 case NE: op = inverted ? "f" : "t"; break; 1813 default: gcc_unreachable (); 1814 } 1815 } 1816 else 1817 { 1818 switch (code) 1819 { 1820 case EQ: op = inverted ? "nez" : "eqz"; break; 1821 case NE: op = inverted ? "eqz" : "nez"; break; 1822 case LT: op = inverted ? "gez" : "ltz"; break; 1823 case GE: op = inverted ? "ltz" : "gez"; break; 1824 default: gcc_unreachable (); 1825 } 1826 } 1827 1828 sprintf (result, "mov%s%s\t%%0, %%%d, %%1", 1829 op, isfp ? ".s" : "", inverted ? 3 : 2); 1830 return result; 1831 } 1832 1833 1834 char * 1835 xtensa_emit_call (int callop, rtx *operands) 1836 { 1837 static char result[64]; 1838 rtx tgt = operands[callop]; 1839 1840 if (GET_CODE (tgt) == CONST_INT) 1841 sprintf (result, "call%d\t" HOST_WIDE_INT_PRINT_HEX, 1842 WINDOW_SIZE, INTVAL (tgt)); 1843 else if (register_operand (tgt, VOIDmode)) 1844 sprintf (result, "callx%d\t%%%d", WINDOW_SIZE, callop); 1845 else 1846 sprintf (result, "call%d\t%%%d", WINDOW_SIZE, callop); 1847 1848 return result; 1849 } 1850 1851 1852 bool 1853 xtensa_legitimate_address_p (machine_mode mode, rtx addr, bool strict) 1854 { 1855 /* Allow constant pool addresses. */ 1856 if (mode != BLKmode && GET_MODE_SIZE (mode) >= UNITS_PER_WORD 1857 && ! TARGET_CONST16 && constantpool_address_p (addr) 1858 && ! xtensa_tls_referenced_p (addr)) 1859 return true; 1860 1861 while (GET_CODE (addr) == SUBREG) 1862 addr = SUBREG_REG (addr); 1863 1864 /* Allow base registers. */ 1865 if (GET_CODE (addr) == REG && BASE_REG_P (addr, strict)) 1866 return true; 1867 1868 /* Check for "register + offset" addressing. */ 1869 if (GET_CODE (addr) == PLUS) 1870 { 1871 rtx xplus0 = XEXP (addr, 0); 1872 rtx xplus1 = XEXP (addr, 1); 1873 enum rtx_code code0; 1874 enum rtx_code code1; 1875 1876 while (GET_CODE (xplus0) == SUBREG) 1877 xplus0 = SUBREG_REG (xplus0); 1878 code0 = GET_CODE (xplus0); 1879 1880 while (GET_CODE (xplus1) == SUBREG) 1881 xplus1 = SUBREG_REG (xplus1); 1882 code1 = GET_CODE (xplus1); 1883 1884 /* Swap operands if necessary so the register is first. */ 1885 if (code0 != REG && code1 == REG) 1886 { 1887 xplus0 = XEXP (addr, 1); 1888 xplus1 = XEXP (addr, 0); 1889 code0 = GET_CODE (xplus0); 1890 code1 = GET_CODE (xplus1); 1891 } 1892 1893 if (code0 == REG && BASE_REG_P (xplus0, strict) 1894 && code1 == CONST_INT 1895 && xtensa_mem_offset (INTVAL (xplus1), mode)) 1896 return true; 1897 } 1898 1899 return false; 1900 } 1901 1902 1903 /* Construct the SYMBOL_REF for the _TLS_MODULE_BASE_ symbol. */ 1904 1905 static GTY(()) rtx xtensa_tls_module_base_symbol; 1906 1907 static rtx 1908 xtensa_tls_module_base (void) 1909 { 1910 if (! xtensa_tls_module_base_symbol) 1911 { 1912 xtensa_tls_module_base_symbol = 1913 gen_rtx_SYMBOL_REF (Pmode, "_TLS_MODULE_BASE_"); 1914 SYMBOL_REF_FLAGS (xtensa_tls_module_base_symbol) 1915 |= TLS_MODEL_GLOBAL_DYNAMIC << SYMBOL_FLAG_TLS_SHIFT; 1916 } 1917 1918 return xtensa_tls_module_base_symbol; 1919 } 1920 1921 1922 static rtx_insn * 1923 xtensa_call_tls_desc (rtx sym, rtx *retp) 1924 { 1925 rtx fn, arg, a_io; 1926 rtx_insn *call_insn, *insns; 1927 1928 start_sequence (); 1929 fn = gen_reg_rtx (Pmode); 1930 arg = gen_reg_rtx (Pmode); 1931 a_io = gen_rtx_REG (Pmode, WINDOW_SIZE + 2); 1932 1933 emit_insn (gen_tls_func (fn, sym)); 1934 emit_insn (gen_tls_arg (arg, sym)); 1935 emit_move_insn (a_io, arg); 1936 call_insn = emit_call_insn (gen_tls_call (a_io, fn, sym, const1_rtx)); 1937 use_reg (&CALL_INSN_FUNCTION_USAGE (call_insn), a_io); 1938 insns = get_insns (); 1939 end_sequence (); 1940 1941 *retp = a_io; 1942 return insns; 1943 } 1944 1945 1946 static rtx 1947 xtensa_legitimize_tls_address (rtx x) 1948 { 1949 unsigned int model = SYMBOL_REF_TLS_MODEL (x); 1950 rtx dest, tp, ret, modbase, base, addend; 1951 rtx_insn *insns; 1952 1953 dest = gen_reg_rtx (Pmode); 1954 switch (model) 1955 { 1956 case TLS_MODEL_GLOBAL_DYNAMIC: 1957 insns = xtensa_call_tls_desc (x, &ret); 1958 emit_libcall_block (insns, dest, ret, x); 1959 break; 1960 1961 case TLS_MODEL_LOCAL_DYNAMIC: 1962 base = gen_reg_rtx (Pmode); 1963 modbase = xtensa_tls_module_base (); 1964 insns = xtensa_call_tls_desc (modbase, &ret); 1965 emit_libcall_block (insns, base, ret, modbase); 1966 addend = force_reg (SImode, gen_sym_DTPOFF (x)); 1967 emit_insn (gen_addsi3 (dest, base, addend)); 1968 break; 1969 1970 case TLS_MODEL_INITIAL_EXEC: 1971 case TLS_MODEL_LOCAL_EXEC: 1972 tp = gen_reg_rtx (SImode); 1973 emit_insn (gen_get_thread_pointersi (tp)); 1974 addend = force_reg (SImode, gen_sym_TPOFF (x)); 1975 emit_insn (gen_addsi3 (dest, tp, addend)); 1976 break; 1977 1978 default: 1979 gcc_unreachable (); 1980 } 1981 1982 return dest; 1983 } 1984 1985 1986 rtx 1987 xtensa_legitimize_address (rtx x, 1988 rtx oldx ATTRIBUTE_UNUSED, 1989 machine_mode mode) 1990 { 1991 if (xtensa_tls_symbol_p (x)) 1992 return xtensa_legitimize_tls_address (x); 1993 1994 if (GET_CODE (x) == PLUS) 1995 { 1996 rtx plus0 = XEXP (x, 0); 1997 rtx plus1 = XEXP (x, 1); 1998 1999 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG) 2000 { 2001 plus0 = XEXP (x, 1); 2002 plus1 = XEXP (x, 0); 2003 } 2004 2005 /* Try to split up the offset to use an ADDMI instruction. */ 2006 if (GET_CODE (plus0) == REG 2007 && GET_CODE (plus1) == CONST_INT 2008 && !xtensa_mem_offset (INTVAL (plus1), mode) 2009 && !xtensa_simm8 (INTVAL (plus1)) 2010 && xtensa_mem_offset (INTVAL (plus1) & 0xff, mode) 2011 && xtensa_simm8x256 (INTVAL (plus1) & ~0xff)) 2012 { 2013 rtx temp = gen_reg_rtx (Pmode); 2014 rtx addmi_offset = GEN_INT (INTVAL (plus1) & ~0xff); 2015 emit_insn (gen_rtx_SET (temp, gen_rtx_PLUS (Pmode, plus0, 2016 addmi_offset))); 2017 return gen_rtx_PLUS (Pmode, temp, GEN_INT (INTVAL (plus1) & 0xff)); 2018 } 2019 } 2020 2021 return x; 2022 } 2023 2024 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. 2025 2026 Treat constant-pool references as "mode dependent" since they can 2027 only be accessed with SImode loads. This works around a bug in the 2028 combiner where a constant pool reference is temporarily converted 2029 to an HImode load, which is then assumed to zero-extend based on 2030 our definition of LOAD_EXTEND_OP. This is wrong because the high 2031 bits of a 16-bit value in the constant pool are now sign-extended 2032 by default. */ 2033 2034 static bool 2035 xtensa_mode_dependent_address_p (const_rtx addr, 2036 addr_space_t as ATTRIBUTE_UNUSED) 2037 { 2038 return constantpool_address_p (addr); 2039 } 2040 2041 /* Return TRUE if X contains any TLS symbol references. */ 2042 2043 bool 2044 xtensa_tls_referenced_p (rtx x) 2045 { 2046 if (! targetm.have_tls) 2047 return false; 2048 2049 subrtx_iterator::array_type array; 2050 FOR_EACH_SUBRTX (iter, array, x, ALL) 2051 { 2052 const_rtx x = *iter; 2053 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0) 2054 return true; 2055 2056 /* Ignore TLS references that have already been legitimized. */ 2057 if (GET_CODE (x) == UNSPEC) 2058 switch (XINT (x, 1)) 2059 { 2060 case UNSPEC_TPOFF: 2061 case UNSPEC_DTPOFF: 2062 case UNSPEC_TLS_FUNC: 2063 case UNSPEC_TLS_ARG: 2064 case UNSPEC_TLS_CALL: 2065 iter.skip_subrtxes (); 2066 break; 2067 default: 2068 break; 2069 } 2070 } 2071 return false; 2072 } 2073 2074 2075 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 2076 2077 static bool 2078 xtensa_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 2079 { 2080 return xtensa_tls_referenced_p (x); 2081 } 2082 2083 2084 /* Return the debugger register number to use for 'regno'. */ 2085 2086 int 2087 xtensa_dbx_register_number (int regno) 2088 { 2089 int first = -1; 2090 2091 if (GP_REG_P (regno)) 2092 { 2093 regno -= GP_REG_FIRST; 2094 first = 0; 2095 } 2096 else if (BR_REG_P (regno)) 2097 { 2098 regno -= BR_REG_FIRST; 2099 first = 16; 2100 } 2101 else if (FP_REG_P (regno)) 2102 { 2103 regno -= FP_REG_FIRST; 2104 first = 48; 2105 } 2106 else if (ACC_REG_P (regno)) 2107 { 2108 first = 0x200; /* Start of Xtensa special registers. */ 2109 regno = 16; /* ACCLO is special register 16. */ 2110 } 2111 2112 /* When optimizing, we sometimes get asked about pseudo-registers 2113 that don't represent hard registers. Return 0 for these. */ 2114 if (first == -1) 2115 return 0; 2116 2117 return first + regno; 2118 } 2119 2120 2121 /* Argument support functions. */ 2122 2123 /* Initialize CUMULATIVE_ARGS for a function. */ 2124 2125 void 2126 init_cumulative_args (CUMULATIVE_ARGS *cum, int incoming) 2127 { 2128 cum->arg_words = 0; 2129 cum->incoming = incoming; 2130 } 2131 2132 2133 /* Advance the argument to the next argument position. */ 2134 2135 static void 2136 xtensa_function_arg_advance (cumulative_args_t cum, 2137 const function_arg_info &arg) 2138 { 2139 int words, max; 2140 int *arg_words; 2141 2142 arg_words = &get_cumulative_args (cum)->arg_words; 2143 max = MAX_ARGS_IN_REGISTERS; 2144 2145 words = ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1) 2146 / UNITS_PER_WORD); 2147 2148 if (*arg_words < max 2149 && (targetm.calls.must_pass_in_stack (arg) 2150 || *arg_words + words > max)) 2151 *arg_words = max; 2152 2153 *arg_words += words; 2154 } 2155 2156 2157 /* Return an RTL expression containing the register for the given argument, 2158 or 0 if the argument is to be passed on the stack. INCOMING_P is nonzero 2159 if this is an incoming argument to the current function. */ 2160 2161 static rtx 2162 xtensa_function_arg_1 (cumulative_args_t cum_v, const function_arg_info &arg, 2163 bool incoming_p) 2164 { 2165 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2166 int regbase, words, max; 2167 int *arg_words; 2168 int regno; 2169 2170 arg_words = &cum->arg_words; 2171 regbase = (incoming_p ? GP_ARG_FIRST : GP_OUTGOING_ARG_FIRST); 2172 max = MAX_ARGS_IN_REGISTERS; 2173 2174 words = ((arg.promoted_size_in_bytes () + UNITS_PER_WORD - 1) 2175 / UNITS_PER_WORD); 2176 2177 if (arg.type && (TYPE_ALIGN (arg.type) > BITS_PER_WORD)) 2178 { 2179 int align = MIN (TYPE_ALIGN (arg.type), STACK_BOUNDARY) / BITS_PER_WORD; 2180 *arg_words = (*arg_words + align - 1) & -align; 2181 } 2182 2183 if (*arg_words + words > max) 2184 return (rtx)0; 2185 2186 regno = regbase + *arg_words; 2187 2188 if (cum->incoming && regno <= A7_REG && regno + words > A7_REG) 2189 cfun->machine->need_a7_copy = TARGET_WINDOWED_ABI; 2190 2191 return gen_rtx_REG (arg.mode, regno); 2192 } 2193 2194 /* Implement TARGET_FUNCTION_ARG. */ 2195 2196 static rtx 2197 xtensa_function_arg (cumulative_args_t cum, const function_arg_info &arg) 2198 { 2199 return xtensa_function_arg_1 (cum, arg, false); 2200 } 2201 2202 /* Implement TARGET_FUNCTION_INCOMING_ARG. */ 2203 2204 static rtx 2205 xtensa_function_incoming_arg (cumulative_args_t cum, 2206 const function_arg_info &arg) 2207 { 2208 return xtensa_function_arg_1 (cum, arg, true); 2209 } 2210 2211 static unsigned int 2212 xtensa_function_arg_boundary (machine_mode mode, const_tree type) 2213 { 2214 unsigned int alignment; 2215 2216 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 2217 if (alignment < PARM_BOUNDARY) 2218 alignment = PARM_BOUNDARY; 2219 if (alignment > STACK_BOUNDARY) 2220 alignment = STACK_BOUNDARY; 2221 return alignment; 2222 } 2223 2224 2225 static bool 2226 xtensa_return_in_msb (const_tree valtype) 2227 { 2228 return (TARGET_BIG_ENDIAN 2229 && AGGREGATE_TYPE_P (valtype) 2230 && int_size_in_bytes (valtype) >= UNITS_PER_WORD); 2231 } 2232 2233 2234 static void 2235 xtensa_option_override (void) 2236 { 2237 int regno; 2238 machine_mode mode; 2239 2240 if (xtensa_windowed_abi == -1) 2241 xtensa_windowed_abi = TARGET_WINDOWED_ABI_DEFAULT; 2242 2243 if (! TARGET_THREADPTR) 2244 targetm.have_tls = false; 2245 2246 /* Use CONST16 in the absence of L32R. 2247 Set it in the TARGET_OPTION_OVERRIDE to avoid dependency on xtensa 2248 configuration in the xtensa-common.cc */ 2249 2250 if (!TARGET_L32R) 2251 target_flags |= MASK_CONST16; 2252 2253 if (!TARGET_BOOLEANS && TARGET_HARD_FLOAT) 2254 error ("boolean registers required for the floating-point option"); 2255 2256 /* Set up array giving whether a given register can hold a given mode. */ 2257 for (mode = VOIDmode; 2258 mode != MAX_MACHINE_MODE; 2259 mode = (machine_mode) ((int) mode + 1)) 2260 { 2261 int size = GET_MODE_SIZE (mode); 2262 enum mode_class mclass = GET_MODE_CLASS (mode); 2263 2264 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 2265 { 2266 int temp; 2267 2268 if (ACC_REG_P (regno)) 2269 temp = (TARGET_MAC16 2270 && (mclass == MODE_INT) && (size <= UNITS_PER_WORD)); 2271 else if (GP_REG_P (regno)) 2272 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD)); 2273 else if (FP_REG_P (regno)) 2274 temp = (TARGET_HARD_FLOAT && (mode == SFmode)); 2275 else if (BR_REG_P (regno)) 2276 temp = (TARGET_BOOLEANS && (mode == CCmode)); 2277 else 2278 temp = FALSE; 2279 2280 xtensa_hard_regno_mode_ok_p[(int) mode][regno] = temp; 2281 } 2282 } 2283 2284 init_machine_status = xtensa_init_machine_status; 2285 2286 /* Check PIC settings. PIC is only supported when using L32R 2287 instructions, and some targets need to always use PIC. */ 2288 if (flag_pic && TARGET_CONST16) 2289 error ("%<-f%s%> is not supported with CONST16 instructions", 2290 (flag_pic > 1 ? "PIC" : "pic")); 2291 else if (TARGET_FORCE_NO_PIC) 2292 flag_pic = 0; 2293 else if (XTENSA_ALWAYS_PIC) 2294 { 2295 if (TARGET_CONST16) 2296 error ("PIC is required but not supported with CONST16 instructions"); 2297 flag_pic = 1; 2298 } 2299 /* There's no need for -fPIC (as opposed to -fpic) on Xtensa. */ 2300 if (flag_pic > 1) 2301 flag_pic = 1; 2302 if (flag_pic && !flag_pie) 2303 flag_shlib = 1; 2304 2305 /* Hot/cold partitioning does not work on this architecture, because of 2306 constant pools (the load instruction cannot necessarily reach that far). 2307 Therefore disable it on this architecture. */ 2308 if (flag_reorder_blocks_and_partition) 2309 { 2310 flag_reorder_blocks_and_partition = 0; 2311 flag_reorder_blocks = 1; 2312 } 2313 } 2314 2315 /* Implement TARGET_HARD_REGNO_NREGS. */ 2316 2317 static unsigned int 2318 xtensa_hard_regno_nregs (unsigned int regno, machine_mode mode) 2319 { 2320 if (FP_REG_P (regno)) 2321 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_FPREG); 2322 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); 2323 } 2324 2325 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 2326 2327 static bool 2328 xtensa_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 2329 { 2330 return xtensa_hard_regno_mode_ok_p[mode][regno]; 2331 } 2332 2333 /* Implement TARGET_MODES_TIEABLE_P. */ 2334 2335 static bool 2336 xtensa_modes_tieable_p (machine_mode mode1, machine_mode mode2) 2337 { 2338 return ((GET_MODE_CLASS (mode1) == MODE_FLOAT 2339 || GET_MODE_CLASS (mode1) == MODE_COMPLEX_FLOAT) 2340 == (GET_MODE_CLASS (mode2) == MODE_FLOAT 2341 || GET_MODE_CLASS (mode2) == MODE_COMPLEX_FLOAT)); 2342 } 2343 2344 /* A C compound statement to output to stdio stream STREAM the 2345 assembler syntax for an instruction operand X. X is an RTL 2346 expression. 2347 2348 CODE is a value that can be used to specify one of several ways 2349 of printing the operand. It is used when identical operands 2350 must be printed differently depending on the context. CODE 2351 comes from the '%' specification that was used to request 2352 printing of the operand. If the specification was just '%DIGIT' 2353 then CODE is 0; if the specification was '%LTR DIGIT' then CODE 2354 is the ASCII code for LTR. 2355 2356 If X is a register, this macro should print the register's name. 2357 The names can be found in an array 'reg_names' whose type is 2358 'char *[]'. 'reg_names' is initialized from 'REGISTER_NAMES'. 2359 2360 When the machine description has a specification '%PUNCT' (a '%' 2361 followed by a punctuation character), this macro is called with 2362 a null pointer for X and the punctuation character for CODE. 2363 2364 'a', 'c', 'l', and 'n' are reserved. 2365 2366 The Xtensa specific codes are: 2367 2368 'd' CONST_INT, print as signed decimal 2369 'x' CONST_INT, print as signed hexadecimal 2370 'K' CONST_INT, print number of bits in mask for EXTUI 2371 'R' CONST_INT, print (X & 0x1f) 2372 'L' CONST_INT, print ((32 - X) & 0x1f) 2373 'D' REG, print second register of double-word register operand 2374 'N' MEM, print address of next word following a memory operand 2375 'v' MEM, if memory reference is volatile, output a MEMW before it 2376 't' any constant, add "@h" suffix for top 16 bits 2377 'b' any constant, add "@l" suffix for bottom 16 bits 2378 */ 2379 2380 static void 2381 printx (FILE *file, signed int val) 2382 { 2383 /* Print a hexadecimal value in a nice way. */ 2384 if ((val > -0xa) && (val < 0xa)) 2385 fprintf (file, "%d", val); 2386 else if (val < 0) 2387 fprintf (file, "-0x%x", -val); 2388 else 2389 fprintf (file, "0x%x", val); 2390 } 2391 2392 2393 void 2394 print_operand (FILE *file, rtx x, int letter) 2395 { 2396 if (!x) 2397 error ("%<PRINT_OPERAND%> null pointer"); 2398 2399 switch (letter) 2400 { 2401 case 'D': 2402 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) 2403 fprintf (file, "%s", reg_names[xt_true_regnum (x) + 1]); 2404 else 2405 output_operand_lossage ("invalid %%D value"); 2406 break; 2407 2408 case 'v': 2409 if (GET_CODE (x) == MEM) 2410 { 2411 /* For a volatile memory reference, emit a MEMW before the 2412 load or store. */ 2413 if (MEM_VOLATILE_P (x) && TARGET_SERIALIZE_VOLATILE) 2414 fprintf (file, "memw\n\t"); 2415 } 2416 else 2417 output_operand_lossage ("invalid %%v value"); 2418 break; 2419 2420 case 'N': 2421 if (GET_CODE (x) == MEM 2422 && (GET_MODE (x) == DFmode || GET_MODE (x) == DImode)) 2423 { 2424 x = adjust_address (x, GET_MODE (x) == DFmode ? E_SFmode : E_SImode, 2425 4); 2426 output_address (GET_MODE (x), XEXP (x, 0)); 2427 } 2428 else 2429 output_operand_lossage ("invalid %%N value"); 2430 break; 2431 2432 case 'K': 2433 if (GET_CODE (x) == CONST_INT) 2434 { 2435 int num_bits = 0; 2436 unsigned val = INTVAL (x); 2437 while (val & 1) 2438 { 2439 num_bits += 1; 2440 val = val >> 1; 2441 } 2442 if ((val != 0) || (num_bits == 0) || (num_bits > 16)) 2443 fatal_insn ("invalid mask", x); 2444 2445 fprintf (file, "%d", num_bits); 2446 } 2447 else 2448 output_operand_lossage ("invalid %%K value"); 2449 break; 2450 2451 case 'L': 2452 if (GET_CODE (x) == CONST_INT) 2453 fprintf (file, HOST_WIDE_INT_PRINT_DEC, (32 - INTVAL (x)) & 0x1f); 2454 else 2455 output_operand_lossage ("invalid %%L value"); 2456 break; 2457 2458 case 'R': 2459 if (GET_CODE (x) == CONST_INT) 2460 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x) & 0x1f); 2461 else 2462 output_operand_lossage ("invalid %%R value"); 2463 break; 2464 2465 case 'x': 2466 if (GET_CODE (x) == CONST_INT) 2467 printx (file, INTVAL (x)); 2468 else 2469 output_operand_lossage ("invalid %%x value"); 2470 break; 2471 2472 case 'd': 2473 if (GET_CODE (x) == CONST_INT) 2474 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); 2475 else 2476 output_operand_lossage ("invalid %%d value"); 2477 break; 2478 2479 case 't': 2480 case 'b': 2481 if (GET_CODE (x) == CONST_INT) 2482 { 2483 printx (file, INTVAL (x)); 2484 fputs (letter == 't' ? "@h" : "@l", file); 2485 } 2486 else if (GET_CODE (x) == CONST_DOUBLE) 2487 { 2488 if (GET_MODE (x) == SFmode) 2489 { 2490 long l; 2491 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l); 2492 fprintf (file, "0x%08lx@%c", l, letter == 't' ? 'h' : 'l'); 2493 } 2494 else 2495 output_operand_lossage ("invalid %%t/%%b value"); 2496 } 2497 else if (GET_CODE (x) == CONST) 2498 { 2499 /* X must be a symbolic constant on ELF. Write an expression 2500 suitable for 'const16' that sets the high or low 16 bits. */ 2501 if (GET_CODE (XEXP (x, 0)) != PLUS 2502 || (GET_CODE (XEXP (XEXP (x, 0), 0)) != SYMBOL_REF 2503 && GET_CODE (XEXP (XEXP (x, 0), 0)) != LABEL_REF) 2504 || GET_CODE (XEXP (XEXP (x, 0), 1)) != CONST_INT) 2505 output_operand_lossage ("invalid %%t/%%b value"); 2506 print_operand (file, XEXP (XEXP (x, 0), 0), 0); 2507 fputs (letter == 't' ? "@h" : "@l", file); 2508 /* There must be a non-alphanumeric character between 'h' or 'l' 2509 and the number. The '-' is added by print_operand() already. */ 2510 if (INTVAL (XEXP (XEXP (x, 0), 1)) >= 0) 2511 fputs ("+", file); 2512 print_operand (file, XEXP (XEXP (x, 0), 1), 0); 2513 } 2514 else 2515 { 2516 output_addr_const (file, x); 2517 fputs (letter == 't' ? "@h" : "@l", file); 2518 } 2519 break; 2520 2521 case 'y': 2522 if (GET_CODE (x) == CONST_DOUBLE && 2523 GET_MODE (x) == SFmode) 2524 { 2525 long l; 2526 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), l); 2527 fprintf (file, "0x%08lx", l); 2528 break; 2529 } 2530 2531 /* fall through */ 2532 2533 default: 2534 if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG) 2535 fprintf (file, "%s", reg_names[xt_true_regnum (x)]); 2536 else if (GET_CODE (x) == MEM) 2537 output_address (GET_MODE (x), XEXP (x, 0)); 2538 else if (GET_CODE (x) == CONST_INT) 2539 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (x)); 2540 else 2541 output_addr_const (file, x); 2542 } 2543 } 2544 2545 2546 /* A C compound statement to output to stdio stream STREAM the 2547 assembler syntax for an instruction operand that is a memory 2548 reference whose address is ADDR. ADDR is an RTL expression. */ 2549 2550 void 2551 print_operand_address (FILE *file, rtx addr) 2552 { 2553 if (!addr) 2554 error ("%<PRINT_OPERAND_ADDRESS%>, null pointer"); 2555 2556 switch (GET_CODE (addr)) 2557 { 2558 default: 2559 fatal_insn ("invalid address", addr); 2560 break; 2561 2562 case REG: 2563 fprintf (file, "%s, 0", reg_names [REGNO (addr)]); 2564 break; 2565 2566 case PLUS: 2567 { 2568 rtx reg = (rtx)0; 2569 rtx offset = (rtx)0; 2570 rtx arg0 = XEXP (addr, 0); 2571 rtx arg1 = XEXP (addr, 1); 2572 2573 if (GET_CODE (arg0) == REG) 2574 { 2575 reg = arg0; 2576 offset = arg1; 2577 } 2578 else if (GET_CODE (arg1) == REG) 2579 { 2580 reg = arg1; 2581 offset = arg0; 2582 } 2583 else 2584 fatal_insn ("no register in address", addr); 2585 2586 if (CONSTANT_P (offset)) 2587 { 2588 fprintf (file, "%s, ", reg_names [REGNO (reg)]); 2589 output_addr_const (file, offset); 2590 } 2591 else 2592 fatal_insn ("address offset not a constant", addr); 2593 } 2594 break; 2595 2596 case LABEL_REF: 2597 case SYMBOL_REF: 2598 case CONST_INT: 2599 case CONST: 2600 output_addr_const (file, addr); 2601 break; 2602 } 2603 } 2604 2605 /* Implement TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA. */ 2606 2607 static bool 2608 xtensa_output_addr_const_extra (FILE *fp, rtx x) 2609 { 2610 if (GET_CODE (x) == UNSPEC && XVECLEN (x, 0) == 1) 2611 { 2612 switch (XINT (x, 1)) 2613 { 2614 case UNSPEC_TPOFF: 2615 output_addr_const (fp, XVECEXP (x, 0, 0)); 2616 fputs ("@TPOFF", fp); 2617 return true; 2618 case UNSPEC_DTPOFF: 2619 output_addr_const (fp, XVECEXP (x, 0, 0)); 2620 fputs ("@DTPOFF", fp); 2621 return true; 2622 case UNSPEC_PLT: 2623 if (flag_pic) 2624 { 2625 output_addr_const (fp, XVECEXP (x, 0, 0)); 2626 fputs ("@PLT", fp); 2627 return true; 2628 } 2629 break; 2630 default: 2631 break; 2632 } 2633 } 2634 return false; 2635 } 2636 2637 static void 2638 xtensa_output_integer_literal_parts (FILE *file, rtx x, int size) 2639 { 2640 if (size > 4 && !(size & (size - 1))) 2641 { 2642 rtx first, second; 2643 2644 split_double (x, &first, &second); 2645 xtensa_output_integer_literal_parts (file, first, size / 2); 2646 fputs (", ", file); 2647 xtensa_output_integer_literal_parts (file, second, size / 2); 2648 } 2649 else if (size == 4) 2650 { 2651 output_addr_const (file, x); 2652 } 2653 else 2654 { 2655 gcc_unreachable(); 2656 } 2657 } 2658 2659 void 2660 xtensa_output_literal (FILE *file, rtx x, machine_mode mode, int labelno) 2661 { 2662 long value_long[2]; 2663 2664 fprintf (file, "\t.literal .LC%u, ", (unsigned) labelno); 2665 2666 switch (GET_MODE_CLASS (mode)) 2667 { 2668 case MODE_FLOAT: 2669 gcc_assert (GET_CODE (x) == CONST_DOUBLE); 2670 2671 switch (mode) 2672 { 2673 case E_SFmode: 2674 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (x), 2675 value_long[0]); 2676 if (HOST_BITS_PER_LONG > 32) 2677 value_long[0] &= 0xffffffff; 2678 fprintf (file, "0x%08lx\n", value_long[0]); 2679 break; 2680 2681 case E_DFmode: 2682 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), 2683 value_long); 2684 if (HOST_BITS_PER_LONG > 32) 2685 { 2686 value_long[0] &= 0xffffffff; 2687 value_long[1] &= 0xffffffff; 2688 } 2689 fprintf (file, "0x%08lx, 0x%08lx\n", 2690 value_long[0], value_long[1]); 2691 break; 2692 2693 default: 2694 gcc_unreachable (); 2695 } 2696 2697 break; 2698 2699 case MODE_INT: 2700 case MODE_PARTIAL_INT: 2701 xtensa_output_integer_literal_parts (file, x, GET_MODE_SIZE (mode)); 2702 fputs ("\n", file); 2703 break; 2704 2705 default: 2706 gcc_unreachable (); 2707 } 2708 } 2709 2710 static bool 2711 xtensa_call_save_reg(int regno) 2712 { 2713 if (TARGET_WINDOWED_ABI) 2714 return false; 2715 2716 if (regno == A0_REG) 2717 return crtl->profile || !crtl->is_leaf || crtl->calls_eh_return || 2718 df_regs_ever_live_p (regno); 2719 2720 if (crtl->calls_eh_return && regno >= 2 && regno < 4) 2721 return true; 2722 2723 return !call_used_or_fixed_reg_p (regno) && df_regs_ever_live_p (regno); 2724 } 2725 2726 /* Return the bytes needed to compute the frame pointer from the current 2727 stack pointer. */ 2728 2729 #define STACK_BYTES (STACK_BOUNDARY / BITS_PER_UNIT) 2730 #define XTENSA_STACK_ALIGN(LOC) (((LOC) + STACK_BYTES-1) & ~(STACK_BYTES-1)) 2731 2732 long 2733 compute_frame_size (poly_int64 size) 2734 { 2735 int regno; 2736 2737 if (reload_completed && cfun->machine->frame_laid_out) 2738 return cfun->machine->current_frame_size; 2739 2740 /* Add space for the incoming static chain value. */ 2741 if (cfun->static_chain_decl != NULL) 2742 size += (1 * UNITS_PER_WORD); 2743 2744 cfun->machine->callee_save_size = 0; 2745 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) 2746 { 2747 if (xtensa_call_save_reg(regno)) 2748 cfun->machine->callee_save_size += UNITS_PER_WORD; 2749 } 2750 2751 cfun->machine->current_frame_size = 2752 XTENSA_STACK_ALIGN (size 2753 + cfun->machine->callee_save_size 2754 + crtl->outgoing_args_size 2755 + (WINDOW_SIZE * UNITS_PER_WORD)); 2756 cfun->machine->callee_save_size = 2757 XTENSA_STACK_ALIGN (cfun->machine->callee_save_size); 2758 cfun->machine->frame_laid_out = true; 2759 return cfun->machine->current_frame_size; 2760 } 2761 2762 2763 bool 2764 xtensa_frame_pointer_required (void) 2765 { 2766 /* The code to expand builtin_frame_addr and builtin_return_addr 2767 currently uses the hard_frame_pointer instead of frame_pointer. 2768 This seems wrong but maybe it's necessary for other architectures. 2769 This function is derived from the i386 code. */ 2770 2771 if (cfun->machine->accesses_prev_frame || cfun->has_nonlocal_label) 2772 return true; 2773 2774 return false; 2775 } 2776 2777 HOST_WIDE_INT 2778 xtensa_initial_elimination_offset (int from, int to ATTRIBUTE_UNUSED) 2779 { 2780 long frame_size = compute_frame_size (get_frame_size ()); 2781 HOST_WIDE_INT offset; 2782 2783 switch (from) 2784 { 2785 case FRAME_POINTER_REGNUM: 2786 if (FRAME_GROWS_DOWNWARD) 2787 offset = frame_size - (WINDOW_SIZE * UNITS_PER_WORD) 2788 - cfun->machine->callee_save_size; 2789 else 2790 offset = 0; 2791 break; 2792 case ARG_POINTER_REGNUM: 2793 offset = frame_size; 2794 break; 2795 default: 2796 gcc_unreachable (); 2797 } 2798 2799 return offset; 2800 } 2801 2802 /* minimum frame = reg save area (4 words) plus static chain (1 word) 2803 and the total number of words must be a multiple of 128 bits. */ 2804 #define MIN_FRAME_SIZE (8 * UNITS_PER_WORD) 2805 2806 void 2807 xtensa_expand_prologue (void) 2808 { 2809 HOST_WIDE_INT total_size; 2810 rtx_insn *insn = NULL; 2811 rtx note_rtx; 2812 2813 2814 total_size = compute_frame_size (get_frame_size ()); 2815 2816 if (flag_stack_usage_info) 2817 current_function_static_stack_size = total_size; 2818 2819 if (TARGET_WINDOWED_ABI) 2820 { 2821 if (total_size < (1 << (12+3))) 2822 insn = emit_insn (gen_entry (GEN_INT (total_size))); 2823 else 2824 { 2825 /* Use a8 as a temporary since a0-a7 may be live. */ 2826 rtx tmp_reg = gen_rtx_REG (Pmode, A8_REG); 2827 emit_insn (gen_entry (GEN_INT (MIN_FRAME_SIZE))); 2828 emit_move_insn (tmp_reg, GEN_INT (total_size - MIN_FRAME_SIZE)); 2829 emit_insn (gen_subsi3 (tmp_reg, stack_pointer_rtx, tmp_reg)); 2830 insn = emit_insn (gen_movsi (stack_pointer_rtx, tmp_reg)); 2831 } 2832 } 2833 else 2834 { 2835 int regno; 2836 HOST_WIDE_INT offset = 0; 2837 int callee_save_size = cfun->machine->callee_save_size; 2838 2839 /* -128 is a limit of single addi instruction. */ 2840 if (total_size > 0 && total_size <= 128) 2841 { 2842 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 2843 GEN_INT (-total_size))); 2844 RTX_FRAME_RELATED_P (insn) = 1; 2845 note_rtx = gen_rtx_SET (stack_pointer_rtx, 2846 plus_constant (Pmode, stack_pointer_rtx, 2847 -total_size)); 2848 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); 2849 offset = total_size - UNITS_PER_WORD; 2850 } 2851 else if (callee_save_size) 2852 { 2853 /* 1020 is maximal s32i offset, if the frame is bigger than that 2854 * we move sp to the end of callee-saved save area, save and then 2855 * move it to its final location. */ 2856 if (total_size > 1024) 2857 { 2858 insn = emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 2859 GEN_INT (-callee_save_size))); 2860 RTX_FRAME_RELATED_P (insn) = 1; 2861 note_rtx = gen_rtx_SET (stack_pointer_rtx, 2862 plus_constant (Pmode, stack_pointer_rtx, 2863 -callee_save_size)); 2864 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); 2865 offset = callee_save_size - UNITS_PER_WORD; 2866 } 2867 else 2868 { 2869 rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); 2870 emit_move_insn (tmp_reg, GEN_INT (total_size)); 2871 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, 2872 stack_pointer_rtx, tmp_reg)); 2873 RTX_FRAME_RELATED_P (insn) = 1; 2874 note_rtx = gen_rtx_SET (stack_pointer_rtx, 2875 plus_constant (Pmode, stack_pointer_rtx, 2876 -total_size)); 2877 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); 2878 offset = total_size - UNITS_PER_WORD; 2879 } 2880 } 2881 2882 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) 2883 { 2884 if (xtensa_call_save_reg(regno)) 2885 { 2886 rtx x = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); 2887 rtx mem = gen_frame_mem (SImode, x); 2888 rtx reg = gen_rtx_REG (SImode, regno); 2889 2890 offset -= UNITS_PER_WORD; 2891 insn = emit_move_insn (mem, reg); 2892 RTX_FRAME_RELATED_P (insn) = 1; 2893 add_reg_note (insn, REG_FRAME_RELATED_EXPR, 2894 gen_rtx_SET (mem, reg)); 2895 } 2896 } 2897 if (total_size > 1024 2898 || (!callee_save_size && total_size > 128)) 2899 { 2900 rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); 2901 emit_move_insn (tmp_reg, GEN_INT (total_size - 2902 callee_save_size)); 2903 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, 2904 stack_pointer_rtx, tmp_reg)); 2905 RTX_FRAME_RELATED_P (insn) = 1; 2906 note_rtx = gen_rtx_SET (stack_pointer_rtx, 2907 plus_constant (Pmode, stack_pointer_rtx, 2908 callee_save_size - 2909 total_size)); 2910 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); 2911 } 2912 } 2913 2914 if (frame_pointer_needed) 2915 { 2916 if (cfun->machine->set_frame_ptr_insn) 2917 { 2918 rtx_insn *first; 2919 2920 push_topmost_sequence (); 2921 first = get_insns (); 2922 pop_topmost_sequence (); 2923 2924 /* For all instructions prior to set_frame_ptr_insn, replace 2925 hard_frame_pointer references with stack_pointer. */ 2926 for (insn = first; 2927 insn != cfun->machine->set_frame_ptr_insn; 2928 insn = NEXT_INSN (insn)) 2929 { 2930 if (INSN_P (insn)) 2931 { 2932 PATTERN (insn) = replace_rtx (copy_rtx (PATTERN (insn)), 2933 hard_frame_pointer_rtx, 2934 stack_pointer_rtx); 2935 df_insn_rescan (insn); 2936 } 2937 } 2938 } 2939 else 2940 { 2941 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, 2942 stack_pointer_rtx)); 2943 if (!TARGET_WINDOWED_ABI) 2944 { 2945 note_rtx = gen_rtx_SET (hard_frame_pointer_rtx, 2946 stack_pointer_rtx); 2947 RTX_FRAME_RELATED_P (insn) = 1; 2948 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); 2949 } 2950 } 2951 } 2952 2953 if (TARGET_WINDOWED_ABI) 2954 { 2955 /* Create a note to describe the CFA. Because this is only used to set 2956 DW_AT_frame_base for debug info, don't bother tracking changes through 2957 each instruction in the prologue. It just takes up space. */ 2958 note_rtx = gen_rtx_SET ((frame_pointer_needed 2959 ? hard_frame_pointer_rtx 2960 : stack_pointer_rtx), 2961 plus_constant (Pmode, stack_pointer_rtx, 2962 -total_size)); 2963 RTX_FRAME_RELATED_P (insn) = 1; 2964 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note_rtx); 2965 } 2966 } 2967 2968 void 2969 xtensa_expand_epilogue (void) 2970 { 2971 if (!TARGET_WINDOWED_ABI) 2972 { 2973 int regno; 2974 HOST_WIDE_INT offset; 2975 2976 if (cfun->machine->current_frame_size > (frame_pointer_needed ? 127 : 1024)) 2977 { 2978 rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); 2979 emit_move_insn (tmp_reg, GEN_INT (cfun->machine->current_frame_size - 2980 cfun->machine->callee_save_size)); 2981 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_needed ? 2982 hard_frame_pointer_rtx : stack_pointer_rtx, 2983 tmp_reg)); 2984 offset = cfun->machine->callee_save_size - UNITS_PER_WORD; 2985 } 2986 else 2987 { 2988 if (frame_pointer_needed) 2989 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); 2990 offset = cfun->machine->current_frame_size - UNITS_PER_WORD; 2991 } 2992 2993 /* Prevent reordering of saved a0 update and loading it back from 2994 the save area. */ 2995 if (crtl->calls_eh_return) 2996 emit_insn (gen_blockage ()); 2997 2998 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; ++regno) 2999 { 3000 if (xtensa_call_save_reg(regno)) 3001 { 3002 rtx x = gen_rtx_PLUS (Pmode, stack_pointer_rtx, GEN_INT (offset)); 3003 3004 offset -= UNITS_PER_WORD; 3005 emit_move_insn (gen_rtx_REG (SImode, regno), 3006 gen_frame_mem (SImode, x)); 3007 } 3008 } 3009 3010 if (cfun->machine->current_frame_size > 0) 3011 { 3012 if (frame_pointer_needed || /* always reachable with addi */ 3013 cfun->machine->current_frame_size > 1024 || 3014 cfun->machine->current_frame_size <= 127) 3015 { 3016 if (cfun->machine->current_frame_size <= 127) 3017 offset = cfun->machine->current_frame_size; 3018 else 3019 offset = cfun->machine->callee_save_size; 3020 3021 emit_insn (gen_addsi3 (stack_pointer_rtx, 3022 stack_pointer_rtx, 3023 GEN_INT (offset))); 3024 } 3025 else 3026 { 3027 rtx tmp_reg = gen_rtx_REG (Pmode, A9_REG); 3028 emit_move_insn (tmp_reg, 3029 GEN_INT (cfun->machine->current_frame_size)); 3030 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 3031 tmp_reg)); 3032 } 3033 } 3034 3035 if (crtl->calls_eh_return) 3036 emit_insn (gen_add3_insn (stack_pointer_rtx, 3037 stack_pointer_rtx, 3038 EH_RETURN_STACKADJ_RTX)); 3039 } 3040 cfun->machine->epilogue_done = true; 3041 emit_jump_insn (gen_return ()); 3042 } 3043 3044 bool 3045 xtensa_use_return_instruction_p (void) 3046 { 3047 if (!reload_completed) 3048 return false; 3049 if (TARGET_WINDOWED_ABI) 3050 return true; 3051 if (compute_frame_size (get_frame_size ()) == 0) 3052 return true; 3053 return cfun->machine->epilogue_done; 3054 } 3055 3056 void 3057 xtensa_set_return_address (rtx address, rtx scratch) 3058 { 3059 HOST_WIDE_INT total_size = compute_frame_size (get_frame_size ()); 3060 rtx frame = frame_pointer_needed ? 3061 hard_frame_pointer_rtx : stack_pointer_rtx; 3062 rtx a0_addr = plus_constant (Pmode, frame, 3063 total_size - UNITS_PER_WORD); 3064 rtx note = gen_rtx_SET (gen_frame_mem (SImode, a0_addr), 3065 gen_rtx_REG (SImode, A0_REG)); 3066 rtx insn; 3067 3068 if (total_size > 1024) { 3069 emit_move_insn (scratch, GEN_INT (total_size - UNITS_PER_WORD)); 3070 emit_insn (gen_addsi3 (scratch, frame, scratch)); 3071 a0_addr = scratch; 3072 } 3073 3074 insn = emit_move_insn (gen_frame_mem (SImode, a0_addr), address); 3075 RTX_FRAME_RELATED_P (insn) = 1; 3076 add_reg_note (insn, REG_FRAME_RELATED_EXPR, note); 3077 } 3078 3079 rtx 3080 xtensa_return_addr (int count, rtx frame) 3081 { 3082 rtx result, retaddr, curaddr, label; 3083 3084 if (!TARGET_WINDOWED_ABI) 3085 { 3086 if (count != 0) 3087 return const0_rtx; 3088 3089 return get_hard_reg_initial_val (Pmode, A0_REG); 3090 } 3091 3092 if (count == -1) 3093 retaddr = gen_rtx_REG (Pmode, A0_REG); 3094 else 3095 { 3096 rtx addr = plus_constant (Pmode, frame, -4 * UNITS_PER_WORD); 3097 addr = memory_address (Pmode, addr); 3098 retaddr = gen_reg_rtx (Pmode); 3099 emit_move_insn (retaddr, gen_rtx_MEM (Pmode, addr)); 3100 } 3101 3102 /* The 2 most-significant bits of the return address on Xtensa hold 3103 the register window size. To get the real return address, these 3104 bits must be replaced with the high bits from some address in the 3105 code. */ 3106 3107 /* Get the 2 high bits of a local label in the code. */ 3108 curaddr = gen_reg_rtx (Pmode); 3109 label = gen_label_rtx (); 3110 emit_label (label); 3111 LABEL_PRESERVE_P (label) = 1; 3112 emit_move_insn (curaddr, gen_rtx_LABEL_REF (Pmode, label)); 3113 emit_insn (gen_lshrsi3 (curaddr, curaddr, GEN_INT (30))); 3114 emit_insn (gen_ashlsi3 (curaddr, curaddr, GEN_INT (30))); 3115 3116 /* Clear the 2 high bits of the return address. */ 3117 result = gen_reg_rtx (Pmode); 3118 emit_insn (gen_ashlsi3 (result, retaddr, GEN_INT (2))); 3119 emit_insn (gen_lshrsi3 (result, result, GEN_INT (2))); 3120 3121 /* Combine them to get the result. */ 3122 emit_insn (gen_iorsi3 (result, result, curaddr)); 3123 return result; 3124 } 3125 3126 /* Disable the use of word-sized or smaller complex modes for structures, 3127 and for function arguments in particular, where they cause problems with 3128 register a7. The xtensa_copy_incoming_a7 function assumes that there is 3129 a single reference to an argument in a7, but with small complex modes the 3130 real and imaginary components may be extracted separately, leading to two 3131 uses of the register, only one of which would be replaced. */ 3132 3133 static bool 3134 xtensa_member_type_forces_blk (const_tree, machine_mode mode) 3135 { 3136 return mode == CQImode || mode == CHImode; 3137 } 3138 3139 /* Create the va_list data type. 3140 3141 This structure is set up by __builtin_saveregs. The __va_reg field 3142 points to a stack-allocated region holding the contents of the 3143 incoming argument registers. The __va_ndx field is an index 3144 initialized to the position of the first unnamed (variable) 3145 argument. This same index is also used to address the arguments 3146 passed in memory. Thus, the __va_stk field is initialized to point 3147 to the position of the first argument in memory offset to account 3148 for the arguments passed in registers and to account for the size 3149 of the argument registers not being 16-byte aligned. E.G., there 3150 are 6 argument registers of 4 bytes each, but we want the __va_ndx 3151 for the first stack argument to have the maximal alignment of 16 3152 bytes, so we offset the __va_stk address by 32 bytes so that 3153 __va_stk[32] references the first argument on the stack. */ 3154 3155 static tree 3156 xtensa_build_builtin_va_list (void) 3157 { 3158 tree f_stk, f_reg, f_ndx, record, type_decl; 3159 3160 record = (*lang_hooks.types.make_type) (RECORD_TYPE); 3161 type_decl = build_decl (BUILTINS_LOCATION, 3162 TYPE_DECL, get_identifier ("__va_list_tag"), record); 3163 3164 f_stk = build_decl (BUILTINS_LOCATION, 3165 FIELD_DECL, get_identifier ("__va_stk"), 3166 ptr_type_node); 3167 f_reg = build_decl (BUILTINS_LOCATION, 3168 FIELD_DECL, get_identifier ("__va_reg"), 3169 ptr_type_node); 3170 f_ndx = build_decl (BUILTINS_LOCATION, 3171 FIELD_DECL, get_identifier ("__va_ndx"), 3172 integer_type_node); 3173 3174 DECL_FIELD_CONTEXT (f_stk) = record; 3175 DECL_FIELD_CONTEXT (f_reg) = record; 3176 DECL_FIELD_CONTEXT (f_ndx) = record; 3177 3178 TYPE_STUB_DECL (record) = type_decl; 3179 TYPE_NAME (record) = type_decl; 3180 TYPE_FIELDS (record) = f_stk; 3181 DECL_CHAIN (f_stk) = f_reg; 3182 DECL_CHAIN (f_reg) = f_ndx; 3183 3184 layout_type (record); 3185 return record; 3186 } 3187 3188 3189 /* Save the incoming argument registers on the stack. Returns the 3190 address of the saved registers. */ 3191 3192 static rtx 3193 xtensa_builtin_saveregs (void) 3194 { 3195 rtx gp_regs; 3196 int arg_words = crtl->args.info.arg_words; 3197 int gp_left = MAX_ARGS_IN_REGISTERS - arg_words; 3198 3199 if (gp_left <= 0) 3200 return const0_rtx; 3201 3202 /* Allocate the general-purpose register space. */ 3203 gp_regs = assign_stack_local 3204 (BLKmode, MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD, -1); 3205 set_mem_alias_set (gp_regs, get_varargs_alias_set ()); 3206 3207 /* Now store the incoming registers. */ 3208 cfun->machine->need_a7_copy = TARGET_WINDOWED_ABI; 3209 cfun->machine->vararg_a7 = true; 3210 move_block_from_reg (GP_ARG_FIRST + arg_words, 3211 adjust_address (gp_regs, BLKmode, 3212 arg_words * UNITS_PER_WORD), 3213 gp_left); 3214 if (cfun->machine->vararg_a7_copy != 0) 3215 emit_insn_before (cfun->machine->vararg_a7_copy, get_insns ()); 3216 3217 return XEXP (gp_regs, 0); 3218 } 3219 3220 3221 /* Implement `va_start' for varargs and stdarg. We look at the 3222 current function to fill in an initial va_list. */ 3223 3224 static void 3225 xtensa_va_start (tree valist, rtx nextarg ATTRIBUTE_UNUSED) 3226 { 3227 tree f_stk, stk; 3228 tree f_reg, reg; 3229 tree f_ndx, ndx; 3230 tree t, u; 3231 int arg_words; 3232 3233 arg_words = crtl->args.info.arg_words; 3234 3235 f_stk = TYPE_FIELDS (va_list_type_node); 3236 f_reg = DECL_CHAIN (f_stk); 3237 f_ndx = DECL_CHAIN (f_reg); 3238 3239 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, f_stk, NULL_TREE); 3240 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), 3241 f_reg, NULL_TREE); 3242 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), 3243 f_ndx, NULL_TREE); 3244 3245 /* Call __builtin_saveregs; save the result in __va_reg */ 3246 u = make_tree (sizetype, expand_builtin_saveregs ()); 3247 u = fold_convert (ptr_type_node, u); 3248 t = build2 (MODIFY_EXPR, ptr_type_node, reg, u); 3249 TREE_SIDE_EFFECTS (t) = 1; 3250 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 3251 3252 /* Set the __va_stk member to ($arg_ptr - 32). */ 3253 u = make_tree (ptr_type_node, virtual_incoming_args_rtx); 3254 u = fold_build_pointer_plus_hwi (u, -32); 3255 t = build2 (MODIFY_EXPR, ptr_type_node, stk, u); 3256 TREE_SIDE_EFFECTS (t) = 1; 3257 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 3258 3259 /* Set the __va_ndx member. If the first variable argument is on 3260 the stack, adjust __va_ndx by 2 words to account for the extra 3261 alignment offset for __va_stk. */ 3262 if (arg_words >= MAX_ARGS_IN_REGISTERS) 3263 arg_words += 2; 3264 t = build2 (MODIFY_EXPR, integer_type_node, ndx, 3265 build_int_cst (integer_type_node, arg_words * UNITS_PER_WORD)); 3266 TREE_SIDE_EFFECTS (t) = 1; 3267 expand_expr (t, const0_rtx, VOIDmode, EXPAND_NORMAL); 3268 } 3269 3270 3271 /* Implement `va_arg'. */ 3272 3273 static tree 3274 xtensa_gimplify_va_arg_expr (tree valist, tree type, gimple_seq *pre_p, 3275 gimple_seq *post_p ATTRIBUTE_UNUSED) 3276 { 3277 tree f_stk, stk; 3278 tree f_reg, reg; 3279 tree f_ndx, ndx; 3280 tree type_size, array, orig_ndx, addr, size, va_size, t; 3281 tree lab_false, lab_over, lab_false2; 3282 bool indirect; 3283 3284 indirect = pass_va_arg_by_reference (type); 3285 if (indirect) 3286 type = build_pointer_type (type); 3287 3288 /* Handle complex values as separate real and imaginary parts. */ 3289 if (TREE_CODE (type) == COMPLEX_TYPE) 3290 { 3291 tree real_part, imag_part; 3292 3293 real_part = xtensa_gimplify_va_arg_expr (valist, TREE_TYPE (type), 3294 pre_p, NULL); 3295 real_part = get_initialized_tmp_var (real_part, pre_p, NULL); 3296 3297 imag_part = xtensa_gimplify_va_arg_expr (unshare_expr (valist), 3298 TREE_TYPE (type), 3299 pre_p, NULL); 3300 imag_part = get_initialized_tmp_var (imag_part, pre_p, NULL); 3301 3302 return build2 (COMPLEX_EXPR, type, real_part, imag_part); 3303 } 3304 3305 f_stk = TYPE_FIELDS (va_list_type_node); 3306 f_reg = DECL_CHAIN (f_stk); 3307 f_ndx = DECL_CHAIN (f_reg); 3308 3309 stk = build3 (COMPONENT_REF, TREE_TYPE (f_stk), valist, 3310 f_stk, NULL_TREE); 3311 reg = build3 (COMPONENT_REF, TREE_TYPE (f_reg), unshare_expr (valist), 3312 f_reg, NULL_TREE); 3313 ndx = build3 (COMPONENT_REF, TREE_TYPE (f_ndx), unshare_expr (valist), 3314 f_ndx, NULL_TREE); 3315 3316 type_size = size_in_bytes (type); 3317 va_size = round_up (type_size, UNITS_PER_WORD); 3318 gimplify_expr (&va_size, pre_p, NULL, is_gimple_val, fb_rvalue); 3319 3320 3321 /* First align __va_ndx if necessary for this arg: 3322 3323 orig_ndx = (AP).__va_ndx; 3324 if (__alignof__ (TYPE) > 4 ) 3325 orig_ndx = ((orig_ndx + __alignof__ (TYPE) - 1) 3326 & -__alignof__ (TYPE)); */ 3327 3328 orig_ndx = get_initialized_tmp_var (ndx, pre_p, NULL); 3329 3330 if (TYPE_ALIGN (type) > BITS_PER_WORD) 3331 { 3332 int align = MIN (TYPE_ALIGN (type), STACK_BOUNDARY) / BITS_PER_UNIT; 3333 3334 t = build2 (PLUS_EXPR, integer_type_node, unshare_expr (orig_ndx), 3335 build_int_cst (integer_type_node, align - 1)); 3336 t = build2 (BIT_AND_EXPR, integer_type_node, t, 3337 build_int_cst (integer_type_node, -align)); 3338 gimplify_assign (unshare_expr (orig_ndx), t, pre_p); 3339 } 3340 3341 3342 /* Increment __va_ndx to point past the argument: 3343 3344 (AP).__va_ndx = orig_ndx + __va_size (TYPE); */ 3345 3346 t = fold_convert (integer_type_node, va_size); 3347 t = build2 (PLUS_EXPR, integer_type_node, orig_ndx, t); 3348 gimplify_assign (unshare_expr (ndx), t, pre_p); 3349 3350 3351 /* Check if the argument is in registers: 3352 3353 if ((AP).__va_ndx <= __MAX_ARGS_IN_REGISTERS * 4 3354 && !must_pass_in_stack (type)) 3355 __array = (AP).__va_reg; */ 3356 3357 array = create_tmp_var (ptr_type_node); 3358 3359 lab_over = NULL; 3360 if (!must_pass_va_arg_in_stack (type)) 3361 { 3362 lab_false = create_artificial_label (UNKNOWN_LOCATION); 3363 lab_over = create_artificial_label (UNKNOWN_LOCATION); 3364 3365 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (ndx), 3366 build_int_cst (integer_type_node, 3367 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); 3368 t = build3 (COND_EXPR, void_type_node, t, 3369 build1 (GOTO_EXPR, void_type_node, lab_false), 3370 NULL_TREE); 3371 gimplify_and_add (t, pre_p); 3372 3373 gimplify_assign (unshare_expr (array), reg, pre_p); 3374 3375 t = build1 (GOTO_EXPR, void_type_node, lab_over); 3376 gimplify_and_add (t, pre_p); 3377 3378 t = build1 (LABEL_EXPR, void_type_node, lab_false); 3379 gimplify_and_add (t, pre_p); 3380 } 3381 3382 3383 /* ...otherwise, the argument is on the stack (never split between 3384 registers and the stack -- change __va_ndx if necessary): 3385 3386 else 3387 { 3388 if (orig_ndx <= __MAX_ARGS_IN_REGISTERS * 4) 3389 (AP).__va_ndx = 32 + __va_size (TYPE); 3390 __array = (AP).__va_stk; 3391 } */ 3392 3393 lab_false2 = create_artificial_label (UNKNOWN_LOCATION); 3394 3395 t = build2 (GT_EXPR, boolean_type_node, unshare_expr (orig_ndx), 3396 build_int_cst (integer_type_node, 3397 MAX_ARGS_IN_REGISTERS * UNITS_PER_WORD)); 3398 t = build3 (COND_EXPR, void_type_node, t, 3399 build1 (GOTO_EXPR, void_type_node, lab_false2), 3400 NULL_TREE); 3401 gimplify_and_add (t, pre_p); 3402 3403 t = size_binop (PLUS_EXPR, unshare_expr (va_size), size_int (32)); 3404 t = fold_convert (integer_type_node, t); 3405 gimplify_assign (unshare_expr (ndx), t, pre_p); 3406 3407 t = build1 (LABEL_EXPR, void_type_node, lab_false2); 3408 gimplify_and_add (t, pre_p); 3409 3410 gimplify_assign (array, stk, pre_p); 3411 3412 if (lab_over) 3413 { 3414 t = build1 (LABEL_EXPR, void_type_node, lab_over); 3415 gimplify_and_add (t, pre_p); 3416 } 3417 3418 3419 /* Given the base array pointer (__array) and index to the subsequent 3420 argument (__va_ndx), find the address: 3421 3422 __array + (AP).__va_ndx - (BYTES_BIG_ENDIAN && sizeof (TYPE) < 4 3423 ? sizeof (TYPE) 3424 : __va_size (TYPE)) 3425 3426 The results are endian-dependent because values smaller than one word 3427 are aligned differently. */ 3428 3429 3430 if (BYTES_BIG_ENDIAN && TREE_CODE (type_size) == INTEGER_CST) 3431 { 3432 t = fold_build2 (GE_EXPR, boolean_type_node, unshare_expr (type_size), 3433 size_int (PARM_BOUNDARY / BITS_PER_UNIT)); 3434 t = fold_build3 (COND_EXPR, sizetype, t, unshare_expr (va_size), 3435 unshare_expr (type_size)); 3436 size = t; 3437 } 3438 else 3439 size = unshare_expr (va_size); 3440 3441 t = fold_convert (sizetype, unshare_expr (ndx)); 3442 t = build2 (MINUS_EXPR, sizetype, t, size); 3443 addr = fold_build_pointer_plus (unshare_expr (array), t); 3444 3445 addr = fold_convert (build_pointer_type (type), addr); 3446 if (indirect) 3447 addr = build_va_arg_indirect_ref (addr); 3448 return build_va_arg_indirect_ref (addr); 3449 } 3450 3451 3452 /* Builtins. */ 3453 3454 enum xtensa_builtin 3455 { 3456 XTENSA_BUILTIN_UMULSIDI3, 3457 XTENSA_BUILTIN_max 3458 }; 3459 3460 3461 static void 3462 xtensa_init_builtins (void) 3463 { 3464 tree ftype, decl; 3465 3466 ftype = build_function_type_list (unsigned_intDI_type_node, 3467 unsigned_intSI_type_node, 3468 unsigned_intSI_type_node, NULL_TREE); 3469 3470 decl = add_builtin_function ("__builtin_umulsidi3", ftype, 3471 XTENSA_BUILTIN_UMULSIDI3, BUILT_IN_MD, 3472 "__umulsidi3", NULL_TREE); 3473 TREE_NOTHROW (decl) = 1; 3474 TREE_READONLY (decl) = 1; 3475 } 3476 3477 3478 static tree 3479 xtensa_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, tree *args, 3480 bool ignore ATTRIBUTE_UNUSED) 3481 { 3482 unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl); 3483 tree arg0, arg1; 3484 3485 switch (fcode) 3486 { 3487 case XTENSA_BUILTIN_UMULSIDI3: 3488 arg0 = args[0]; 3489 arg1 = args[1]; 3490 if ((TREE_CODE (arg0) == INTEGER_CST && TREE_CODE (arg1) == INTEGER_CST) 3491 || TARGET_MUL32_HIGH) 3492 return fold_build2 (MULT_EXPR, unsigned_intDI_type_node, 3493 fold_convert (unsigned_intDI_type_node, arg0), 3494 fold_convert (unsigned_intDI_type_node, arg1)); 3495 break; 3496 3497 default: 3498 internal_error ("bad builtin code"); 3499 break; 3500 } 3501 3502 return NULL; 3503 } 3504 3505 3506 static rtx 3507 xtensa_expand_builtin (tree exp, rtx target, 3508 rtx subtarget ATTRIBUTE_UNUSED, 3509 machine_mode mode ATTRIBUTE_UNUSED, 3510 int ignore) 3511 { 3512 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 3513 unsigned int fcode = DECL_MD_FUNCTION_CODE (fndecl); 3514 3515 switch (fcode) 3516 { 3517 case XTENSA_BUILTIN_UMULSIDI3: 3518 /* The umulsidi3 builtin is just a mechanism to avoid calling the real 3519 __umulsidi3 function when the Xtensa configuration can directly 3520 implement it. If not, just call the function. */ 3521 return expand_call (exp, target, ignore); 3522 3523 default: 3524 internal_error ("bad builtin code"); 3525 } 3526 return NULL_RTX; 3527 } 3528 3529 /* Worker function for TARGET_PREFERRED_RELOAD_CLASS. */ 3530 3531 static reg_class_t 3532 xtensa_preferred_reload_class (rtx x, reg_class_t rclass) 3533 { 3534 if (CONSTANT_P (x) && CONST_DOUBLE_P (x)) 3535 return NO_REGS; 3536 3537 /* Don't use the stack pointer or hard frame pointer for reloads! 3538 The hard frame pointer would normally be OK except that it may 3539 briefly hold an incoming argument in the prologue, and reload 3540 won't know that it is live because the hard frame pointer is 3541 treated specially. */ 3542 3543 if (rclass == AR_REGS || rclass == GR_REGS) 3544 return RL_REGS; 3545 3546 return rclass; 3547 } 3548 3549 /* Worker function for TARGET_PREFERRED_OUTPUT_RELOAD_CLASS. */ 3550 3551 static reg_class_t 3552 xtensa_preferred_output_reload_class (rtx x ATTRIBUTE_UNUSED, 3553 reg_class_t rclass) 3554 { 3555 /* Don't use the stack pointer or hard frame pointer for reloads! 3556 The hard frame pointer would normally be OK except that it may 3557 briefly hold an incoming argument in the prologue, and reload 3558 won't know that it is live because the hard frame pointer is 3559 treated specially. */ 3560 3561 if (rclass == AR_REGS || rclass == GR_REGS) 3562 return RL_REGS; 3563 3564 return rclass; 3565 } 3566 3567 /* Worker function for TARGET_SECONDARY_RELOAD. */ 3568 3569 static reg_class_t 3570 xtensa_secondary_reload (bool in_p, rtx x, reg_class_t rclass, 3571 machine_mode mode, secondary_reload_info *sri) 3572 { 3573 int regno; 3574 3575 if (in_p && constantpool_mem_p (x)) 3576 { 3577 if (rclass == FP_REGS) 3578 return RL_REGS; 3579 3580 if (mode == QImode) 3581 sri->icode = CODE_FOR_reloadqi_literal; 3582 else if (mode == HImode) 3583 sri->icode = CODE_FOR_reloadhi_literal; 3584 } 3585 3586 regno = xt_true_regnum (x); 3587 if (ACC_REG_P (regno)) 3588 return ((rclass == GR_REGS || rclass == RL_REGS) ? NO_REGS : RL_REGS); 3589 if (rclass == ACC_REG) 3590 return (GP_REG_P (regno) ? NO_REGS : RL_REGS); 3591 3592 return NO_REGS; 3593 } 3594 3595 3596 void 3597 order_regs_for_local_alloc (void) 3598 { 3599 if (!leaf_function_p ()) 3600 { 3601 static const int reg_nonleaf_alloc_order[FIRST_PSEUDO_REGISTER] = 3602 REG_ALLOC_ORDER; 3603 static const int reg_nonleaf_alloc_order_call0[FIRST_PSEUDO_REGISTER] = 3604 { 3605 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 12, 13, 14, 15, 3606 18, 3607 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 3608 0, 1, 16, 17, 3609 35, 3610 }; 3611 3612 memcpy (reg_alloc_order, TARGET_WINDOWED_ABI ? 3613 reg_nonleaf_alloc_order : reg_nonleaf_alloc_order_call0, 3614 FIRST_PSEUDO_REGISTER * sizeof (int)); 3615 } 3616 else 3617 { 3618 int i, num_arg_regs; 3619 int nxt = 0; 3620 3621 /* Use the AR registers in increasing order (skipping a0 and a1) 3622 but save the incoming argument registers for a last resort. */ 3623 num_arg_regs = crtl->args.info.arg_words; 3624 if (num_arg_regs > MAX_ARGS_IN_REGISTERS) 3625 num_arg_regs = MAX_ARGS_IN_REGISTERS; 3626 for (i = GP_ARG_FIRST; i < 16 - num_arg_regs; i++) 3627 reg_alloc_order[nxt++] = i + num_arg_regs; 3628 for (i = 0; i < num_arg_regs; i++) 3629 reg_alloc_order[nxt++] = GP_ARG_FIRST + i; 3630 3631 /* List the coprocessor registers in order. */ 3632 for (i = 0; i < BR_REG_NUM; i++) 3633 reg_alloc_order[nxt++] = BR_REG_FIRST + i; 3634 3635 /* List the FP registers in order for now. */ 3636 for (i = 0; i < 16; i++) 3637 reg_alloc_order[nxt++] = FP_REG_FIRST + i; 3638 3639 /* GCC requires that we list *all* the registers.... */ 3640 reg_alloc_order[nxt++] = 0; /* a0 = return address */ 3641 reg_alloc_order[nxt++] = 1; /* a1 = stack pointer */ 3642 reg_alloc_order[nxt++] = 16; /* pseudo frame pointer */ 3643 reg_alloc_order[nxt++] = 17; /* pseudo arg pointer */ 3644 3645 reg_alloc_order[nxt++] = ACC_REG_FIRST; /* MAC16 accumulator */ 3646 } 3647 } 3648 3649 3650 /* Some Xtensa targets support multiple bss sections. If the section 3651 name ends with ".bss", add SECTION_BSS to the flags. */ 3652 3653 static unsigned int 3654 xtensa_multibss_section_type_flags (tree decl, const char *name, int reloc) 3655 { 3656 unsigned int flags = default_section_type_flags (decl, name, reloc); 3657 const char *suffix; 3658 3659 suffix = strrchr (name, '.'); 3660 if (suffix && strcmp (suffix, ".bss") == 0) 3661 { 3662 if (!decl || (TREE_CODE (decl) == VAR_DECL 3663 && DECL_INITIAL (decl) == NULL_TREE)) 3664 flags |= SECTION_BSS; /* @nobits */ 3665 else 3666 warning (0, "only uninitialized variables can be placed in a " 3667 "%<.bss%> section"); 3668 } 3669 3670 return flags; 3671 } 3672 3673 3674 /* The literal pool stays with the function. */ 3675 3676 static section * 3677 xtensa_select_rtx_section (machine_mode mode ATTRIBUTE_UNUSED, 3678 rtx x ATTRIBUTE_UNUSED, 3679 unsigned HOST_WIDE_INT align ATTRIBUTE_UNUSED) 3680 { 3681 return function_section (current_function_decl); 3682 } 3683 3684 /* Worker function for TARGET_REGISTER_MOVE_COST. */ 3685 3686 static int 3687 xtensa_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 3688 reg_class_t from, reg_class_t to) 3689 { 3690 if (from == to && from != BR_REGS && to != BR_REGS) 3691 return 2; 3692 else if (reg_class_subset_p (from, AR_REGS) 3693 && reg_class_subset_p (to, AR_REGS)) 3694 return 2; 3695 else if (reg_class_subset_p (from, AR_REGS) && to == ACC_REG) 3696 return 3; 3697 else if (from == ACC_REG && reg_class_subset_p (to, AR_REGS)) 3698 return 3; 3699 else 3700 return 10; 3701 } 3702 3703 /* Worker function for TARGET_MEMORY_MOVE_COST. */ 3704 3705 static int 3706 xtensa_memory_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 3707 reg_class_t rclass ATTRIBUTE_UNUSED, 3708 bool in ATTRIBUTE_UNUSED) 3709 { 3710 return 4; 3711 } 3712 3713 /* Compute a (partial) cost for rtx X. Return true if the complete 3714 cost has been computed, and false if subexpressions should be 3715 scanned. In either case, *TOTAL contains the cost result. */ 3716 3717 static bool 3718 xtensa_rtx_costs (rtx x, machine_mode mode, int outer_code, 3719 int opno ATTRIBUTE_UNUSED, 3720 int *total, bool speed ATTRIBUTE_UNUSED) 3721 { 3722 int code = GET_CODE (x); 3723 3724 switch (code) 3725 { 3726 case CONST_INT: 3727 switch (outer_code) 3728 { 3729 case SET: 3730 if (xtensa_simm12b (INTVAL (x))) 3731 { 3732 *total = 4; 3733 return true; 3734 } 3735 break; 3736 case PLUS: 3737 if (xtensa_simm8 (INTVAL (x)) 3738 || xtensa_simm8x256 (INTVAL (x))) 3739 { 3740 *total = 0; 3741 return true; 3742 } 3743 break; 3744 case AND: 3745 if (xtensa_mask_immediate (INTVAL (x))) 3746 { 3747 *total = 0; 3748 return true; 3749 } 3750 break; 3751 case COMPARE: 3752 if ((INTVAL (x) == 0) || xtensa_b4const (INTVAL (x))) 3753 { 3754 *total = 0; 3755 return true; 3756 } 3757 break; 3758 case ASHIFT: 3759 case ASHIFTRT: 3760 case LSHIFTRT: 3761 case ROTATE: 3762 case ROTATERT: 3763 /* No way to tell if X is the 2nd operand so be conservative. */ 3764 default: break; 3765 } 3766 if (xtensa_simm12b (INTVAL (x))) 3767 *total = 5; 3768 else if (TARGET_CONST16) 3769 *total = COSTS_N_INSNS (2); 3770 else 3771 *total = 6; 3772 return true; 3773 3774 case CONST: 3775 case LABEL_REF: 3776 case SYMBOL_REF: 3777 if (TARGET_CONST16) 3778 *total = COSTS_N_INSNS (2); 3779 else 3780 *total = 5; 3781 return true; 3782 3783 case CONST_DOUBLE: 3784 if (TARGET_CONST16) 3785 *total = COSTS_N_INSNS (4); 3786 else 3787 *total = 7; 3788 return true; 3789 3790 case MEM: 3791 { 3792 int num_words = 3793 (GET_MODE_SIZE (mode) > UNITS_PER_WORD) ? 2 : 1; 3794 3795 if (memory_address_p (mode, XEXP ((x), 0))) 3796 *total = COSTS_N_INSNS (num_words); 3797 else 3798 *total = COSTS_N_INSNS (2*num_words); 3799 return true; 3800 } 3801 3802 case FFS: 3803 case CTZ: 3804 *total = COSTS_N_INSNS (TARGET_NSA ? 5 : 50); 3805 return true; 3806 3807 case CLZ: 3808 *total = COSTS_N_INSNS (TARGET_NSA ? 1 : 50); 3809 return true; 3810 3811 case NOT: 3812 *total = COSTS_N_INSNS (mode == DImode ? 3 : 2); 3813 return true; 3814 3815 case AND: 3816 case IOR: 3817 case XOR: 3818 if (mode == DImode) 3819 *total = COSTS_N_INSNS (2); 3820 else 3821 *total = COSTS_N_INSNS (1); 3822 return true; 3823 3824 case ASHIFT: 3825 case ASHIFTRT: 3826 case LSHIFTRT: 3827 if (mode == DImode) 3828 *total = COSTS_N_INSNS (50); 3829 else 3830 *total = COSTS_N_INSNS (1); 3831 return true; 3832 3833 case ABS: 3834 { 3835 if (mode == SFmode) 3836 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); 3837 else if (mode == DFmode) 3838 *total = COSTS_N_INSNS (50); 3839 else 3840 *total = COSTS_N_INSNS (4); 3841 return true; 3842 } 3843 3844 case PLUS: 3845 case MINUS: 3846 { 3847 if (mode == SFmode) 3848 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 1 : 50); 3849 else if (mode == DFmode || mode == DImode) 3850 *total = COSTS_N_INSNS (50); 3851 else 3852 *total = COSTS_N_INSNS (1); 3853 return true; 3854 } 3855 3856 case NEG: 3857 *total = COSTS_N_INSNS (mode == DImode ? 4 : 2); 3858 return true; 3859 3860 case MULT: 3861 { 3862 if (mode == SFmode) 3863 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT ? 4 : 50); 3864 else if (mode == DFmode) 3865 *total = COSTS_N_INSNS (50); 3866 else if (mode == DImode) 3867 *total = COSTS_N_INSNS (TARGET_MUL32_HIGH ? 10 : 50); 3868 else if (TARGET_MUL32) 3869 *total = COSTS_N_INSNS (4); 3870 else if (TARGET_MAC16) 3871 *total = COSTS_N_INSNS (16); 3872 else if (TARGET_MUL16) 3873 *total = COSTS_N_INSNS (12); 3874 else 3875 *total = COSTS_N_INSNS (50); 3876 return true; 3877 } 3878 3879 case DIV: 3880 case MOD: 3881 { 3882 if (mode == SFmode) 3883 { 3884 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_DIV ? 8 : 50); 3885 return true; 3886 } 3887 else if (mode == DFmode) 3888 { 3889 *total = COSTS_N_INSNS (50); 3890 return true; 3891 } 3892 } 3893 /* Fall through. */ 3894 3895 case UDIV: 3896 case UMOD: 3897 { 3898 if (mode == DImode) 3899 *total = COSTS_N_INSNS (50); 3900 else if (TARGET_DIV32) 3901 *total = COSTS_N_INSNS (32); 3902 else 3903 *total = COSTS_N_INSNS (50); 3904 return true; 3905 } 3906 3907 case SQRT: 3908 if (mode == SFmode) 3909 *total = COSTS_N_INSNS (TARGET_HARD_FLOAT_SQRT ? 8 : 50); 3910 else 3911 *total = COSTS_N_INSNS (50); 3912 return true; 3913 3914 case SMIN: 3915 case UMIN: 3916 case SMAX: 3917 case UMAX: 3918 *total = COSTS_N_INSNS (TARGET_MINMAX ? 1 : 50); 3919 return true; 3920 3921 case SIGN_EXTRACT: 3922 case SIGN_EXTEND: 3923 *total = COSTS_N_INSNS (TARGET_SEXT ? 1 : 2); 3924 return true; 3925 3926 case ZERO_EXTRACT: 3927 case ZERO_EXTEND: 3928 *total = COSTS_N_INSNS (1); 3929 return true; 3930 3931 default: 3932 return false; 3933 } 3934 } 3935 3936 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 3937 3938 static bool 3939 xtensa_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 3940 { 3941 return ((unsigned HOST_WIDE_INT) int_size_in_bytes (type) 3942 > 4 * UNITS_PER_WORD); 3943 } 3944 3945 /* Worker function for TARGET_FUNCTION_VALUE. */ 3946 3947 rtx 3948 xtensa_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED, 3949 bool outgoing) 3950 { 3951 return gen_rtx_REG ((INTEGRAL_TYPE_P (valtype) 3952 && TYPE_PRECISION (valtype) < BITS_PER_WORD) 3953 ? SImode : TYPE_MODE (valtype), 3954 outgoing ? GP_OUTGOING_RETURN : GP_RETURN); 3955 } 3956 3957 /* Worker function for TARGET_LIBCALL_VALUE. */ 3958 3959 static rtx 3960 xtensa_libcall_value (machine_mode mode, const_rtx fun ATTRIBUTE_UNUSED) 3961 { 3962 return gen_rtx_REG ((GET_MODE_CLASS (mode) == MODE_INT 3963 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 3964 ? SImode : mode, GP_RETURN); 3965 } 3966 3967 /* Worker function TARGET_FUNCTION_VALUE_REGNO_P. */ 3968 3969 static bool 3970 xtensa_function_value_regno_p (const unsigned int regno) 3971 { 3972 return (regno == GP_RETURN); 3973 } 3974 3975 /* The static chain is passed in memory. Provide rtx giving 'mem' 3976 expressions that denote where they are stored. */ 3977 3978 static rtx 3979 xtensa_static_chain (const_tree ARG_UNUSED (fndecl_or_type), bool incoming_p) 3980 { 3981 if (TARGET_WINDOWED_ABI) 3982 { 3983 rtx base = incoming_p ? arg_pointer_rtx : stack_pointer_rtx; 3984 return gen_frame_mem (Pmode, plus_constant (Pmode, base, 3985 -5 * UNITS_PER_WORD)); 3986 } 3987 else 3988 return gen_rtx_REG (Pmode, A8_REG); 3989 } 3990 3991 3992 /* TRAMPOLINE_TEMPLATE: For Xtensa, the trampoline must perform an ENTRY 3993 instruction with a minimal stack frame in order to get some free 3994 registers. Once the actual call target is known, the proper stack frame 3995 size is extracted from the ENTRY instruction at the target and the 3996 current frame is adjusted to match. The trampoline then transfers 3997 control to the instruction following the ENTRY at the target. Note: 3998 this assumes that the target begins with an ENTRY instruction. */ 3999 4000 static void 4001 xtensa_asm_trampoline_template (FILE *stream) 4002 { 4003 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); 4004 4005 fprintf (stream, "\t.begin no-transform\n"); 4006 4007 if (TARGET_WINDOWED_ABI) 4008 { 4009 fprintf (stream, "\tentry\tsp, %d\n", MIN_FRAME_SIZE); 4010 4011 if (use_call0) 4012 { 4013 /* Save the return address. */ 4014 fprintf (stream, "\tmov\ta10, a0\n"); 4015 4016 /* Use a CALL0 instruction to skip past the constants and in the 4017 process get the PC into A0. This allows PC-relative access to 4018 the constants without relying on L32R. */ 4019 fprintf (stream, "\tcall0\t.Lskipconsts\n"); 4020 } 4021 else 4022 fprintf (stream, "\tj\t.Lskipconsts\n"); 4023 4024 fprintf (stream, "\t.align\t4\n"); 4025 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); 4026 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); 4027 fprintf (stream, ".Lskipconsts:\n"); 4028 4029 /* Load the static chain and function address from the trampoline. */ 4030 if (use_call0) 4031 { 4032 fprintf (stream, "\taddi\ta0, a0, 3\n"); 4033 fprintf (stream, "\tl32i\ta9, a0, 0\n"); 4034 fprintf (stream, "\tl32i\ta8, a0, 4\n"); 4035 } 4036 else 4037 { 4038 fprintf (stream, "\tl32r\ta9, .Lchainval\n"); 4039 fprintf (stream, "\tl32r\ta8, .Lfnaddr\n"); 4040 } 4041 4042 /* Store the static chain. */ 4043 fprintf (stream, "\ts32i\ta9, sp, %d\n", MIN_FRAME_SIZE - 20); 4044 4045 /* Set the proper stack pointer value. */ 4046 fprintf (stream, "\tl32i\ta9, a8, 0\n"); 4047 fprintf (stream, "\textui\ta9, a9, %d, 12\n", 4048 TARGET_BIG_ENDIAN ? 8 : 12); 4049 fprintf (stream, "\tslli\ta9, a9, 3\n"); 4050 fprintf (stream, "\taddi\ta9, a9, %d\n", -MIN_FRAME_SIZE); 4051 fprintf (stream, "\tsub\ta9, sp, a9\n"); 4052 fprintf (stream, "\tmovsp\tsp, a9\n"); 4053 4054 if (use_call0) 4055 /* Restore the return address. */ 4056 fprintf (stream, "\tmov\ta0, a10\n"); 4057 4058 /* Jump to the instruction following the ENTRY. */ 4059 fprintf (stream, "\taddi\ta8, a8, 3\n"); 4060 fprintf (stream, "\tjx\ta8\n"); 4061 4062 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */ 4063 if (use_call0) 4064 fprintf (stream, "\t.byte\t0\n"); 4065 else 4066 fprintf (stream, "\tnop\n"); 4067 } 4068 else 4069 { 4070 if (use_call0) 4071 { 4072 /* Save the return address. */ 4073 fprintf (stream, "\tmov\ta10, a0\n"); 4074 4075 /* Use a CALL0 instruction to skip past the constants and in the 4076 process get the PC into A0. This allows PC-relative access to 4077 the constants without relying on L32R. */ 4078 fprintf (stream, "\tcall0\t.Lskipconsts\n"); 4079 } 4080 else 4081 fprintf (stream, "\tj\t.Lskipconsts\n"); 4082 4083 fprintf (stream, "\t.align\t4\n"); 4084 fprintf (stream, ".Lchainval:%s0\n", integer_asm_op (4, TRUE)); 4085 fprintf (stream, ".Lfnaddr:%s0\n", integer_asm_op (4, TRUE)); 4086 fprintf (stream, ".Lskipconsts:\n"); 4087 4088 /* Load the static chain and function address from the trampoline. */ 4089 if (use_call0) 4090 { 4091 fprintf (stream, "\taddi\ta0, a0, 3\n"); 4092 fprintf (stream, "\tl32i\ta8, a0, 0\n"); 4093 fprintf (stream, "\tl32i\ta9, a0, 4\n"); 4094 fprintf (stream, "\tmov\ta0, a10\n"); 4095 } 4096 else 4097 { 4098 fprintf (stream, "\tl32r\ta8, .Lchainval\n"); 4099 fprintf (stream, "\tl32r\ta9, .Lfnaddr\n"); 4100 } 4101 fprintf (stream, "\tjx\ta9\n"); 4102 4103 /* Pad size to a multiple of TRAMPOLINE_ALIGNMENT. */ 4104 if (use_call0) 4105 fprintf (stream, "\t.byte\t0\n"); 4106 else 4107 fprintf (stream, "\tnop\n"); 4108 } 4109 fprintf (stream, "\t.end no-transform\n"); 4110 } 4111 4112 static void 4113 xtensa_trampoline_init (rtx m_tramp, tree fndecl, rtx chain) 4114 { 4115 rtx func = XEXP (DECL_RTL (fndecl), 0); 4116 bool use_call0 = (TARGET_CONST16 || TARGET_ABSOLUTE_LITERALS); 4117 int chain_off; 4118 int func_off; 4119 4120 if (TARGET_WINDOWED_ABI) 4121 { 4122 chain_off = use_call0 ? 12 : 8; 4123 func_off = use_call0 ? 16 : 12; 4124 } 4125 else 4126 { 4127 chain_off = use_call0 ? 8 : 4; 4128 func_off = use_call0 ? 12 : 8; 4129 } 4130 4131 emit_block_move (m_tramp, assemble_trampoline_template (), 4132 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL); 4133 4134 emit_move_insn (adjust_address (m_tramp, SImode, chain_off), chain); 4135 emit_move_insn (adjust_address (m_tramp, SImode, func_off), func); 4136 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__xtensa_sync_caches"), 4137 LCT_NORMAL, VOIDmode, XEXP (m_tramp, 0), Pmode); 4138 } 4139 4140 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 4141 4142 static bool 4143 xtensa_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 4144 { 4145 return !xtensa_tls_referenced_p (x); 4146 } 4147 4148 /* Implement TARGET_CAN_USE_DOLOOP_P. */ 4149 4150 static bool 4151 xtensa_can_use_doloop_p (const widest_int &, const widest_int &, 4152 unsigned int loop_depth, bool entered_at_top) 4153 { 4154 /* Considering limitations in the hardware, only use doloop 4155 for innermost loops which must be entered from the top. */ 4156 if (loop_depth > 1 || !entered_at_top) 4157 return false; 4158 4159 return true; 4160 } 4161 4162 /* NULL if INSN insn is valid within a low-overhead loop. 4163 Otherwise return why doloop cannot be applied. */ 4164 4165 static const char * 4166 xtensa_invalid_within_doloop (const rtx_insn *insn) 4167 { 4168 if (CALL_P (insn)) 4169 return "Function call in the loop."; 4170 4171 if (JUMP_P (insn) && INSN_CODE (insn) == CODE_FOR_return) 4172 return "Return from a call instruction in the loop."; 4173 4174 return NULL; 4175 } 4176 4177 /* Optimize LOOP. */ 4178 4179 static bool 4180 hwloop_optimize (hwloop_info loop) 4181 { 4182 int i; 4183 edge entry_edge; 4184 basic_block entry_bb; 4185 rtx iter_reg; 4186 rtx_insn *insn, *seq, *entry_after; 4187 4188 if (loop->depth > 1) 4189 { 4190 if (dump_file) 4191 fprintf (dump_file, ";; loop %d is not innermost\n", 4192 loop->loop_no); 4193 return false; 4194 } 4195 4196 if (!loop->incoming_dest) 4197 { 4198 if (dump_file) 4199 fprintf (dump_file, ";; loop %d has more than one entry\n", 4200 loop->loop_no); 4201 return false; 4202 } 4203 4204 if (loop->incoming_dest != loop->head) 4205 { 4206 if (dump_file) 4207 fprintf (dump_file, ";; loop %d is not entered from head\n", 4208 loop->loop_no); 4209 return false; 4210 } 4211 4212 if (loop->has_call || loop->has_asm) 4213 { 4214 if (dump_file) 4215 fprintf (dump_file, ";; loop %d has invalid insn\n", 4216 loop->loop_no); 4217 return false; 4218 } 4219 4220 /* Scan all the blocks to make sure they don't use iter_reg. */ 4221 if (loop->iter_reg_used || loop->iter_reg_used_outside) 4222 { 4223 if (dump_file) 4224 fprintf (dump_file, ";; loop %d uses iterator\n", 4225 loop->loop_no); 4226 return false; 4227 } 4228 4229 /* Check if start_label appears before doloop_end. */ 4230 insn = loop->start_label; 4231 while (insn && insn != loop->loop_end) 4232 insn = NEXT_INSN (insn); 4233 4234 if (!insn) 4235 { 4236 if (dump_file) 4237 fprintf (dump_file, ";; loop %d start_label not before loop_end\n", 4238 loop->loop_no); 4239 return false; 4240 } 4241 4242 /* Get the loop iteration register. */ 4243 iter_reg = loop->iter_reg; 4244 4245 gcc_assert (REG_P (iter_reg)); 4246 4247 entry_edge = NULL; 4248 4249 FOR_EACH_VEC_SAFE_ELT (loop->incoming, i, entry_edge) 4250 if (entry_edge->flags & EDGE_FALLTHRU) 4251 break; 4252 4253 if (entry_edge == NULL) 4254 return false; 4255 4256 /* Place the zero_cost_loop_start instruction before the loop. */ 4257 entry_bb = entry_edge->src; 4258 4259 start_sequence (); 4260 4261 insn = emit_insn (gen_zero_cost_loop_start (loop->iter_reg, 4262 loop->start_label, 4263 loop->iter_reg)); 4264 4265 seq = get_insns (); 4266 4267 entry_after = BB_END (entry_bb); 4268 if (!single_succ_p (entry_bb) || vec_safe_length (loop->incoming) > 1 4269 || !entry_after) 4270 { 4271 basic_block new_bb; 4272 edge e; 4273 edge_iterator ei; 4274 4275 emit_insn_before (seq, BB_HEAD (loop->head)); 4276 seq = emit_label_before (gen_label_rtx (), seq); 4277 new_bb = create_basic_block (seq, insn, entry_bb); 4278 FOR_EACH_EDGE (e, ei, loop->incoming) 4279 { 4280 if (!(e->flags & EDGE_FALLTHRU)) 4281 redirect_edge_and_branch_force (e, new_bb); 4282 else 4283 redirect_edge_succ (e, new_bb); 4284 } 4285 4286 make_edge (new_bb, loop->head, 0); 4287 } 4288 else 4289 { 4290 while (DEBUG_INSN_P (entry_after) 4291 || (NOTE_P (entry_after) 4292 && NOTE_KIND (entry_after) != NOTE_INSN_BASIC_BLOCK)) 4293 entry_after = PREV_INSN (entry_after); 4294 4295 emit_insn_after (seq, entry_after); 4296 } 4297 4298 end_sequence (); 4299 4300 return true; 4301 } 4302 4303 /* A callback for the hw-doloop pass. Called when a loop we have discovered 4304 turns out not to be optimizable; we have to split the loop_end pattern into 4305 a subtract and a test. */ 4306 4307 static void 4308 hwloop_fail (hwloop_info loop) 4309 { 4310 rtx test; 4311 rtx_insn *insn = loop->loop_end; 4312 4313 emit_insn_before (gen_addsi3 (loop->iter_reg, 4314 loop->iter_reg, 4315 constm1_rtx), 4316 loop->loop_end); 4317 4318 test = gen_rtx_NE (VOIDmode, loop->iter_reg, const0_rtx); 4319 insn = emit_jump_insn_before (gen_cbranchsi4 (test, 4320 loop->iter_reg, const0_rtx, 4321 loop->start_label), 4322 loop->loop_end); 4323 4324 JUMP_LABEL (insn) = loop->start_label; 4325 LABEL_NUSES (loop->start_label)++; 4326 delete_insn (loop->loop_end); 4327 } 4328 4329 /* A callback for the hw-doloop pass. This function examines INSN; if 4330 it is a doloop_end pattern we recognize, return the reg rtx for the 4331 loop counter. Otherwise, return NULL_RTX. */ 4332 4333 static rtx 4334 hwloop_pattern_reg (rtx_insn *insn) 4335 { 4336 rtx reg; 4337 4338 if (!JUMP_P (insn) || recog_memoized (insn) != CODE_FOR_loop_end) 4339 return NULL_RTX; 4340 4341 reg = SET_DEST (XVECEXP (PATTERN (insn), 0, 1)); 4342 if (!REG_P (reg)) 4343 return NULL_RTX; 4344 4345 return reg; 4346 } 4347 4348 4349 static struct hw_doloop_hooks xtensa_doloop_hooks = 4350 { 4351 hwloop_pattern_reg, 4352 hwloop_optimize, 4353 hwloop_fail 4354 }; 4355 4356 /* Run from machine_dependent_reorg, this pass looks for doloop_end insns 4357 and tries to rewrite the RTL of these loops so that proper Xtensa 4358 hardware loops are generated. */ 4359 4360 static void 4361 xtensa_reorg_loops (void) 4362 { 4363 if (TARGET_LOOPS) 4364 reorg_loops (false, &xtensa_doloop_hooks); 4365 } 4366 4367 /* Implement the TARGET_MACHINE_DEPENDENT_REORG pass. */ 4368 4369 static void 4370 xtensa_reorg (void) 4371 { 4372 /* We are freeing block_for_insn in the toplev to keep compatibility 4373 with old MDEP_REORGS that are not CFG based. Recompute it now. */ 4374 compute_bb_for_insn (); 4375 4376 df_analyze (); 4377 4378 /* Doloop optimization. */ 4379 xtensa_reorg_loops (); 4380 } 4381 4382 /* Update register usage after having seen the compiler flags. */ 4383 4384 static void 4385 xtensa_conditional_register_usage (void) 4386 { 4387 unsigned i, c_mask; 4388 4389 c_mask = TARGET_WINDOWED_ABI ? (1 << 1) : (1 << 2); 4390 4391 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4392 { 4393 /* Set/reset conditionally defined registers from 4394 CALL_USED_REGISTERS initializer. */ 4395 if (call_used_regs[i] > 1) 4396 call_used_regs[i] = !!(call_used_regs[i] & c_mask); 4397 } 4398 4399 /* Remove hard FP register from the preferred reload registers set. */ 4400 CLEAR_HARD_REG_BIT (reg_class_contents[(int)RL_REGS], 4401 HARD_FRAME_POINTER_REGNUM); 4402 } 4403 4404 /* Map hard register number to register class */ 4405 4406 enum reg_class xtensa_regno_to_class (int regno) 4407 { 4408 static const enum reg_class regno_to_class[FIRST_PSEUDO_REGISTER] = 4409 { 4410 RL_REGS, SP_REG, RL_REGS, RL_REGS, 4411 RL_REGS, RL_REGS, RL_REGS, RL_REGS, 4412 RL_REGS, RL_REGS, RL_REGS, RL_REGS, 4413 RL_REGS, RL_REGS, RL_REGS, RL_REGS, 4414 AR_REGS, AR_REGS, BR_REGS, 4415 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 4416 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 4417 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 4418 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 4419 ACC_REG, 4420 }; 4421 4422 if (regno == HARD_FRAME_POINTER_REGNUM) 4423 return GR_REGS; 4424 else 4425 return regno_to_class[regno]; 4426 } 4427 4428 /* Implement TARGET_CONSTANT_ALIGNMENT. Align string constants and 4429 constructors to at least a word boundary. The typical use of this 4430 macro is to increase alignment for string constants to be word 4431 aligned so that 'strcpy' calls that copy constants can be done 4432 inline. */ 4433 4434 static HOST_WIDE_INT 4435 xtensa_constant_alignment (const_tree exp, HOST_WIDE_INT align) 4436 { 4437 if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) 4438 && !optimize_size) 4439 return MAX (align, BITS_PER_WORD); 4440 return align; 4441 } 4442 4443 static bool 4444 xtensa_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 4445 { 4446 gcc_assert (from == ARG_POINTER_REGNUM || from == FRAME_POINTER_REGNUM); 4447 4448 /* If we need a frame pointer, ARG_POINTER_REGNUM and FRAME_POINTER_REGNUM 4449 can only eliminate to HARD_FRAME_POINTER_REGNUM. */ 4450 return to == HARD_FRAME_POINTER_REGNUM 4451 || (!frame_pointer_needed && to == STACK_POINTER_REGNUM); 4452 } 4453 4454 /* Implement TARGET_STARTING_FRAME_OFFSET. */ 4455 4456 static HOST_WIDE_INT 4457 xtensa_starting_frame_offset (void) 4458 { 4459 if (FRAME_GROWS_DOWNWARD) 4460 return 0; 4461 return crtl->outgoing_args_size; 4462 } 4463 4464 /* Implement TARGET_ASAN_SHADOW_OFFSET. */ 4465 4466 static unsigned HOST_WIDE_INT 4467 xtensa_asan_shadow_offset (void) 4468 { 4469 return HOST_WIDE_INT_UC (0x10000000); 4470 } 4471 4472 static rtx 4473 xtensa_delegitimize_address (rtx op) 4474 { 4475 switch (GET_CODE (op)) 4476 { 4477 case CONST: 4478 return xtensa_delegitimize_address (XEXP (op, 0)); 4479 4480 case UNSPEC: 4481 if (XINT (op, 1) == UNSPEC_PLT) 4482 return XVECEXP(op, 0, 0); 4483 break; 4484 4485 default: 4486 break; 4487 } 4488 return op; 4489 } 4490 4491 #include "gt-xtensa.h" 4492
Indexes created Mon Mar 30 00:23:01 UTC 2026