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ira-int.h revision 1.1.1.1
      1  1.1  mrg /* Integrated Register Allocator (IRA) intercommunication header file.
      2  1.1  mrg    Copyright (C) 2006, 2007, 2008, 2009
      3  1.1  mrg    Free Software Foundation, Inc.
      4  1.1  mrg    Contributed by Vladimir Makarov <vmakarov (at) redhat.com>.
      5  1.1  mrg 
      6  1.1  mrg This file is part of GCC.
      7  1.1  mrg 
      8  1.1  mrg GCC is free software; you can redistribute it and/or modify it under
      9  1.1  mrg the terms of the GNU General Public License as published by the Free
     10  1.1  mrg Software Foundation; either version 3, or (at your option) any later
     11  1.1  mrg version.
     12  1.1  mrg 
     13  1.1  mrg GCC is distributed in the hope that it will be useful, but WITHOUT ANY
     14  1.1  mrg WARRANTY; without even the implied warranty of MERCHANTABILITY or
     15  1.1  mrg FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
     16  1.1  mrg for more details.
     17  1.1  mrg 
     18  1.1  mrg You should have received a copy of the GNU General Public License
     19  1.1  mrg along with GCC; see the file COPYING3.  If not see
     20  1.1  mrg <http://www.gnu.org/licenses/>.  */
     21  1.1  mrg 
     22  1.1  mrg #include "cfgloop.h"
     23  1.1  mrg #include "ira.h"
     24  1.1  mrg #include "alloc-pool.h"
     25  1.1  mrg 
     26  1.1  mrg /* To provide consistency in naming, all IRA external variables,
     27  1.1  mrg    functions, common typedefs start with prefix ira_.  */
     28  1.1  mrg 
     29  1.1  mrg #ifdef ENABLE_CHECKING
     30  1.1  mrg #define ENABLE_IRA_CHECKING
     31  1.1  mrg #endif
     32  1.1  mrg 
     33  1.1  mrg #ifdef ENABLE_IRA_CHECKING
     34  1.1  mrg #define ira_assert(c) gcc_assert (c)
     35  1.1  mrg #else
     36  1.1  mrg /* Always define and include C, so that warnings for empty body in an
     37  1.1  mrg   if statement and unused variable do not occur.  */
     38  1.1  mrg #define ira_assert(c) ((void)(0 && (c)))
     39  1.1  mrg #endif
     40  1.1  mrg 
     41  1.1  mrg /* Compute register frequency from edge frequency FREQ.  It is
     42  1.1  mrg    analogous to REG_FREQ_FROM_BB.  When optimizing for size, or
     43  1.1  mrg    profile driven feedback is available and the function is never
     44  1.1  mrg    executed, frequency is always equivalent.  Otherwise rescale the
     45  1.1  mrg    edge frequency.  */
     46  1.1  mrg #define REG_FREQ_FROM_EDGE_FREQ(freq)					      \
     47  1.1  mrg   (optimize_size || (flag_branch_probabilities && !ENTRY_BLOCK_PTR->count)    \
     48  1.1  mrg    ? REG_FREQ_MAX : (freq * REG_FREQ_MAX / BB_FREQ_MAX)			      \
     49  1.1  mrg    ? (freq * REG_FREQ_MAX / BB_FREQ_MAX) : 1)
     50  1.1  mrg 
     51  1.1  mrg /* All natural loops.  */
     52  1.1  mrg extern struct loops ira_loops;
     53  1.1  mrg 
     54  1.1  mrg /* A modified value of flag `-fira-verbose' used internally.  */
     55  1.1  mrg extern int internal_flag_ira_verbose;
     56  1.1  mrg 
     57  1.1  mrg /* Dump file of the allocator if it is not NULL.  */
     58  1.1  mrg extern FILE *ira_dump_file;
     59  1.1  mrg 
     60  1.1  mrg /* Typedefs for pointers to allocno live range, allocno, and copy of
     61  1.1  mrg    allocnos.  */
     62  1.1  mrg typedef struct ira_allocno_live_range *allocno_live_range_t;
     63  1.1  mrg typedef struct ira_allocno *ira_allocno_t;
     64  1.1  mrg typedef struct ira_allocno_copy *ira_copy_t;
     65  1.1  mrg 
     66  1.1  mrg /* Definition of vector of allocnos and copies.  */
     67  1.1  mrg DEF_VEC_P(ira_allocno_t);
     68  1.1  mrg DEF_VEC_ALLOC_P(ira_allocno_t, heap);
     69  1.1  mrg DEF_VEC_P(ira_copy_t);
     70  1.1  mrg DEF_VEC_ALLOC_P(ira_copy_t, heap);
     71  1.1  mrg 
     72  1.1  mrg /* Typedef for pointer to the subsequent structure.  */
     73  1.1  mrg typedef struct ira_loop_tree_node *ira_loop_tree_node_t;
     74  1.1  mrg 
     75  1.1  mrg /* In general case, IRA is a regional allocator.  The regions are
     76  1.1  mrg    nested and form a tree.  Currently regions are natural loops.  The
     77  1.1  mrg    following structure describes loop tree node (representing basic
     78  1.1  mrg    block or loop).  We need such tree because the loop tree from
     79  1.1  mrg    cfgloop.h is not convenient for the optimization: basic blocks are
     80  1.1  mrg    not a part of the tree from cfgloop.h.  We also use the nodes for
     81  1.1  mrg    storing additional information about basic blocks/loops for the
     82  1.1  mrg    register allocation purposes.  */
     83  1.1  mrg struct ira_loop_tree_node
     84  1.1  mrg {
     85  1.1  mrg   /* The node represents basic block if children == NULL.  */
     86  1.1  mrg   basic_block bb;    /* NULL for loop.  */
     87  1.1  mrg   struct loop *loop; /* NULL for BB.  */
     88  1.1  mrg   /* NEXT/SUBLOOP_NEXT is the next node/loop-node of the same parent.
     89  1.1  mrg      SUBLOOP_NEXT is always NULL for BBs.  */
     90  1.1  mrg   ira_loop_tree_node_t subloop_next, next;
     91  1.1  mrg   /* CHILDREN/SUBLOOPS is the first node/loop-node immediately inside
     92  1.1  mrg      the node.  They are NULL for BBs.  */
     93  1.1  mrg   ira_loop_tree_node_t subloops, children;
     94  1.1  mrg   /* The node immediately containing given node.  */
     95  1.1  mrg   ira_loop_tree_node_t parent;
     96  1.1  mrg 
     97  1.1  mrg   /* Loop level in range [0, ira_loop_tree_height).  */
     98  1.1  mrg   int level;
     99  1.1  mrg 
    100  1.1  mrg   /* All the following members are defined only for nodes representing
    101  1.1  mrg      loops.  */
    102  1.1  mrg 
    103  1.1  mrg   /* True if the loop was marked for removal from the register
    104  1.1  mrg      allocation.  */
    105  1.1  mrg   bool to_remove_p;
    106  1.1  mrg 
    107  1.1  mrg   /* Allocnos in the loop corresponding to their regnos.  If it is
    108  1.1  mrg      NULL the loop does not form a separate register allocation region
    109  1.1  mrg      (e.g. because it has abnormal enter/exit edges and we can not put
    110  1.1  mrg      code for register shuffling on the edges if a different
    111  1.1  mrg      allocation is used for a pseudo-register on different sides of
    112  1.1  mrg      the edges).  Caps are not in the map (remember we can have more
    113  1.1  mrg      one cap with the same regno in a region).  */
    114  1.1  mrg   ira_allocno_t *regno_allocno_map;
    115  1.1  mrg 
    116  1.1  mrg   /* True if there is an entry to given loop not from its parent (or
    117  1.1  mrg      grandparent) basic block.  For example, it is possible for two
    118  1.1  mrg      adjacent loops inside another loop.  */
    119  1.1  mrg   bool entered_from_non_parent_p;
    120  1.1  mrg 
    121  1.1  mrg   /* Maximal register pressure inside loop for given register class
    122  1.1  mrg      (defined only for the cover classes).  */
    123  1.1  mrg   int reg_pressure[N_REG_CLASSES];
    124  1.1  mrg 
    125  1.1  mrg   /* Numbers of allocnos referred or living in the loop node (except
    126  1.1  mrg      for its subloops).  */
    127  1.1  mrg   bitmap all_allocnos;
    128  1.1  mrg 
    129  1.1  mrg   /* Numbers of allocnos living at the loop borders.  */
    130  1.1  mrg   bitmap border_allocnos;
    131  1.1  mrg 
    132  1.1  mrg   /* Regnos of pseudos modified in the loop node (including its
    133  1.1  mrg      subloops).  */
    134  1.1  mrg   bitmap modified_regnos;
    135  1.1  mrg 
    136  1.1  mrg   /* Numbers of copies referred in the corresponding loop.  */
    137  1.1  mrg   bitmap local_copies;
    138  1.1  mrg };
    139  1.1  mrg 
    140  1.1  mrg /* The root of the loop tree corresponding to the all function.  */
    141  1.1  mrg extern ira_loop_tree_node_t ira_loop_tree_root;
    142  1.1  mrg 
    143  1.1  mrg /* Height of the loop tree.  */
    144  1.1  mrg extern int ira_loop_tree_height;
    145  1.1  mrg 
    146  1.1  mrg /* All nodes representing basic blocks are referred through the
    147  1.1  mrg    following array.  We can not use basic block member `aux' for this
    148  1.1  mrg    because it is used for insertion of insns on edges.  */
    149  1.1  mrg extern ira_loop_tree_node_t ira_bb_nodes;
    150  1.1  mrg 
    151  1.1  mrg /* Two access macros to the nodes representing basic blocks.  */
    152  1.1  mrg #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007)
    153  1.1  mrg #define IRA_BB_NODE_BY_INDEX(index) __extension__			\
    154  1.1  mrg (({ ira_loop_tree_node_t _node = (&ira_bb_nodes[index]);	\
    155  1.1  mrg      if (_node->children != NULL || _node->loop != NULL || _node->bb == NULL)\
    156  1.1  mrg        {								\
    157  1.1  mrg          fprintf (stderr,						\
    158  1.1  mrg                   "\n%s: %d: error in %s: it is not a block node\n",	\
    159  1.1  mrg                   __FILE__, __LINE__, __FUNCTION__);			\
    160  1.1  mrg          gcc_unreachable ();						\
    161  1.1  mrg        }								\
    162  1.1  mrg      _node; }))
    163  1.1  mrg #else
    164  1.1  mrg #define IRA_BB_NODE_BY_INDEX(index) (&ira_bb_nodes[index])
    165  1.1  mrg #endif
    166  1.1  mrg 
    167  1.1  mrg #define IRA_BB_NODE(bb) IRA_BB_NODE_BY_INDEX ((bb)->index)
    168  1.1  mrg 
    169  1.1  mrg /* All nodes representing loops are referred through the following
    170  1.1  mrg    array.  */
    171  1.1  mrg extern ira_loop_tree_node_t ira_loop_nodes;
    172  1.1  mrg 
    173  1.1  mrg /* Two access macros to the nodes representing loops.  */
    174  1.1  mrg #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007)
    175  1.1  mrg #define IRA_LOOP_NODE_BY_INDEX(index) __extension__			\
    176  1.1  mrg (({ ira_loop_tree_node_t const _node = (&ira_loop_nodes[index]);\
    177  1.1  mrg      if (_node->children == NULL || _node->bb != NULL || _node->loop == NULL)\
    178  1.1  mrg        {								\
    179  1.1  mrg          fprintf (stderr,						\
    180  1.1  mrg                   "\n%s: %d: error in %s: it is not a loop node\n",	\
    181  1.1  mrg                   __FILE__, __LINE__, __FUNCTION__);			\
    182  1.1  mrg          gcc_unreachable ();						\
    183  1.1  mrg        }								\
    184  1.1  mrg      _node; }))
    185  1.1  mrg #else
    186  1.1  mrg #define IRA_LOOP_NODE_BY_INDEX(index) (&ira_loop_nodes[index])
    187  1.1  mrg #endif
    188  1.1  mrg 
    189  1.1  mrg #define IRA_LOOP_NODE(loop) IRA_LOOP_NODE_BY_INDEX ((loop)->num)
    190  1.1  mrg 
    191  1.1  mrg 
    192  1.1  mrg 
    194  1.1  mrg /* The structure describes program points where a given allocno lives.
    195  1.1  mrg    To save memory we store allocno conflicts only for the same cover
    196  1.1  mrg    class allocnos which is enough to assign hard registers.  To find
    197  1.1  mrg    conflicts for other allocnos (e.g. to assign stack memory slot) we
    198  1.1  mrg    use the live ranges.  If the live ranges of two allocnos are
    199  1.1  mrg    intersected, the allocnos are in conflict.  */
    200  1.1  mrg struct ira_allocno_live_range
    201  1.1  mrg {
    202  1.1  mrg   /* Allocno whose live range is described by given structure.  */
    203  1.1  mrg   ira_allocno_t allocno;
    204  1.1  mrg   /* Program point range.  */
    205  1.1  mrg   int start, finish;
    206  1.1  mrg   /* Next structure describing program points where the allocno
    207  1.1  mrg      lives.  */
    208  1.1  mrg   allocno_live_range_t next;
    209  1.1  mrg   /* Pointer to structures with the same start/finish.  */
    210  1.1  mrg   allocno_live_range_t start_next, finish_next;
    211  1.1  mrg };
    212  1.1  mrg 
    213  1.1  mrg /* Program points are enumerated by numbers from range
    214  1.1  mrg    0..IRA_MAX_POINT-1.  There are approximately two times more program
    215  1.1  mrg    points than insns.  Program points are places in the program where
    216  1.1  mrg    liveness info can be changed.  In most general case (there are more
    217  1.1  mrg    complicated cases too) some program points correspond to places
    218  1.1  mrg    where input operand dies and other ones correspond to places where
    219  1.1  mrg    output operands are born.  */
    220  1.1  mrg extern int ira_max_point;
    221  1.1  mrg 
    222  1.1  mrg /* Arrays of size IRA_MAX_POINT mapping a program point to the allocno
    223  1.1  mrg    live ranges with given start/finish point.  */
    224  1.1  mrg extern allocno_live_range_t *ira_start_point_ranges, *ira_finish_point_ranges;
    225  1.1  mrg 
    226  1.1  mrg /* A structure representing an allocno (allocation entity).  Allocno
    227  1.1  mrg    represents a pseudo-register in an allocation region.  If
    228  1.1  mrg    pseudo-register does not live in a region but it lives in the
    229  1.1  mrg    nested regions, it is represented in the region by special allocno
    230  1.1  mrg    called *cap*.  There may be more one cap representing the same
    231  1.1  mrg    pseudo-register in region.  It means that the corresponding
    232  1.1  mrg    pseudo-register lives in more one non-intersected subregion.  */
    233  1.1  mrg struct ira_allocno
    234  1.1  mrg {
    235  1.1  mrg   /* The allocno order number starting with 0.  Each allocno has an
    236  1.1  mrg      unique number and the number is never changed for the
    237  1.1  mrg      allocno.  */
    238  1.1  mrg   int num;
    239  1.1  mrg   /* Regno for allocno or cap.  */
    240  1.1  mrg   int regno;
    241  1.1  mrg   /* Mode of the allocno which is the mode of the corresponding
    242  1.1  mrg      pseudo-register.  */
    243  1.1  mrg   enum machine_mode mode;
    244  1.1  mrg   /* Hard register assigned to given allocno.  Negative value means
    245  1.1  mrg      that memory was allocated to the allocno.  During the reload,
    246  1.1  mrg      spilled allocno has value equal to the corresponding stack slot
    247  1.1  mrg      number (0, ...) - 2.  Value -1 is used for allocnos spilled by the
    248  1.1  mrg      reload (at this point pseudo-register has only one allocno) which
    249  1.1  mrg      did not get stack slot yet.  */
    250  1.1  mrg   int hard_regno;
    251  1.1  mrg   /* Final rtx representation of the allocno.  */
    252  1.1  mrg   rtx reg;
    253  1.1  mrg   /* Allocnos with the same regno are linked by the following member.
    254  1.1  mrg      Allocnos corresponding to inner loops are first in the list (it
    255  1.1  mrg      corresponds to depth-first traverse of the loops).  */
    256  1.1  mrg   ira_allocno_t next_regno_allocno;
    257  1.1  mrg   /* There may be different allocnos with the same regno in different
    258  1.1  mrg      regions.  Allocnos are bound to the corresponding loop tree node.
    259  1.1  mrg      Pseudo-register may have only one regular allocno with given loop
    260  1.1  mrg      tree node but more than one cap (see comments above).  */
    261  1.1  mrg   ira_loop_tree_node_t loop_tree_node;
    262  1.1  mrg   /* Accumulated usage references of the allocno.  Here and below,
    263  1.1  mrg      word 'accumulated' means info for given region and all nested
    264  1.1  mrg      subregions.  In this case, 'accumulated' means sum of references
    265  1.1  mrg      of the corresponding pseudo-register in this region and in all
    266  1.1  mrg      nested subregions recursively. */
    267  1.1  mrg   int nrefs;
    268  1.1  mrg   /* Accumulated frequency of usage of the allocno.  */
    269  1.1  mrg   int freq;
    270  1.1  mrg   /* Register class which should be used for allocation for given
    271  1.1  mrg      allocno.  NO_REGS means that we should use memory.  */
    272  1.1  mrg   enum reg_class cover_class;
    273  1.1  mrg   /* Minimal accumulated and updated costs of usage register of the
    274  1.1  mrg      cover class for the allocno.  */
    275  1.1  mrg   int cover_class_cost, updated_cover_class_cost;
    276  1.1  mrg   /* Minimal accumulated, and updated costs of memory for the allocno.
    277  1.1  mrg      At the allocation start, the original and updated costs are
    278  1.1  mrg      equal.  The updated cost may be changed after finishing
    279  1.1  mrg      allocation in a region and starting allocation in a subregion.
    280  1.1  mrg      The change reflects the cost of spill/restore code on the
    281  1.1  mrg      subregion border if we assign memory to the pseudo in the
    282  1.1  mrg      subregion.  */
    283  1.1  mrg   int memory_cost, updated_memory_cost;
    284  1.1  mrg   /* Accumulated number of points where the allocno lives and there is
    285  1.1  mrg      excess pressure for its class.  Excess pressure for a register
    286  1.1  mrg      class at some point means that there are more allocnos of given
    287  1.1  mrg      register class living at the point than number of hard-registers
    288  1.1  mrg      of the class available for the allocation.  */
    289  1.1  mrg   int excess_pressure_points_num;
    290  1.1  mrg   /* Copies to other non-conflicting allocnos.  The copies can
    291  1.1  mrg      represent move insn or potential move insn usually because of two
    292  1.1  mrg      operand insn constraints.  */
    293  1.1  mrg   ira_copy_t allocno_copies;
    294  1.1  mrg   /* It is a allocno (cap) representing given allocno on upper loop tree
    295  1.1  mrg      level.  */
    296  1.1  mrg   ira_allocno_t cap;
    297  1.1  mrg   /* It is a link to allocno (cap) on lower loop level represented by
    298  1.1  mrg      given cap.  Null if given allocno is not a cap.  */
    299  1.1  mrg   ira_allocno_t cap_member;
    300  1.1  mrg   /* Coalesced allocnos form a cyclic list.  One allocno given by
    301  1.1  mrg      FIRST_COALESCED_ALLOCNO represents all coalesced allocnos.  The
    302  1.1  mrg      list is chained by NEXT_COALESCED_ALLOCNO.  */
    303  1.1  mrg   ira_allocno_t first_coalesced_allocno;
    304  1.1  mrg   ira_allocno_t next_coalesced_allocno;
    305  1.1  mrg   /* Pointer to structures describing at what program point the
    306  1.1  mrg      allocno lives.  We always maintain the list in such way that *the
    307  1.1  mrg      ranges in the list are not intersected and ordered by decreasing
    308  1.1  mrg      their program points*.  */
    309  1.1  mrg   allocno_live_range_t live_ranges;
    310  1.1  mrg   /* Before building conflicts the two member values are
    311  1.1  mrg      correspondingly minimal and maximal points of the accumulated
    312  1.1  mrg      allocno live ranges.  After building conflicts the values are
    313  1.1  mrg      correspondingly minimal and maximal conflict ids of allocnos with
    314  1.1  mrg      which given allocno can conflict.  */
    315  1.1  mrg   int min, max;
    316  1.1  mrg   /* Vector of accumulated conflicting allocnos with NULL end marker
    317  1.1  mrg      (if CONFLICT_VEC_P is true) or conflict bit vector otherwise.
    318  1.1  mrg      Only allocnos with the same cover class are in the vector or in
    319  1.1  mrg      the bit vector.  */
    320  1.1  mrg   void *conflict_allocno_array;
    321  1.1  mrg   /* The unique member value represents given allocno in conflict bit
    322  1.1  mrg      vectors.  */
    323  1.1  mrg   int conflict_id;
    324  1.1  mrg   /* Allocated size of the previous array.  */
    325  1.1  mrg   unsigned int conflict_allocno_array_size;
    326  1.1  mrg   /* Initial and accumulated hard registers conflicting with this
    327  1.1  mrg      allocno and as a consequences can not be assigned to the allocno.
    328  1.1  mrg      All non-allocatable hard regs and hard regs of cover classes
    329  1.1  mrg      different from given allocno one are included in the sets.  */
    330  1.1  mrg   HARD_REG_SET conflict_hard_regs, total_conflict_hard_regs;
    331  1.1  mrg   /* Number of accumulated conflicts in the vector of conflicting
    332  1.1  mrg      allocnos.  */
    333  1.1  mrg   int conflict_allocnos_num;
    334  1.1  mrg   /* Accumulated frequency of calls which given allocno
    335  1.1  mrg      intersects.  */
    336  1.1  mrg   int call_freq;
    337  1.1  mrg   /* Accumulated number of the intersected calls.  */
    338  1.1  mrg   int calls_crossed_num;
    339  1.1  mrg   /* TRUE if the allocno assigned to memory was a destination of
    340  1.1  mrg      removed move (see ira-emit.c) at loop exit because the value of
    341  1.1  mrg      the corresponding pseudo-register is not changed inside the
    342  1.1  mrg      loop.  */
    343  1.1  mrg   unsigned int mem_optimized_dest_p : 1;
    344  1.1  mrg   /* TRUE if the corresponding pseudo-register has disjoint live
    345  1.1  mrg      ranges and the other allocnos of the pseudo-register except this
    346  1.1  mrg      one changed REG.  */
    347  1.1  mrg   unsigned int somewhere_renamed_p : 1;
    348  1.1  mrg   /* TRUE if allocno with the same REGNO in a subregion has been
    349  1.1  mrg      renamed, in other words, got a new pseudo-register.  */
    350  1.1  mrg   unsigned int child_renamed_p : 1;
    351  1.1  mrg   /* During the reload, value TRUE means that we should not reassign a
    352  1.1  mrg      hard register to the allocno got memory earlier.  It is set up
    353  1.1  mrg      when we removed memory-memory move insn before each iteration of
    354  1.1  mrg      the reload.  */
    355  1.1  mrg   unsigned int dont_reassign_p : 1;
    356  1.1  mrg #ifdef STACK_REGS
    357  1.1  mrg   /* Set to TRUE if allocno can't be assigned to the stack hard
    358  1.1  mrg      register correspondingly in this region and area including the
    359  1.1  mrg      region and all its subregions recursively.  */
    360  1.1  mrg   unsigned int no_stack_reg_p : 1, total_no_stack_reg_p : 1;
    361  1.1  mrg #endif
    362  1.1  mrg   /* TRUE value means that there is no sense to spill the allocno
    363  1.1  mrg      during coloring because the spill will result in additional
    364  1.1  mrg      reloads in reload pass.  */
    365  1.1  mrg   unsigned int bad_spill_p : 1;
    366  1.1  mrg   /* TRUE value means that the allocno was not removed yet from the
    367  1.1  mrg      conflicting graph during colouring.  */
    368  1.1  mrg   unsigned int in_graph_p : 1;
    369  1.1  mrg   /* TRUE if a hard register or memory has been assigned to the
    370  1.1  mrg      allocno.  */
    371  1.1  mrg   unsigned int assigned_p : 1;
    372  1.1  mrg   /* TRUE if it is put on the stack to make other allocnos
    373  1.1  mrg      colorable.  */
    374  1.1  mrg   unsigned int may_be_spilled_p : 1;
    375  1.1  mrg   /* TRUE if the allocno was removed from the splay tree used to
    376  1.1  mrg      choose allocn for spilling (see ira-color.c::.  */
    377  1.1  mrg   unsigned int splay_removed_p : 1;
    378  1.1  mrg   /* TRUE if conflicts for given allocno are represented by vector of
    379  1.1  mrg      pointers to the conflicting allocnos.  Otherwise, we use a bit
    380  1.1  mrg      vector where a bit with given index represents allocno with the
    381  1.1  mrg      same number.  */
    382  1.1  mrg   unsigned int conflict_vec_p : 1;
    383  1.1  mrg   /* Non NULL if we remove restoring value from given allocno to
    384  1.1  mrg      MEM_OPTIMIZED_DEST at loop exit (see ira-emit.c) because the
    385  1.1  mrg      allocno value is not changed inside the loop.  */
    386  1.1  mrg   ira_allocno_t mem_optimized_dest;
    387  1.1  mrg   /* Array of usage costs (accumulated and the one updated during
    388  1.1  mrg      coloring) for each hard register of the allocno cover class.  The
    389  1.1  mrg      member value can be NULL if all costs are the same and equal to
    390  1.1  mrg      COVER_CLASS_COST.  For example, the costs of two different hard
    391  1.1  mrg      registers can be different if one hard register is callee-saved
    392  1.1  mrg      and another one is callee-used and the allocno lives through
    393  1.1  mrg      calls.  Another example can be case when for some insn the
    394  1.1  mrg      corresponding pseudo-register value should be put in specific
    395  1.1  mrg      register class (e.g. AREG for x86) which is a strict subset of
    396  1.1  mrg      the allocno cover class (GENERAL_REGS for x86).  We have updated
    397  1.1  mrg      costs to reflect the situation when the usage cost of a hard
    398  1.1  mrg      register is decreased because the allocno is connected to another
    399  1.1  mrg      allocno by a copy and the another allocno has been assigned to
    400  1.1  mrg      the hard register.  */
    401  1.1  mrg   int *hard_reg_costs, *updated_hard_reg_costs;
    402  1.1  mrg   /* Array of decreasing costs (accumulated and the one updated during
    403  1.1  mrg      coloring) for allocnos conflicting with given allocno for hard
    404  1.1  mrg      regno of the allocno cover class.  The member value can be NULL
    405  1.1  mrg      if all costs are the same.  These costs are used to reflect
    406  1.1  mrg      preferences of other allocnos not assigned yet during assigning
    407  1.1  mrg      to given allocno.  */
    408  1.1  mrg   int *conflict_hard_reg_costs, *updated_conflict_hard_reg_costs;
    409  1.1  mrg   /* Size (in hard registers) of the same cover class allocnos with
    410  1.1  mrg      TRUE in_graph_p value and conflicting with given allocno during
    411  1.1  mrg      each point of graph coloring.  */
    412  1.1  mrg   int left_conflicts_size;
    413  1.1  mrg   /* Number of hard registers of the allocno cover class really
    414  1.1  mrg      available for the allocno allocation.  */
    415  1.1  mrg   int available_regs_num;
    416  1.1  mrg   /* Allocnos in a bucket (used in coloring) chained by the following
    417  1.1  mrg      two members.  */
    418  1.1  mrg   ira_allocno_t next_bucket_allocno;
    419  1.1  mrg   ira_allocno_t prev_bucket_allocno;
    420  1.1  mrg   /* Used for temporary purposes.  */
    421  1.1  mrg   int temp;
    422  1.1  mrg };
    423  1.1  mrg 
    424  1.1  mrg /* All members of the allocno structures should be accessed only
    425  1.1  mrg    through the following macros.  */
    426  1.1  mrg #define ALLOCNO_NUM(A) ((A)->num)
    427  1.1  mrg #define ALLOCNO_REGNO(A) ((A)->regno)
    428  1.1  mrg #define ALLOCNO_REG(A) ((A)->reg)
    429  1.1  mrg #define ALLOCNO_NEXT_REGNO_ALLOCNO(A) ((A)->next_regno_allocno)
    430  1.1  mrg #define ALLOCNO_LOOP_TREE_NODE(A) ((A)->loop_tree_node)
    431  1.1  mrg #define ALLOCNO_CAP(A) ((A)->cap)
    432  1.1  mrg #define ALLOCNO_CAP_MEMBER(A) ((A)->cap_member)
    433  1.1  mrg #define ALLOCNO_CONFLICT_ALLOCNO_ARRAY(A) ((A)->conflict_allocno_array)
    434  1.1  mrg #define ALLOCNO_CONFLICT_ALLOCNO_ARRAY_SIZE(A) \
    435  1.1  mrg   ((A)->conflict_allocno_array_size)
    436  1.1  mrg #define ALLOCNO_CONFLICT_ALLOCNOS_NUM(A) \
    437  1.1  mrg   ((A)->conflict_allocnos_num)
    438  1.1  mrg #define ALLOCNO_CONFLICT_HARD_REGS(A) ((A)->conflict_hard_regs)
    439  1.1  mrg #define ALLOCNO_TOTAL_CONFLICT_HARD_REGS(A) ((A)->total_conflict_hard_regs)
    440  1.1  mrg #define ALLOCNO_NREFS(A) ((A)->nrefs)
    441  1.1  mrg #define ALLOCNO_FREQ(A) ((A)->freq)
    442  1.1  mrg #define ALLOCNO_HARD_REGNO(A) ((A)->hard_regno)
    443  1.1  mrg #define ALLOCNO_CALL_FREQ(A) ((A)->call_freq)
    444  1.1  mrg #define ALLOCNO_CALLS_CROSSED_NUM(A) ((A)->calls_crossed_num)
    445  1.1  mrg #define ALLOCNO_MEM_OPTIMIZED_DEST(A) ((A)->mem_optimized_dest)
    446  1.1  mrg #define ALLOCNO_MEM_OPTIMIZED_DEST_P(A) ((A)->mem_optimized_dest_p)
    447  1.1  mrg #define ALLOCNO_SOMEWHERE_RENAMED_P(A) ((A)->somewhere_renamed_p)
    448  1.1  mrg #define ALLOCNO_CHILD_RENAMED_P(A) ((A)->child_renamed_p)
    449  1.1  mrg #define ALLOCNO_DONT_REASSIGN_P(A) ((A)->dont_reassign_p)
    450  1.1  mrg #ifdef STACK_REGS
    451  1.1  mrg #define ALLOCNO_NO_STACK_REG_P(A) ((A)->no_stack_reg_p)
    452  1.1  mrg #define ALLOCNO_TOTAL_NO_STACK_REG_P(A) ((A)->total_no_stack_reg_p)
    453  1.1  mrg #endif
    454  1.1  mrg #define ALLOCNO_BAD_SPILL_P(A) ((A)->bad_spill_p)
    455  1.1  mrg #define ALLOCNO_IN_GRAPH_P(A) ((A)->in_graph_p)
    456  1.1  mrg #define ALLOCNO_ASSIGNED_P(A) ((A)->assigned_p)
    457  1.1  mrg #define ALLOCNO_MAY_BE_SPILLED_P(A) ((A)->may_be_spilled_p)
    458  1.1  mrg #define ALLOCNO_SPLAY_REMOVED_P(A) ((A)->splay_removed_p)
    459  1.1  mrg #define ALLOCNO_CONFLICT_VEC_P(A) ((A)->conflict_vec_p)
    460  1.1  mrg #define ALLOCNO_MODE(A) ((A)->mode)
    461  1.1  mrg #define ALLOCNO_COPIES(A) ((A)->allocno_copies)
    462  1.1  mrg #define ALLOCNO_HARD_REG_COSTS(A) ((A)->hard_reg_costs)
    463  1.1  mrg #define ALLOCNO_UPDATED_HARD_REG_COSTS(A) ((A)->updated_hard_reg_costs)
    464  1.1  mrg #define ALLOCNO_CONFLICT_HARD_REG_COSTS(A) \
    465  1.1  mrg   ((A)->conflict_hard_reg_costs)
    466  1.1  mrg #define ALLOCNO_UPDATED_CONFLICT_HARD_REG_COSTS(A) \
    467  1.1  mrg   ((A)->updated_conflict_hard_reg_costs)
    468  1.1  mrg #define ALLOCNO_LEFT_CONFLICTS_SIZE(A) ((A)->left_conflicts_size)
    469  1.1  mrg #define ALLOCNO_COVER_CLASS(A) ((A)->cover_class)
    470  1.1  mrg #define ALLOCNO_COVER_CLASS_COST(A) ((A)->cover_class_cost)
    471  1.1  mrg #define ALLOCNO_UPDATED_COVER_CLASS_COST(A) ((A)->updated_cover_class_cost)
    472  1.1  mrg #define ALLOCNO_MEMORY_COST(A) ((A)->memory_cost)
    473  1.1  mrg #define ALLOCNO_UPDATED_MEMORY_COST(A) ((A)->updated_memory_cost)
    474  1.1  mrg #define ALLOCNO_EXCESS_PRESSURE_POINTS_NUM(A) ((A)->excess_pressure_points_num)
    475  1.1  mrg #define ALLOCNO_AVAILABLE_REGS_NUM(A) ((A)->available_regs_num)
    476  1.1  mrg #define ALLOCNO_NEXT_BUCKET_ALLOCNO(A) ((A)->next_bucket_allocno)
    477  1.1  mrg #define ALLOCNO_PREV_BUCKET_ALLOCNO(A) ((A)->prev_bucket_allocno)
    478  1.1  mrg #define ALLOCNO_TEMP(A) ((A)->temp)
    479  1.1  mrg #define ALLOCNO_FIRST_COALESCED_ALLOCNO(A) ((A)->first_coalesced_allocno)
    480  1.1  mrg #define ALLOCNO_NEXT_COALESCED_ALLOCNO(A) ((A)->next_coalesced_allocno)
    481  1.1  mrg #define ALLOCNO_LIVE_RANGES(A) ((A)->live_ranges)
    482  1.1  mrg #define ALLOCNO_MIN(A) ((A)->min)
    483  1.1  mrg #define ALLOCNO_MAX(A) ((A)->max)
    484  1.1  mrg #define ALLOCNO_CONFLICT_ID(A) ((A)->conflict_id)
    485  1.1  mrg 
    486  1.1  mrg /* Map regno -> allocnos with given regno (see comments for
    487  1.1  mrg    allocno member `next_regno_allocno').  */
    488  1.1  mrg extern ira_allocno_t *ira_regno_allocno_map;
    489  1.1  mrg 
    490  1.1  mrg /* Array of references to all allocnos.  The order number of the
    491  1.1  mrg    allocno corresponds to the index in the array.  Removed allocnos
    492  1.1  mrg    have NULL element value.  */
    493  1.1  mrg extern ira_allocno_t *ira_allocnos;
    494  1.1  mrg 
    495  1.1  mrg /* Sizes of the previous array.  */
    496  1.1  mrg extern int ira_allocnos_num;
    497  1.1  mrg 
    498  1.1  mrg /* Map conflict id -> allocno with given conflict id (see comments for
    499  1.1  mrg    allocno member `conflict_id').  */
    500  1.1  mrg extern ira_allocno_t *ira_conflict_id_allocno_map;
    501  1.1  mrg 
    502  1.1  mrg /* The following structure represents a copy of two allocnos.  The
    503  1.1  mrg    copies represent move insns or potential move insns usually because
    504  1.1  mrg    of two operand insn constraints.  To remove register shuffle, we
    505  1.1  mrg    also create copies between allocno which is output of an insn and
    506  1.1  mrg    allocno becoming dead in the insn.  */
    507  1.1  mrg struct ira_allocno_copy
    508  1.1  mrg {
    509  1.1  mrg   /* The unique order number of the copy node starting with 0.  */
    510  1.1  mrg   int num;
    511  1.1  mrg   /* Allocnos connected by the copy.  The first allocno should have
    512  1.1  mrg      smaller order number than the second one.  */
    513  1.1  mrg   ira_allocno_t first, second;
    514  1.1  mrg   /* Execution frequency of the copy.  */
    515  1.1  mrg   int freq;
    516  1.1  mrg   bool constraint_p;
    517  1.1  mrg   /* It is a move insn which is an origin of the copy.  The member
    518  1.1  mrg      value for the copy representing two operand insn constraints or
    519  1.1  mrg      for the copy created to remove register shuffle is NULL.  In last
    520  1.1  mrg      case the copy frequency is smaller than the corresponding insn
    521  1.1  mrg      execution frequency.  */
    522  1.1  mrg   rtx insn;
    523  1.1  mrg   /* All copies with the same allocno as FIRST are linked by the two
    524  1.1  mrg      following members.  */
    525  1.1  mrg   ira_copy_t prev_first_allocno_copy, next_first_allocno_copy;
    526  1.1  mrg   /* All copies with the same allocno as SECOND are linked by the two
    527  1.1  mrg      following members.  */
    528  1.1  mrg   ira_copy_t prev_second_allocno_copy, next_second_allocno_copy;
    529  1.1  mrg   /* Region from which given copy is originated.  */
    530  1.1  mrg   ira_loop_tree_node_t loop_tree_node;
    531  1.1  mrg };
    532  1.1  mrg 
    533  1.1  mrg /* Array of references to all copies.  The order number of the copy
    534  1.1  mrg    corresponds to the index in the array.  Removed copies have NULL
    535  1.1  mrg    element value.  */
    536  1.1  mrg extern ira_copy_t *ira_copies;
    537  1.1  mrg 
    538  1.1  mrg /* Size of the previous array.  */
    539  1.1  mrg extern int ira_copies_num;
    540  1.1  mrg 
    541  1.1  mrg /* The following structure describes a stack slot used for spilled
    542  1.1  mrg    pseudo-registers.  */
    543  1.1  mrg struct ira_spilled_reg_stack_slot
    544  1.1  mrg {
    545  1.1  mrg   /* pseudo-registers assigned to the stack slot.  */
    546  1.1  mrg   regset_head spilled_regs;
    547  1.1  mrg   /* RTL representation of the stack slot.  */
    548  1.1  mrg   rtx mem;
    549  1.1  mrg   /* Size of the stack slot.  */
    550  1.1  mrg   unsigned int width;
    551  1.1  mrg };
    552  1.1  mrg 
    553  1.1  mrg /* The number of elements in the following array.  */
    554  1.1  mrg extern int ira_spilled_reg_stack_slots_num;
    555  1.1  mrg 
    556  1.1  mrg /* The following array contains info about spilled pseudo-registers
    557  1.1  mrg    stack slots used in current function so far.  */
    558  1.1  mrg extern struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots;
    559  1.1  mrg 
    560  1.1  mrg /* Correspondingly overall cost of the allocation, cost of the
    561  1.1  mrg    allocnos assigned to hard-registers, cost of the allocnos assigned
    562  1.1  mrg    to memory, cost of loads, stores and register move insns generated
    563  1.1  mrg    for pseudo-register live range splitting (see ira-emit.c).  */
    564  1.1  mrg extern int ira_overall_cost;
    565  1.1  mrg extern int ira_reg_cost, ira_mem_cost;
    566  1.1  mrg extern int ira_load_cost, ira_store_cost, ira_shuffle_cost;
    567  1.1  mrg extern int ira_move_loops_num, ira_additional_jumps_num;
    568  1.1  mrg 
    569  1.1  mrg /* Maximal value of element of array ira_reg_class_nregs.  */
    570  1.1  mrg extern int ira_max_nregs;
    571  1.1  mrg 
    572  1.1  mrg /* The number of bits in each element of array used to implement a bit
    573  1.1  mrg    vector of allocnos and what type that element has.  We use the
    574  1.1  mrg    largest integer format on the host machine.  */
    575  1.1  mrg #define IRA_INT_BITS HOST_BITS_PER_WIDE_INT
    576  1.1  mrg #define IRA_INT_TYPE HOST_WIDE_INT
    577  1.1  mrg 
    578  1.1  mrg /* Set, clear or test bit number I in R, a bit vector of elements with
    579  1.1  mrg    minimal index and maximal index equal correspondingly to MIN and
    580  1.1  mrg    MAX.  */
    581  1.1  mrg #if defined ENABLE_IRA_CHECKING && (GCC_VERSION >= 2007)
    582  1.1  mrg 
    583  1.1  mrg #define SET_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__	        \
    584  1.1  mrg   (({ int _min = (MIN), _max = (MAX), _i = (I);				\
    585  1.1  mrg      if (_i < _min || _i > _max)					\
    586  1.1  mrg        {								\
    587  1.1  mrg          fprintf (stderr,						\
    588  1.1  mrg                   "\n%s: %d: error in %s: %d not in range [%d,%d]\n",   \
    589  1.1  mrg                   __FILE__, __LINE__, __FUNCTION__, _i, _min, _max);	\
    590  1.1  mrg          gcc_unreachable ();						\
    591  1.1  mrg        }								\
    592  1.1  mrg      ((R)[(unsigned) (_i - _min) / IRA_INT_BITS]			\
    593  1.1  mrg       |= ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
    594  1.1  mrg 
    595  1.1  mrg 
    596  1.1  mrg #define CLEAR_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__	        \
    597  1.1  mrg   (({ int _min = (MIN), _max = (MAX), _i = (I);				\
    598  1.1  mrg      if (_i < _min || _i > _max)					\
    599  1.1  mrg        {								\
    600  1.1  mrg          fprintf (stderr,						\
    601  1.1  mrg                   "\n%s: %d: error in %s: %d not in range [%d,%d]\n",   \
    602  1.1  mrg                   __FILE__, __LINE__, __FUNCTION__, _i, _min, _max);	\
    603  1.1  mrg          gcc_unreachable ();						\
    604  1.1  mrg        }								\
    605  1.1  mrg      ((R)[(unsigned) (_i - _min) / IRA_INT_BITS]			\
    606  1.1  mrg       &= ~((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
    607  1.1  mrg 
    608  1.1  mrg #define TEST_ALLOCNO_SET_BIT(R, I, MIN, MAX) __extension__	        \
    609  1.1  mrg   (({ int _min = (MIN), _max = (MAX), _i = (I);				\
    610  1.1  mrg      if (_i < _min || _i > _max)					\
    611  1.1  mrg        {								\
    612  1.1  mrg          fprintf (stderr,						\
    613  1.1  mrg                   "\n%s: %d: error in %s: %d not in range [%d,%d]\n",   \
    614  1.1  mrg                   __FILE__, __LINE__, __FUNCTION__, _i, _min, _max);	\
    615  1.1  mrg          gcc_unreachable ();						\
    616  1.1  mrg        }								\
    617  1.1  mrg      ((R)[(unsigned) (_i - _min) / IRA_INT_BITS]			\
    618  1.1  mrg       & ((IRA_INT_TYPE) 1 << ((unsigned) (_i - _min) % IRA_INT_BITS))); }))
    619  1.1  mrg 
    620  1.1  mrg #else
    621  1.1  mrg 
    622  1.1  mrg #define SET_ALLOCNO_SET_BIT(R, I, MIN, MAX)			\
    623  1.1  mrg   ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS]			\
    624  1.1  mrg    |= ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS)))
    625  1.1  mrg 
    626  1.1  mrg #define CLEAR_ALLOCNO_SET_BIT(R, I, MIN, MAX)			\
    627  1.1  mrg   ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS]			\
    628  1.1  mrg    &= ~((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS)))
    629  1.1  mrg 
    630  1.1  mrg #define TEST_ALLOCNO_SET_BIT(R, I, MIN, MAX)			\
    631  1.1  mrg   ((R)[(unsigned) ((I) - (MIN)) / IRA_INT_BITS]			\
    632  1.1  mrg    & ((IRA_INT_TYPE) 1 << ((unsigned) ((I) - (MIN)) % IRA_INT_BITS)))
    633  1.1  mrg 
    634  1.1  mrg #endif
    635  1.1  mrg 
    636  1.1  mrg /* The iterator for allocno set implemented ed as allocno bit
    637  1.1  mrg    vector.  */
    638  1.1  mrg typedef struct {
    639  1.1  mrg 
    640  1.1  mrg   /* Array containing the allocno bit vector.  */
    641  1.1  mrg   IRA_INT_TYPE *vec;
    642  1.1  mrg 
    643  1.1  mrg   /* The number of the current element in the vector.  */
    644  1.1  mrg   unsigned int word_num;
    645  1.1  mrg 
    646  1.1  mrg   /* The number of bits in the bit vector.  */
    647  1.1  mrg   unsigned int nel;
    648  1.1  mrg 
    649  1.1  mrg   /* The current bit index of the bit vector.  */
    650  1.1  mrg   unsigned int bit_num;
    651  1.1  mrg 
    652  1.1  mrg   /* Index corresponding to the 1st bit of the bit vector.   */
    653  1.1  mrg   int start_val;
    654  1.1  mrg 
    655  1.1  mrg   /* The word of the bit vector currently visited.  */
    656  1.1  mrg   unsigned IRA_INT_TYPE word;
    657  1.1  mrg } ira_allocno_set_iterator;
    658  1.1  mrg 
    659  1.1  mrg /* Initialize the iterator I for allocnos bit vector VEC containing
    660  1.1  mrg    minimal and maximal values MIN and MAX.  */
    661  1.1  mrg static inline void
    662  1.1  mrg ira_allocno_set_iter_init (ira_allocno_set_iterator *i,
    663  1.1  mrg 			   IRA_INT_TYPE *vec, int min, int max)
    664  1.1  mrg {
    665  1.1  mrg   i->vec = vec;
    666  1.1  mrg   i->word_num = 0;
    667  1.1  mrg   i->nel = max < min ? 0 : max - min + 1;
    668  1.1  mrg   i->start_val = min;
    669  1.1  mrg   i->bit_num = 0;
    670  1.1  mrg   i->word = i->nel == 0 ? 0 : vec[0];
    671  1.1  mrg }
    672  1.1  mrg 
    673  1.1  mrg /* Return TRUE if we have more allocnos to visit, in which case *N is
    674  1.1  mrg    set to the allocno number to be visited.  Otherwise, return
    675  1.1  mrg    FALSE.  */
    676  1.1  mrg static inline bool
    677  1.1  mrg ira_allocno_set_iter_cond (ira_allocno_set_iterator *i, int *n)
    678  1.1  mrg {
    679  1.1  mrg   /* Skip words that are zeros.  */
    680  1.1  mrg   for (; i->word == 0; i->word = i->vec[i->word_num])
    681  1.1  mrg     {
    682  1.1  mrg       i->word_num++;
    683  1.1  mrg       i->bit_num = i->word_num * IRA_INT_BITS;
    684  1.1  mrg 
    685  1.1  mrg       /* If we have reached the end, break.  */
    686  1.1  mrg       if (i->bit_num >= i->nel)
    687  1.1  mrg 	return false;
    688  1.1  mrg     }
    689  1.1  mrg 
    690  1.1  mrg   /* Skip bits that are zero.  */
    691  1.1  mrg   for (; (i->word & 1) == 0; i->word >>= 1)
    692  1.1  mrg     i->bit_num++;
    693  1.1  mrg 
    694  1.1  mrg   *n = (int) i->bit_num + i->start_val;
    695  1.1  mrg 
    696  1.1  mrg   return true;
    697  1.1  mrg }
    698  1.1  mrg 
    699  1.1  mrg /* Advance to the next allocno in the set.  */
    700  1.1  mrg static inline void
    701  1.1  mrg ira_allocno_set_iter_next (ira_allocno_set_iterator *i)
    702  1.1  mrg {
    703  1.1  mrg   i->word >>= 1;
    704  1.1  mrg   i->bit_num++;
    705  1.1  mrg }
    706  1.1  mrg 
    707  1.1  mrg /* Loop over all elements of allocno set given by bit vector VEC and
    708  1.1  mrg    their minimal and maximal values MIN and MAX.  In each iteration, N
    709  1.1  mrg    is set to the number of next allocno.  ITER is an instance of
    710  1.1  mrg    ira_allocno_set_iterator used to iterate the allocnos in the set.  */
    711  1.1  mrg #define FOR_EACH_ALLOCNO_IN_SET(VEC, MIN, MAX, N, ITER)		\
    712  1.1  mrg   for (ira_allocno_set_iter_init (&(ITER), (VEC), (MIN), (MAX));	\
    713  1.1  mrg        ira_allocno_set_iter_cond (&(ITER), &(N));			\
    714  1.1  mrg        ira_allocno_set_iter_next (&(ITER)))
    715  1.1  mrg 
    716  1.1  mrg /* ira.c: */
    717  1.1  mrg 
    718  1.1  mrg /* Map: hard regs X modes -> set of hard registers for storing value
    719  1.1  mrg    of given mode starting with given hard register.  */
    720  1.1  mrg extern HARD_REG_SET ira_reg_mode_hard_regset
    721  1.1  mrg                     [FIRST_PSEUDO_REGISTER][NUM_MACHINE_MODES];
    722  1.1  mrg 
    723  1.1  mrg /* Array analogous to macro REGISTER_MOVE_COST.  Don't use
    724  1.1  mrg    ira_register_move_cost directly.  Use function of
    725  1.1  mrg    ira_get_may_move_cost instead.  */
    726  1.1  mrg extern move_table *ira_register_move_cost[MAX_MACHINE_MODE];
    727  1.1  mrg 
    728  1.1  mrg /* Similar to may_move_in_cost but it is calculated in IRA instead of
    729  1.1  mrg    regclass.  Another difference we take only available hard registers
    730  1.1  mrg    into account to figure out that one register class is a subset of
    731  1.1  mrg    the another one.  Don't use it directly.  Use function of
    732  1.1  mrg    ira_get_may_move_cost instead.  */
    733  1.1  mrg extern move_table *ira_may_move_in_cost[MAX_MACHINE_MODE];
    734  1.1  mrg 
    735  1.1  mrg /* Similar to may_move_out_cost but it is calculated in IRA instead of
    736  1.1  mrg    regclass.  Another difference we take only available hard registers
    737  1.1  mrg    into account to figure out that one register class is a subset of
    738  1.1  mrg    the another one.  Don't use it directly.  Use function of
    739  1.1  mrg    ira_get_may_move_cost instead.  */
    740  1.1  mrg extern move_table *ira_may_move_out_cost[MAX_MACHINE_MODE];
    741  1.1  mrg 
    742  1.1  mrg /* Register class subset relation: TRUE if the first class is a subset
    743  1.1  mrg    of the second one considering only hard registers available for the
    744  1.1  mrg    allocation.  */
    745  1.1  mrg extern int ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
    746  1.1  mrg 
    747  1.1  mrg /* Index (in ira_class_hard_regs) for given register class and hard
    748  1.1  mrg    register (in general case a hard register can belong to several
    749  1.1  mrg    register classes).  The index is negative for hard registers
    750  1.1  mrg    unavailable for the allocation. */
    751  1.1  mrg extern short ira_class_hard_reg_index[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
    752  1.1  mrg 
    753  1.1  mrg /* Array whose values are hard regset of hard registers available for
    754  1.1  mrg    the allocation of given register class whose HARD_REGNO_MODE_OK
    755  1.1  mrg    values for given mode are zero.  */
    756  1.1  mrg extern HARD_REG_SET prohibited_class_mode_regs
    757  1.1  mrg                     [N_REG_CLASSES][NUM_MACHINE_MODES];
    758  1.1  mrg 
    759  1.1  mrg /* Array whose values are hard regset of hard registers for which
    760  1.1  mrg    move of the hard register in given mode into itself is
    761  1.1  mrg    prohibited.  */
    762  1.1  mrg extern HARD_REG_SET ira_prohibited_mode_move_regs[NUM_MACHINE_MODES];
    763  1.1  mrg 
    764  1.1  mrg /* The value is number of elements in the subsequent array.  */
    765  1.1  mrg extern int ira_important_classes_num;
    766  1.1  mrg 
    767  1.1  mrg /* The array containing non-empty classes (including non-empty cover
    768  1.1  mrg    classes) which are subclasses of cover classes.  Such classes is
    769  1.1  mrg    important for calculation of the hard register usage costs.  */
    770  1.1  mrg extern enum reg_class ira_important_classes[N_REG_CLASSES];
    771  1.1  mrg 
    772  1.1  mrg /* The array containing indexes of important classes in the previous
    773  1.1  mrg    array.  The array elements are defined only for important
    774  1.1  mrg    classes.  */
    775  1.1  mrg extern int ira_important_class_nums[N_REG_CLASSES];
    776  1.1  mrg 
    777  1.1  mrg /* The biggest important class inside of intersection of the two
    778  1.1  mrg    classes (that is calculated taking only hard registers available
    779  1.1  mrg    for allocation into account).  If the both classes contain no hard
    780  1.1  mrg    registers available for allocation, the value is calculated with
    781  1.1  mrg    taking all hard-registers including fixed ones into account.  */
    782  1.1  mrg extern enum reg_class ira_reg_class_intersect[N_REG_CLASSES][N_REG_CLASSES];
    783  1.1  mrg 
    784  1.1  mrg /* True if the two classes (that is calculated taking only hard
    785  1.1  mrg    registers available for allocation into account) are
    786  1.1  mrg    intersected.  */
    787  1.1  mrg extern bool ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
    788  1.1  mrg 
    789  1.1  mrg /* Classes with end marker LIM_REG_CLASSES which are intersected with
    790  1.1  mrg    given class (the first index).  That includes given class itself.
    791  1.1  mrg    This is calculated taking only hard registers available for
    792  1.1  mrg    allocation into account.  */
    793  1.1  mrg extern enum reg_class ira_reg_class_super_classes[N_REG_CLASSES][N_REG_CLASSES];
    794  1.1  mrg /* The biggest important class inside of union of the two classes
    795  1.1  mrg    (that is calculated taking only hard registers available for
    796  1.1  mrg    allocation into account).  If the both classes contain no hard
    797  1.1  mrg    registers available for allocation, the value is calculated with
    798  1.1  mrg    taking all hard-registers including fixed ones into account.  In
    799  1.1  mrg    other words, the value is the corresponding reg_class_subunion
    800  1.1  mrg    value.  */
    801  1.1  mrg extern enum reg_class ira_reg_class_union[N_REG_CLASSES][N_REG_CLASSES];
    802  1.1  mrg 
    803  1.1  mrg extern void *ira_allocate (size_t);
    804  1.1  mrg extern void *ira_reallocate (void *, size_t);
    805  1.1  mrg extern void ira_free (void *addr);
    806  1.1  mrg extern bitmap ira_allocate_bitmap (void);
    807  1.1  mrg extern void ira_free_bitmap (bitmap);
    808  1.1  mrg extern void ira_print_disposition (FILE *);
    809  1.1  mrg extern void ira_debug_disposition (void);
    810  1.1  mrg extern void ira_debug_class_cover (void);
    811  1.1  mrg extern void ira_init_register_move_cost (enum machine_mode);
    812  1.1  mrg 
    813  1.1  mrg /* The length of the two following arrays.  */
    814  1.1  mrg extern int ira_reg_equiv_len;
    815  1.1  mrg 
    816  1.1  mrg /* The element value is TRUE if the corresponding regno value is
    817  1.1  mrg    invariant.  */
    818  1.1  mrg extern bool *ira_reg_equiv_invariant_p;
    819  1.1  mrg 
    820  1.1  mrg /* The element value is equiv constant of given pseudo-register or
    821  1.1  mrg    NULL_RTX.  */
    822  1.1  mrg extern rtx *ira_reg_equiv_const;
    823  1.1  mrg 
    824  1.1  mrg /* ira-build.c */
    825  1.1  mrg 
    826  1.1  mrg /* The current loop tree node and its regno allocno map.  */
    827  1.1  mrg extern ira_loop_tree_node_t ira_curr_loop_tree_node;
    828  1.1  mrg extern ira_allocno_t *ira_curr_regno_allocno_map;
    829  1.1  mrg 
    830  1.1  mrg extern void ira_debug_copy (ira_copy_t);
    831  1.1  mrg extern void ira_debug_copies (void);
    832  1.1  mrg extern void ira_debug_allocno_copies (ira_allocno_t);
    833  1.1  mrg 
    834  1.1  mrg extern void ira_traverse_loop_tree (bool, ira_loop_tree_node_t,
    835  1.1  mrg 				    void (*) (ira_loop_tree_node_t),
    836  1.1  mrg 				    void (*) (ira_loop_tree_node_t));
    837  1.1  mrg extern ira_allocno_t ira_create_allocno (int, bool, ira_loop_tree_node_t);
    838  1.1  mrg extern void ira_set_allocno_cover_class (ira_allocno_t, enum reg_class);
    839  1.1  mrg extern bool ira_conflict_vector_profitable_p (ira_allocno_t, int);
    840  1.1  mrg extern void ira_allocate_allocno_conflict_vec (ira_allocno_t, int);
    841  1.1  mrg extern void ira_allocate_allocno_conflicts (ira_allocno_t, int);
    842  1.1  mrg extern void ira_add_allocno_conflict (ira_allocno_t, ira_allocno_t);
    843  1.1  mrg extern void ira_print_expanded_allocno (ira_allocno_t);
    844  1.1  mrg extern allocno_live_range_t ira_create_allocno_live_range
    845  1.1  mrg 	                    (ira_allocno_t, int, int, allocno_live_range_t);
    846  1.1  mrg extern allocno_live_range_t ira_copy_allocno_live_range_list
    847  1.1  mrg                             (allocno_live_range_t);
    848  1.1  mrg extern allocno_live_range_t ira_merge_allocno_live_ranges
    849  1.1  mrg                             (allocno_live_range_t, allocno_live_range_t);
    850  1.1  mrg extern bool ira_allocno_live_ranges_intersect_p (allocno_live_range_t,
    851  1.1  mrg 						 allocno_live_range_t);
    852  1.1  mrg extern void ira_finish_allocno_live_range (allocno_live_range_t);
    853  1.1  mrg extern void ira_finish_allocno_live_range_list (allocno_live_range_t);
    854  1.1  mrg extern void ira_free_allocno_updated_costs (ira_allocno_t);
    855  1.1  mrg extern ira_copy_t ira_create_copy (ira_allocno_t, ira_allocno_t,
    856  1.1  mrg 				   int, bool, rtx, ira_loop_tree_node_t);
    857  1.1  mrg extern void ira_add_allocno_copy_to_list (ira_copy_t);
    858  1.1  mrg extern void ira_swap_allocno_copy_ends_if_necessary (ira_copy_t);
    859  1.1  mrg extern void ira_remove_allocno_copy_from_list (ira_copy_t);
    860  1.1  mrg extern ira_copy_t ira_add_allocno_copy (ira_allocno_t, ira_allocno_t, int,
    861  1.1  mrg 					bool, rtx, ira_loop_tree_node_t);
    862  1.1  mrg 
    863  1.1  mrg extern int *ira_allocate_cost_vector (enum reg_class);
    864  1.1  mrg extern void ira_free_cost_vector (int *, enum reg_class);
    865  1.1  mrg 
    866  1.1  mrg extern void ira_flattening (int, int);
    867  1.1  mrg extern bool ira_build (bool);
    868  1.1  mrg extern void ira_destroy (void);
    869  1.1  mrg 
    870  1.1  mrg /* ira-costs.c */
    871  1.1  mrg extern void ira_init_costs_once (void);
    872  1.1  mrg extern void ira_init_costs (void);
    873  1.1  mrg extern void ira_finish_costs_once (void);
    874  1.1  mrg extern void ira_costs (void);
    875  1.1  mrg extern void ira_tune_allocno_costs_and_cover_classes (void);
    876  1.1  mrg 
    877  1.1  mrg /* ira-lives.c */
    878  1.1  mrg 
    879  1.1  mrg extern void ira_rebuild_start_finish_chains (void);
    880  1.1  mrg extern void ira_print_live_range_list (FILE *, allocno_live_range_t);
    881  1.1  mrg extern void ira_debug_live_range_list (allocno_live_range_t);
    882  1.1  mrg extern void ira_debug_allocno_live_ranges (ira_allocno_t);
    883  1.1  mrg extern void ira_debug_live_ranges (void);
    884  1.1  mrg extern void ira_create_allocno_live_ranges (void);
    885  1.1  mrg extern void ira_compress_allocno_live_ranges (void);
    886  1.1  mrg extern void ira_finish_allocno_live_ranges (void);
    887  1.1  mrg 
    888  1.1  mrg /* ira-conflicts.c */
    889  1.1  mrg extern void ira_debug_conflicts (bool);
    890  1.1  mrg extern void ira_build_conflicts (void);
    891  1.1  mrg 
    892  1.1  mrg /* ira-color.c */
    893  1.1  mrg extern int ira_loop_edge_freq (ira_loop_tree_node_t, int, bool);
    894  1.1  mrg extern void ira_reassign_conflict_allocnos (int);
    895  1.1  mrg extern void ira_initiate_assign (void);
    896  1.1  mrg extern void ira_finish_assign (void);
    897  1.1  mrg extern void ira_color (void);
    898  1.1  mrg 
    899  1.1  mrg /* ira-emit.c */
    900  1.1  mrg extern void ira_emit (bool);
    901  1.1  mrg 
    902  1.1  mrg 
    903  1.1  mrg 
    905  1.1  mrg /* Return cost of moving value of MODE from register of class FROM to
    906  1.1  mrg    register of class TO.  */
    907  1.1  mrg static inline int
    908  1.1  mrg ira_get_register_move_cost (enum machine_mode mode,
    909  1.1  mrg 			    enum reg_class from, enum reg_class to)
    910  1.1  mrg {
    911  1.1  mrg   if (ira_register_move_cost[mode] == NULL)
    912  1.1  mrg     ira_init_register_move_cost (mode);
    913  1.1  mrg   return ira_register_move_cost[mode][from][to];
    914  1.1  mrg }
    915  1.1  mrg 
    916  1.1  mrg /* Return cost of moving value of MODE from register of class FROM to
    917  1.1  mrg    register of class TO.  Return zero if IN_P is true and FROM is
    918  1.1  mrg    subset of TO or if IN_P is false and FROM is superset of TO.  */
    919  1.1  mrg static inline int
    920  1.1  mrg ira_get_may_move_cost (enum machine_mode mode,
    921  1.1  mrg 		       enum reg_class from, enum reg_class to,
    922  1.1  mrg 		       bool in_p)
    923  1.1  mrg {
    924  1.1  mrg   if (ira_register_move_cost[mode] == NULL)
    925  1.1  mrg     ira_init_register_move_cost (mode);
    926  1.1  mrg   return (in_p
    927  1.1  mrg 	  ? ira_may_move_in_cost[mode][from][to]
    928  1.1  mrg 	  : ira_may_move_out_cost[mode][from][to]);
    929  1.1  mrg }
    930  1.1  mrg 
    931  1.1  mrg 
    932  1.1  mrg 
    934  1.1  mrg /* The iterator for all allocnos.  */
    935  1.1  mrg typedef struct {
    936  1.1  mrg   /* The number of the current element in IRA_ALLOCNOS.  */
    937  1.1  mrg   int n;
    938  1.1  mrg } ira_allocno_iterator;
    939  1.1  mrg 
    940  1.1  mrg /* Initialize the iterator I.  */
    941  1.1  mrg static inline void
    942  1.1  mrg ira_allocno_iter_init (ira_allocno_iterator *i)
    943  1.1  mrg {
    944  1.1  mrg   i->n = 0;
    945  1.1  mrg }
    946  1.1  mrg 
    947  1.1  mrg /* Return TRUE if we have more allocnos to visit, in which case *A is
    948  1.1  mrg    set to the allocno to be visited.  Otherwise, return FALSE.  */
    949  1.1  mrg static inline bool
    950  1.1  mrg ira_allocno_iter_cond (ira_allocno_iterator *i, ira_allocno_t *a)
    951  1.1  mrg {
    952  1.1  mrg   int n;
    953  1.1  mrg 
    954  1.1  mrg   for (n = i->n; n < ira_allocnos_num; n++)
    955  1.1  mrg     if (ira_allocnos[n] != NULL)
    956  1.1  mrg       {
    957  1.1  mrg 	*a = ira_allocnos[n];
    958  1.1  mrg 	i->n = n + 1;
    959  1.1  mrg 	return true;
    960  1.1  mrg       }
    961  1.1  mrg   return false;
    962  1.1  mrg }
    963  1.1  mrg 
    964  1.1  mrg /* Loop over all allocnos.  In each iteration, A is set to the next
    965  1.1  mrg    allocno.  ITER is an instance of ira_allocno_iterator used to iterate
    966  1.1  mrg    the allocnos.  */
    967  1.1  mrg #define FOR_EACH_ALLOCNO(A, ITER)			\
    968  1.1  mrg   for (ira_allocno_iter_init (&(ITER));			\
    969  1.1  mrg        ira_allocno_iter_cond (&(ITER), &(A));)
    970  1.1  mrg 
    971  1.1  mrg 
    972  1.1  mrg 
    973  1.1  mrg 
    975  1.1  mrg /* The iterator for copies.  */
    976  1.1  mrg typedef struct {
    977  1.1  mrg   /* The number of the current element in IRA_COPIES.  */
    978  1.1  mrg   int n;
    979  1.1  mrg } ira_copy_iterator;
    980  1.1  mrg 
    981  1.1  mrg /* Initialize the iterator I.  */
    982  1.1  mrg static inline void
    983  1.1  mrg ira_copy_iter_init (ira_copy_iterator *i)
    984  1.1  mrg {
    985  1.1  mrg   i->n = 0;
    986  1.1  mrg }
    987  1.1  mrg 
    988  1.1  mrg /* Return TRUE if we have more copies to visit, in which case *CP is
    989  1.1  mrg    set to the copy to be visited.  Otherwise, return FALSE.  */
    990  1.1  mrg static inline bool
    991  1.1  mrg ira_copy_iter_cond (ira_copy_iterator *i, ira_copy_t *cp)
    992  1.1  mrg {
    993  1.1  mrg   int n;
    994  1.1  mrg 
    995  1.1  mrg   for (n = i->n; n < ira_copies_num; n++)
    996  1.1  mrg     if (ira_copies[n] != NULL)
    997  1.1  mrg       {
    998  1.1  mrg 	*cp = ira_copies[n];
    999  1.1  mrg 	i->n = n + 1;
   1000  1.1  mrg 	return true;
   1001  1.1  mrg       }
   1002  1.1  mrg   return false;
   1003  1.1  mrg }
   1004  1.1  mrg 
   1005  1.1  mrg /* Loop over all copies.  In each iteration, C is set to the next
   1006  1.1  mrg    copy.  ITER is an instance of ira_copy_iterator used to iterate
   1007  1.1  mrg    the copies.  */
   1008  1.1  mrg #define FOR_EACH_COPY(C, ITER)				\
   1009  1.1  mrg   for (ira_copy_iter_init (&(ITER));			\
   1010  1.1  mrg        ira_copy_iter_cond (&(ITER), &(C));)
   1011  1.1  mrg 
   1012  1.1  mrg 
   1013  1.1  mrg 
   1014  1.1  mrg 
   1016  1.1  mrg /* The iterator for allocno conflicts.  */
   1017  1.1  mrg typedef struct {
   1018  1.1  mrg 
   1019  1.1  mrg   /* TRUE if the conflicts are represented by vector of allocnos.  */
   1020  1.1  mrg   bool allocno_conflict_vec_p;
   1021  1.1  mrg 
   1022  1.1  mrg   /* The conflict vector or conflict bit vector.  */
   1023  1.1  mrg   void *vec;
   1024  1.1  mrg 
   1025  1.1  mrg   /* The number of the current element in the vector (of type
   1026  1.1  mrg      ira_allocno_t or IRA_INT_TYPE).  */
   1027  1.1  mrg   unsigned int word_num;
   1028  1.1  mrg 
   1029  1.1  mrg   /* The bit vector size.  It is defined only if
   1030  1.1  mrg      ALLOCNO_CONFLICT_VEC_P is FALSE.  */
   1031  1.1  mrg   unsigned int size;
   1032  1.1  mrg 
   1033  1.1  mrg   /* The current bit index of bit vector.  It is defined only if
   1034  1.1  mrg      ALLOCNO_CONFLICT_VEC_P is FALSE.  */
   1035  1.1  mrg   unsigned int bit_num;
   1036  1.1  mrg 
   1037  1.1  mrg   /* Allocno conflict id corresponding to the 1st bit of the bit
   1038  1.1  mrg      vector.  It is defined only if ALLOCNO_CONFLICT_VEC_P is
   1039  1.1  mrg      FALSE.  */
   1040  1.1  mrg   int base_conflict_id;
   1041  1.1  mrg 
   1042  1.1  mrg   /* The word of bit vector currently visited.  It is defined only if
   1043  1.1  mrg      ALLOCNO_CONFLICT_VEC_P is FALSE.  */
   1044  1.1  mrg   unsigned IRA_INT_TYPE word;
   1045  1.1  mrg } ira_allocno_conflict_iterator;
   1046  1.1  mrg 
   1047  1.1  mrg /* Initialize the iterator I with ALLOCNO conflicts.  */
   1048  1.1  mrg static inline void
   1049  1.1  mrg ira_allocno_conflict_iter_init (ira_allocno_conflict_iterator *i,
   1050  1.1  mrg 				ira_allocno_t allocno)
   1051  1.1  mrg {
   1052  1.1  mrg   i->allocno_conflict_vec_p = ALLOCNO_CONFLICT_VEC_P (allocno);
   1053  1.1  mrg   i->vec = ALLOCNO_CONFLICT_ALLOCNO_ARRAY (allocno);
   1054  1.1  mrg   i->word_num = 0;
   1055  1.1  mrg   if (i->allocno_conflict_vec_p)
   1056  1.1  mrg     i->size = i->bit_num = i->base_conflict_id = i->word = 0;
   1057  1.1  mrg   else
   1058  1.1  mrg     {
   1059  1.1  mrg       if (ALLOCNO_MIN (allocno) > ALLOCNO_MAX (allocno))
   1060  1.1  mrg 	i->size = 0;
   1061  1.1  mrg       else
   1062  1.1  mrg 	i->size = ((ALLOCNO_MAX (allocno) - ALLOCNO_MIN (allocno)
   1063  1.1  mrg 		    + IRA_INT_BITS)
   1064  1.1  mrg 		   / IRA_INT_BITS) * sizeof (IRA_INT_TYPE);
   1065  1.1  mrg       i->bit_num = 0;
   1066  1.1  mrg       i->base_conflict_id = ALLOCNO_MIN (allocno);
   1067  1.1  mrg       i->word = (i->size == 0 ? 0 : ((IRA_INT_TYPE *) i->vec)[0]);
   1068  1.1  mrg     }
   1069  1.1  mrg }
   1070  1.1  mrg 
   1071  1.1  mrg /* Return TRUE if we have more conflicting allocnos to visit, in which
   1072  1.1  mrg    case *A is set to the allocno to be visited.  Otherwise, return
   1073  1.1  mrg    FALSE.  */
   1074  1.1  mrg static inline bool
   1075  1.1  mrg ira_allocno_conflict_iter_cond (ira_allocno_conflict_iterator *i,
   1076  1.1  mrg 				ira_allocno_t *a)
   1077  1.1  mrg {
   1078  1.1  mrg   ira_allocno_t conflict_allocno;
   1079  1.1  mrg 
   1080  1.1  mrg   if (i->allocno_conflict_vec_p)
   1081  1.1  mrg     {
   1082  1.1  mrg       conflict_allocno = ((ira_allocno_t *) i->vec)[i->word_num];
   1083  1.1  mrg       if (conflict_allocno == NULL)
   1084  1.1  mrg 	return false;
   1085  1.1  mrg       *a = conflict_allocno;
   1086  1.1  mrg       return true;
   1087  1.1  mrg     }
   1088  1.1  mrg   else
   1089  1.1  mrg     {
   1090  1.1  mrg       /* Skip words that are zeros.  */
   1091  1.1  mrg       for (; i->word == 0; i->word = ((IRA_INT_TYPE *) i->vec)[i->word_num])
   1092  1.1  mrg 	{
   1093  1.1  mrg 	  i->word_num++;
   1094  1.1  mrg 
   1095  1.1  mrg 	  /* If we have reached the end, break.  */
   1096  1.1  mrg 	  if (i->word_num * sizeof (IRA_INT_TYPE) >= i->size)
   1097  1.1  mrg 	    return false;
   1098  1.1  mrg 
   1099  1.1  mrg 	  i->bit_num = i->word_num * IRA_INT_BITS;
   1100  1.1  mrg 	}
   1101  1.1  mrg 
   1102  1.1  mrg       /* Skip bits that are zero.  */
   1103  1.1  mrg       for (; (i->word & 1) == 0; i->word >>= 1)
   1104  1.1  mrg 	i->bit_num++;
   1105  1.1  mrg 
   1106  1.1  mrg       *a = ira_conflict_id_allocno_map[i->bit_num + i->base_conflict_id];
   1107  1.1  mrg 
   1108  1.1  mrg       return true;
   1109  1.1  mrg     }
   1110  1.1  mrg }
   1111  1.1  mrg 
   1112  1.1  mrg /* Advance to the next conflicting allocno.  */
   1113  1.1  mrg static inline void
   1114  1.1  mrg ira_allocno_conflict_iter_next (ira_allocno_conflict_iterator *i)
   1115  1.1  mrg {
   1116  1.1  mrg   if (i->allocno_conflict_vec_p)
   1117  1.1  mrg     i->word_num++;
   1118  1.1  mrg   else
   1119  1.1  mrg     {
   1120  1.1  mrg       i->word >>= 1;
   1121  1.1  mrg       i->bit_num++;
   1122  1.1  mrg     }
   1123  1.1  mrg }
   1124  1.1  mrg 
   1125  1.1  mrg /* Loop over all allocnos conflicting with ALLOCNO.  In each
   1126  1.1  mrg    iteration, A is set to the next conflicting allocno.  ITER is an
   1127  1.1  mrg    instance of ira_allocno_conflict_iterator used to iterate the
   1128  1.1  mrg    conflicts.  */
   1129  1.1  mrg #define FOR_EACH_ALLOCNO_CONFLICT(ALLOCNO, A, ITER)			\
   1130  1.1  mrg   for (ira_allocno_conflict_iter_init (&(ITER), (ALLOCNO));		\
   1131  1.1  mrg        ira_allocno_conflict_iter_cond (&(ITER), &(A));			\
   1132  1.1  mrg        ira_allocno_conflict_iter_next (&(ITER)))
   1133  1.1  mrg 
   1134  1.1  mrg 
   1135  1.1  mrg 
   1137  1.1  mrg /* The function returns TRUE if hard registers starting with
   1138  1.1  mrg    HARD_REGNO and containing value of MODE are not in set
   1139  1.1  mrg    HARD_REGSET.  */
   1140  1.1  mrg static inline bool
   1141  1.1  mrg ira_hard_reg_not_in_set_p (int hard_regno, enum machine_mode mode,
   1142  1.1  mrg 			   HARD_REG_SET hard_regset)
   1143  1.1  mrg {
   1144  1.1  mrg   int i;
   1145  1.1  mrg 
   1146  1.1  mrg   ira_assert (hard_regno >= 0);
   1147  1.1  mrg   for (i = hard_regno_nregs[hard_regno][mode] - 1; i >= 0; i--)
   1148  1.1  mrg     if (TEST_HARD_REG_BIT (hard_regset, hard_regno + i))
   1149  1.1  mrg       return false;
   1150  1.1  mrg   return true;
   1151  1.1  mrg }
   1152  1.1  mrg 
   1153  1.1  mrg 
   1154  1.1  mrg 
   1156  1.1  mrg /* To save memory we use a lazy approach for allocation and
   1157  1.1  mrg    initialization of the cost vectors.  We do this only when it is
   1158  1.1  mrg    really necessary.  */
   1159  1.1  mrg 
   1160  1.1  mrg /* Allocate cost vector *VEC for hard registers of COVER_CLASS and
   1161  1.1  mrg    initialize the elements by VAL if it is necessary */
   1162  1.1  mrg static inline void
   1163  1.1  mrg ira_allocate_and_set_costs (int **vec, enum reg_class cover_class, int val)
   1164  1.1  mrg {
   1165  1.1  mrg   int i, *reg_costs;
   1166  1.1  mrg   int len;
   1167  1.1  mrg 
   1168  1.1  mrg   if (*vec != NULL)
   1169  1.1  mrg     return;
   1170  1.1  mrg   *vec = reg_costs = ira_allocate_cost_vector (cover_class);
   1171  1.1  mrg   len = ira_class_hard_regs_num[cover_class];
   1172  1.1  mrg   for (i = 0; i < len; i++)
   1173  1.1  mrg     reg_costs[i] = val;
   1174  1.1  mrg }
   1175  1.1  mrg 
   1176  1.1  mrg /* Allocate cost vector *VEC for hard registers of COVER_CLASS and
   1177  1.1  mrg    copy values of vector SRC into the vector if it is necessary */
   1178  1.1  mrg static inline void
   1179  1.1  mrg ira_allocate_and_copy_costs (int **vec, enum reg_class cover_class, int *src)
   1180  1.1  mrg {
   1181  1.1  mrg   int len;
   1182  1.1  mrg 
   1183  1.1  mrg   if (*vec != NULL || src == NULL)
   1184  1.1  mrg     return;
   1185  1.1  mrg   *vec = ira_allocate_cost_vector (cover_class);
   1186  1.1  mrg   len = ira_class_hard_regs_num[cover_class];
   1187  1.1  mrg   memcpy (*vec, src, sizeof (int) * len);
   1188  1.1  mrg }
   1189  1.1  mrg 
   1190  1.1  mrg /* Allocate cost vector *VEC for hard registers of COVER_CLASS and
   1191  1.1  mrg    add values of vector SRC into the vector if it is necessary */
   1192  1.1  mrg static inline void
   1193  1.1  mrg ira_allocate_and_accumulate_costs (int **vec, enum reg_class cover_class,
   1194  1.1  mrg 				   int *src)
   1195  1.1  mrg {
   1196  1.1  mrg   int i, len;
   1197  1.1  mrg 
   1198  1.1  mrg   if (src == NULL)
   1199  1.1  mrg     return;
   1200  1.1  mrg   len = ira_class_hard_regs_num[cover_class];
   1201  1.1  mrg   if (*vec == NULL)
   1202  1.1  mrg     {
   1203  1.1  mrg       *vec = ira_allocate_cost_vector (cover_class);
   1204  1.1  mrg       memset (*vec, 0, sizeof (int) * len);
   1205  1.1  mrg     }
   1206  1.1  mrg   for (i = 0; i < len; i++)
   1207  1.1  mrg     (*vec)[i] += src[i];
   1208  1.1  mrg }
   1209  1.1  mrg 
   1210  1.1  mrg /* Allocate cost vector *VEC for hard registers of COVER_CLASS and
   1211  1.1  mrg    copy values of vector SRC into the vector or initialize it by VAL
   1212  1.1  mrg    (if SRC is null).  */
   1213  1.1  mrg static inline void
   1214  1.1  mrg ira_allocate_and_set_or_copy_costs (int **vec, enum reg_class cover_class,
   1215  1.1  mrg 				    int val, int *src)
   1216  1.1  mrg {
   1217  1.1  mrg   int i, *reg_costs;
   1218  1.1  mrg   int len;
   1219  1.1  mrg 
   1220  1.1  mrg   if (*vec != NULL)
   1221  1.1  mrg     return;
   1222  1.1  mrg   *vec = reg_costs = ira_allocate_cost_vector (cover_class);
   1223  1.1  mrg   len = ira_class_hard_regs_num[cover_class];
   1224  1.1  mrg   if (src != NULL)
   1225               memcpy (reg_costs, src, sizeof (int) * len);
   1226             else
   1227               {
   1228                 for (i = 0; i < len; i++)
   1229           	reg_costs[i] = val;
   1230               }
   1231           }
   1232