regs.h revision 1.1 1 1.1 mrg /* Define per-register tables for data flow info and register allocation.
2 1.1 mrg Copyright (C) 1987, 1993, 1994, 1995, 1996, 1997, 1998,
3 1.1 mrg 1999, 2000, 2003, 2004, 2005, 2006, 2007, 2008 Free Software
4 1.1 mrg Foundation, Inc.
5 1.1 mrg
6 1.1 mrg This file is part of GCC.
7 1.1 mrg
8 1.1 mrg GCC is free software; you can redistribute it and/or modify it under
9 1.1 mrg the terms of the GNU General Public License as published by the Free
10 1.1 mrg Software Foundation; either version 3, or (at your option) any later
11 1.1 mrg version.
12 1.1 mrg
13 1.1 mrg GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 1.1 mrg WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 1.1 mrg FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 1.1 mrg for more details.
17 1.1 mrg
18 1.1 mrg You should have received a copy of the GNU General Public License
19 1.1 mrg along with GCC; see the file COPYING3. If not see
20 1.1 mrg <http://www.gnu.org/licenses/>. */
21 1.1 mrg
22 1.1 mrg #ifndef GCC_REGS_H
23 1.1 mrg #define GCC_REGS_H
24 1.1 mrg
25 1.1 mrg #include "varray.h"
26 1.1 mrg #include "obstack.h"
27 1.1 mrg #include "hard-reg-set.h"
28 1.1 mrg #include "basic-block.h"
29 1.1 mrg
30 1.1 mrg #define REG_BYTES(R) mode_size[(int) GET_MODE (R)]
31 1.1 mrg
32 1.1 mrg /* When you only have the mode of a pseudo register before it has a hard
33 1.1 mrg register chosen for it, this reports the size of each hard register
34 1.1 mrg a pseudo in such a mode would get allocated to. A target may
35 1.1 mrg override this. */
36 1.1 mrg
37 1.1 mrg #ifndef REGMODE_NATURAL_SIZE
38 1.1 mrg #define REGMODE_NATURAL_SIZE(MODE) UNITS_PER_WORD
39 1.1 mrg #endif
40 1.1 mrg
41 1.1 mrg #ifndef SMALL_REGISTER_CLASSES
42 1.1 mrg #define SMALL_REGISTER_CLASSES 0
43 1.1 mrg #endif
44 1.1 mrg
45 1.1 mrg /* Maximum register number used in this function, plus one. */
46 1.1 mrg
47 1.1 mrg extern int max_regno;
48 1.1 mrg
49 1.1 mrg /* REG_N_REFS and REG_N_SETS are initialized by a call to
50 1.1 mrg regstat_init_n_sets_and_refs from the current values of
51 1.1 mrg DF_REG_DEF_COUNT and DF_REG_USE_COUNT. REG_N_REFS and REG_N_SETS
52 1.1 mrg should only be used if a pass need to change these values in some
53 1.1 mrg magical way or or the pass needs to have accurate values for these
54 1.1 mrg and is not using incremental df scanning.
55 1.1 mrg
56 1.1 mrg At the end of a pass that uses REG_N_REFS and REG_N_SETS, a call
57 1.1 mrg should be made to regstat_free_n_sets_and_refs.
58 1.1 mrg
59 1.1 mrg Local alloc seems to play pretty loose with these values.
60 1.1 mrg REG_N_REFS is set to 0 if the register is used in an asm.
61 1.1 mrg Furthermore, local_alloc calls regclass to hack both REG_N_REFS and
62 1.1 mrg REG_N_SETS for three address insns. Other passes seem to have
63 1.1 mrg other special values. */
64 1.1 mrg
65 1.1 mrg
66 1.1 mrg
67 1.1 mrg /* Structure to hold values for REG_N_SETS (i) and REG_N_REFS (i). */
68 1.1 mrg
69 1.1 mrg struct regstat_n_sets_and_refs_t
70 1.1 mrg {
71 1.1 mrg int sets; /* # of times (REG n) is set */
72 1.1 mrg int refs; /* # of times (REG n) is used or set */
73 1.1 mrg };
74 1.1 mrg
75 1.1 mrg extern struct regstat_n_sets_and_refs_t *regstat_n_sets_and_refs;
76 1.1 mrg
77 1.1 mrg /* Indexed by n, gives number of times (REG n) is used or set. */
78 1.1 mrg static inline int
79 1.1 mrg REG_N_REFS(int regno)
80 1.1 mrg {
81 1.1 mrg return regstat_n_sets_and_refs[regno].refs;
82 1.1 mrg }
83 1.1 mrg
84 1.1 mrg /* Indexed by n, gives number of times (REG n) is used or set. */
85 1.1 mrg #define SET_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs = V)
86 1.1 mrg #define INC_REG_N_REFS(N,V) (regstat_n_sets_and_refs[N].refs += V)
87 1.1 mrg
88 1.1 mrg /* Indexed by n, gives number of times (REG n) is set. */
89 1.1 mrg static inline int
90 1.1 mrg REG_N_SETS (int regno)
91 1.1 mrg {
92 1.1 mrg return regstat_n_sets_and_refs[regno].sets;
93 1.1 mrg }
94 1.1 mrg
95 1.1 mrg /* Indexed by n, gives number of times (REG n) is set. */
96 1.1 mrg #define SET_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets = V)
97 1.1 mrg #define INC_REG_N_SETS(N,V) (regstat_n_sets_and_refs[N].sets += V)
98 1.1 mrg
99 1.1 mrg
100 1.1 mrg /* Functions defined in reg-stat.c. */
101 1.1 mrg extern void regstat_init_n_sets_and_refs (void);
102 1.1 mrg extern void regstat_free_n_sets_and_refs (void);
103 1.1 mrg extern void regstat_compute_ri (void);
104 1.1 mrg extern void regstat_free_ri (void);
105 1.1 mrg extern bitmap regstat_get_setjmp_crosses (void);
106 1.1 mrg extern void regstat_compute_calls_crossed (void);
107 1.1 mrg extern void regstat_free_calls_crossed (void);
108 1.1 mrg
109 1.1 mrg
110 1.1 mrg /* Register information indexed by register number. This structure is
111 1.1 mrg initialized by calling regstat_compute_ri and is destroyed by
112 1.1 mrg calling regstat_free_ri. */
113 1.1 mrg struct reg_info_t
114 1.1 mrg {
115 1.1 mrg int freq; /* # estimated frequency (REG n) is used or set */
116 1.1 mrg int deaths; /* # of times (REG n) dies */
117 1.1 mrg int live_length; /* # of instructions (REG n) is live */
118 1.1 mrg int calls_crossed; /* # of calls (REG n) is live across */
119 1.1 mrg int freq_calls_crossed; /* # estimated frequency (REG n) crosses call */
120 1.1 mrg int throw_calls_crossed; /* # of calls that may throw (REG n) is live across */
121 1.1 mrg int basic_block; /* # of basic blocks (REG n) is used in */
122 1.1 mrg };
123 1.1 mrg
124 1.1 mrg extern struct reg_info_t *reg_info_p;
125 1.1 mrg
126 1.1 mrg /* The number allocated elements of reg_info_p. */
127 1.1 mrg extern size_t reg_info_p_size;
128 1.1 mrg
129 1.1 mrg /* Estimate frequency of references to register N. */
130 1.1 mrg
131 1.1 mrg #define REG_FREQ(N) (reg_info_p[N].freq)
132 1.1 mrg
133 1.1 mrg /* The weights for each insn varies from 0 to REG_FREQ_BASE.
134 1.1 mrg This constant does not need to be high, as in infrequently executed
135 1.1 mrg regions we want to count instructions equivalently to optimize for
136 1.1 mrg size instead of speed. */
137 1.1 mrg #define REG_FREQ_MAX 1000
138 1.1 mrg
139 1.1 mrg /* Compute register frequency from the BB frequency. When optimizing for size,
140 1.1 mrg or profile driven feedback is available and the function is never executed,
141 1.1 mrg frequency is always equivalent. Otherwise rescale the basic block
142 1.1 mrg frequency. */
143 1.1 mrg #define REG_FREQ_FROM_BB(bb) (optimize_size \
144 1.1 mrg || (flag_branch_probabilities \
145 1.1 mrg && !ENTRY_BLOCK_PTR->count) \
146 1.1 mrg ? REG_FREQ_MAX \
147 1.1 mrg : ((bb)->frequency * REG_FREQ_MAX / BB_FREQ_MAX)\
148 1.1 mrg ? ((bb)->frequency * REG_FREQ_MAX / BB_FREQ_MAX)\
149 1.1 mrg : 1)
150 1.1 mrg
151 1.1 mrg /* Indexed by N, gives number of insns in which register N dies.
152 1.1 mrg Note that if register N is live around loops, it can die
153 1.1 mrg in transitions between basic blocks, and that is not counted here.
154 1.1 mrg So this is only a reliable indicator of how many regions of life there are
155 1.1 mrg for registers that are contained in one basic block. */
156 1.1 mrg
157 1.1 mrg #define REG_N_DEATHS(N) (reg_info_p[N].deaths)
158 1.1 mrg
159 1.1 mrg /* Get the number of consecutive words required to hold pseudo-reg N. */
160 1.1 mrg
161 1.1 mrg #define PSEUDO_REGNO_SIZE(N) \
162 1.1 mrg ((GET_MODE_SIZE (PSEUDO_REGNO_MODE (N)) + UNITS_PER_WORD - 1) \
163 1.1 mrg / UNITS_PER_WORD)
164 1.1 mrg
165 1.1 mrg /* Get the number of bytes required to hold pseudo-reg N. */
166 1.1 mrg
167 1.1 mrg #define PSEUDO_REGNO_BYTES(N) \
168 1.1 mrg GET_MODE_SIZE (PSEUDO_REGNO_MODE (N))
169 1.1 mrg
170 1.1 mrg /* Get the machine mode of pseudo-reg N. */
171 1.1 mrg
172 1.1 mrg #define PSEUDO_REGNO_MODE(N) GET_MODE (regno_reg_rtx[N])
173 1.1 mrg
174 1.1 mrg /* Indexed by N, gives number of CALL_INSNS across which (REG n) is live. */
175 1.1 mrg
176 1.1 mrg #define REG_N_CALLS_CROSSED(N) (reg_info_p[N].calls_crossed)
177 1.1 mrg #define REG_FREQ_CALLS_CROSSED(N) (reg_info_p[N].freq_calls_crossed)
178 1.1 mrg
179 1.1 mrg /* Indexed by N, gives number of CALL_INSNS that may throw, across which
180 1.1 mrg (REG n) is live. */
181 1.1 mrg
182 1.1 mrg #define REG_N_THROWING_CALLS_CROSSED(N) (reg_info_p[N].throw_calls_crossed)
183 1.1 mrg
184 1.1 mrg /* Total number of instructions at which (REG n) is live. The larger
185 1.1 mrg this is, the less priority (REG n) gets for allocation in a hard
186 1.1 mrg register (in global-alloc). This is set in df-problems.c whenever
187 1.1 mrg register info is requested and remains valid for the rest of the
188 1.1 mrg compilation of the function; it is used to control register
189 1.1 mrg allocation.
190 1.1 mrg
191 1.1 mrg local-alloc.c may alter this number to change the priority.
192 1.1 mrg
193 1.1 mrg Negative values are special.
194 1.1 mrg -1 is used to mark a pseudo reg which has a constant or memory equivalent
195 1.1 mrg and is used infrequently enough that it should not get a hard register.
196 1.1 mrg -2 is used to mark a pseudo reg for a parameter, when a frame pointer
197 1.1 mrg is not required. global.c makes an allocno for this but does
198 1.1 mrg not try to assign a hard register to it. */
199 1.1 mrg
200 1.1 mrg #define REG_LIVE_LENGTH(N) (reg_info_p[N].live_length)
201 1.1 mrg
202 1.1 mrg /* Indexed by n, gives number of basic block that (REG n) is used in.
203 1.1 mrg If the value is REG_BLOCK_GLOBAL (-1),
204 1.1 mrg it means (REG n) is used in more than one basic block.
205 1.1 mrg REG_BLOCK_UNKNOWN (0) means it hasn't been seen yet so we don't know.
206 1.1 mrg This information remains valid for the rest of the compilation
207 1.1 mrg of the current function; it is used to control register allocation. */
208 1.1 mrg
209 1.1 mrg #define REG_BLOCK_UNKNOWN 0
210 1.1 mrg #define REG_BLOCK_GLOBAL -1
211 1.1 mrg
212 1.1 mrg #define REG_BASIC_BLOCK(N) (reg_info_p[N].basic_block)
213 1.1 mrg
214 1.1 mrg /* Vector of substitutions of register numbers,
215 1.1 mrg used to map pseudo regs into hardware regs.
216 1.1 mrg
217 1.1 mrg This can't be folded into reg_n_info without changing all of the
218 1.1 mrg machine dependent directories, since the reload functions
219 1.1 mrg in the machine dependent files access it. */
220 1.1 mrg
221 1.1 mrg extern short *reg_renumber;
222 1.1 mrg
223 1.1 mrg /* Vector indexed by machine mode saying whether there are regs of that mode. */
224 1.1 mrg
225 1.1 mrg extern bool have_regs_of_mode [MAX_MACHINE_MODE];
226 1.1 mrg
227 1.1 mrg /* For each hard register, the widest mode object that it can contain.
228 1.1 mrg This will be a MODE_INT mode if the register can hold integers. Otherwise
229 1.1 mrg it will be a MODE_FLOAT or a MODE_CC mode, whichever is valid for the
230 1.1 mrg register. */
231 1.1 mrg
232 1.1 mrg extern enum machine_mode reg_raw_mode[FIRST_PSEUDO_REGISTER];
233 1.1 mrg
234 1.1 mrg /* Flag set by local-alloc or global-alloc if they decide to allocate
235 1.1 mrg something in a call-clobbered register. */
236 1.1 mrg
237 1.1 mrg extern int caller_save_needed;
238 1.1 mrg
239 1.1 mrg /* Predicate to decide whether to give a hard reg to a pseudo which
240 1.1 mrg is referenced REFS times and would need to be saved and restored
241 1.1 mrg around a call CALLS times. */
242 1.1 mrg
243 1.1 mrg #ifndef CALLER_SAVE_PROFITABLE
244 1.1 mrg #define CALLER_SAVE_PROFITABLE(REFS, CALLS) (4 * (CALLS) < (REFS))
245 1.1 mrg #endif
246 1.1 mrg
247 1.1 mrg /* On most machines a register class is likely to be spilled if it
248 1.1 mrg only has one register. */
249 1.1 mrg #ifndef CLASS_LIKELY_SPILLED_P
250 1.1 mrg #define CLASS_LIKELY_SPILLED_P(CLASS) (reg_class_size[(int) (CLASS)] == 1)
251 1.1 mrg #endif
252 1.1 mrg
253 1.1 mrg /* Select a register mode required for caller save of hard regno REGNO. */
254 1.1 mrg #ifndef HARD_REGNO_CALLER_SAVE_MODE
255 1.1 mrg #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \
256 1.1 mrg choose_hard_reg_mode (REGNO, NREGS, false)
257 1.1 mrg #endif
258 1.1 mrg
259 1.1 mrg /* Registers that get partially clobbered by a call in a given mode.
260 1.1 mrg These must not be call used registers. */
261 1.1 mrg #ifndef HARD_REGNO_CALL_PART_CLOBBERED
262 1.1 mrg #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) 0
263 1.1 mrg #endif
264 1.1 mrg
265 1.1 mrg /* 1 if the corresponding class does contain register of given
266 1.1 mrg mode. */
267 1.1 mrg extern char contains_reg_of_mode [N_REG_CLASSES] [MAX_MACHINE_MODE];
268 1.1 mrg
269 1.1 mrg typedef unsigned short move_table[N_REG_CLASSES];
270 1.1 mrg
271 1.1 mrg /* Maximum cost of moving from a register in one class to a register
272 1.1 mrg in another class. */
273 1.1 mrg extern move_table *move_cost[MAX_MACHINE_MODE];
274 1.1 mrg
275 1.1 mrg /* Specify number of hard registers given machine mode occupy. */
276 1.1 mrg extern unsigned char hard_regno_nregs[FIRST_PSEUDO_REGISTER][MAX_MACHINE_MODE];
277 1.1 mrg
278 1.1 mrg /* Similar, but here we don't have to move if the first index is a
279 1.1 mrg subset of the second so in that case the cost is zero. */
280 1.1 mrg extern move_table *may_move_in_cost[MAX_MACHINE_MODE];
281 1.1 mrg
282 1.1 mrg /* Similar, but here we don't have to move if the first index is a
283 1.1 mrg superset of the second so in that case the cost is zero. */
284 1.1 mrg extern move_table *may_move_out_cost[MAX_MACHINE_MODE];
285 1.1 mrg
286 1.1 mrg /* Return an exclusive upper bound on the registers occupied by hard
287 1.1 mrg register (reg:MODE REGNO). */
288 1.1 mrg
289 1.1 mrg static inline unsigned int
290 1.1 mrg end_hard_regno (enum machine_mode mode, unsigned int regno)
291 1.1 mrg {
292 1.1 mrg return regno + hard_regno_nregs[regno][(int) mode];
293 1.1 mrg }
294 1.1 mrg
295 1.1 mrg /* Likewise for hard register X. */
296 1.1 mrg
297 1.1 mrg #define END_HARD_REGNO(X) end_hard_regno (GET_MODE (X), REGNO (X))
298 1.1 mrg
299 1.1 mrg /* Likewise for hard or pseudo register X. */
300 1.1 mrg
301 1.1 mrg #define END_REGNO(X) (HARD_REGISTER_P (X) ? END_HARD_REGNO (X) : REGNO (X) + 1)
302 1.1 mrg
303 1.1 mrg /* Add to REGS all the registers required to store a value of mode MODE
304 1.1 mrg in register REGNO. */
305 1.1 mrg
306 1.1 mrg static inline void
307 1.1 mrg add_to_hard_reg_set (HARD_REG_SET *regs, enum machine_mode mode,
308 1.1 mrg unsigned int regno)
309 1.1 mrg {
310 1.1 mrg unsigned int end_regno;
311 1.1 mrg
312 1.1 mrg end_regno = end_hard_regno (mode, regno);
313 1.1 mrg do
314 1.1 mrg SET_HARD_REG_BIT (*regs, regno);
315 1.1 mrg while (++regno < end_regno);
316 1.1 mrg }
317 1.1 mrg
318 1.1 mrg /* Likewise, but remove the registers. */
319 1.1 mrg
320 1.1 mrg static inline void
321 1.1 mrg remove_from_hard_reg_set (HARD_REG_SET *regs, enum machine_mode mode,
322 1.1 mrg unsigned int regno)
323 1.1 mrg {
324 1.1 mrg unsigned int end_regno;
325 1.1 mrg
326 1.1 mrg end_regno = end_hard_regno (mode, regno);
327 1.1 mrg do
328 1.1 mrg CLEAR_HARD_REG_BIT (*regs, regno);
329 1.1 mrg while (++regno < end_regno);
330 1.1 mrg }
331 1.1 mrg
332 1.1 mrg /* Return true if REGS contains the whole of (reg:MODE REGNO). */
333 1.1 mrg
334 1.1 mrg static inline bool
335 1.1 mrg in_hard_reg_set_p (const HARD_REG_SET regs, enum machine_mode mode,
336 1.1 mrg unsigned int regno)
337 1.1 mrg {
338 1.1 mrg unsigned int end_regno;
339 1.1 mrg
340 1.1 mrg if (!TEST_HARD_REG_BIT (regs, regno))
341 1.1 mrg return false;
342 1.1 mrg
343 1.1 mrg end_regno = end_hard_regno (mode, regno);
344 1.1 mrg while (++regno < end_regno)
345 1.1 mrg if (!TEST_HARD_REG_BIT (regs, regno))
346 1.1 mrg return false;
347 1.1 mrg
348 1.1 mrg return true;
349 1.1 mrg }
350 1.1 mrg
351 1.1 mrg /* Return true if (reg:MODE REGNO) includes an element of REGS. */
352 1.1 mrg
353 1.1 mrg static inline bool
354 1.1 mrg overlaps_hard_reg_set_p (const HARD_REG_SET regs, enum machine_mode mode,
355 1.1 mrg unsigned int regno)
356 1.1 mrg {
357 1.1 mrg unsigned int end_regno;
358 1.1 mrg
359 1.1 mrg if (TEST_HARD_REG_BIT (regs, regno))
360 1.1 mrg return true;
361 1.1 mrg
362 1.1 mrg end_regno = end_hard_regno (mode, regno);
363 1.1 mrg while (++regno < end_regno)
364 1.1 mrg if (TEST_HARD_REG_BIT (regs, regno))
365 1.1 mrg return true;
366 1.1 mrg
367 1.1 mrg return false;
368 1.1 mrg }
369 1.1 mrg
370 1.1 mrg #endif /* GCC_REGS_H */
371