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sync-cache.c revision 1.1 
      1 /* Machine description for AArch64 architecture.
      2    Copyright (C) 2012-2013 Free Software Foundation, Inc.
      3    Contributed by ARM Ltd.
      4 
      5 This file is part of GCC.
      6 
      7 GCC is free software; you can redistribute it and/or modify it under
      8 the terms of the GNU General Public License as published by the Free
      9 Software Foundation; either version 3, or (at your option) any later
     10 version.
     11 
     12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
     13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
     14 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
     15 for more details.
     16 
     17 Under Section 7 of GPL version 3, you are granted additional
     18 permissions described in the GCC Runtime Library Exception, version
     19 3.1, as published by the Free Software Foundation.
     20 
     21 You should have received a copy of the GNU General Public License and
     22 a copy of the GCC Runtime Library Exception along with this program;
     23 see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     24 <http://www.gnu.org/licenses/>.  */
     25 
     26 void __aarch64_sync_cache_range (const void *, const void *);
     27 
     28 void
     29 __aarch64_sync_cache_range (const void *base, const void *end)
     30 {
     31   unsigned icache_lsize;
     32   unsigned dcache_lsize;
     33   static unsigned int cache_info = 0;
     34   const char *address;
     35 
     36   if (! cache_info)
     37     /* CTR_EL0 [3:0] contains log2 of icache line size in words.
     38        CTR_EL0 [19:16] contains log2 of dcache line size in words.  */
     39     asm volatile ("mrs\t%0, ctr_el0":"=r" (cache_info));
     40 
     41   icache_lsize = 4 << (cache_info & 0xF);
     42   dcache_lsize = 4 << ((cache_info >> 16) & 0xF);
     43 
     44   /* Loop over the address range, clearing one cache line at once.
     45      Data cache must be flushed to unification first to make sure the
     46      instruction cache fetches the updated data.  'end' is exclusive,
     47      as per the GNU definition of __clear_cache.  */
     48 
     49   /* Make the start address of the loop cache aligned.  */
     50   address = (const char*) ((__UINTPTR_TYPE__) base
     51 			   & ~ (__UINTPTR_TYPE__) (dcache_lsize - 1));
     52 
     53   for (; address < (const char *) end; address += dcache_lsize)
     54     asm volatile ("dc\tcvau, %0"
     55 		  :
     56 		  : "r" (address)
     57 		  : "memory");
     58 
     59   asm volatile ("dsb\tish" : : : "memory");
     60 
     61   /* Make the start address of the loop cache aligned.  */
     62   address = (const char*) ((__UINTPTR_TYPE__) base
     63 			   & ~ (__UINTPTR_TYPE__) (icache_lsize - 1));
     64 
     65   for (; address < (const char *) end; address += icache_lsize)
     66     asm volatile ("ic\tivau, %0"
     67 		  :
     68 		  : "r" (address)
     69 		  : "memory");
     70 
     71   asm volatile ("dsb\tish; isb" : : : "memory");
     72 }
     73