1 1.1 mrg /* c-isr library stuff of Andes NDS32 cpu for GNU compiler 2 1.7 mrg Copyright (C) 2012-2022 Free Software Foundation, Inc. 3 1.1 mrg Contributed by Andes Technology Corporation. 4 1.1 mrg 5 1.1 mrg This file is part of GCC. 6 1.1 mrg 7 1.1 mrg GCC is free software; you can redistribute it and/or modify it 8 1.1 mrg under the terms of the GNU General Public License as published 9 1.1 mrg by the Free Software Foundation; either version 3, or (at your 10 1.1 mrg option) any later version. 11 1.1 mrg 12 1.1 mrg GCC is distributed in the hope that it will be useful, but WITHOUT 13 1.1 mrg ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 1.1 mrg or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 1.1 mrg License for more details. 16 1.1 mrg 17 1.1 mrg Under Section 7 of GPL version 3, you are granted additional 18 1.1 mrg permissions described in the GCC Runtime Library Exception, version 19 1.1 mrg 3.1, as published by the Free Software Foundation. 20 1.1 mrg 21 1.1 mrg You should have received a copy of the GNU General Public License and 22 1.1 mrg a copy of the GCC Runtime Library Exception along with this program; 23 1.1 mrg see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 24 1.1 mrg <http://www.gnu.org/licenses/>. */ 25 1.1 mrg 26 1.1 mrg .section .nds32_isr, "ax" /* Put it in the section of 1st level handler. */ 27 1.1 mrg .align 1 28 1.1 mrg .weak _SDA_BASE_ /* For reset handler only. */ 29 1.1 mrg .weak _nds32_init_mem /* User defined memory initialization function. */ 30 1.1 mrg .globl _start 31 1.1 mrg .globl _nds32_reset 32 1.1 mrg .type _nds32_reset, @function 33 1.1 mrg _nds32_reset: 34 1.1 mrg _start: 35 1.1 mrg /* Handle NMI and warm boot if any of them exists. */ 36 1.1 mrg beqz $sp, 1f /* Reset, NMI or warm boot? */ 37 1.1 mrg /* Either NMI or warm boot; save all regs. */ 38 1.1 mrg 39 1.1 mrg /* Preserve registers for context-switching. */ 40 1.5 mrg #if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS 41 1.1 mrg /* For 16-reg mode. */ 42 1.1 mrg smw.adm $r0, [$sp], $r10, #0x0 43 1.1 mrg smw.adm $r15, [$sp], $r15, #0xf 44 1.1 mrg #else 45 1.1 mrg /* For 32-reg mode. */ 46 1.1 mrg smw.adm $r0, [$sp], $r27, #0xf 47 1.1 mrg #endif 48 1.5 mrg #if __NDS32_EXT_IFC__ 49 1.1 mrg mfusr $r1, $IFC_LP 50 1.5 mrg smw.adm $r1, [$sp], $r2, #0x0 /* Save extra $r2 to keep stack 8-byte alignment. */ 51 1.1 mrg #endif 52 1.1 mrg 53 1.1 mrg la $gp, _SDA_BASE_ /* Init GP for small data access. */ 54 1.1 mrg move $r0, $sp /* Init parameter. */ 55 1.1 mrg mfsr $r1, $ITYPE /* Check ITYPE for NMI or warm boot. */ 56 1.1 mrg andi $r1, $r1, #0xf 57 1.1 mrg addi $r1, $r1, #-1 58 1.1 mrg beqz $r1, 2f /* Warm boot if true. */ 59 1.1 mrg l.w $r15, _nds32_nmih /* Load NMI handler. */ 60 1.1 mrg j 3f 61 1.1 mrg 2: 62 1.1 mrg l.w $r15, _nds32_wrh /* Load warm boot handler. */ 63 1.1 mrg 3: 64 1.1 mrg beqz $r15, 1f /* If no handler, do cold boot. */ 65 1.1 mrg jral $r15 /* Call handler. */ 66 1.1 mrg bnez $r0, 1f /* If fail to resume, do cold boot. */ 67 1.1 mrg 68 1.1 mrg /* Restore registers for context-switching. */ 69 1.5 mrg #if __NDS32_EXT_IFC__ 70 1.5 mrg lmw.bim $r1, [$sp], $r2, #0x0 /* Restore extra $r2 to keep stack 8-byte alignment. */ 71 1.1 mrg mtusr $r1, $IFC_LP 72 1.1 mrg #endif 73 1.5 mrg #if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS 74 1.1 mrg /* For 16-reg mode. */ 75 1.1 mrg lmw.bim $r15, [$sp], $r15, #0xf 76 1.1 mrg lmw.bim $r0, [$sp], $r10, #0x0 77 1.1 mrg #else 78 1.1 mrg /* For 32-reg mode. */ 79 1.1 mrg lmw.bim $r0, [$sp], $r27, #0xf 80 1.1 mrg #endif 81 1.1 mrg iret /* Resume operation. */ 82 1.1 mrg 83 1.1 mrg 84 1.1 mrg 1: /* Cold boot. */ 85 1.5 mrg #if __NDS32_ISR_VECTOR_SIZE_4__ 86 1.5 mrg /* With vector ID feature for v3 architecture, default vector size is 4-byte. */ 87 1.5 mrg /* Set IVB.ESZ = 0 (vector table entry size = 4 bytes) */ 88 1.5 mrg mfsr $r0, $IVB 89 1.5 mrg li $r1, #0xc000 90 1.5 mrg or $r0, $r0, $r1 91 1.5 mrg xor $r0, $r0, $r1 92 1.5 mrg mtsr $r0, $IVB 93 1.5 mrg dsb 94 1.5 mrg #else 95 1.5 mrg /* There is no vector ID feature, so the vector size must be 16-byte. */ 96 1.1 mrg /* Set IVB.ESZ = 1 (vector table entry size = 16 bytes) */ 97 1.1 mrg mfsr $r0, $IVB 98 1.1 mrg li $r1, #0xffff3fff 99 1.1 mrg and $r0, $r0, $r1 100 1.1 mrg ori $r0, $r0, #0x4000 101 1.1 mrg mtsr $r0, $IVB 102 1.1 mrg dsb 103 1.5 mrg #endif 104 1.1 mrg 105 1.1 mrg la $gp, _SDA_BASE_ /* Init $gp. */ 106 1.1 mrg la $sp, _stack /* Init $sp. */ 107 1.5 mrg 108 1.5 mrg #if __NDS32_EXT_EX9__ 109 1.5 mrg .L_init_itb: 110 1.5 mrg /* Initialization for Instruction Table Base (ITB). 111 1.5 mrg The symbol _ITB_BASE_ is determined by Linker. 112 1.5 mrg Set $ITB only if MSC_CFG.EIT (cr4.b'24) is set. */ 113 1.5 mrg mfsr $r0, $MSC_CFG 114 1.1 mrg srli $r0, $r0, 24 115 1.1 mrg andi $r0, $r0, 0x1 116 1.5 mrg beqz $r0, 4f /* Fall through ? */ 117 1.5 mrg la $r0, _ITB_BASE_ 118 1.1 mrg mtusr $r0, $ITB 119 1.1 mrg 4: 120 1.1 mrg #endif 121 1.5 mrg 122 1.5 mrg #if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__ 123 1.5 mrg .L_init_fpu: 124 1.5 mrg /* Initialize FPU 125 1.5 mrg Set FUCOP_CTL.CP0EN (fucpr.b'0). */ 126 1.5 mrg mfsr $r0, $FUCOP_CTL 127 1.5 mrg ori $r0, $r0, 0x1 128 1.5 mrg mtsr $r0, $FUCOP_CTL 129 1.5 mrg dsb 130 1.5 mrg /* According to [bugzilla #9425], set flush-to-zero mode. 131 1.5 mrg That is, set $FPCSR.DNZ(b'12) = 1. */ 132 1.5 mrg FMFCSR $r0 133 1.5 mrg ori $r0, $r0, 0x1000 134 1.5 mrg FMTCSR $r0 135 1.5 mrg dsb 136 1.5 mrg #endif 137 1.5 mrg 138 1.5 mrg /* Call DRAM init. _nds32_init_mem may written by C language. */ 139 1.5 mrg la $r15, _nds32_init_mem 140 1.1 mrg beqz $r15, 6f 141 1.1 mrg jral $r15 142 1.1 mrg 6: 143 1.1 mrg l.w $r15, _nds32_jmptbl_00 /* Load reset handler. */ 144 1.1 mrg jral $r15 145 1.5 mrg 146 1.5 mrg /* Reset handler() should never return in a RTOS or non-OS system. 147 1.5 mrg In case it does return, an exception will be generated. 148 1.5 mrg This exception will be caught either by default break handler or by EDM. 149 1.5 mrg Default break handle may just do an infinite loop. 150 1.5 mrg EDM will notify GDB and GDB will regain control when the ID is 0x7fff. */ 151 1.1 mrg 5: 152 1.1 mrg break #0x7fff 153 1.1 mrg .size _nds32_reset, .-_nds32_reset 154
Indexes created Wed May 06 00:24:28 UTC 2026