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      1  1.1  mrg /* c-isr library stuff of Andes NDS32 cpu for GNU compiler
      2  1.7  mrg    Copyright (C) 2012-2022 Free Software Foundation, Inc.
      3  1.1  mrg    Contributed by Andes Technology Corporation.
      4  1.1  mrg 
      5  1.1  mrg    This file is part of GCC.
      6  1.1  mrg 
      7  1.1  mrg    GCC is free software; you can redistribute it and/or modify it
      8  1.1  mrg    under the terms of the GNU General Public License as published
      9  1.1  mrg    by the Free Software Foundation; either version 3, or (at your
     10  1.1  mrg    option) any later version.
     11  1.1  mrg 
     12  1.1  mrg    GCC is distributed in the hope that it will be useful, but WITHOUT
     13  1.1  mrg    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
     14  1.1  mrg    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
     15  1.1  mrg    License for more details.
     16  1.1  mrg 
     17  1.1  mrg    Under Section 7 of GPL version 3, you are granted additional
     18  1.1  mrg    permissions described in the GCC Runtime Library Exception, version
     19  1.1  mrg    3.1, as published by the Free Software Foundation.
     20  1.1  mrg 
     21  1.1  mrg    You should have received a copy of the GNU General Public License and
     22  1.1  mrg    a copy of the GCC Runtime Library Exception along with this program;
     23  1.1  mrg    see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see
     24  1.1  mrg    <http://www.gnu.org/licenses/>.  */
     25  1.1  mrg 
     26  1.5  mrg #if __NDS32_ISR_VECTOR_SIZE_4__
     27  1.5  mrg 
     28  1.5  mrg /* If vector size is 4-byte, we have to save registers
     29  1.5  mrg    in the macro implementation.  */
     30  1.5  mrg .macro SAVE_PARTIAL
     31  1.5  mrg #if __NDS32_REDUCED_REGS__ || __NDS32_REDUCE_REGS
     32  1.1  mrg 	smw.adm $r15, [$sp], $r15, #0x2
     33  1.5  mrg #else
     34  1.1  mrg 	smw.adm $r15, [$sp], $r27, #0x2
     35  1.5  mrg #endif
     36  1.1  mrg 	smw.adm $r0, [$sp], $r5, #0x0
     37  1.5  mrg   SAVE_USR_REGS
     38  1.5  mrg   SAVE_MAC_REGS
     39  1.5  mrg   SAVE_FPU_REGS
     40  1.1  mrg #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
     41  1.1  mrg        mfsr    $r1, $IPC       /* Get IPC.  */
     42  1.1  mrg        mfsr    $r2, $IPSW      /* Get IPSW.  */
     43  1.1  mrg        smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
     44  1.1  mrg #endif
     45  1.1  mrg 	mfsr	$r0, $ITYPE	/* Get VID to $r0.  */
     46  1.1  mrg 	srli	$r0, $r0, #5
     47  1.1  mrg 	andi	$r0, $r0, #127
     48  1.1  mrg .endm
     49  1.1  mrg 
     50  1.5  mrg #else /* not __NDS32_ISR_VECTOR_SIZE_4__ */
     51  1.5  mrg 
     52  1.5  mrg /* If vector size is 16-byte, some works can be done in
     53  1.5  mrg    the vector section generated by compiler, so that we
     54  1.5  mrg    can implement less in the macro.  */
     55  1.5  mrg 
     56  1.1  mrg .macro SAVE_PARTIAL
     57  1.5  mrg   SAVE_USR_REGS
     58  1.5  mrg   SAVE_MAC_REGS
     59  1.5  mrg   SAVE_FPU_REGS
     60  1.1  mrg #if defined(NDS32_NESTED) || defined(NDS32_NESTED_READY)
     61  1.1  mrg        mfsr    $r1, $IPC       /* Get IPC.  */
     62  1.1  mrg        mfsr    $r2, $IPSW      /* Get IPSW.  */
     63  1.1  mrg        smw.adm $r1, [$sp], $r2, #0x0   /* Push IPC, IPSW.  */
     64  1.1  mrg #endif
     65  1.1  mrg .endm
     66  1.5  mrg 
     67  1.5  mrg #endif /* not __NDS32_ISR_VECTOR_SIZE_4__ */
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