arm-cpu-cdata.h revision 1.1
1 1.1 mrg /* This file is automatically generated. DO NOT EDIT! */ 2 1.1 mrg /* Generated from: NetBSD: mknative-gcc,v 1.103 2019/10/24 03:19:14 christos Exp */ 3 1.1 mrg /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp */ 4 1.1 mrg 5 1.1 mrg /* -*- buffer-read-only: t -*- 6 1.1 mrg Generated automatically by parsecpu.awk from arm-cpus.in. 7 1.1 mrg Do not edit. 8 1.1 mrg 9 1.1 mrg Copyright (C) 2011-2018 Free Software Foundation, Inc. 10 1.1 mrg 11 1.1 mrg This file is part of GCC. 12 1.1 mrg 13 1.1 mrg GCC is free software; you can redistribute it and/or modify 14 1.1 mrg it under the terms of the GNU General Public License as 15 1.1 mrg published by the Free Software Foundation; either version 3, 16 1.1 mrg or (at your option) any later version. 17 1.1 mrg 18 1.1 mrg GCC is distributed in the hope that it will be useful, 19 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of 20 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 1.1 mrg GNU General Public License for more details. 22 1.1 mrg 23 1.1 mrg You should have received a copy of the GNU General Public 24 1.1 mrg License along with GCC; see the file COPYING3. If not see 25 1.1 mrg <http://www.gnu.org/licenses/>. */ 26 1.1 mrg 27 1.1 mrg static const cpu_arch_extension cpu_opttab_arm9e[] = { 28 1.1 mrg { 29 1.1 mrg "nofp", true, false, 30 1.1 mrg { 31 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 32 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 33 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 34 1.1 mrg } 35 1.1 mrg }, 36 1.1 mrg { NULL, false, false, {isa_nobit}} 37 1.1 mrg }; 38 1.1 mrg 39 1.1 mrg static const cpu_arch_extension cpu_opttab_arm946es[] = { 40 1.1 mrg { 41 1.1 mrg "nofp", true, false, 42 1.1 mrg { 43 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 44 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 45 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 46 1.1 mrg } 47 1.1 mrg }, 48 1.1 mrg { NULL, false, false, {isa_nobit}} 49 1.1 mrg }; 50 1.1 mrg 51 1.1 mrg static const cpu_arch_extension cpu_opttab_arm966es[] = { 52 1.1 mrg { 53 1.1 mrg "nofp", true, false, 54 1.1 mrg { 55 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 56 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 57 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 58 1.1 mrg } 59 1.1 mrg }, 60 1.1 mrg { NULL, false, false, {isa_nobit}} 61 1.1 mrg }; 62 1.1 mrg 63 1.1 mrg static const cpu_arch_extension cpu_opttab_arm968es[] = { 64 1.1 mrg { 65 1.1 mrg "nofp", true, false, 66 1.1 mrg { 67 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 68 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 69 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 70 1.1 mrg } 71 1.1 mrg }, 72 1.1 mrg { NULL, false, false, {isa_nobit}} 73 1.1 mrg }; 74 1.1 mrg 75 1.1 mrg static const cpu_arch_extension cpu_opttab_arm10e[] = { 76 1.1 mrg { 77 1.1 mrg "nofp", true, false, 78 1.1 mrg { 79 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 80 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 81 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 82 1.1 mrg } 83 1.1 mrg }, 84 1.1 mrg { NULL, false, false, {isa_nobit}} 85 1.1 mrg }; 86 1.1 mrg 87 1.1 mrg static const cpu_arch_extension cpu_opttab_arm1020e[] = { 88 1.1 mrg { 89 1.1 mrg "nofp", true, false, 90 1.1 mrg { 91 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 92 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 93 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 94 1.1 mrg } 95 1.1 mrg }, 96 1.1 mrg { NULL, false, false, {isa_nobit}} 97 1.1 mrg }; 98 1.1 mrg 99 1.1 mrg static const cpu_arch_extension cpu_opttab_arm1022e[] = { 100 1.1 mrg { 101 1.1 mrg "nofp", true, false, 102 1.1 mrg { 103 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 104 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 105 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 106 1.1 mrg } 107 1.1 mrg }, 108 1.1 mrg { NULL, false, false, {isa_nobit}} 109 1.1 mrg }; 110 1.1 mrg 111 1.1 mrg static const cpu_arch_extension cpu_opttab_arm926ejs[] = { 112 1.1 mrg { 113 1.1 mrg "nofp", true, false, 114 1.1 mrg { 115 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 116 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 117 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 118 1.1 mrg } 119 1.1 mrg }, 120 1.1 mrg { NULL, false, false, {isa_nobit}} 121 1.1 mrg }; 122 1.1 mrg 123 1.1 mrg static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { 124 1.1 mrg { 125 1.1 mrg "nofp", true, false, 126 1.1 mrg { 127 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 128 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 129 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 130 1.1 mrg } 131 1.1 mrg }, 132 1.1 mrg { NULL, false, false, {isa_nobit}} 133 1.1 mrg }; 134 1.1 mrg 135 1.1 mrg static const cpu_arch_extension cpu_opttab_genericv7a[] = { 136 1.1 mrg { 137 1.1 mrg "mp", false, false, 138 1.1 mrg { 139 1.1 mrg isa_bit_mp, isa_nobit 140 1.1 mrg } 141 1.1 mrg }, 142 1.1 mrg { 143 1.1 mrg "sec", false, false, 144 1.1 mrg { 145 1.1 mrg isa_bit_sec, isa_nobit 146 1.1 mrg } 147 1.1 mrg }, 148 1.1 mrg { 149 1.1 mrg "vfpv3-d16", false, false, 150 1.1 mrg { 151 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 152 1.1 mrg } 153 1.1 mrg }, 154 1.1 mrg { 155 1.1 mrg "vfpv3", false, false, 156 1.1 mrg { 157 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 158 1.1 mrg isa_nobit 159 1.1 mrg } 160 1.1 mrg }, 161 1.1 mrg { 162 1.1 mrg "vfpv3-d16-fp16", false, false, 163 1.1 mrg { 164 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 165 1.1 mrg isa_nobit 166 1.1 mrg } 167 1.1 mrg }, 168 1.1 mrg { 169 1.1 mrg "vfpv3-fp16", false, false, 170 1.1 mrg { 171 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 172 1.1 mrg isa_bit_fp_dbl, isa_nobit 173 1.1 mrg } 174 1.1 mrg }, 175 1.1 mrg { 176 1.1 mrg "vfpv4-d16", false, false, 177 1.1 mrg { 178 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 179 1.1 mrg isa_bit_fp_dbl, isa_nobit 180 1.1 mrg } 181 1.1 mrg }, 182 1.1 mrg { 183 1.1 mrg "vfpv4", false, false, 184 1.1 mrg { 185 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 186 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 187 1.1 mrg } 188 1.1 mrg }, 189 1.1 mrg { 190 1.1 mrg "simd", false, false, 191 1.1 mrg { 192 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 193 1.1 mrg isa_bit_fp_dbl, isa_nobit 194 1.1 mrg } 195 1.1 mrg }, 196 1.1 mrg { 197 1.1 mrg "neon-fp16", false, false, 198 1.1 mrg { 199 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 200 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 201 1.1 mrg } 202 1.1 mrg }, 203 1.1 mrg { 204 1.1 mrg "neon-vfpv4", false, false, 205 1.1 mrg { 206 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 207 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 208 1.1 mrg } 209 1.1 mrg }, 210 1.1 mrg { 211 1.1 mrg "nosimd", true, false, 212 1.1 mrg { 213 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 214 1.1 mrg isa_bit_crypto, isa_nobit 215 1.1 mrg } 216 1.1 mrg }, 217 1.1 mrg { 218 1.1 mrg "nofp", true, false, 219 1.1 mrg { 220 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 221 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 222 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 223 1.1 mrg } 224 1.1 mrg }, 225 1.1 mrg { 226 1.1 mrg "neon", false, true, 227 1.1 mrg { 228 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 229 1.1 mrg isa_bit_fp_dbl, isa_nobit 230 1.1 mrg } 231 1.1 mrg }, 232 1.1 mrg { 233 1.1 mrg "neon-vfpv3", false, true, 234 1.1 mrg { 235 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 236 1.1 mrg isa_bit_fp_dbl, isa_nobit 237 1.1 mrg } 238 1.1 mrg }, 239 1.1 mrg { NULL, false, false, {isa_nobit}} 240 1.1 mrg }; 241 1.1 mrg 242 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa5[] = { 243 1.1 mrg { 244 1.1 mrg "nosimd", true, false, 245 1.1 mrg { 246 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 247 1.1 mrg isa_bit_crypto, isa_nobit 248 1.1 mrg } 249 1.1 mrg }, 250 1.1 mrg { 251 1.1 mrg "nofp", true, false, 252 1.1 mrg { 253 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 254 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 255 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 256 1.1 mrg } 257 1.1 mrg }, 258 1.1 mrg { NULL, false, false, {isa_nobit}} 259 1.1 mrg }; 260 1.1 mrg 261 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa7[] = { 262 1.1 mrg { 263 1.1 mrg "nosimd", true, false, 264 1.1 mrg { 265 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 266 1.1 mrg isa_bit_crypto, isa_nobit 267 1.1 mrg } 268 1.1 mrg }, 269 1.1 mrg { 270 1.1 mrg "nofp", true, false, 271 1.1 mrg { 272 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 273 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 274 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 275 1.1 mrg } 276 1.1 mrg }, 277 1.1 mrg { NULL, false, false, {isa_nobit}} 278 1.1 mrg }; 279 1.1 mrg 280 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa8[] = { 281 1.1 mrg { 282 1.1 mrg "nofp", true, false, 283 1.1 mrg { 284 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 285 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 286 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 287 1.1 mrg } 288 1.1 mrg }, 289 1.1 mrg { NULL, false, false, {isa_nobit}} 290 1.1 mrg }; 291 1.1 mrg 292 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa9[] = { 293 1.1 mrg { 294 1.1 mrg "nosimd", true, false, 295 1.1 mrg { 296 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 297 1.1 mrg isa_bit_crypto, isa_nobit 298 1.1 mrg } 299 1.1 mrg }, 300 1.1 mrg { 301 1.1 mrg "nofp", true, false, 302 1.1 mrg { 303 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 304 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 305 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 306 1.1 mrg } 307 1.1 mrg }, 308 1.1 mrg { NULL, false, false, {isa_nobit}} 309 1.1 mrg }; 310 1.1 mrg 311 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa12[] = { 312 1.1 mrg { 313 1.1 mrg "nofp", true, false, 314 1.1 mrg { 315 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 316 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 317 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 318 1.1 mrg } 319 1.1 mrg }, 320 1.1 mrg { NULL, false, false, {isa_nobit}} 321 1.1 mrg }; 322 1.1 mrg 323 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa15[] = { 324 1.1 mrg { 325 1.1 mrg "nofp", true, false, 326 1.1 mrg { 327 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 328 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 329 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 330 1.1 mrg } 331 1.1 mrg }, 332 1.1 mrg { NULL, false, false, {isa_nobit}} 333 1.1 mrg }; 334 1.1 mrg 335 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa17[] = { 336 1.1 mrg { 337 1.1 mrg "nofp", true, false, 338 1.1 mrg { 339 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 340 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 341 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 342 1.1 mrg } 343 1.1 mrg }, 344 1.1 mrg { NULL, false, false, {isa_nobit}} 345 1.1 mrg }; 346 1.1 mrg 347 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr5[] = { 348 1.1 mrg { 349 1.1 mrg "nofp.dp", true, false, 350 1.1 mrg { 351 1.1 mrg isa_bit_fp_dbl, isa_nobit 352 1.1 mrg } 353 1.1 mrg }, 354 1.1 mrg { 355 1.1 mrg "nofp", true, false, 356 1.1 mrg { 357 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 358 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 359 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 360 1.1 mrg } 361 1.1 mrg }, 362 1.1 mrg { NULL, false, false, {isa_nobit}} 363 1.1 mrg }; 364 1.1 mrg 365 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr7[] = { 366 1.1 mrg { 367 1.1 mrg "nofp.dp", true, false, 368 1.1 mrg { 369 1.1 mrg isa_bit_fp_dbl, isa_nobit 370 1.1 mrg } 371 1.1 mrg }, 372 1.1 mrg { 373 1.1 mrg "nofp", true, false, 374 1.1 mrg { 375 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 376 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 377 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 378 1.1 mrg } 379 1.1 mrg }, 380 1.1 mrg { NULL, false, false, {isa_nobit}} 381 1.1 mrg }; 382 1.1 mrg 383 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr8[] = { 384 1.1 mrg { 385 1.1 mrg "nofp.dp", true, false, 386 1.1 mrg { 387 1.1 mrg isa_bit_fp_dbl, isa_nobit 388 1.1 mrg } 389 1.1 mrg }, 390 1.1 mrg { 391 1.1 mrg "nofp", true, false, 392 1.1 mrg { 393 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 394 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 395 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 396 1.1 mrg } 397 1.1 mrg }, 398 1.1 mrg { NULL, false, false, {isa_nobit}} 399 1.1 mrg }; 400 1.1 mrg 401 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm7[] = { 402 1.1 mrg { 403 1.1 mrg "nofp.dp", true, false, 404 1.1 mrg { 405 1.1 mrg isa_bit_fp_dbl, isa_nobit 406 1.1 mrg } 407 1.1 mrg }, 408 1.1 mrg { 409 1.1 mrg "nofp", true, false, 410 1.1 mrg { 411 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 412 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 413 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 414 1.1 mrg } 415 1.1 mrg }, 416 1.1 mrg { NULL, false, false, {isa_nobit}} 417 1.1 mrg }; 418 1.1 mrg 419 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm4[] = { 420 1.1 mrg { 421 1.1 mrg "nofp", true, false, 422 1.1 mrg { 423 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 424 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 425 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 426 1.1 mrg } 427 1.1 mrg }, 428 1.1 mrg { NULL, false, false, {isa_nobit}} 429 1.1 mrg }; 430 1.1 mrg 431 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { 432 1.1 mrg { 433 1.1 mrg "nofp", true, false, 434 1.1 mrg { 435 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 436 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 437 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 438 1.1 mrg } 439 1.1 mrg }, 440 1.1 mrg { NULL, false, false, {isa_nobit}} 441 1.1 mrg }; 442 1.1 mrg 443 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { 444 1.1 mrg { 445 1.1 mrg "nofp", true, false, 446 1.1 mrg { 447 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 448 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 449 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 450 1.1 mrg } 451 1.1 mrg }, 452 1.1 mrg { NULL, false, false, {isa_nobit}} 453 1.1 mrg }; 454 1.1 mrg 455 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa32[] = { 456 1.1 mrg { 457 1.1 mrg "crypto", false, false, 458 1.1 mrg { 459 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 460 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 461 1.1 mrg isa_bit_fp_dbl, isa_nobit 462 1.1 mrg } 463 1.1 mrg }, 464 1.1 mrg { 465 1.1 mrg "nofp", true, false, 466 1.1 mrg { 467 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 468 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 469 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 470 1.1 mrg } 471 1.1 mrg }, 472 1.1 mrg { NULL, false, false, {isa_nobit}} 473 1.1 mrg }; 474 1.1 mrg 475 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa35[] = { 476 1.1 mrg { 477 1.1 mrg "crypto", false, false, 478 1.1 mrg { 479 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 480 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 481 1.1 mrg isa_bit_fp_dbl, isa_nobit 482 1.1 mrg } 483 1.1 mrg }, 484 1.1 mrg { 485 1.1 mrg "nofp", true, false, 486 1.1 mrg { 487 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 488 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 489 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 490 1.1 mrg } 491 1.1 mrg }, 492 1.1 mrg { NULL, false, false, {isa_nobit}} 493 1.1 mrg }; 494 1.1 mrg 495 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa53[] = { 496 1.1 mrg { 497 1.1 mrg "crypto", false, false, 498 1.1 mrg { 499 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 500 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 501 1.1 mrg isa_bit_fp_dbl, isa_nobit 502 1.1 mrg } 503 1.1 mrg }, 504 1.1 mrg { 505 1.1 mrg "nofp", true, false, 506 1.1 mrg { 507 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 508 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 509 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 510 1.1 mrg } 511 1.1 mrg }, 512 1.1 mrg { NULL, false, false, {isa_nobit}} 513 1.1 mrg }; 514 1.1 mrg 515 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa57[] = { 516 1.1 mrg { 517 1.1 mrg "crypto", false, false, 518 1.1 mrg { 519 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 520 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 521 1.1 mrg isa_bit_fp_dbl, isa_nobit 522 1.1 mrg } 523 1.1 mrg }, 524 1.1 mrg { NULL, false, false, {isa_nobit}} 525 1.1 mrg }; 526 1.1 mrg 527 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa72[] = { 528 1.1 mrg { 529 1.1 mrg "crypto", false, false, 530 1.1 mrg { 531 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 532 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 533 1.1 mrg isa_bit_fp_dbl, isa_nobit 534 1.1 mrg } 535 1.1 mrg }, 536 1.1 mrg { NULL, false, false, {isa_nobit}} 537 1.1 mrg }; 538 1.1 mrg 539 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73[] = { 540 1.1 mrg { 541 1.1 mrg "crypto", false, false, 542 1.1 mrg { 543 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 544 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 545 1.1 mrg isa_bit_fp_dbl, isa_nobit 546 1.1 mrg } 547 1.1 mrg }, 548 1.1 mrg { NULL, false, false, {isa_nobit}} 549 1.1 mrg }; 550 1.1 mrg 551 1.1 mrg static const cpu_arch_extension cpu_opttab_exynosm1[] = { 552 1.1 mrg { 553 1.1 mrg "crypto", false, false, 554 1.1 mrg { 555 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 556 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 557 1.1 mrg isa_bit_fp_dbl, isa_nobit 558 1.1 mrg } 559 1.1 mrg }, 560 1.1 mrg { NULL, false, false, {isa_nobit}} 561 1.1 mrg }; 562 1.1 mrg 563 1.1 mrg static const cpu_arch_extension cpu_opttab_xgene1[] = { 564 1.1 mrg { 565 1.1 mrg "crypto", false, false, 566 1.1 mrg { 567 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 568 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 569 1.1 mrg isa_bit_fp_dbl, isa_nobit 570 1.1 mrg } 571 1.1 mrg }, 572 1.1 mrg { NULL, false, false, {isa_nobit}} 573 1.1 mrg }; 574 1.1 mrg 575 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { 576 1.1 mrg { 577 1.1 mrg "crypto", false, false, 578 1.1 mrg { 579 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 580 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 581 1.1 mrg isa_bit_fp_dbl, isa_nobit 582 1.1 mrg } 583 1.1 mrg }, 584 1.1 mrg { NULL, false, false, {isa_nobit}} 585 1.1 mrg }; 586 1.1 mrg 587 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { 588 1.1 mrg { 589 1.1 mrg "crypto", false, false, 590 1.1 mrg { 591 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 592 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 593 1.1 mrg isa_bit_fp_dbl, isa_nobit 594 1.1 mrg } 595 1.1 mrg }, 596 1.1 mrg { NULL, false, false, {isa_nobit}} 597 1.1 mrg }; 598 1.1 mrg 599 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { 600 1.1 mrg { 601 1.1 mrg "crypto", false, false, 602 1.1 mrg { 603 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 604 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 605 1.1 mrg isa_bit_fp_dbl, isa_nobit 606 1.1 mrg } 607 1.1 mrg }, 608 1.1 mrg { NULL, false, false, {isa_nobit}} 609 1.1 mrg }; 610 1.1 mrg 611 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { 612 1.1 mrg { 613 1.1 mrg "crypto", false, false, 614 1.1 mrg { 615 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 616 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 617 1.1 mrg isa_bit_fp_dbl, isa_nobit 618 1.1 mrg } 619 1.1 mrg }, 620 1.1 mrg { NULL, false, false, {isa_nobit}} 621 1.1 mrg }; 622 1.1 mrg 623 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa55[] = { 624 1.1 mrg { 625 1.1 mrg "crypto", false, false, 626 1.1 mrg { 627 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 628 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 629 1.1 mrg isa_bit_fp_dbl, isa_nobit 630 1.1 mrg } 631 1.1 mrg }, 632 1.1 mrg { 633 1.1 mrg "nofp", true, false, 634 1.1 mrg { 635 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 636 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 637 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 638 1.1 mrg } 639 1.1 mrg }, 640 1.1 mrg { NULL, false, false, {isa_nobit}} 641 1.1 mrg }; 642 1.1 mrg 643 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa75[] = { 644 1.1 mrg { 645 1.1 mrg "crypto", false, false, 646 1.1 mrg { 647 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 648 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 649 1.1 mrg isa_bit_fp_dbl, isa_nobit 650 1.1 mrg } 651 1.1 mrg }, 652 1.1 mrg { NULL, false, false, {isa_nobit}} 653 1.1 mrg }; 654 1.1 mrg 655 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = { 656 1.1 mrg { 657 1.1 mrg "crypto", false, false, 658 1.1 mrg { 659 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 660 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 661 1.1 mrg isa_bit_fp_dbl, isa_nobit 662 1.1 mrg } 663 1.1 mrg }, 664 1.1 mrg { NULL, false, false, {isa_nobit}} 665 1.1 mrg }; 666 1.1 mrg 667 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm33[] = { 668 1.1 mrg { 669 1.1 mrg "nofp", true, false, 670 1.1 mrg { 671 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 672 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 673 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 674 1.1 mrg } 675 1.1 mrg }, 676 1.1 mrg { 677 1.1 mrg "nodsp", true, false, 678 1.1 mrg { 679 1.1 mrg isa_bit_armv7em, isa_nobit 680 1.1 mrg } 681 1.1 mrg }, 682 1.1 mrg { NULL, false, false, {isa_nobit}} 683 1.1 mrg }; 684 1.1 mrg 685 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr52[] = { 686 1.1 mrg { 687 1.1 mrg "nofp.dp", true, false, 688 1.1 mrg { 689 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 690 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 691 1.1 mrg } 692 1.1 mrg }, 693 1.1 mrg { NULL, false, false, {isa_nobit}} 694 1.1 mrg }; 695 1.1 mrg 696 1.1 mrg const cpu_option all_cores[] = 697 1.1 mrg { 698 1.1 mrg { 699 1.1 mrg { 700 1.1 mrg "arm2", 701 1.1 mrg NULL, 702 1.1 mrg { 703 1.1 mrg isa_bit_mode26, isa_bit_notm, isa_nobit 704 1.1 mrg } 705 1.1 mrg }, 706 1.1 mrg TARGET_ARCH_armv2 707 1.1 mrg }, 708 1.1 mrg { 709 1.1 mrg { 710 1.1 mrg "arm250", 711 1.1 mrg NULL, 712 1.1 mrg { 713 1.1 mrg isa_bit_mode26, isa_bit_notm, isa_nobit 714 1.1 mrg } 715 1.1 mrg }, 716 1.1 mrg TARGET_ARCH_armv2 717 1.1 mrg }, 718 1.1 mrg { 719 1.1 mrg { 720 1.1 mrg "arm3", 721 1.1 mrg NULL, 722 1.1 mrg { 723 1.1 mrg isa_bit_mode26, isa_bit_notm, isa_nobit 724 1.1 mrg } 725 1.1 mrg }, 726 1.1 mrg TARGET_ARCH_armv2 727 1.1 mrg }, 728 1.1 mrg { 729 1.1 mrg { 730 1.1 mrg "arm6", 731 1.1 mrg NULL, 732 1.1 mrg { 733 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 734 1.1 mrg } 735 1.1 mrg }, 736 1.1 mrg TARGET_ARCH_armv3 737 1.1 mrg }, 738 1.1 mrg { 739 1.1 mrg { 740 1.1 mrg "arm60", 741 1.1 mrg NULL, 742 1.1 mrg { 743 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 744 1.1 mrg } 745 1.1 mrg }, 746 1.1 mrg TARGET_ARCH_armv3 747 1.1 mrg }, 748 1.1 mrg { 749 1.1 mrg { 750 1.1 mrg "arm600", 751 1.1 mrg NULL, 752 1.1 mrg { 753 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 754 1.1 mrg } 755 1.1 mrg }, 756 1.1 mrg TARGET_ARCH_armv3 757 1.1 mrg }, 758 1.1 mrg { 759 1.1 mrg { 760 1.1 mrg "arm610", 761 1.1 mrg NULL, 762 1.1 mrg { 763 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 764 1.1 mrg } 765 1.1 mrg }, 766 1.1 mrg TARGET_ARCH_armv3 767 1.1 mrg }, 768 1.1 mrg { 769 1.1 mrg { 770 1.1 mrg "arm620", 771 1.1 mrg NULL, 772 1.1 mrg { 773 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 774 1.1 mrg } 775 1.1 mrg }, 776 1.1 mrg TARGET_ARCH_armv3 777 1.1 mrg }, 778 1.1 mrg { 779 1.1 mrg { 780 1.1 mrg "arm7", 781 1.1 mrg NULL, 782 1.1 mrg { 783 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 784 1.1 mrg } 785 1.1 mrg }, 786 1.1 mrg TARGET_ARCH_armv3 787 1.1 mrg }, 788 1.1 mrg { 789 1.1 mrg { 790 1.1 mrg "arm7d", 791 1.1 mrg NULL, 792 1.1 mrg { 793 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 794 1.1 mrg } 795 1.1 mrg }, 796 1.1 mrg TARGET_ARCH_armv3 797 1.1 mrg }, 798 1.1 mrg { 799 1.1 mrg { 800 1.1 mrg "arm7di", 801 1.1 mrg NULL, 802 1.1 mrg { 803 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 804 1.1 mrg } 805 1.1 mrg }, 806 1.1 mrg TARGET_ARCH_armv3 807 1.1 mrg }, 808 1.1 mrg { 809 1.1 mrg { 810 1.1 mrg "arm70", 811 1.1 mrg NULL, 812 1.1 mrg { 813 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 814 1.1 mrg } 815 1.1 mrg }, 816 1.1 mrg TARGET_ARCH_armv3 817 1.1 mrg }, 818 1.1 mrg { 819 1.1 mrg { 820 1.1 mrg "arm700", 821 1.1 mrg NULL, 822 1.1 mrg { 823 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 824 1.1 mrg } 825 1.1 mrg }, 826 1.1 mrg TARGET_ARCH_armv3 827 1.1 mrg }, 828 1.1 mrg { 829 1.1 mrg { 830 1.1 mrg "arm700i", 831 1.1 mrg NULL, 832 1.1 mrg { 833 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 834 1.1 mrg } 835 1.1 mrg }, 836 1.1 mrg TARGET_ARCH_armv3 837 1.1 mrg }, 838 1.1 mrg { 839 1.1 mrg { 840 1.1 mrg "arm710", 841 1.1 mrg NULL, 842 1.1 mrg { 843 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 844 1.1 mrg } 845 1.1 mrg }, 846 1.1 mrg TARGET_ARCH_armv3 847 1.1 mrg }, 848 1.1 mrg { 849 1.1 mrg { 850 1.1 mrg "arm720", 851 1.1 mrg NULL, 852 1.1 mrg { 853 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 854 1.1 mrg } 855 1.1 mrg }, 856 1.1 mrg TARGET_ARCH_armv3 857 1.1 mrg }, 858 1.1 mrg { 859 1.1 mrg { 860 1.1 mrg "arm710c", 861 1.1 mrg NULL, 862 1.1 mrg { 863 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 864 1.1 mrg } 865 1.1 mrg }, 866 1.1 mrg TARGET_ARCH_armv3 867 1.1 mrg }, 868 1.1 mrg { 869 1.1 mrg { 870 1.1 mrg "arm7100", 871 1.1 mrg NULL, 872 1.1 mrg { 873 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 874 1.1 mrg } 875 1.1 mrg }, 876 1.1 mrg TARGET_ARCH_armv3 877 1.1 mrg }, 878 1.1 mrg { 879 1.1 mrg { 880 1.1 mrg "arm7500", 881 1.1 mrg NULL, 882 1.1 mrg { 883 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 884 1.1 mrg } 885 1.1 mrg }, 886 1.1 mrg TARGET_ARCH_armv3 887 1.1 mrg }, 888 1.1 mrg { 889 1.1 mrg { 890 1.1 mrg "arm7500fe", 891 1.1 mrg NULL, 892 1.1 mrg { 893 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 894 1.1 mrg } 895 1.1 mrg }, 896 1.1 mrg TARGET_ARCH_armv3 897 1.1 mrg }, 898 1.1 mrg { 899 1.1 mrg { 900 1.1 mrg "arm7m", 901 1.1 mrg NULL, 902 1.1 mrg { 903 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, 904 1.1 mrg isa_nobit 905 1.1 mrg } 906 1.1 mrg }, 907 1.1 mrg TARGET_ARCH_armv3m 908 1.1 mrg }, 909 1.1 mrg { 910 1.1 mrg { 911 1.1 mrg "arm7dm", 912 1.1 mrg NULL, 913 1.1 mrg { 914 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, 915 1.1 mrg isa_nobit 916 1.1 mrg } 917 1.1 mrg }, 918 1.1 mrg TARGET_ARCH_armv3m 919 1.1 mrg }, 920 1.1 mrg { 921 1.1 mrg { 922 1.1 mrg "arm7dmi", 923 1.1 mrg NULL, 924 1.1 mrg { 925 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, 926 1.1 mrg isa_nobit 927 1.1 mrg } 928 1.1 mrg }, 929 1.1 mrg TARGET_ARCH_armv3m 930 1.1 mrg }, 931 1.1 mrg { 932 1.1 mrg { 933 1.1 mrg "arm8", 934 1.1 mrg NULL, 935 1.1 mrg { 936 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 937 1.1 mrg isa_bit_armv3m, isa_nobit 938 1.1 mrg } 939 1.1 mrg }, 940 1.1 mrg TARGET_ARCH_armv4 941 1.1 mrg }, 942 1.1 mrg { 943 1.1 mrg { 944 1.1 mrg "arm810", 945 1.1 mrg NULL, 946 1.1 mrg { 947 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 948 1.1 mrg isa_bit_armv3m, isa_nobit 949 1.1 mrg } 950 1.1 mrg }, 951 1.1 mrg TARGET_ARCH_armv4 952 1.1 mrg }, 953 1.1 mrg { 954 1.1 mrg { 955 1.1 mrg "strongarm", 956 1.1 mrg NULL, 957 1.1 mrg { 958 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 959 1.1 mrg isa_bit_armv3m, isa_nobit 960 1.1 mrg } 961 1.1 mrg }, 962 1.1 mrg TARGET_ARCH_armv4 963 1.1 mrg }, 964 1.1 mrg { 965 1.1 mrg { 966 1.1 mrg "strongarm110", 967 1.1 mrg NULL, 968 1.1 mrg { 969 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 970 1.1 mrg isa_bit_armv3m, isa_nobit 971 1.1 mrg } 972 1.1 mrg }, 973 1.1 mrg TARGET_ARCH_armv4 974 1.1 mrg }, 975 1.1 mrg { 976 1.1 mrg { 977 1.1 mrg "strongarm1100", 978 1.1 mrg NULL, 979 1.1 mrg { 980 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 981 1.1 mrg isa_bit_armv3m, isa_nobit 982 1.1 mrg } 983 1.1 mrg }, 984 1.1 mrg TARGET_ARCH_armv4 985 1.1 mrg }, 986 1.1 mrg { 987 1.1 mrg { 988 1.1 mrg "strongarm1110", 989 1.1 mrg NULL, 990 1.1 mrg { 991 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 992 1.1 mrg isa_bit_armv3m, isa_nobit 993 1.1 mrg } 994 1.1 mrg }, 995 1.1 mrg TARGET_ARCH_armv4 996 1.1 mrg }, 997 1.1 mrg { 998 1.1 mrg { 999 1.1 mrg "fa526", 1000 1.1 mrg NULL, 1001 1.1 mrg { 1002 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1003 1.1 mrg isa_bit_armv3m, isa_nobit 1004 1.1 mrg } 1005 1.1 mrg }, 1006 1.1 mrg TARGET_ARCH_armv4 1007 1.1 mrg }, 1008 1.1 mrg { 1009 1.1 mrg { 1010 1.1 mrg "fa626", 1011 1.1 mrg NULL, 1012 1.1 mrg { 1013 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1014 1.1 mrg isa_bit_armv3m, isa_nobit 1015 1.1 mrg } 1016 1.1 mrg }, 1017 1.1 mrg TARGET_ARCH_armv4 1018 1.1 mrg }, 1019 1.1 mrg { 1020 1.1 mrg { 1021 1.1 mrg "arm7tdmi", 1022 1.1 mrg NULL, 1023 1.1 mrg { 1024 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1025 1.1 mrg isa_bit_armv3m, isa_nobit 1026 1.1 mrg } 1027 1.1 mrg }, 1028 1.1 mrg TARGET_ARCH_armv4t 1029 1.1 mrg }, 1030 1.1 mrg { 1031 1.1 mrg { 1032 1.1 mrg "arm7tdmi-s", 1033 1.1 mrg NULL, 1034 1.1 mrg { 1035 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1036 1.1 mrg isa_bit_armv3m, isa_nobit 1037 1.1 mrg } 1038 1.1 mrg }, 1039 1.1 mrg TARGET_ARCH_armv4t 1040 1.1 mrg }, 1041 1.1 mrg { 1042 1.1 mrg { 1043 1.1 mrg "arm710t", 1044 1.1 mrg NULL, 1045 1.1 mrg { 1046 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1047 1.1 mrg isa_bit_armv3m, isa_nobit 1048 1.1 mrg } 1049 1.1 mrg }, 1050 1.1 mrg TARGET_ARCH_armv4t 1051 1.1 mrg }, 1052 1.1 mrg { 1053 1.1 mrg { 1054 1.1 mrg "arm720t", 1055 1.1 mrg NULL, 1056 1.1 mrg { 1057 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1058 1.1 mrg isa_bit_armv3m, isa_nobit 1059 1.1 mrg } 1060 1.1 mrg }, 1061 1.1 mrg TARGET_ARCH_armv4t 1062 1.1 mrg }, 1063 1.1 mrg { 1064 1.1 mrg { 1065 1.1 mrg "arm740t", 1066 1.1 mrg NULL, 1067 1.1 mrg { 1068 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1069 1.1 mrg isa_bit_armv3m, isa_nobit 1070 1.1 mrg } 1071 1.1 mrg }, 1072 1.1 mrg TARGET_ARCH_armv4t 1073 1.1 mrg }, 1074 1.1 mrg { 1075 1.1 mrg { 1076 1.1 mrg "arm9", 1077 1.1 mrg NULL, 1078 1.1 mrg { 1079 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1080 1.1 mrg isa_bit_armv3m, isa_nobit 1081 1.1 mrg } 1082 1.1 mrg }, 1083 1.1 mrg TARGET_ARCH_armv4t 1084 1.1 mrg }, 1085 1.1 mrg { 1086 1.1 mrg { 1087 1.1 mrg "arm9tdmi", 1088 1.1 mrg NULL, 1089 1.1 mrg { 1090 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1091 1.1 mrg isa_bit_armv3m, isa_nobit 1092 1.1 mrg } 1093 1.1 mrg }, 1094 1.1 mrg TARGET_ARCH_armv4t 1095 1.1 mrg }, 1096 1.1 mrg { 1097 1.1 mrg { 1098 1.1 mrg "arm920", 1099 1.1 mrg NULL, 1100 1.1 mrg { 1101 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1102 1.1 mrg isa_bit_armv3m, isa_nobit 1103 1.1 mrg } 1104 1.1 mrg }, 1105 1.1 mrg TARGET_ARCH_armv4t 1106 1.1 mrg }, 1107 1.1 mrg { 1108 1.1 mrg { 1109 1.1 mrg "arm920t", 1110 1.1 mrg NULL, 1111 1.1 mrg { 1112 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1113 1.1 mrg isa_bit_armv3m, isa_nobit 1114 1.1 mrg } 1115 1.1 mrg }, 1116 1.1 mrg TARGET_ARCH_armv4t 1117 1.1 mrg }, 1118 1.1 mrg { 1119 1.1 mrg { 1120 1.1 mrg "arm922t", 1121 1.1 mrg NULL, 1122 1.1 mrg { 1123 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1124 1.1 mrg isa_bit_armv3m, isa_nobit 1125 1.1 mrg } 1126 1.1 mrg }, 1127 1.1 mrg TARGET_ARCH_armv4t 1128 1.1 mrg }, 1129 1.1 mrg { 1130 1.1 mrg { 1131 1.1 mrg "arm940t", 1132 1.1 mrg NULL, 1133 1.1 mrg { 1134 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1135 1.1 mrg isa_bit_armv3m, isa_nobit 1136 1.1 mrg } 1137 1.1 mrg }, 1138 1.1 mrg TARGET_ARCH_armv4t 1139 1.1 mrg }, 1140 1.1 mrg { 1141 1.1 mrg { 1142 1.1 mrg "ep9312", 1143 1.1 mrg NULL, 1144 1.1 mrg { 1145 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 1146 1.1 mrg isa_bit_armv3m, isa_nobit 1147 1.1 mrg } 1148 1.1 mrg }, 1149 1.1 mrg TARGET_ARCH_armv4t 1150 1.1 mrg }, 1151 1.1 mrg { 1152 1.1 mrg { 1153 1.1 mrg "arm10tdmi", 1154 1.1 mrg NULL, 1155 1.1 mrg { 1156 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, 1157 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 1158 1.1 mrg } 1159 1.1 mrg }, 1160 1.1 mrg TARGET_ARCH_armv5t 1161 1.1 mrg }, 1162 1.1 mrg { 1163 1.1 mrg { 1164 1.1 mrg "arm1020t", 1165 1.1 mrg NULL, 1166 1.1 mrg { 1167 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, 1168 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 1169 1.1 mrg } 1170 1.1 mrg }, 1171 1.1 mrg TARGET_ARCH_armv5t 1172 1.1 mrg }, 1173 1.1 mrg { 1174 1.1 mrg { 1175 1.1 mrg "arm9e", 1176 1.1 mrg cpu_opttab_arm9e, 1177 1.1 mrg { 1178 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1179 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1180 1.1 mrg isa_bit_armv3m, isa_nobit 1181 1.1 mrg } 1182 1.1 mrg }, 1183 1.1 mrg TARGET_ARCH_armv5te 1184 1.1 mrg }, 1185 1.1 mrg { 1186 1.1 mrg { 1187 1.1 mrg "arm946e-s", 1188 1.1 mrg cpu_opttab_arm946es, 1189 1.1 mrg { 1190 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1191 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1192 1.1 mrg isa_bit_armv3m, isa_nobit 1193 1.1 mrg } 1194 1.1 mrg }, 1195 1.1 mrg TARGET_ARCH_armv5te 1196 1.1 mrg }, 1197 1.1 mrg { 1198 1.1 mrg { 1199 1.1 mrg "arm966e-s", 1200 1.1 mrg cpu_opttab_arm966es, 1201 1.1 mrg { 1202 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1203 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1204 1.1 mrg isa_bit_armv3m, isa_nobit 1205 1.1 mrg } 1206 1.1 mrg }, 1207 1.1 mrg TARGET_ARCH_armv5te 1208 1.1 mrg }, 1209 1.1 mrg { 1210 1.1 mrg { 1211 1.1 mrg "arm968e-s", 1212 1.1 mrg cpu_opttab_arm968es, 1213 1.1 mrg { 1214 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1215 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1216 1.1 mrg isa_bit_armv3m, isa_nobit 1217 1.1 mrg } 1218 1.1 mrg }, 1219 1.1 mrg TARGET_ARCH_armv5te 1220 1.1 mrg }, 1221 1.1 mrg { 1222 1.1 mrg { 1223 1.1 mrg "arm10e", 1224 1.1 mrg cpu_opttab_arm10e, 1225 1.1 mrg { 1226 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1227 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1228 1.1 mrg isa_bit_armv3m, isa_nobit 1229 1.1 mrg } 1230 1.1 mrg }, 1231 1.1 mrg TARGET_ARCH_armv5te 1232 1.1 mrg }, 1233 1.1 mrg { 1234 1.1 mrg { 1235 1.1 mrg "arm1020e", 1236 1.1 mrg cpu_opttab_arm1020e, 1237 1.1 mrg { 1238 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1239 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1240 1.1 mrg isa_bit_armv3m, isa_nobit 1241 1.1 mrg } 1242 1.1 mrg }, 1243 1.1 mrg TARGET_ARCH_armv5te 1244 1.1 mrg }, 1245 1.1 mrg { 1246 1.1 mrg { 1247 1.1 mrg "arm1022e", 1248 1.1 mrg cpu_opttab_arm1022e, 1249 1.1 mrg { 1250 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1251 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1252 1.1 mrg isa_bit_armv3m, isa_nobit 1253 1.1 mrg } 1254 1.1 mrg }, 1255 1.1 mrg TARGET_ARCH_armv5te 1256 1.1 mrg }, 1257 1.1 mrg { 1258 1.1 mrg { 1259 1.1 mrg "xscale", 1260 1.1 mrg NULL, 1261 1.1 mrg { 1262 1.1 mrg isa_bit_armv5e, isa_bit_xscale, isa_bit_thumb, isa_bit_armv4, 1263 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, 1264 1.1 mrg isa_nobit 1265 1.1 mrg } 1266 1.1 mrg }, 1267 1.1 mrg TARGET_ARCH_armv5te 1268 1.1 mrg }, 1269 1.1 mrg { 1270 1.1 mrg { 1271 1.1 mrg "iwmmxt", 1272 1.1 mrg NULL, 1273 1.1 mrg { 1274 1.1 mrg isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb, 1275 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm, 1276 1.1 mrg isa_bit_armv3m, isa_nobit 1277 1.1 mrg } 1278 1.1 mrg }, 1279 1.1 mrg TARGET_ARCH_iwmmxt 1280 1.1 mrg }, 1281 1.1 mrg { 1282 1.1 mrg { 1283 1.1 mrg "iwmmxt2", 1284 1.1 mrg NULL, 1285 1.1 mrg { 1286 1.1 mrg isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb, 1287 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_iwmmxt2, 1288 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 1289 1.1 mrg } 1290 1.1 mrg }, 1291 1.1 mrg TARGET_ARCH_iwmmxt2 1292 1.1 mrg }, 1293 1.1 mrg { 1294 1.1 mrg { 1295 1.1 mrg "fa606te", 1296 1.1 mrg NULL, 1297 1.1 mrg { 1298 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, 1299 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit 1300 1.1 mrg } 1301 1.1 mrg }, 1302 1.1 mrg TARGET_ARCH_armv5te 1303 1.1 mrg }, 1304 1.1 mrg { 1305 1.1 mrg { 1306 1.1 mrg "fa626te", 1307 1.1 mrg NULL, 1308 1.1 mrg { 1309 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, 1310 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit 1311 1.1 mrg } 1312 1.1 mrg }, 1313 1.1 mrg TARGET_ARCH_armv5te 1314 1.1 mrg }, 1315 1.1 mrg { 1316 1.1 mrg { 1317 1.1 mrg "fmp626", 1318 1.1 mrg NULL, 1319 1.1 mrg { 1320 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, 1321 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit 1322 1.1 mrg } 1323 1.1 mrg }, 1324 1.1 mrg TARGET_ARCH_armv5te 1325 1.1 mrg }, 1326 1.1 mrg { 1327 1.1 mrg { 1328 1.1 mrg "fa726te", 1329 1.1 mrg NULL, 1330 1.1 mrg { 1331 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, 1332 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit 1333 1.1 mrg } 1334 1.1 mrg }, 1335 1.1 mrg TARGET_ARCH_armv5te 1336 1.1 mrg }, 1337 1.1 mrg { 1338 1.1 mrg { 1339 1.1 mrg "arm926ej-s", 1340 1.1 mrg cpu_opttab_arm926ejs, 1341 1.1 mrg { 1342 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1343 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1344 1.1 mrg isa_bit_armv3m, isa_nobit 1345 1.1 mrg } 1346 1.1 mrg }, 1347 1.1 mrg TARGET_ARCH_armv5tej 1348 1.1 mrg }, 1349 1.1 mrg { 1350 1.1 mrg { 1351 1.1 mrg "arm1026ej-s", 1352 1.1 mrg cpu_opttab_arm1026ejs, 1353 1.1 mrg { 1354 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, 1355 1.1 mrg isa_bit_armv5, isa_bit_mode32, isa_bit_notm, isa_bit_fp_dbl, 1356 1.1 mrg isa_bit_armv3m, isa_nobit 1357 1.1 mrg } 1358 1.1 mrg }, 1359 1.1 mrg TARGET_ARCH_armv5tej 1360 1.1 mrg }, 1361 1.1 mrg { 1362 1.1 mrg { 1363 1.1 mrg "arm1136j-s", 1364 1.1 mrg NULL, 1365 1.1 mrg { 1366 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1367 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm, 1368 1.1 mrg isa_bit_armv3m, isa_nobit 1369 1.1 mrg } 1370 1.1 mrg }, 1371 1.1 mrg TARGET_ARCH_armv6j 1372 1.1 mrg }, 1373 1.1 mrg { 1374 1.1 mrg { 1375 1.1 mrg "arm1136jf-s", 1376 1.1 mrg NULL, 1377 1.1 mrg { 1378 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 1379 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, 1380 1.1 mrg isa_bit_notm, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit 1381 1.1 mrg } 1382 1.1 mrg }, 1383 1.1 mrg TARGET_ARCH_armv6j 1384 1.1 mrg }, 1385 1.1 mrg { 1386 1.1 mrg { 1387 1.1 mrg "arm1176jz-s", 1388 1.1 mrg NULL, 1389 1.1 mrg { 1390 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1391 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32, 1392 1.1 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit 1393 1.1 mrg } 1394 1.1 mrg }, 1395 1.1 mrg TARGET_ARCH_armv6kz 1396 1.1 mrg }, 1397 1.1 mrg { 1398 1.1 mrg { 1399 1.1 mrg "arm1176jzf-s", 1400 1.1 mrg NULL, 1401 1.1 mrg { 1402 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 1403 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, 1404 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, 1405 1.1 mrg isa_bit_armv3m, isa_nobit 1406 1.1 mrg } 1407 1.1 mrg }, 1408 1.1 mrg TARGET_ARCH_armv6kz 1409 1.1 mrg }, 1410 1.1 mrg { 1411 1.1 mrg { 1412 1.1 mrg "mpcorenovfp", 1413 1.1 mrg NULL, 1414 1.1 mrg { 1415 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1416 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm, 1417 1.1 mrg isa_bit_armv6k, isa_bit_armv3m, isa_nobit 1418 1.1 mrg } 1419 1.1 mrg }, 1420 1.1 mrg TARGET_ARCH_armv6k 1421 1.1 mrg }, 1422 1.1 mrg { 1423 1.1 mrg { 1424 1.1 mrg "mpcore", 1425 1.1 mrg NULL, 1426 1.1 mrg { 1427 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 1428 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, 1429 1.1 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m, 1430 1.1 mrg isa_nobit 1431 1.1 mrg } 1432 1.1 mrg }, 1433 1.1 mrg TARGET_ARCH_armv6k 1434 1.1 mrg }, 1435 1.1 mrg { 1436 1.1 mrg { 1437 1.1 mrg "arm1156t2-s", 1438 1.1 mrg NULL, 1439 1.1 mrg { 1440 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1441 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_thumb2, 1442 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 1443 1.1 mrg } 1444 1.1 mrg }, 1445 1.1 mrg TARGET_ARCH_armv6t2 1446 1.1 mrg }, 1447 1.1 mrg { 1448 1.1 mrg { 1449 1.1 mrg "arm1156t2f-s", 1450 1.1 mrg NULL, 1451 1.1 mrg { 1452 1.1 mrg isa_bit_vfpv2, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 1453 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, 1454 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp_dbl, isa_bit_armv3m, 1455 1.1 mrg isa_nobit 1456 1.1 mrg } 1457 1.1 mrg }, 1458 1.1 mrg TARGET_ARCH_armv6t2 1459 1.1 mrg }, 1460 1.1 mrg { 1461 1.1 mrg { 1462 1.1 mrg "cortex-m1", 1463 1.1 mrg NULL, 1464 1.1 mrg { 1465 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1466 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 1467 1.1 mrg isa_nobit 1468 1.1 mrg } 1469 1.1 mrg }, 1470 1.1 mrg TARGET_ARCH_armv6s_m 1471 1.1 mrg }, 1472 1.1 mrg { 1473 1.1 mrg { 1474 1.1 mrg "cortex-m0", 1475 1.1 mrg NULL, 1476 1.1 mrg { 1477 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1478 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 1479 1.1 mrg isa_nobit 1480 1.1 mrg } 1481 1.1 mrg }, 1482 1.1 mrg TARGET_ARCH_armv6s_m 1483 1.1 mrg }, 1484 1.1 mrg { 1485 1.1 mrg { 1486 1.1 mrg "cortex-m0plus", 1487 1.1 mrg NULL, 1488 1.1 mrg { 1489 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1490 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 1491 1.1 mrg isa_nobit 1492 1.1 mrg } 1493 1.1 mrg }, 1494 1.1 mrg TARGET_ARCH_armv6s_m 1495 1.1 mrg }, 1496 1.1 mrg { 1497 1.1 mrg { 1498 1.1 mrg "cortex-m1.small-multiply", 1499 1.1 mrg NULL, 1500 1.1 mrg { 1501 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1502 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 1503 1.1 mrg isa_nobit 1504 1.1 mrg } 1505 1.1 mrg }, 1506 1.1 mrg TARGET_ARCH_armv6s_m 1507 1.1 mrg }, 1508 1.1 mrg { 1509 1.1 mrg { 1510 1.1 mrg "cortex-m0.small-multiply", 1511 1.1 mrg NULL, 1512 1.1 mrg { 1513 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1514 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 1515 1.1 mrg isa_nobit 1516 1.1 mrg } 1517 1.1 mrg }, 1518 1.1 mrg TARGET_ARCH_armv6s_m 1519 1.1 mrg }, 1520 1.1 mrg { 1521 1.1 mrg { 1522 1.1 mrg "cortex-m0plus.small-multiply", 1523 1.1 mrg NULL, 1524 1.1 mrg { 1525 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1526 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 1527 1.1 mrg isa_nobit 1528 1.1 mrg } 1529 1.1 mrg }, 1530 1.1 mrg TARGET_ARCH_armv6s_m 1531 1.1 mrg }, 1532 1.1 mrg { 1533 1.1 mrg { 1534 1.1 mrg "generic-armv7-a", 1535 1.1 mrg cpu_opttab_genericv7a, 1536 1.1 mrg { 1537 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb, 1538 1.1 mrg isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 1539 1.1 mrg isa_bit_armv7, isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, 1540 1.1 mrg isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit 1541 1.1 mrg } 1542 1.1 mrg }, 1543 1.1 mrg TARGET_ARCH_armv7_a 1544 1.1 mrg }, 1545 1.1 mrg { 1546 1.1 mrg { 1547 1.1 mrg "cortex-a5", 1548 1.1 mrg cpu_opttab_cortexa5, 1549 1.1 mrg { 1550 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb, 1551 1.1 mrg isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon, 1552 1.1 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32, 1553 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1554 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1555 1.1 mrg isa_nobit 1556 1.1 mrg } 1557 1.1 mrg }, 1558 1.1 mrg TARGET_ARCH_armv7_a 1559 1.1 mrg }, 1560 1.1 mrg { 1561 1.1 mrg { 1562 1.1 mrg "cortex-a7", 1563 1.1 mrg cpu_opttab_cortexa7, 1564 1.1 mrg { 1565 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1566 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1567 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1568 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 1569 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1570 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1571 1.1 mrg isa_nobit 1572 1.1 mrg } 1573 1.1 mrg }, 1574 1.1 mrg TARGET_ARCH_armv7ve 1575 1.1 mrg }, 1576 1.1 mrg { 1577 1.1 mrg { 1578 1.1 mrg "cortex-a8", 1579 1.1 mrg cpu_opttab_cortexa8, 1580 1.1 mrg { 1581 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb, 1582 1.1 mrg isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon, 1583 1.1 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32, 1584 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, 1585 1.1 mrg isa_bit_sec, isa_bit_armv3m, isa_nobit 1586 1.1 mrg } 1587 1.1 mrg }, 1588 1.1 mrg TARGET_ARCH_armv7_a 1589 1.1 mrg }, 1590 1.1 mrg { 1591 1.1 mrg { 1592 1.1 mrg "cortex-a9", 1593 1.1 mrg cpu_opttab_cortexa9, 1594 1.1 mrg { 1595 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb, 1596 1.1 mrg isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_neon, 1597 1.1 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_mode32, 1598 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1599 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1600 1.1 mrg isa_nobit 1601 1.1 mrg } 1602 1.1 mrg }, 1603 1.1 mrg TARGET_ARCH_armv7_a 1604 1.1 mrg }, 1605 1.1 mrg { 1606 1.1 mrg { 1607 1.1 mrg "cortex-a12", 1608 1.1 mrg cpu_opttab_cortexa12, 1609 1.1 mrg { 1610 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1611 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1612 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1613 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 1614 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1615 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1616 1.1 mrg isa_nobit 1617 1.1 mrg } 1618 1.1 mrg }, 1619 1.1 mrg TARGET_ARCH_armv7ve 1620 1.1 mrg }, 1621 1.1 mrg { 1622 1.1 mrg { 1623 1.1 mrg "cortex-a15", 1624 1.1 mrg cpu_opttab_cortexa15, 1625 1.1 mrg { 1626 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1627 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1628 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1629 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 1630 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1631 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1632 1.1 mrg isa_nobit 1633 1.1 mrg } 1634 1.1 mrg }, 1635 1.1 mrg TARGET_ARCH_armv7ve 1636 1.1 mrg }, 1637 1.1 mrg { 1638 1.1 mrg { 1639 1.1 mrg "cortex-a17", 1640 1.1 mrg cpu_opttab_cortexa17, 1641 1.1 mrg { 1642 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1643 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1644 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1645 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 1646 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1647 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1648 1.1 mrg isa_nobit 1649 1.1 mrg } 1650 1.1 mrg }, 1651 1.1 mrg TARGET_ARCH_armv7ve 1652 1.1 mrg }, 1653 1.1 mrg { 1654 1.1 mrg { 1655 1.1 mrg "cortex-r4", 1656 1.1 mrg NULL, 1657 1.1 mrg { 1658 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1659 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 1660 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, 1661 1.1 mrg isa_bit_armv3m, isa_nobit 1662 1.1 mrg } 1663 1.1 mrg }, 1664 1.1 mrg TARGET_ARCH_armv7_r 1665 1.1 mrg }, 1666 1.1 mrg { 1667 1.1 mrg { 1668 1.1 mrg "cortex-r4f", 1669 1.1 mrg NULL, 1670 1.1 mrg { 1671 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5e, isa_bit_thumb, 1672 1.1 mrg isa_bit_be8, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 1673 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, 1674 1.1 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_armv3m, 1675 1.1 mrg isa_nobit 1676 1.1 mrg } 1677 1.1 mrg }, 1678 1.1 mrg TARGET_ARCH_armv7_r 1679 1.1 mrg }, 1680 1.1 mrg { 1681 1.1 mrg { 1682 1.1 mrg "cortex-r5", 1683 1.1 mrg cpu_opttab_cortexr5, 1684 1.1 mrg { 1685 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e, 1686 1.1 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5, 1687 1.1 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, 1688 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, 1689 1.1 mrg isa_bit_armv3m, isa_nobit 1690 1.1 mrg } 1691 1.1 mrg }, 1692 1.1 mrg TARGET_ARCH_armv7_r 1693 1.1 mrg }, 1694 1.1 mrg { 1695 1.1 mrg { 1696 1.1 mrg "cortex-r7", 1697 1.1 mrg cpu_opttab_cortexr7, 1698 1.1 mrg { 1699 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e, 1700 1.1 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5, 1701 1.1 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, 1702 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1703 1.1 mrg isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit 1704 1.1 mrg } 1705 1.1 mrg }, 1706 1.1 mrg TARGET_ARCH_armv7_r 1707 1.1 mrg }, 1708 1.1 mrg { 1709 1.1 mrg { 1710 1.1 mrg "cortex-r8", 1711 1.1 mrg cpu_opttab_cortexr8, 1712 1.1 mrg { 1713 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5e, 1714 1.1 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5, 1715 1.1 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, 1716 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1717 1.1 mrg isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit 1718 1.1 mrg } 1719 1.1 mrg }, 1720 1.1 mrg TARGET_ARCH_armv7_r 1721 1.1 mrg }, 1722 1.1 mrg { 1723 1.1 mrg { 1724 1.1 mrg "cortex-m7", 1725 1.1 mrg cpu_opttab_cortexm7, 1726 1.1 mrg { 1727 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e, 1728 1.1 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5, 1729 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5, 1730 1.1 mrg isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_mode32, isa_bit_thumb2, 1731 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_bit_armv3m, isa_nobit 1732 1.1 mrg } 1733 1.1 mrg }, 1734 1.1 mrg TARGET_ARCH_armv7e_m 1735 1.1 mrg }, 1736 1.1 mrg { 1737 1.1 mrg { 1738 1.1 mrg "cortex-m4", 1739 1.1 mrg cpu_opttab_cortexm4, 1740 1.1 mrg { 1741 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e, 1742 1.1 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5, 1743 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv, 1744 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_fp16conv, isa_bit_armv3m, 1745 1.1 mrg isa_nobit 1746 1.1 mrg } 1747 1.1 mrg }, 1748 1.1 mrg TARGET_ARCH_armv7e_m 1749 1.1 mrg }, 1750 1.1 mrg { 1751 1.1 mrg { 1752 1.1 mrg "cortex-m3", 1753 1.1 mrg NULL, 1754 1.1 mrg { 1755 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8, 1756 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, 1757 1.1 mrg isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m, 1758 1.1 mrg isa_nobit 1759 1.1 mrg } 1760 1.1 mrg }, 1761 1.1 mrg TARGET_ARCH_armv7_m 1762 1.1 mrg }, 1763 1.1 mrg { 1764 1.1 mrg { 1765 1.1 mrg "marvell-pj4", 1766 1.1 mrg NULL, 1767 1.1 mrg { 1768 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 1769 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32, 1770 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp, 1771 1.1 mrg isa_bit_sec, isa_bit_armv3m, isa_nobit 1772 1.1 mrg } 1773 1.1 mrg }, 1774 1.1 mrg TARGET_ARCH_armv7_a 1775 1.1 mrg }, 1776 1.1 mrg { 1777 1.1 mrg { 1778 1.1 mrg "cortex-a15.cortex-a7", 1779 1.1 mrg cpu_opttab_cortexa15cortexa7, 1780 1.1 mrg { 1781 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1782 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1783 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1784 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 1785 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1786 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1787 1.1 mrg isa_nobit 1788 1.1 mrg } 1789 1.1 mrg }, 1790 1.1 mrg TARGET_ARCH_armv7ve 1791 1.1 mrg }, 1792 1.1 mrg { 1793 1.1 mrg { 1794 1.1 mrg "cortex-a17.cortex-a7", 1795 1.1 mrg cpu_opttab_cortexa17cortexa7, 1796 1.1 mrg { 1797 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1798 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1799 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1800 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 1801 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, 1802 1.1 mrg isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, 1803 1.1 mrg isa_nobit 1804 1.1 mrg } 1805 1.1 mrg }, 1806 1.1 mrg TARGET_ARCH_armv7ve 1807 1.1 mrg }, 1808 1.1 mrg { 1809 1.1 mrg { 1810 1.1 mrg "cortex-a32", 1811 1.1 mrg cpu_opttab_cortexa32, 1812 1.1 mrg { 1813 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1814 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1815 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1816 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1817 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1818 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1819 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1820 1.1 mrg } 1821 1.1 mrg }, 1822 1.1 mrg TARGET_ARCH_armv8_a 1823 1.1 mrg }, 1824 1.1 mrg { 1825 1.1 mrg { 1826 1.1 mrg "cortex-a35", 1827 1.1 mrg cpu_opttab_cortexa35, 1828 1.1 mrg { 1829 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1830 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1831 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1832 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1833 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1834 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1835 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1836 1.1 mrg } 1837 1.1 mrg }, 1838 1.1 mrg TARGET_ARCH_armv8_a 1839 1.1 mrg }, 1840 1.1 mrg { 1841 1.1 mrg { 1842 1.1 mrg "cortex-a53", 1843 1.1 mrg cpu_opttab_cortexa53, 1844 1.1 mrg { 1845 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1846 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1847 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1848 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1849 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1850 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1851 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1852 1.1 mrg } 1853 1.1 mrg }, 1854 1.1 mrg TARGET_ARCH_armv8_a 1855 1.1 mrg }, 1856 1.1 mrg { 1857 1.1 mrg { 1858 1.1 mrg "cortex-a57", 1859 1.1 mrg cpu_opttab_cortexa57, 1860 1.1 mrg { 1861 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1862 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1863 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1864 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1865 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1866 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1867 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1868 1.1 mrg } 1869 1.1 mrg }, 1870 1.1 mrg TARGET_ARCH_armv8_a 1871 1.1 mrg }, 1872 1.1 mrg { 1873 1.1 mrg { 1874 1.1 mrg "cortex-a72", 1875 1.1 mrg cpu_opttab_cortexa72, 1876 1.1 mrg { 1877 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1878 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1879 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1880 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1881 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1882 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1883 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1884 1.1 mrg } 1885 1.1 mrg }, 1886 1.1 mrg TARGET_ARCH_armv8_a 1887 1.1 mrg }, 1888 1.1 mrg { 1889 1.1 mrg { 1890 1.1 mrg "cortex-a73", 1891 1.1 mrg cpu_opttab_cortexa73, 1892 1.1 mrg { 1893 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1894 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1895 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1896 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1897 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1898 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1899 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1900 1.1 mrg } 1901 1.1 mrg }, 1902 1.1 mrg TARGET_ARCH_armv8_a 1903 1.1 mrg }, 1904 1.1 mrg { 1905 1.1 mrg { 1906 1.1 mrg "exynos-m1", 1907 1.1 mrg cpu_opttab_exynosm1, 1908 1.1 mrg { 1909 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1910 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1911 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1912 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1913 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1914 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1915 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1916 1.1 mrg } 1917 1.1 mrg }, 1918 1.1 mrg TARGET_ARCH_armv8_a 1919 1.1 mrg }, 1920 1.1 mrg { 1921 1.1 mrg { 1922 1.1 mrg "xgene1", 1923 1.1 mrg cpu_opttab_xgene1, 1924 1.1 mrg { 1925 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1926 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1927 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1928 1.1 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, 1929 1.1 mrg isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, 1930 1.1 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1931 1.1 mrg isa_bit_sec, isa_bit_armv3m, isa_nobit 1932 1.1 mrg } 1933 1.1 mrg }, 1934 1.1 mrg TARGET_ARCH_armv8_a 1935 1.1 mrg }, 1936 1.1 mrg { 1937 1.1 mrg { 1938 1.1 mrg "cortex-a57.cortex-a53", 1939 1.1 mrg cpu_opttab_cortexa57cortexa53, 1940 1.1 mrg { 1941 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1942 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1943 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1944 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1945 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1946 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1947 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1948 1.1 mrg } 1949 1.1 mrg }, 1950 1.1 mrg TARGET_ARCH_armv8_a 1951 1.1 mrg }, 1952 1.1 mrg { 1953 1.1 mrg { 1954 1.1 mrg "cortex-a72.cortex-a53", 1955 1.1 mrg cpu_opttab_cortexa72cortexa53, 1956 1.1 mrg { 1957 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1958 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1959 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1960 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1961 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1962 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1963 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1964 1.1 mrg } 1965 1.1 mrg }, 1966 1.1 mrg TARGET_ARCH_armv8_a 1967 1.1 mrg }, 1968 1.1 mrg { 1969 1.1 mrg { 1970 1.1 mrg "cortex-a73.cortex-a35", 1971 1.1 mrg cpu_opttab_cortexa73cortexa35, 1972 1.1 mrg { 1973 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1974 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1975 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1976 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1977 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1978 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1979 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1980 1.1 mrg } 1981 1.1 mrg }, 1982 1.1 mrg TARGET_ARCH_armv8_a 1983 1.1 mrg }, 1984 1.1 mrg { 1985 1.1 mrg { 1986 1.1 mrg "cortex-a73.cortex-a53", 1987 1.1 mrg cpu_opttab_cortexa73cortexa53, 1988 1.1 mrg { 1989 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1990 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 1991 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 1992 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1993 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 1994 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1995 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 1996 1.1 mrg } 1997 1.1 mrg }, 1998 1.1 mrg TARGET_ARCH_armv8_a 1999 1.1 mrg }, 2000 1.1 mrg { 2001 1.1 mrg { 2002 1.1 mrg "cortex-a55", 2003 1.1 mrg cpu_opttab_cortexa55, 2004 1.1 mrg { 2005 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2006 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod, 2007 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon, 2008 1.1 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2009 1.1 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 2010 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, 2011 1.1 mrg isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, 2012 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 2013 1.1 mrg } 2014 1.1 mrg }, 2015 1.1 mrg TARGET_ARCH_armv8_2_a 2016 1.1 mrg }, 2017 1.1 mrg { 2018 1.1 mrg { 2019 1.1 mrg "cortex-a75", 2020 1.1 mrg cpu_opttab_cortexa75, 2021 1.1 mrg { 2022 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2023 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod, 2024 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon, 2025 1.1 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2026 1.1 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 2027 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, 2028 1.1 mrg isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, 2029 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 2030 1.1 mrg } 2031 1.1 mrg }, 2032 1.1 mrg TARGET_ARCH_armv8_2_a 2033 1.1 mrg }, 2034 1.1 mrg { 2035 1.1 mrg { 2036 1.1 mrg "cortex-a75.cortex-a55", 2037 1.1 mrg cpu_opttab_cortexa75cortexa55, 2038 1.1 mrg { 2039 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2040 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_dotprod, 2041 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_neon, 2042 1.1 mrg isa_bit_armv6, isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, 2043 1.1 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, 2044 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, 2045 1.1 mrg isa_bit_fp16conv, isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, 2046 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 2047 1.1 mrg } 2048 1.1 mrg }, 2049 1.1 mrg TARGET_ARCH_armv8_2_a 2050 1.1 mrg }, 2051 1.1 mrg { 2052 1.1 mrg { 2053 1.1 mrg "cortex-m23", 2054 1.1 mrg NULL, 2055 1.1 mrg { 2056 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 2057 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse, 2058 1.1 mrg isa_bit_tdiv, isa_bit_mode32, isa_bit_armv3m, isa_nobit 2059 1.1 mrg } 2060 1.1 mrg }, 2061 1.1 mrg TARGET_ARCH_armv8_m_base 2062 1.1 mrg }, 2063 1.1 mrg { 2064 1.1 mrg { 2065 1.1 mrg "cortex-m33", 2066 1.1 mrg cpu_opttab_cortexm33, 2067 1.1 mrg { 2068 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5e, 2069 1.1 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv4, isa_bit_armv5, 2070 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_armv8, 2071 1.1 mrg isa_bit_cmse, isa_bit_fpv5, isa_bit_tdiv, isa_bit_mode32, 2072 1.1 mrg isa_bit_thumb2, isa_bit_fp16conv, isa_bit_armv3m, isa_nobit 2073 1.1 mrg } 2074 1.1 mrg }, 2075 1.1 mrg TARGET_ARCH_armv8_m_main 2076 1.1 mrg }, 2077 1.1 mrg { 2078 1.1 mrg { 2079 1.1 mrg "cortex-r52", 2080 1.1 mrg cpu_opttab_cortexr52, 2081 1.1 mrg { 2082 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 2083 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_lpae, 2084 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_neon, isa_bit_armv6, 2085 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 2086 1.1 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_mode32, isa_bit_thumb2, 2087 1.1 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 2088 1.1 mrg isa_bit_fp_dbl, isa_bit_sec, isa_bit_armv3m, isa_nobit 2089 1.1 mrg } 2090 1.1 mrg }, 2091 1.1 mrg TARGET_ARCH_armv8_r 2092 1.1 mrg }, 2093 1.1 mrg {{NULL, NULL, {isa_nobit}}, TARGET_ARCH_arm_none} 2094 1.1 mrg }; 2095 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5e[] = { 2096 1.1 mrg { 2097 1.1 mrg "fp", false, false, 2098 1.1 mrg { 2099 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2100 1.1 mrg } 2101 1.1 mrg }, 2102 1.1 mrg { 2103 1.1 mrg "nofp", true, false, 2104 1.1 mrg { 2105 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2106 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2107 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2108 1.1 mrg } 2109 1.1 mrg }, 2110 1.1 mrg { 2111 1.1 mrg "vfpv2", false, true, 2112 1.1 mrg { 2113 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2114 1.1 mrg } 2115 1.1 mrg }, 2116 1.1 mrg { NULL, false, false, {isa_nobit}} 2117 1.1 mrg }; 2118 1.1 mrg 2119 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5te[] = { 2120 1.1 mrg { 2121 1.1 mrg "fp", false, false, 2122 1.1 mrg { 2123 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2124 1.1 mrg } 2125 1.1 mrg }, 2126 1.1 mrg { 2127 1.1 mrg "nofp", true, false, 2128 1.1 mrg { 2129 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2130 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2131 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2132 1.1 mrg } 2133 1.1 mrg }, 2134 1.1 mrg { 2135 1.1 mrg "vfpv2", false, true, 2136 1.1 mrg { 2137 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2138 1.1 mrg } 2139 1.1 mrg }, 2140 1.1 mrg { NULL, false, false, {isa_nobit}} 2141 1.1 mrg }; 2142 1.1 mrg 2143 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5tej[] = { 2144 1.1 mrg { 2145 1.1 mrg "fp", false, false, 2146 1.1 mrg { 2147 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2148 1.1 mrg } 2149 1.1 mrg }, 2150 1.1 mrg { 2151 1.1 mrg "nofp", true, false, 2152 1.1 mrg { 2153 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2154 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2155 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2156 1.1 mrg } 2157 1.1 mrg }, 2158 1.1 mrg { 2159 1.1 mrg "vfpv2", false, true, 2160 1.1 mrg { 2161 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2162 1.1 mrg } 2163 1.1 mrg }, 2164 1.1 mrg { NULL, false, false, {isa_nobit}} 2165 1.1 mrg }; 2166 1.1 mrg 2167 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6[] = { 2168 1.1 mrg { 2169 1.1 mrg "fp", false, false, 2170 1.1 mrg { 2171 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2172 1.1 mrg } 2173 1.1 mrg }, 2174 1.1 mrg { 2175 1.1 mrg "nofp", true, false, 2176 1.1 mrg { 2177 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2178 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2179 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2180 1.1 mrg } 2181 1.1 mrg }, 2182 1.1 mrg { 2183 1.1 mrg "vfpv2", false, true, 2184 1.1 mrg { 2185 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2186 1.1 mrg } 2187 1.1 mrg }, 2188 1.1 mrg { NULL, false, false, {isa_nobit}} 2189 1.1 mrg }; 2190 1.1 mrg 2191 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6j[] = { 2192 1.1 mrg { 2193 1.1 mrg "fp", false, false, 2194 1.1 mrg { 2195 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2196 1.1 mrg } 2197 1.1 mrg }, 2198 1.1 mrg { 2199 1.1 mrg "nofp", true, false, 2200 1.1 mrg { 2201 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2202 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2203 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2204 1.1 mrg } 2205 1.1 mrg }, 2206 1.1 mrg { 2207 1.1 mrg "vfpv2", false, true, 2208 1.1 mrg { 2209 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2210 1.1 mrg } 2211 1.1 mrg }, 2212 1.1 mrg { NULL, false, false, {isa_nobit}} 2213 1.1 mrg }; 2214 1.1 mrg 2215 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6k[] = { 2216 1.1 mrg { 2217 1.1 mrg "fp", false, false, 2218 1.1 mrg { 2219 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2220 1.1 mrg } 2221 1.1 mrg }, 2222 1.1 mrg { 2223 1.1 mrg "nofp", true, false, 2224 1.1 mrg { 2225 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2226 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2227 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2228 1.1 mrg } 2229 1.1 mrg }, 2230 1.1 mrg { 2231 1.1 mrg "vfpv2", false, true, 2232 1.1 mrg { 2233 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2234 1.1 mrg } 2235 1.1 mrg }, 2236 1.1 mrg { NULL, false, false, {isa_nobit}} 2237 1.1 mrg }; 2238 1.1 mrg 2239 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6z[] = { 2240 1.1 mrg { 2241 1.1 mrg "fp", false, false, 2242 1.1 mrg { 2243 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2244 1.1 mrg } 2245 1.1 mrg }, 2246 1.1 mrg { 2247 1.1 mrg "nofp", true, false, 2248 1.1 mrg { 2249 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2250 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2251 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2252 1.1 mrg } 2253 1.1 mrg }, 2254 1.1 mrg { 2255 1.1 mrg "vfpv2", false, true, 2256 1.1 mrg { 2257 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2258 1.1 mrg } 2259 1.1 mrg }, 2260 1.1 mrg { NULL, false, false, {isa_nobit}} 2261 1.1 mrg }; 2262 1.1 mrg 2263 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6kz[] = { 2264 1.1 mrg { 2265 1.1 mrg "fp", false, false, 2266 1.1 mrg { 2267 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2268 1.1 mrg } 2269 1.1 mrg }, 2270 1.1 mrg { 2271 1.1 mrg "nofp", true, false, 2272 1.1 mrg { 2273 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2274 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2275 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2276 1.1 mrg } 2277 1.1 mrg }, 2278 1.1 mrg { 2279 1.1 mrg "vfpv2", false, true, 2280 1.1 mrg { 2281 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2282 1.1 mrg } 2283 1.1 mrg }, 2284 1.1 mrg { NULL, false, false, {isa_nobit}} 2285 1.1 mrg }; 2286 1.1 mrg 2287 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6zk[] = { 2288 1.1 mrg { 2289 1.1 mrg "fp", false, false, 2290 1.1 mrg { 2291 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2292 1.1 mrg } 2293 1.1 mrg }, 2294 1.1 mrg { 2295 1.1 mrg "nofp", true, false, 2296 1.1 mrg { 2297 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2298 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2299 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2300 1.1 mrg } 2301 1.1 mrg }, 2302 1.1 mrg { 2303 1.1 mrg "vfpv2", false, true, 2304 1.1 mrg { 2305 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2306 1.1 mrg } 2307 1.1 mrg }, 2308 1.1 mrg { NULL, false, false, {isa_nobit}} 2309 1.1 mrg }; 2310 1.1 mrg 2311 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6t2[] = { 2312 1.1 mrg { 2313 1.1 mrg "fp", false, false, 2314 1.1 mrg { 2315 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2316 1.1 mrg } 2317 1.1 mrg }, 2318 1.1 mrg { 2319 1.1 mrg "nofp", true, false, 2320 1.1 mrg { 2321 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2322 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2323 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2324 1.1 mrg } 2325 1.1 mrg }, 2326 1.1 mrg { 2327 1.1 mrg "vfpv2", false, true, 2328 1.1 mrg { 2329 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2330 1.1 mrg } 2331 1.1 mrg }, 2332 1.1 mrg { NULL, false, false, {isa_nobit}} 2333 1.1 mrg }; 2334 1.1 mrg 2335 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7[] = { 2336 1.1 mrg { 2337 1.1 mrg "fp", false, false, 2338 1.1 mrg { 2339 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2340 1.1 mrg } 2341 1.1 mrg }, 2342 1.1 mrg { 2343 1.1 mrg "nofp", true, false, 2344 1.1 mrg { 2345 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2346 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2347 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2348 1.1 mrg } 2349 1.1 mrg }, 2350 1.1 mrg { 2351 1.1 mrg "vfpv3-d16", false, true, 2352 1.1 mrg { 2353 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2354 1.1 mrg } 2355 1.1 mrg }, 2356 1.1 mrg { NULL, false, false, {isa_nobit}} 2357 1.1 mrg }; 2358 1.1 mrg 2359 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7_a[] = { 2360 1.1 mrg { 2361 1.1 mrg "mp", false, false, 2362 1.1 mrg { 2363 1.1 mrg isa_bit_mp, isa_nobit 2364 1.1 mrg } 2365 1.1 mrg }, 2366 1.1 mrg { 2367 1.1 mrg "sec", false, false, 2368 1.1 mrg { 2369 1.1 mrg isa_bit_sec, isa_nobit 2370 1.1 mrg } 2371 1.1 mrg }, 2372 1.1 mrg { 2373 1.1 mrg "fp", false, false, 2374 1.1 mrg { 2375 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2376 1.1 mrg } 2377 1.1 mrg }, 2378 1.1 mrg { 2379 1.1 mrg "vfpv3", false, false, 2380 1.1 mrg { 2381 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2382 1.1 mrg isa_nobit 2383 1.1 mrg } 2384 1.1 mrg }, 2385 1.1 mrg { 2386 1.1 mrg "vfpv3-d16-fp16", false, false, 2387 1.1 mrg { 2388 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2389 1.1 mrg isa_nobit 2390 1.1 mrg } 2391 1.1 mrg }, 2392 1.1 mrg { 2393 1.1 mrg "vfpv3-fp16", false, false, 2394 1.1 mrg { 2395 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2396 1.1 mrg isa_bit_fp_dbl, isa_nobit 2397 1.1 mrg } 2398 1.1 mrg }, 2399 1.1 mrg { 2400 1.1 mrg "vfpv4-d16", false, false, 2401 1.1 mrg { 2402 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2403 1.1 mrg isa_bit_fp_dbl, isa_nobit 2404 1.1 mrg } 2405 1.1 mrg }, 2406 1.1 mrg { 2407 1.1 mrg "vfpv4", false, false, 2408 1.1 mrg { 2409 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2410 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2411 1.1 mrg } 2412 1.1 mrg }, 2413 1.1 mrg { 2414 1.1 mrg "simd", false, false, 2415 1.1 mrg { 2416 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2417 1.1 mrg isa_bit_fp_dbl, isa_nobit 2418 1.1 mrg } 2419 1.1 mrg }, 2420 1.1 mrg { 2421 1.1 mrg "neon-fp16", false, false, 2422 1.1 mrg { 2423 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2424 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2425 1.1 mrg } 2426 1.1 mrg }, 2427 1.1 mrg { 2428 1.1 mrg "neon-vfpv4", false, false, 2429 1.1 mrg { 2430 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2431 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2432 1.1 mrg } 2433 1.1 mrg }, 2434 1.1 mrg { 2435 1.1 mrg "nosimd", true, false, 2436 1.1 mrg { 2437 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2438 1.1 mrg isa_bit_crypto, isa_nobit 2439 1.1 mrg } 2440 1.1 mrg }, 2441 1.1 mrg { 2442 1.1 mrg "nofp", true, false, 2443 1.1 mrg { 2444 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2445 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2446 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2447 1.1 mrg } 2448 1.1 mrg }, 2449 1.1 mrg { 2450 1.1 mrg "vfpv3-d16", false, true, 2451 1.1 mrg { 2452 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2453 1.1 mrg } 2454 1.1 mrg }, 2455 1.1 mrg { 2456 1.1 mrg "neon", false, true, 2457 1.1 mrg { 2458 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2459 1.1 mrg isa_bit_fp_dbl, isa_nobit 2460 1.1 mrg } 2461 1.1 mrg }, 2462 1.1 mrg { 2463 1.1 mrg "neon-vfpv3", false, true, 2464 1.1 mrg { 2465 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2466 1.1 mrg isa_bit_fp_dbl, isa_nobit 2467 1.1 mrg } 2468 1.1 mrg }, 2469 1.1 mrg { NULL, false, false, {isa_nobit}} 2470 1.1 mrg }; 2471 1.1 mrg 2472 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7ve[] = { 2473 1.1 mrg { 2474 1.1 mrg "vfpv3-d16", false, false, 2475 1.1 mrg { 2476 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2477 1.1 mrg } 2478 1.1 mrg }, 2479 1.1 mrg { 2480 1.1 mrg "vfpv3", false, false, 2481 1.1 mrg { 2482 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2483 1.1 mrg isa_nobit 2484 1.1 mrg } 2485 1.1 mrg }, 2486 1.1 mrg { 2487 1.1 mrg "vfpv3-d16-fp16", false, false, 2488 1.1 mrg { 2489 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2490 1.1 mrg isa_nobit 2491 1.1 mrg } 2492 1.1 mrg }, 2493 1.1 mrg { 2494 1.1 mrg "vfpv3-fp16", false, false, 2495 1.1 mrg { 2496 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2497 1.1 mrg isa_bit_fp_dbl, isa_nobit 2498 1.1 mrg } 2499 1.1 mrg }, 2500 1.1 mrg { 2501 1.1 mrg "fp", false, false, 2502 1.1 mrg { 2503 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2504 1.1 mrg isa_bit_fp_dbl, isa_nobit 2505 1.1 mrg } 2506 1.1 mrg }, 2507 1.1 mrg { 2508 1.1 mrg "vfpv4", false, false, 2509 1.1 mrg { 2510 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2511 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2512 1.1 mrg } 2513 1.1 mrg }, 2514 1.1 mrg { 2515 1.1 mrg "neon", false, false, 2516 1.1 mrg { 2517 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2518 1.1 mrg isa_bit_fp_dbl, isa_nobit 2519 1.1 mrg } 2520 1.1 mrg }, 2521 1.1 mrg { 2522 1.1 mrg "neon-fp16", false, false, 2523 1.1 mrg { 2524 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2525 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2526 1.1 mrg } 2527 1.1 mrg }, 2528 1.1 mrg { 2529 1.1 mrg "simd", false, false, 2530 1.1 mrg { 2531 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2532 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2533 1.1 mrg } 2534 1.1 mrg }, 2535 1.1 mrg { 2536 1.1 mrg "nosimd", true, false, 2537 1.1 mrg { 2538 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2539 1.1 mrg isa_bit_crypto, isa_nobit 2540 1.1 mrg } 2541 1.1 mrg }, 2542 1.1 mrg { 2543 1.1 mrg "nofp", true, false, 2544 1.1 mrg { 2545 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2546 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2547 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2548 1.1 mrg } 2549 1.1 mrg }, 2550 1.1 mrg { 2551 1.1 mrg "vfpv4-d16", false, true, 2552 1.1 mrg { 2553 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2554 1.1 mrg isa_bit_fp_dbl, isa_nobit 2555 1.1 mrg } 2556 1.1 mrg }, 2557 1.1 mrg { 2558 1.1 mrg "neon-vfpv3", false, true, 2559 1.1 mrg { 2560 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2561 1.1 mrg isa_bit_fp_dbl, isa_nobit 2562 1.1 mrg } 2563 1.1 mrg }, 2564 1.1 mrg { 2565 1.1 mrg "neon-vfpv4", false, true, 2566 1.1 mrg { 2567 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2568 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2569 1.1 mrg } 2570 1.1 mrg }, 2571 1.1 mrg { NULL, false, false, {isa_nobit}} 2572 1.1 mrg }; 2573 1.1 mrg 2574 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7_r[] = { 2575 1.1 mrg { 2576 1.1 mrg "fp.sp", false, false, 2577 1.1 mrg { 2578 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2579 1.1 mrg } 2580 1.1 mrg }, 2581 1.1 mrg { 2582 1.1 mrg "fp", false, false, 2583 1.1 mrg { 2584 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2585 1.1 mrg } 2586 1.1 mrg }, 2587 1.1 mrg { 2588 1.1 mrg "vfpv3xd-fp16", false, false, 2589 1.1 mrg { 2590 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 2591 1.1 mrg } 2592 1.1 mrg }, 2593 1.1 mrg { 2594 1.1 mrg "vfpv3-d16-fp16", false, false, 2595 1.1 mrg { 2596 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2597 1.1 mrg isa_nobit 2598 1.1 mrg } 2599 1.1 mrg }, 2600 1.1 mrg { 2601 1.1 mrg "idiv", false, false, 2602 1.1 mrg { 2603 1.1 mrg isa_bit_adiv, isa_nobit 2604 1.1 mrg } 2605 1.1 mrg }, 2606 1.1 mrg { 2607 1.1 mrg "nofp", true, false, 2608 1.1 mrg { 2609 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2610 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2611 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2612 1.1 mrg } 2613 1.1 mrg }, 2614 1.1 mrg { 2615 1.1 mrg "noidiv", true, false, 2616 1.1 mrg { 2617 1.1 mrg isa_bit_adiv, isa_nobit 2618 1.1 mrg } 2619 1.1 mrg }, 2620 1.1 mrg { 2621 1.1 mrg "vfpv3xd", false, true, 2622 1.1 mrg { 2623 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2624 1.1 mrg } 2625 1.1 mrg }, 2626 1.1 mrg { 2627 1.1 mrg "vfpv3-d16", false, true, 2628 1.1 mrg { 2629 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2630 1.1 mrg } 2631 1.1 mrg }, 2632 1.1 mrg { NULL, false, false, {isa_nobit}} 2633 1.1 mrg }; 2634 1.1 mrg 2635 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { 2636 1.1 mrg { 2637 1.1 mrg "fp", false, false, 2638 1.1 mrg { 2639 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2640 1.1 mrg isa_nobit 2641 1.1 mrg } 2642 1.1 mrg }, 2643 1.1 mrg { 2644 1.1 mrg "fpv5", false, false, 2645 1.1 mrg { 2646 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2647 1.1 mrg isa_bit_fp16conv, isa_nobit 2648 1.1 mrg } 2649 1.1 mrg }, 2650 1.1 mrg { 2651 1.1 mrg "fp.dp", false, false, 2652 1.1 mrg { 2653 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2654 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2655 1.1 mrg } 2656 1.1 mrg }, 2657 1.1 mrg { 2658 1.1 mrg "nofp", true, false, 2659 1.1 mrg { 2660 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2661 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2662 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2663 1.1 mrg } 2664 1.1 mrg }, 2665 1.1 mrg { 2666 1.1 mrg "vfpv4-sp-d16", false, true, 2667 1.1 mrg { 2668 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2669 1.1 mrg isa_nobit 2670 1.1 mrg } 2671 1.1 mrg }, 2672 1.1 mrg { 2673 1.1 mrg "fpv5-d16", false, true, 2674 1.1 mrg { 2675 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2676 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2677 1.1 mrg } 2678 1.1 mrg }, 2679 1.1 mrg { NULL, false, false, {isa_nobit}} 2680 1.1 mrg }; 2681 1.1 mrg 2682 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_a[] = { 2683 1.1 mrg { 2684 1.1 mrg "crc", false, false, 2685 1.1 mrg { 2686 1.1 mrg isa_bit_crc32, isa_nobit 2687 1.1 mrg } 2688 1.1 mrg }, 2689 1.1 mrg { 2690 1.1 mrg "simd", false, false, 2691 1.1 mrg { 2692 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2693 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2694 1.1 mrg isa_nobit 2695 1.1 mrg } 2696 1.1 mrg }, 2697 1.1 mrg { 2698 1.1 mrg "crypto", false, false, 2699 1.1 mrg { 2700 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2701 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2702 1.1 mrg isa_bit_fp_dbl, isa_nobit 2703 1.1 mrg } 2704 1.1 mrg }, 2705 1.1 mrg { 2706 1.1 mrg "nocrypto", true, false, 2707 1.1 mrg { 2708 1.1 mrg isa_bit_crypto, isa_nobit 2709 1.1 mrg } 2710 1.1 mrg }, 2711 1.1 mrg { 2712 1.1 mrg "nofp", true, false, 2713 1.1 mrg { 2714 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2715 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2716 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2717 1.1 mrg } 2718 1.1 mrg }, 2719 1.1 mrg { NULL, false, false, {isa_nobit}} 2720 1.1 mrg }; 2721 1.1 mrg 2722 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { 2723 1.1 mrg { 2724 1.1 mrg "simd", false, false, 2725 1.1 mrg { 2726 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2727 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2728 1.1 mrg isa_nobit 2729 1.1 mrg } 2730 1.1 mrg }, 2731 1.1 mrg { 2732 1.1 mrg "crypto", false, false, 2733 1.1 mrg { 2734 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2735 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2736 1.1 mrg isa_bit_fp_dbl, isa_nobit 2737 1.1 mrg } 2738 1.1 mrg }, 2739 1.1 mrg { 2740 1.1 mrg "nocrypto", true, false, 2741 1.1 mrg { 2742 1.1 mrg isa_bit_crypto, isa_nobit 2743 1.1 mrg } 2744 1.1 mrg }, 2745 1.1 mrg { 2746 1.1 mrg "nofp", true, false, 2747 1.1 mrg { 2748 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2749 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2750 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2751 1.1 mrg } 2752 1.1 mrg }, 2753 1.1 mrg { NULL, false, false, {isa_nobit}} 2754 1.1 mrg }; 2755 1.1 mrg 2756 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { 2757 1.1 mrg { 2758 1.1 mrg "simd", false, false, 2759 1.1 mrg { 2760 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2761 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2762 1.1 mrg isa_nobit 2763 1.1 mrg } 2764 1.1 mrg }, 2765 1.1 mrg { 2766 1.1 mrg "fp16", false, false, 2767 1.1 mrg { 2768 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2769 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2770 1.1 mrg isa_bit_fp_dbl, isa_nobit 2771 1.1 mrg } 2772 1.1 mrg }, 2773 1.1 mrg { 2774 1.1 mrg "fp16fml", false, false, 2775 1.1 mrg { 2776 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2777 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2778 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2779 1.1 mrg } 2780 1.1 mrg }, 2781 1.1 mrg { 2782 1.1 mrg "crypto", false, false, 2783 1.1 mrg { 2784 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2785 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2786 1.1 mrg isa_bit_fp_dbl, isa_nobit 2787 1.1 mrg } 2788 1.1 mrg }, 2789 1.1 mrg { 2790 1.1 mrg "nocrypto", true, false, 2791 1.1 mrg { 2792 1.1 mrg isa_bit_crypto, isa_nobit 2793 1.1 mrg } 2794 1.1 mrg }, 2795 1.1 mrg { 2796 1.1 mrg "nofp", true, false, 2797 1.1 mrg { 2798 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2799 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2800 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2801 1.1 mrg } 2802 1.1 mrg }, 2803 1.1 mrg { 2804 1.1 mrg "dotprod", false, false, 2805 1.1 mrg { 2806 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2807 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2808 1.1 mrg isa_bit_fp_dbl, isa_nobit 2809 1.1 mrg } 2810 1.1 mrg }, 2811 1.1 mrg { NULL, false, false, {isa_nobit}} 2812 1.1 mrg }; 2813 1.1 mrg 2814 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = { 2815 1.1 mrg { 2816 1.1 mrg "simd", false, false, 2817 1.1 mrg { 2818 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2819 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2820 1.1 mrg isa_nobit 2821 1.1 mrg } 2822 1.1 mrg }, 2823 1.1 mrg { 2824 1.1 mrg "fp16", false, false, 2825 1.1 mrg { 2826 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2827 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2828 1.1 mrg isa_bit_fp_dbl, isa_nobit 2829 1.1 mrg } 2830 1.1 mrg }, 2831 1.1 mrg { 2832 1.1 mrg "fp16fml", false, false, 2833 1.1 mrg { 2834 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2835 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2836 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2837 1.1 mrg } 2838 1.1 mrg }, 2839 1.1 mrg { 2840 1.1 mrg "crypto", false, false, 2841 1.1 mrg { 2842 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2843 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2844 1.1 mrg isa_bit_fp_dbl, isa_nobit 2845 1.1 mrg } 2846 1.1 mrg }, 2847 1.1 mrg { 2848 1.1 mrg "nocrypto", true, false, 2849 1.1 mrg { 2850 1.1 mrg isa_bit_crypto, isa_nobit 2851 1.1 mrg } 2852 1.1 mrg }, 2853 1.1 mrg { 2854 1.1 mrg "nofp", true, false, 2855 1.1 mrg { 2856 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2857 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2858 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2859 1.1 mrg } 2860 1.1 mrg }, 2861 1.1 mrg { 2862 1.1 mrg "dotprod", false, false, 2863 1.1 mrg { 2864 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2865 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2866 1.1 mrg isa_bit_fp_dbl, isa_nobit 2867 1.1 mrg } 2868 1.1 mrg }, 2869 1.1 mrg { NULL, false, false, {isa_nobit}} 2870 1.1 mrg }; 2871 1.1 mrg 2872 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = { 2873 1.1 mrg { 2874 1.1 mrg "simd", false, false, 2875 1.1 mrg { 2876 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2877 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2878 1.1 mrg isa_bit_fp_dbl, isa_nobit 2879 1.1 mrg } 2880 1.1 mrg }, 2881 1.1 mrg { 2882 1.1 mrg "fp16", false, false, 2883 1.1 mrg { 2884 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2885 1.1 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2886 1.1 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2887 1.1 mrg } 2888 1.1 mrg }, 2889 1.1 mrg { 2890 1.1 mrg "crypto", false, false, 2891 1.1 mrg { 2892 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2893 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2894 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2895 1.1 mrg } 2896 1.1 mrg }, 2897 1.1 mrg { 2898 1.1 mrg "nocrypto", true, false, 2899 1.1 mrg { 2900 1.1 mrg isa_bit_crypto, isa_nobit 2901 1.1 mrg } 2902 1.1 mrg }, 2903 1.1 mrg { 2904 1.1 mrg "nofp", true, false, 2905 1.1 mrg { 2906 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2907 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2908 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2909 1.1 mrg } 2910 1.1 mrg }, 2911 1.1 mrg { NULL, false, false, {isa_nobit}} 2912 1.1 mrg }; 2913 1.1 mrg 2914 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { 2915 1.1 mrg { 2916 1.1 mrg "dsp", false, false, 2917 1.1 mrg { 2918 1.1 mrg isa_bit_armv7em, isa_nobit 2919 1.1 mrg } 2920 1.1 mrg }, 2921 1.1 mrg { 2922 1.1 mrg "fp", false, false, 2923 1.1 mrg { 2924 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2925 1.1 mrg isa_bit_fp16conv, isa_nobit 2926 1.1 mrg } 2927 1.1 mrg }, 2928 1.1 mrg { 2929 1.1 mrg "fp.dp", false, false, 2930 1.1 mrg { 2931 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2932 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2933 1.1 mrg } 2934 1.1 mrg }, 2935 1.1 mrg { 2936 1.1 mrg "nofp", true, false, 2937 1.1 mrg { 2938 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2939 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2940 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2941 1.1 mrg } 2942 1.1 mrg }, 2943 1.1 mrg { 2944 1.1 mrg "nodsp", true, false, 2945 1.1 mrg { 2946 1.1 mrg isa_bit_armv7em, isa_nobit 2947 1.1 mrg } 2948 1.1 mrg }, 2949 1.1 mrg { NULL, false, false, {isa_nobit}} 2950 1.1 mrg }; 2951 1.1 mrg 2952 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_r[] = { 2953 1.1 mrg { 2954 1.1 mrg "crc", false, false, 2955 1.1 mrg { 2956 1.1 mrg isa_bit_crc32, isa_nobit 2957 1.1 mrg } 2958 1.1 mrg }, 2959 1.1 mrg { 2960 1.1 mrg "fp.sp", false, false, 2961 1.1 mrg { 2962 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2963 1.1 mrg isa_bit_fp16conv, isa_nobit 2964 1.1 mrg } 2965 1.1 mrg }, 2966 1.1 mrg { 2967 1.1 mrg "simd", false, false, 2968 1.1 mrg { 2969 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2970 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2971 1.1 mrg isa_nobit 2972 1.1 mrg } 2973 1.1 mrg }, 2974 1.1 mrg { 2975 1.1 mrg "crypto", false, false, 2976 1.1 mrg { 2977 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2978 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2979 1.1 mrg isa_bit_fp_dbl, isa_nobit 2980 1.1 mrg } 2981 1.1 mrg }, 2982 1.1 mrg { 2983 1.1 mrg "nocrypto", true, false, 2984 1.1 mrg { 2985 1.1 mrg isa_bit_crypto, isa_nobit 2986 1.1 mrg } 2987 1.1 mrg }, 2988 1.1 mrg { 2989 1.1 mrg "nofp", true, false, 2990 1.1 mrg { 2991 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2992 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2993 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2994 1.1 mrg } 2995 1.1 mrg }, 2996 1.1 mrg { NULL, false, false, {isa_nobit}} 2997 1.1 mrg }; 2998 1.1 mrg 2999 1.1 mrg const arch_option all_architectures[] = 3000 1.1 mrg { 3001 1.1 mrg { 3002 1.1 mrg "armv2", 3003 1.1 mrg NULL, 3004 1.1 mrg { 3005 1.1 mrg isa_bit_mode26, isa_bit_notm, isa_nobit 3006 1.1 mrg }, 3007 1.1 mrg "2", BASE_ARCH_2, 3008 1.1 mrg 0, 3009 1.1 mrg TARGET_CPU_arm2, 3010 1.1 mrg }, 3011 1.1 mrg { 3012 1.1 mrg "armv2a", 3013 1.1 mrg NULL, 3014 1.1 mrg { 3015 1.1 mrg isa_bit_mode26, isa_bit_notm, isa_nobit 3016 1.1 mrg }, 3017 1.1 mrg "2", BASE_ARCH_2, 3018 1.1 mrg 0, 3019 1.1 mrg TARGET_CPU_arm2, 3020 1.1 mrg }, 3021 1.1 mrg { 3022 1.1 mrg "armv3", 3023 1.1 mrg NULL, 3024 1.1 mrg { 3025 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_nobit 3026 1.1 mrg }, 3027 1.1 mrg "3", BASE_ARCH_3, 3028 1.1 mrg 0, 3029 1.1 mrg TARGET_CPU_arm6, 3030 1.1 mrg }, 3031 1.1 mrg { 3032 1.1 mrg "armv3m", 3033 1.1 mrg NULL, 3034 1.1 mrg { 3035 1.1 mrg isa_bit_mode26, isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, 3036 1.1 mrg isa_nobit 3037 1.1 mrg }, 3038 1.1 mrg "3M", BASE_ARCH_3M, 3039 1.1 mrg 0, 3040 1.1 mrg TARGET_CPU_arm7m, 3041 1.1 mrg }, 3042 1.1 mrg { 3043 1.1 mrg "armv4", 3044 1.1 mrg NULL, 3045 1.1 mrg { 3046 1.1 mrg isa_bit_mode26, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 3047 1.1 mrg isa_bit_armv3m, isa_nobit 3048 1.1 mrg }, 3049 1.1 mrg "4", BASE_ARCH_4, 3050 1.1 mrg 0, 3051 1.1 mrg TARGET_CPU_arm7tdmi, 3052 1.1 mrg }, 3053 1.1 mrg { 3054 1.1 mrg "armv4t", 3055 1.1 mrg NULL, 3056 1.1 mrg { 3057 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_mode32, isa_bit_notm, 3058 1.1 mrg isa_bit_armv3m, isa_nobit 3059 1.1 mrg }, 3060 1.1 mrg "4T", BASE_ARCH_4T, 3061 1.1 mrg 0, 3062 1.1 mrg TARGET_CPU_arm7tdmi, 3063 1.1 mrg }, 3064 1.1 mrg { 3065 1.1 mrg "armv5", 3066 1.1 mrg NULL, 3067 1.1 mrg { 3068 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm, 3069 1.1 mrg isa_bit_armv3m, isa_nobit 3070 1.1 mrg }, 3071 1.1 mrg "5", BASE_ARCH_5, 3072 1.1 mrg 0, 3073 1.1 mrg TARGET_CPU_arm10tdmi, 3074 1.1 mrg }, 3075 1.1 mrg { 3076 1.1 mrg "armv5t", 3077 1.1 mrg NULL, 3078 1.1 mrg { 3079 1.1 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, 3080 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 3081 1.1 mrg }, 3082 1.1 mrg "5T", BASE_ARCH_5T, 3083 1.1 mrg 0, 3084 1.1 mrg TARGET_CPU_arm10tdmi, 3085 1.1 mrg }, 3086 1.1 mrg { 3087 1.1 mrg "armv5e", 3088 1.1 mrg arch_opttab_armv5e, 3089 1.1 mrg { 3090 1.1 mrg isa_bit_armv5e, isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, 3091 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 3092 1.1 mrg }, 3093 1.1 mrg "5E", BASE_ARCH_5E, 3094 1.1 mrg 0, 3095 1.1 mrg TARGET_CPU_arm1026ejs, 3096 1.1 mrg }, 3097 1.1 mrg { 3098 1.1 mrg "armv5te", 3099 1.1 mrg arch_opttab_armv5te, 3100 1.1 mrg { 3101 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, 3102 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit 3103 1.1 mrg }, 3104 1.1 mrg "5TE", BASE_ARCH_5TE, 3105 1.1 mrg 0, 3106 1.1 mrg TARGET_CPU_arm1026ejs, 3107 1.1 mrg }, 3108 1.1 mrg { 3109 1.1 mrg "armv5tej", 3110 1.1 mrg arch_opttab_armv5tej, 3111 1.1 mrg { 3112 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_armv4, isa_bit_armv5, 3113 1.1 mrg isa_bit_mode32, isa_bit_notm, isa_bit_armv3m, isa_nobit 3114 1.1 mrg }, 3115 1.1 mrg "5TEJ", BASE_ARCH_5TEJ, 3116 1.1 mrg 0, 3117 1.1 mrg TARGET_CPU_arm1026ejs, 3118 1.1 mrg }, 3119 1.1 mrg { 3120 1.1 mrg "armv6", 3121 1.1 mrg arch_opttab_armv6, 3122 1.1 mrg { 3123 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3124 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm, 3125 1.1 mrg isa_bit_armv3m, isa_nobit 3126 1.1 mrg }, 3127 1.1 mrg "6", BASE_ARCH_6, 3128 1.1 mrg 0, 3129 1.1 mrg TARGET_CPU_arm1136js, 3130 1.1 mrg }, 3131 1.1 mrg { 3132 1.1 mrg "armv6j", 3133 1.1 mrg arch_opttab_armv6j, 3134 1.1 mrg { 3135 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3136 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm, 3137 1.1 mrg isa_bit_armv3m, isa_nobit 3138 1.1 mrg }, 3139 1.1 mrg "6J", BASE_ARCH_6J, 3140 1.1 mrg 0, 3141 1.1 mrg TARGET_CPU_arm1136js, 3142 1.1 mrg }, 3143 1.1 mrg { 3144 1.1 mrg "armv6k", 3145 1.1 mrg arch_opttab_armv6k, 3146 1.1 mrg { 3147 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3148 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm, 3149 1.1 mrg isa_bit_armv6k, isa_bit_armv3m, isa_nobit 3150 1.1 mrg }, 3151 1.1 mrg "6K", BASE_ARCH_6K, 3152 1.1 mrg 0, 3153 1.1 mrg TARGET_CPU_mpcore, 3154 1.1 mrg }, 3155 1.1 mrg { 3156 1.1 mrg "armv6z", 3157 1.1 mrg arch_opttab_armv6z, 3158 1.1 mrg { 3159 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3160 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_notm, 3161 1.1 mrg isa_bit_armv3m, isa_nobit 3162 1.1 mrg }, 3163 1.1 mrg "6Z", BASE_ARCH_6Z, 3164 1.1 mrg 0, 3165 1.1 mrg TARGET_CPU_arm1176jzs, 3166 1.1 mrg }, 3167 1.1 mrg { 3168 1.1 mrg "armv6kz", 3169 1.1 mrg arch_opttab_armv6kz, 3170 1.1 mrg { 3171 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3172 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32, 3173 1.1 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit 3174 1.1 mrg }, 3175 1.1 mrg "6KZ", BASE_ARCH_6KZ, 3176 1.1 mrg 0, 3177 1.1 mrg TARGET_CPU_arm1176jzs, 3178 1.1 mrg }, 3179 1.1 mrg { 3180 1.1 mrg "armv6zk", 3181 1.1 mrg arch_opttab_armv6zk, 3182 1.1 mrg { 3183 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3184 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_quirk_armv6kz, isa_bit_mode32, 3185 1.1 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, isa_nobit 3186 1.1 mrg }, 3187 1.1 mrg "6KZ", BASE_ARCH_6KZ, 3188 1.1 mrg 0, 3189 1.1 mrg TARGET_CPU_arm1176jzs, 3190 1.1 mrg }, 3191 1.1 mrg { 3192 1.1 mrg "armv6t2", 3193 1.1 mrg arch_opttab_armv6t2, 3194 1.1 mrg { 3195 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3196 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_thumb2, 3197 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 3198 1.1 mrg }, 3199 1.1 mrg "6T2", BASE_ARCH_6T2, 3200 1.1 mrg 0, 3201 1.1 mrg TARGET_CPU_arm1156t2s, 3202 1.1 mrg }, 3203 1.1 mrg { 3204 1.1 mrg "armv6-m", 3205 1.1 mrg NULL, 3206 1.1 mrg { 3207 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3208 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 3209 1.1 mrg isa_nobit 3210 1.1 mrg }, 3211 1.1 mrg "6M", BASE_ARCH_6M, 3212 1.1 mrg 'M', 3213 1.1 mrg TARGET_CPU_cortexm1, 3214 1.1 mrg }, 3215 1.1 mrg { 3216 1.1 mrg "armv6s-m", 3217 1.1 mrg NULL, 3218 1.1 mrg { 3219 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3220 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_mode32, isa_bit_armv3m, 3221 1.1 mrg isa_nobit 3222 1.1 mrg }, 3223 1.1 mrg "6M", BASE_ARCH_6M, 3224 1.1 mrg 'M', 3225 1.1 mrg TARGET_CPU_cortexm1, 3226 1.1 mrg }, 3227 1.1 mrg { 3228 1.1 mrg "armv7", 3229 1.1 mrg arch_opttab_armv7, 3230 1.1 mrg { 3231 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3232 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32, 3233 1.1 mrg isa_bit_thumb2, isa_bit_armv3m, isa_nobit 3234 1.1 mrg }, 3235 1.1 mrg "7", BASE_ARCH_7, 3236 1.1 mrg 0, 3237 1.1 mrg TARGET_CPU_cortexa8, 3238 1.1 mrg }, 3239 1.1 mrg { 3240 1.1 mrg "armv7-a", 3241 1.1 mrg arch_opttab_armv7_a, 3242 1.1 mrg { 3243 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3244 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_mode32, 3245 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_armv3m, 3246 1.1 mrg isa_nobit 3247 1.1 mrg }, 3248 1.1 mrg "7A", BASE_ARCH_7A, 3249 1.1 mrg 'A', 3250 1.1 mrg TARGET_CPU_cortexa8, 3251 1.1 mrg }, 3252 1.1 mrg { 3253 1.1 mrg "armv7ve", 3254 1.1 mrg arch_opttab_armv7ve, 3255 1.1 mrg { 3256 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3257 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3258 1.1 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, 3259 1.1 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3260 1.1 mrg isa_bit_armv3m, isa_nobit 3261 1.1 mrg }, 3262 1.1 mrg "7A", BASE_ARCH_7A, 3263 1.1 mrg 'A', 3264 1.1 mrg TARGET_CPU_cortexa8, 3265 1.1 mrg }, 3266 1.1 mrg { 3267 1.1 mrg "armv7-r", 3268 1.1 mrg arch_opttab_armv7_r, 3269 1.1 mrg { 3270 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3271 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 3272 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, 3273 1.1 mrg isa_bit_armv3m, isa_nobit 3274 1.1 mrg }, 3275 1.1 mrg "7R", BASE_ARCH_7R, 3276 1.1 mrg 'R', 3277 1.1 mrg TARGET_CPU_cortexr4, 3278 1.1 mrg }, 3279 1.1 mrg { 3280 1.1 mrg "armv7-m", 3281 1.1 mrg NULL, 3282 1.1 mrg { 3283 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3284 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 3285 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m, isa_nobit 3286 1.1 mrg }, 3287 1.1 mrg "7M", BASE_ARCH_7M, 3288 1.1 mrg 'M', 3289 1.1 mrg TARGET_CPU_cortexm3, 3290 1.1 mrg }, 3291 1.1 mrg { 3292 1.1 mrg "armv7e-m", 3293 1.1 mrg arch_opttab_armv7e_m, 3294 1.1 mrg { 3295 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3296 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, 3297 1.1 mrg isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, isa_bit_armv3m, 3298 1.1 mrg isa_nobit 3299 1.1 mrg }, 3300 1.1 mrg "7EM", BASE_ARCH_7EM, 3301 1.1 mrg 'M', 3302 1.1 mrg TARGET_CPU_cortexm4, 3303 1.1 mrg }, 3304 1.1 mrg { 3305 1.1 mrg "armv8-a", 3306 1.1 mrg arch_opttab_armv8_a, 3307 1.1 mrg { 3308 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3309 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3310 1.1 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_mode32, 3311 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp, 3312 1.1 mrg isa_bit_sec, isa_bit_armv3m, isa_nobit 3313 1.1 mrg }, 3314 1.1 mrg "8A", BASE_ARCH_8A, 3315 1.1 mrg 'A', 3316 1.1 mrg TARGET_CPU_cortexa53, 3317 1.1 mrg }, 3318 1.1 mrg { 3319 1.1 mrg "armv8.1-a", 3320 1.1 mrg arch_opttab_armv8_1_a, 3321 1.1 mrg { 3322 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3323 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3324 1.1 mrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3325 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3326 1.1 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_bit_armv3m, 3327 1.1 mrg isa_nobit 3328 1.1 mrg }, 3329 1.1 mrg "8A", BASE_ARCH_8A, 3330 1.1 mrg 'A', 3331 1.1 mrg TARGET_CPU_cortexa53, 3332 1.1 mrg }, 3333 1.1 mrg { 3334 1.1 mrg "armv8.2-a", 3335 1.1 mrg arch_opttab_armv8_2_a, 3336 1.1 mrg { 3337 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3338 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3339 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3340 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3341 1.1 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3342 1.1 mrg isa_bit_armv3m, isa_nobit 3343 1.1 mrg }, 3344 1.1 mrg "8A", BASE_ARCH_8A, 3345 1.1 mrg 'A', 3346 1.1 mrg TARGET_CPU_cortexa53, 3347 1.1 mrg }, 3348 1.1 mrg { 3349 1.1 mrg "armv8.3-a", 3350 1.1 mrg arch_opttab_armv8_3_a, 3351 1.1 mrg { 3352 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3353 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3354 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3355 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3356 1.1 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_mp, 3357 1.1 mrg isa_bit_sec, isa_bit_armv3m, isa_nobit 3358 1.1 mrg }, 3359 1.1 mrg "8A", BASE_ARCH_8A, 3360 1.1 mrg 'A', 3361 1.1 mrg TARGET_CPU_cortexa53, 3362 1.1 mrg }, 3363 1.1 mrg { 3364 1.1 mrg "armv8.4-a", 3365 1.1 mrg arch_opttab_armv8_4_a, 3366 1.1 mrg { 3367 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3368 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3369 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3370 1.1 mrg isa_bit_mode32, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3371 1.1 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, 3372 1.1 mrg isa_bit_mp, isa_bit_sec, isa_bit_armv3m, isa_nobit 3373 1.1 mrg }, 3374 1.1 mrg "8A", BASE_ARCH_8A, 3375 1.1 mrg 'A', 3376 1.1 mrg TARGET_CPU_cortexa53, 3377 1.1 mrg }, 3378 1.1 mrg { 3379 1.1 mrg "armv8-m.base", 3380 1.1 mrg NULL, 3381 1.1 mrg { 3382 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3383 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv8, isa_bit_cmse, 3384 1.1 mrg isa_bit_tdiv, isa_bit_mode32, isa_bit_armv3m, isa_nobit 3385 1.1 mrg }, 3386 1.1 mrg "8M_BASE", BASE_ARCH_8M_BASE, 3387 1.1 mrg 'M', 3388 1.1 mrg TARGET_CPU_cortexm23, 3389 1.1 mrg }, 3390 1.1 mrg { 3391 1.1 mrg "armv8-m.main", 3392 1.1 mrg arch_opttab_armv8_m_main, 3393 1.1 mrg { 3394 1.1 mrg isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, isa_bit_armv4, 3395 1.1 mrg isa_bit_armv5, isa_bit_armv6, isa_bit_armv7, isa_bit_armv8, 3396 1.1 mrg isa_bit_cmse, isa_bit_tdiv, isa_bit_mode32, isa_bit_thumb2, 3397 1.1 mrg isa_bit_armv3m, isa_nobit 3398 1.1 mrg }, 3399 1.1 mrg "8M_MAIN", BASE_ARCH_8M_MAIN, 3400 1.1 mrg 'M', 3401 1.1 mrg TARGET_CPU_cortexm7, 3402 1.1 mrg }, 3403 1.1 mrg { 3404 1.1 mrg "armv8-r", 3405 1.1 mrg arch_opttab_armv8_r, 3406 1.1 mrg { 3407 1.1 mrg isa_bit_adiv, isa_bit_armv5e, isa_bit_thumb, isa_bit_be8, 3408 1.1 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_armv5, isa_bit_armv6, 3409 1.1 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_mode32, 3410 1.1 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_bit_mp, 3411 1.1 mrg isa_bit_sec, isa_bit_armv3m, isa_nobit 3412 1.1 mrg }, 3413 1.1 mrg "8R", BASE_ARCH_8R, 3414 1.1 mrg 'R', 3415 1.1 mrg TARGET_CPU_cortexr52, 3416 1.1 mrg }, 3417 1.1 mrg { 3418 1.1 mrg "iwmmxt", 3419 1.1 mrg NULL, 3420 1.1 mrg { 3421 1.1 mrg isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb, 3422 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_notm, 3423 1.1 mrg isa_bit_armv3m, isa_nobit 3424 1.1 mrg }, 3425 1.1 mrg "5TE", BASE_ARCH_5TE, 3426 1.1 mrg 0, 3427 1.1 mrg TARGET_CPU_iwmmxt, 3428 1.1 mrg }, 3429 1.1 mrg { 3430 1.1 mrg "iwmmxt2", 3431 1.1 mrg NULL, 3432 1.1 mrg { 3433 1.1 mrg isa_bit_armv5e, isa_bit_iwmmxt, isa_bit_xscale, isa_bit_thumb, 3434 1.1 mrg isa_bit_armv4, isa_bit_armv5, isa_bit_mode32, isa_bit_iwmmxt2, 3435 1.1 mrg isa_bit_notm, isa_bit_armv3m, isa_nobit 3436 1.1 mrg }, 3437 1.1 mrg "5TE", BASE_ARCH_5TE, 3438 1.1 mrg 0, 3439 1.1 mrg TARGET_CPU_iwmmxt2, 3440 1.1 mrg }, 3441 1.1 mrg {{NULL, NULL, {isa_nobit}}, 3442 1.1 mrg NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none} 3443 1.1 mrg }; 3444 1.1 mrg 3445 1.1 mrg const arm_fpu_desc all_fpus[] = 3446 1.1 mrg { 3447 1.1 mrg { 3448 1.1 mrg "vfp", 3449 1.1 mrg { 3450 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3451 1.1 mrg } 3452 1.1 mrg }, 3453 1.1 mrg { 3454 1.1 mrg "vfpv2", 3455 1.1 mrg { 3456 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3457 1.1 mrg } 3458 1.1 mrg }, 3459 1.1 mrg { 3460 1.1 mrg "vfpv3", 3461 1.1 mrg { 3462 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3463 1.1 mrg isa_nobit 3464 1.1 mrg } 3465 1.1 mrg }, 3466 1.1 mrg { 3467 1.1 mrg "vfpv3-fp16", 3468 1.1 mrg { 3469 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 3470 1.1 mrg isa_bit_fp_dbl, isa_nobit 3471 1.1 mrg } 3472 1.1 mrg }, 3473 1.1 mrg { 3474 1.1 mrg "vfpv3-d16", 3475 1.1 mrg { 3476 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 3477 1.1 mrg } 3478 1.1 mrg }, 3479 1.1 mrg { 3480 1.1 mrg "vfpv3-d16-fp16", 3481 1.1 mrg { 3482 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 3483 1.1 mrg isa_nobit 3484 1.1 mrg } 3485 1.1 mrg }, 3486 1.1 mrg { 3487 1.1 mrg "vfpv3xd", 3488 1.1 mrg { 3489 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 3490 1.1 mrg } 3491 1.1 mrg }, 3492 1.1 mrg { 3493 1.1 mrg "vfpv3xd-fp16", 3494 1.1 mrg { 3495 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 3496 1.1 mrg } 3497 1.1 mrg }, 3498 1.1 mrg { 3499 1.1 mrg "neon", 3500 1.1 mrg { 3501 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3502 1.1 mrg isa_bit_fp_dbl, isa_nobit 3503 1.1 mrg } 3504 1.1 mrg }, 3505 1.1 mrg { 3506 1.1 mrg "neon-vfpv3", 3507 1.1 mrg { 3508 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3509 1.1 mrg isa_bit_fp_dbl, isa_nobit 3510 1.1 mrg } 3511 1.1 mrg }, 3512 1.1 mrg { 3513 1.1 mrg "neon-fp16", 3514 1.1 mrg { 3515 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3516 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3517 1.1 mrg } 3518 1.1 mrg }, 3519 1.1 mrg { 3520 1.1 mrg "vfpv4", 3521 1.1 mrg { 3522 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 3523 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3524 1.1 mrg } 3525 1.1 mrg }, 3526 1.1 mrg { 3527 1.1 mrg "neon-vfpv4", 3528 1.1 mrg { 3529 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3530 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3531 1.1 mrg } 3532 1.1 mrg }, 3533 1.1 mrg { 3534 1.1 mrg "vfpv4-d16", 3535 1.1 mrg { 3536 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3537 1.1 mrg isa_bit_fp_dbl, isa_nobit 3538 1.1 mrg } 3539 1.1 mrg }, 3540 1.1 mrg { 3541 1.1 mrg "fpv4-sp-d16", 3542 1.1 mrg { 3543 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3544 1.1 mrg isa_nobit 3545 1.1 mrg } 3546 1.1 mrg }, 3547 1.1 mrg { 3548 1.1 mrg "fpv5-sp-d16", 3549 1.1 mrg { 3550 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3551 1.1 mrg isa_bit_fp16conv, isa_nobit 3552 1.1 mrg } 3553 1.1 mrg }, 3554 1.1 mrg { 3555 1.1 mrg "fpv5-d16", 3556 1.1 mrg { 3557 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3558 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3559 1.1 mrg } 3560 1.1 mrg }, 3561 1.1 mrg { 3562 1.1 mrg "fp-armv8", 3563 1.1 mrg { 3564 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3565 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3566 1.1 mrg } 3567 1.1 mrg }, 3568 1.1 mrg { 3569 1.1 mrg "neon-fp-armv8", 3570 1.1 mrg { 3571 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3572 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 3573 1.1 mrg isa_nobit 3574 1.1 mrg } 3575 1.1 mrg }, 3576 1.1 mrg { 3577 1.1 mrg "crypto-neon-fp-armv8", 3578 1.1 mrg { 3579 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3580 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 3581 1.1 mrg isa_bit_fp_dbl, isa_nobit 3582 1.1 mrg } 3583 1.1 mrg }, 3584 1.1 mrg { 3585 1.1 mrg "vfp3", 3586 1.1 mrg { 3587 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3588 1.1 mrg isa_nobit 3589 1.1 mrg } 3590 1.1 mrg }, 3591 1.1 mrg }; 3592
Indexes created Sat Apr 11 00:22:22 UTC 2026