arm-cpu-cdata.h revision 1.1.1.2
1 1.1 mrg /* This file is automatically generated. DO NOT EDIT! */ 2 1.1.1.2 mrg /* Generated from: NetBSD: mknative-gcc,v 1.108 2020/09/05 10:58:08 mrg Exp */ 3 1.1 mrg /* Generated from: NetBSD: mknative.common,v 1.16 2018/04/15 15:13:37 christos Exp */ 4 1.1 mrg 5 1.1 mrg /* -*- buffer-read-only: t -*- 6 1.1 mrg Generated automatically by parsecpu.awk from arm-cpus.in. 7 1.1 mrg Do not edit. 8 1.1 mrg 9 1.1.1.2 mrg Copyright (C) 2011-2019 Free Software Foundation, Inc. 10 1.1 mrg 11 1.1 mrg This file is part of GCC. 12 1.1 mrg 13 1.1 mrg GCC is free software; you can redistribute it and/or modify 14 1.1 mrg it under the terms of the GNU General Public License as 15 1.1 mrg published by the Free Software Foundation; either version 3, 16 1.1 mrg or (at your option) any later version. 17 1.1 mrg 18 1.1 mrg GCC is distributed in the hope that it will be useful, 19 1.1 mrg but WITHOUT ANY WARRANTY; without even the implied warranty of 20 1.1 mrg MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21 1.1 mrg GNU General Public License for more details. 22 1.1 mrg 23 1.1 mrg You should have received a copy of the GNU General Public 24 1.1 mrg License along with GCC; see the file COPYING3. If not see 25 1.1 mrg <http://www.gnu.org/licenses/>. */ 26 1.1 mrg 27 1.1.1.2 mrg static const cpu_alias cpu_aliastab_strongarm[] = { 28 1.1.1.2 mrg { "strongarm110", true}, 29 1.1.1.2 mrg { "strongarm1100", false}, 30 1.1.1.2 mrg { "strongarm1110", false}, 31 1.1.1.2 mrg { NULL, false} 32 1.1 mrg }; 33 1.1 mrg 34 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm7tdmi[] = { 35 1.1.1.2 mrg { "arm7tdmi-s", true}, 36 1.1.1.2 mrg { NULL, false} 37 1.1 mrg }; 38 1.1 mrg 39 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm710t[] = { 40 1.1.1.2 mrg { "arm720t", true}, 41 1.1.1.2 mrg { "arm740t", true}, 42 1.1.1.2 mrg { NULL, false} 43 1.1 mrg }; 44 1.1 mrg 45 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm920t[] = { 46 1.1.1.2 mrg { "arm920", true}, 47 1.1.1.2 mrg { "arm922t", true}, 48 1.1.1.2 mrg { "arm940t", true}, 49 1.1.1.2 mrg { "ep9312", true}, 50 1.1.1.2 mrg { NULL, false} 51 1.1 mrg }; 52 1.1 mrg 53 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm10tdmi[] = { 54 1.1.1.2 mrg { "arm1020t", true}, 55 1.1.1.2 mrg { NULL, false} 56 1.1 mrg }; 57 1.1 mrg 58 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_arm9e[] = { 59 1.1 mrg { 60 1.1 mrg "nofp", true, false, 61 1.1 mrg { 62 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 63 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 64 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 65 1.1 mrg } 66 1.1 mrg }, 67 1.1 mrg { NULL, false, false, {isa_nobit}} 68 1.1 mrg }; 69 1.1 mrg 70 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm9e[] = { 71 1.1.1.2 mrg { "arm946e-s", true}, 72 1.1.1.2 mrg { "arm966e-s", true}, 73 1.1.1.2 mrg { "arm968e-s", true}, 74 1.1.1.2 mrg { NULL, false} 75 1.1.1.2 mrg }; 76 1.1.1.2 mrg 77 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_arm10e[] = { 78 1.1 mrg { 79 1.1 mrg "nofp", true, false, 80 1.1 mrg { 81 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 82 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 83 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 84 1.1 mrg } 85 1.1 mrg }, 86 1.1 mrg { NULL, false, false, {isa_nobit}} 87 1.1 mrg }; 88 1.1 mrg 89 1.1.1.2 mrg static const cpu_alias cpu_aliastab_arm10e[] = { 90 1.1.1.2 mrg { "arm1020e", true}, 91 1.1.1.2 mrg { "arm1022e", true}, 92 1.1.1.2 mrg { NULL, false} 93 1.1.1.2 mrg }; 94 1.1.1.2 mrg 95 1.1 mrg static const cpu_arch_extension cpu_opttab_arm926ejs[] = { 96 1.1 mrg { 97 1.1 mrg "nofp", true, false, 98 1.1 mrg { 99 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 100 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 101 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 102 1.1 mrg } 103 1.1 mrg }, 104 1.1 mrg { NULL, false, false, {isa_nobit}} 105 1.1 mrg }; 106 1.1 mrg 107 1.1 mrg static const cpu_arch_extension cpu_opttab_arm1026ejs[] = { 108 1.1 mrg { 109 1.1 mrg "nofp", true, false, 110 1.1 mrg { 111 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 112 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 113 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 114 1.1 mrg } 115 1.1 mrg }, 116 1.1 mrg { NULL, false, false, {isa_nobit}} 117 1.1 mrg }; 118 1.1 mrg 119 1.1 mrg static const cpu_arch_extension cpu_opttab_genericv7a[] = { 120 1.1 mrg { 121 1.1 mrg "mp", false, false, 122 1.1 mrg { 123 1.1 mrg isa_bit_mp, isa_nobit 124 1.1 mrg } 125 1.1 mrg }, 126 1.1 mrg { 127 1.1 mrg "sec", false, false, 128 1.1 mrg { 129 1.1 mrg isa_bit_sec, isa_nobit 130 1.1 mrg } 131 1.1 mrg }, 132 1.1 mrg { 133 1.1 mrg "vfpv3-d16", false, false, 134 1.1 mrg { 135 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 136 1.1 mrg } 137 1.1 mrg }, 138 1.1 mrg { 139 1.1 mrg "vfpv3", false, false, 140 1.1 mrg { 141 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 142 1.1 mrg isa_nobit 143 1.1 mrg } 144 1.1 mrg }, 145 1.1 mrg { 146 1.1 mrg "vfpv3-d16-fp16", false, false, 147 1.1 mrg { 148 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 149 1.1 mrg isa_nobit 150 1.1 mrg } 151 1.1 mrg }, 152 1.1 mrg { 153 1.1 mrg "vfpv3-fp16", false, false, 154 1.1 mrg { 155 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 156 1.1 mrg isa_bit_fp_dbl, isa_nobit 157 1.1 mrg } 158 1.1 mrg }, 159 1.1 mrg { 160 1.1 mrg "vfpv4-d16", false, false, 161 1.1 mrg { 162 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 163 1.1 mrg isa_bit_fp_dbl, isa_nobit 164 1.1 mrg } 165 1.1 mrg }, 166 1.1 mrg { 167 1.1 mrg "vfpv4", false, false, 168 1.1 mrg { 169 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 170 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 171 1.1 mrg } 172 1.1 mrg }, 173 1.1 mrg { 174 1.1 mrg "simd", false, false, 175 1.1 mrg { 176 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 177 1.1 mrg isa_bit_fp_dbl, isa_nobit 178 1.1 mrg } 179 1.1 mrg }, 180 1.1 mrg { 181 1.1 mrg "neon-fp16", false, false, 182 1.1 mrg { 183 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 184 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 185 1.1 mrg } 186 1.1 mrg }, 187 1.1 mrg { 188 1.1 mrg "neon-vfpv4", false, false, 189 1.1 mrg { 190 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 191 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 192 1.1 mrg } 193 1.1 mrg }, 194 1.1 mrg { 195 1.1 mrg "nosimd", true, false, 196 1.1 mrg { 197 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 198 1.1 mrg isa_bit_crypto, isa_nobit 199 1.1 mrg } 200 1.1 mrg }, 201 1.1 mrg { 202 1.1 mrg "nofp", true, false, 203 1.1 mrg { 204 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 205 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 206 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 207 1.1 mrg } 208 1.1 mrg }, 209 1.1 mrg { 210 1.1 mrg "neon", false, true, 211 1.1 mrg { 212 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 213 1.1 mrg isa_bit_fp_dbl, isa_nobit 214 1.1 mrg } 215 1.1 mrg }, 216 1.1 mrg { 217 1.1 mrg "neon-vfpv3", false, true, 218 1.1 mrg { 219 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 220 1.1 mrg isa_bit_fp_dbl, isa_nobit 221 1.1 mrg } 222 1.1 mrg }, 223 1.1 mrg { NULL, false, false, {isa_nobit}} 224 1.1 mrg }; 225 1.1 mrg 226 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa5[] = { 227 1.1 mrg { 228 1.1 mrg "nosimd", true, false, 229 1.1 mrg { 230 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 231 1.1 mrg isa_bit_crypto, isa_nobit 232 1.1 mrg } 233 1.1 mrg }, 234 1.1 mrg { 235 1.1 mrg "nofp", true, false, 236 1.1 mrg { 237 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 238 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 239 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 240 1.1 mrg } 241 1.1 mrg }, 242 1.1 mrg { NULL, false, false, {isa_nobit}} 243 1.1 mrg }; 244 1.1 mrg 245 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa7[] = { 246 1.1 mrg { 247 1.1 mrg "nosimd", true, false, 248 1.1 mrg { 249 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 250 1.1 mrg isa_bit_crypto, isa_nobit 251 1.1 mrg } 252 1.1 mrg }, 253 1.1 mrg { 254 1.1 mrg "nofp", true, false, 255 1.1 mrg { 256 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 257 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 258 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 259 1.1 mrg } 260 1.1 mrg }, 261 1.1 mrg { NULL, false, false, {isa_nobit}} 262 1.1 mrg }; 263 1.1 mrg 264 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa8[] = { 265 1.1 mrg { 266 1.1 mrg "nofp", true, false, 267 1.1 mrg { 268 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 269 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 270 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 271 1.1 mrg } 272 1.1 mrg }, 273 1.1 mrg { NULL, false, false, {isa_nobit}} 274 1.1 mrg }; 275 1.1 mrg 276 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa9[] = { 277 1.1 mrg { 278 1.1 mrg "nosimd", true, false, 279 1.1 mrg { 280 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 281 1.1 mrg isa_bit_crypto, isa_nobit 282 1.1 mrg } 283 1.1 mrg }, 284 1.1 mrg { 285 1.1 mrg "nofp", true, false, 286 1.1 mrg { 287 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 288 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 289 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 290 1.1 mrg } 291 1.1 mrg }, 292 1.1 mrg { NULL, false, false, {isa_nobit}} 293 1.1 mrg }; 294 1.1 mrg 295 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa12[] = { 296 1.1 mrg { 297 1.1 mrg "nofp", true, false, 298 1.1 mrg { 299 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 300 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 301 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 302 1.1 mrg } 303 1.1 mrg }, 304 1.1 mrg { NULL, false, false, {isa_nobit}} 305 1.1 mrg }; 306 1.1 mrg 307 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa15[] = { 308 1.1 mrg { 309 1.1 mrg "nofp", true, false, 310 1.1 mrg { 311 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 312 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 313 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 314 1.1 mrg } 315 1.1 mrg }, 316 1.1 mrg { NULL, false, false, {isa_nobit}} 317 1.1 mrg }; 318 1.1 mrg 319 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa17[] = { 320 1.1 mrg { 321 1.1 mrg "nofp", true, false, 322 1.1 mrg { 323 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 324 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 325 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 326 1.1 mrg } 327 1.1 mrg }, 328 1.1 mrg { NULL, false, false, {isa_nobit}} 329 1.1 mrg }; 330 1.1 mrg 331 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr5[] = { 332 1.1 mrg { 333 1.1 mrg "nofp.dp", true, false, 334 1.1 mrg { 335 1.1 mrg isa_bit_fp_dbl, isa_nobit 336 1.1 mrg } 337 1.1 mrg }, 338 1.1 mrg { 339 1.1 mrg "nofp", true, false, 340 1.1 mrg { 341 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 342 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 343 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 344 1.1 mrg } 345 1.1 mrg }, 346 1.1 mrg { NULL, false, false, {isa_nobit}} 347 1.1 mrg }; 348 1.1 mrg 349 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr7[] = { 350 1.1 mrg { 351 1.1 mrg "nofp.dp", true, false, 352 1.1 mrg { 353 1.1 mrg isa_bit_fp_dbl, isa_nobit 354 1.1 mrg } 355 1.1 mrg }, 356 1.1 mrg { 357 1.1 mrg "nofp", true, false, 358 1.1 mrg { 359 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 360 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 361 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 362 1.1 mrg } 363 1.1 mrg }, 364 1.1 mrg { NULL, false, false, {isa_nobit}} 365 1.1 mrg }; 366 1.1 mrg 367 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr8[] = { 368 1.1 mrg { 369 1.1 mrg "nofp.dp", true, false, 370 1.1 mrg { 371 1.1 mrg isa_bit_fp_dbl, isa_nobit 372 1.1 mrg } 373 1.1 mrg }, 374 1.1 mrg { 375 1.1 mrg "nofp", true, false, 376 1.1 mrg { 377 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 378 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 379 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 380 1.1 mrg } 381 1.1 mrg }, 382 1.1 mrg { NULL, false, false, {isa_nobit}} 383 1.1 mrg }; 384 1.1 mrg 385 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm7[] = { 386 1.1 mrg { 387 1.1 mrg "nofp.dp", true, false, 388 1.1 mrg { 389 1.1 mrg isa_bit_fp_dbl, isa_nobit 390 1.1 mrg } 391 1.1 mrg }, 392 1.1 mrg { 393 1.1 mrg "nofp", true, false, 394 1.1 mrg { 395 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 396 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 397 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 398 1.1 mrg } 399 1.1 mrg }, 400 1.1 mrg { NULL, false, false, {isa_nobit}} 401 1.1 mrg }; 402 1.1 mrg 403 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm4[] = { 404 1.1 mrg { 405 1.1 mrg "nofp", true, false, 406 1.1 mrg { 407 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 408 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 409 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 410 1.1 mrg } 411 1.1 mrg }, 412 1.1 mrg { NULL, false, false, {isa_nobit}} 413 1.1 mrg }; 414 1.1 mrg 415 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa15cortexa7[] = { 416 1.1 mrg { 417 1.1 mrg "nofp", true, false, 418 1.1 mrg { 419 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 420 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 421 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 422 1.1 mrg } 423 1.1 mrg }, 424 1.1 mrg { NULL, false, false, {isa_nobit}} 425 1.1 mrg }; 426 1.1 mrg 427 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa17cortexa7[] = { 428 1.1 mrg { 429 1.1 mrg "nofp", true, false, 430 1.1 mrg { 431 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 432 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 433 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 434 1.1 mrg } 435 1.1 mrg }, 436 1.1 mrg { NULL, false, false, {isa_nobit}} 437 1.1 mrg }; 438 1.1 mrg 439 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa32[] = { 440 1.1 mrg { 441 1.1 mrg "crypto", false, false, 442 1.1 mrg { 443 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 444 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 445 1.1 mrg isa_bit_fp_dbl, isa_nobit 446 1.1 mrg } 447 1.1 mrg }, 448 1.1 mrg { 449 1.1 mrg "nofp", true, false, 450 1.1 mrg { 451 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 452 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 453 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 454 1.1 mrg } 455 1.1 mrg }, 456 1.1 mrg { NULL, false, false, {isa_nobit}} 457 1.1 mrg }; 458 1.1 mrg 459 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa35[] = { 460 1.1 mrg { 461 1.1 mrg "crypto", false, false, 462 1.1 mrg { 463 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 464 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 465 1.1 mrg isa_bit_fp_dbl, isa_nobit 466 1.1 mrg } 467 1.1 mrg }, 468 1.1 mrg { 469 1.1 mrg "nofp", true, false, 470 1.1 mrg { 471 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 472 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 473 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 474 1.1 mrg } 475 1.1 mrg }, 476 1.1 mrg { NULL, false, false, {isa_nobit}} 477 1.1 mrg }; 478 1.1 mrg 479 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa53[] = { 480 1.1 mrg { 481 1.1 mrg "crypto", false, false, 482 1.1 mrg { 483 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 484 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 485 1.1 mrg isa_bit_fp_dbl, isa_nobit 486 1.1 mrg } 487 1.1 mrg }, 488 1.1 mrg { 489 1.1 mrg "nofp", true, false, 490 1.1 mrg { 491 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 492 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 493 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 494 1.1 mrg } 495 1.1 mrg }, 496 1.1 mrg { NULL, false, false, {isa_nobit}} 497 1.1 mrg }; 498 1.1 mrg 499 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa57[] = { 500 1.1 mrg { 501 1.1 mrg "crypto", false, false, 502 1.1 mrg { 503 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 504 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 505 1.1 mrg isa_bit_fp_dbl, isa_nobit 506 1.1 mrg } 507 1.1 mrg }, 508 1.1 mrg { NULL, false, false, {isa_nobit}} 509 1.1 mrg }; 510 1.1 mrg 511 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa72[] = { 512 1.1 mrg { 513 1.1 mrg "crypto", false, false, 514 1.1 mrg { 515 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 516 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 517 1.1 mrg isa_bit_fp_dbl, isa_nobit 518 1.1 mrg } 519 1.1 mrg }, 520 1.1 mrg { NULL, false, false, {isa_nobit}} 521 1.1 mrg }; 522 1.1 mrg 523 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73[] = { 524 1.1 mrg { 525 1.1 mrg "crypto", false, false, 526 1.1 mrg { 527 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 528 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 529 1.1 mrg isa_bit_fp_dbl, isa_nobit 530 1.1 mrg } 531 1.1 mrg }, 532 1.1 mrg { NULL, false, false, {isa_nobit}} 533 1.1 mrg }; 534 1.1 mrg 535 1.1 mrg static const cpu_arch_extension cpu_opttab_exynosm1[] = { 536 1.1 mrg { 537 1.1 mrg "crypto", false, false, 538 1.1 mrg { 539 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 540 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 541 1.1 mrg isa_bit_fp_dbl, isa_nobit 542 1.1 mrg } 543 1.1 mrg }, 544 1.1 mrg { NULL, false, false, {isa_nobit}} 545 1.1 mrg }; 546 1.1 mrg 547 1.1 mrg static const cpu_arch_extension cpu_opttab_xgene1[] = { 548 1.1 mrg { 549 1.1 mrg "crypto", false, false, 550 1.1 mrg { 551 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 552 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 553 1.1 mrg isa_bit_fp_dbl, isa_nobit 554 1.1 mrg } 555 1.1 mrg }, 556 1.1 mrg { NULL, false, false, {isa_nobit}} 557 1.1 mrg }; 558 1.1 mrg 559 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa57cortexa53[] = { 560 1.1 mrg { 561 1.1 mrg "crypto", false, false, 562 1.1 mrg { 563 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 564 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 565 1.1 mrg isa_bit_fp_dbl, isa_nobit 566 1.1 mrg } 567 1.1 mrg }, 568 1.1 mrg { NULL, false, false, {isa_nobit}} 569 1.1 mrg }; 570 1.1 mrg 571 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa72cortexa53[] = { 572 1.1 mrg { 573 1.1 mrg "crypto", false, false, 574 1.1 mrg { 575 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 576 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 577 1.1 mrg isa_bit_fp_dbl, isa_nobit 578 1.1 mrg } 579 1.1 mrg }, 580 1.1 mrg { NULL, false, false, {isa_nobit}} 581 1.1 mrg }; 582 1.1 mrg 583 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa35[] = { 584 1.1 mrg { 585 1.1 mrg "crypto", false, false, 586 1.1 mrg { 587 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 588 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 589 1.1 mrg isa_bit_fp_dbl, isa_nobit 590 1.1 mrg } 591 1.1 mrg }, 592 1.1 mrg { NULL, false, false, {isa_nobit}} 593 1.1 mrg }; 594 1.1 mrg 595 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa73cortexa53[] = { 596 1.1 mrg { 597 1.1 mrg "crypto", false, false, 598 1.1 mrg { 599 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 600 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 601 1.1 mrg isa_bit_fp_dbl, isa_nobit 602 1.1 mrg } 603 1.1 mrg }, 604 1.1 mrg { NULL, false, false, {isa_nobit}} 605 1.1 mrg }; 606 1.1 mrg 607 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa55[] = { 608 1.1 mrg { 609 1.1 mrg "crypto", false, false, 610 1.1 mrg { 611 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 612 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 613 1.1 mrg isa_bit_fp_dbl, isa_nobit 614 1.1 mrg } 615 1.1 mrg }, 616 1.1 mrg { 617 1.1 mrg "nofp", true, false, 618 1.1 mrg { 619 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 620 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 621 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 622 1.1 mrg } 623 1.1 mrg }, 624 1.1 mrg { NULL, false, false, {isa_nobit}} 625 1.1 mrg }; 626 1.1 mrg 627 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa75[] = { 628 1.1 mrg { 629 1.1 mrg "crypto", false, false, 630 1.1 mrg { 631 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 632 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 633 1.1 mrg isa_bit_fp_dbl, isa_nobit 634 1.1 mrg } 635 1.1 mrg }, 636 1.1 mrg { NULL, false, false, {isa_nobit}} 637 1.1 mrg }; 638 1.1 mrg 639 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_cortexa76[] = { 640 1.1.1.2 mrg { 641 1.1.1.2 mrg "crypto", false, false, 642 1.1.1.2 mrg { 643 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 644 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 645 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 646 1.1.1.2 mrg } 647 1.1.1.2 mrg }, 648 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 649 1.1.1.2 mrg }; 650 1.1.1.2 mrg 651 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_neoversen1[] = { 652 1.1.1.2 mrg { 653 1.1.1.2 mrg "crypto", false, false, 654 1.1.1.2 mrg { 655 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 656 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 657 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 658 1.1.1.2 mrg } 659 1.1.1.2 mrg }, 660 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 661 1.1.1.2 mrg }; 662 1.1.1.2 mrg 663 1.1.1.2 mrg static const cpu_alias cpu_aliastab_neoversen1[] = { 664 1.1.1.2 mrg { "ares", false}, 665 1.1.1.2 mrg { NULL, false} 666 1.1.1.2 mrg }; 667 1.1.1.2 mrg 668 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexa75cortexa55[] = { 669 1.1 mrg { 670 1.1 mrg "crypto", false, false, 671 1.1 mrg { 672 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 673 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 674 1.1 mrg isa_bit_fp_dbl, isa_nobit 675 1.1 mrg } 676 1.1 mrg }, 677 1.1 mrg { NULL, false, false, {isa_nobit}} 678 1.1 mrg }; 679 1.1 mrg 680 1.1.1.2 mrg static const cpu_arch_extension cpu_opttab_cortexa76cortexa55[] = { 681 1.1.1.2 mrg { 682 1.1.1.2 mrg "crypto", false, false, 683 1.1.1.2 mrg { 684 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 685 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 686 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 687 1.1.1.2 mrg } 688 1.1.1.2 mrg }, 689 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 690 1.1.1.2 mrg }; 691 1.1.1.2 mrg 692 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexm33[] = { 693 1.1 mrg { 694 1.1 mrg "nofp", true, false, 695 1.1 mrg { 696 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 697 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 698 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 699 1.1 mrg } 700 1.1 mrg }, 701 1.1 mrg { 702 1.1 mrg "nodsp", true, false, 703 1.1 mrg { 704 1.1 mrg isa_bit_armv7em, isa_nobit 705 1.1 mrg } 706 1.1 mrg }, 707 1.1 mrg { NULL, false, false, {isa_nobit}} 708 1.1 mrg }; 709 1.1 mrg 710 1.1 mrg static const cpu_arch_extension cpu_opttab_cortexr52[] = { 711 1.1 mrg { 712 1.1 mrg "nofp.dp", true, false, 713 1.1 mrg { 714 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 715 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 716 1.1 mrg } 717 1.1 mrg }, 718 1.1 mrg { NULL, false, false, {isa_nobit}} 719 1.1 mrg }; 720 1.1 mrg 721 1.1 mrg const cpu_option all_cores[] = 722 1.1 mrg { 723 1.1 mrg { 724 1.1 mrg { 725 1.1 mrg "arm8", 726 1.1 mrg NULL, 727 1.1 mrg { 728 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 729 1.1 mrg } 730 1.1 mrg }, 731 1.1.1.2 mrg NULL, 732 1.1 mrg TARGET_ARCH_armv4 733 1.1 mrg }, 734 1.1 mrg { 735 1.1 mrg { 736 1.1 mrg "arm810", 737 1.1 mrg NULL, 738 1.1 mrg { 739 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 740 1.1 mrg } 741 1.1 mrg }, 742 1.1.1.2 mrg NULL, 743 1.1 mrg TARGET_ARCH_armv4 744 1.1 mrg }, 745 1.1 mrg { 746 1.1 mrg { 747 1.1 mrg "strongarm", 748 1.1 mrg NULL, 749 1.1 mrg { 750 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 751 1.1 mrg } 752 1.1 mrg }, 753 1.1.1.2 mrg cpu_aliastab_strongarm, 754 1.1 mrg TARGET_ARCH_armv4 755 1.1 mrg }, 756 1.1 mrg { 757 1.1 mrg { 758 1.1 mrg "fa526", 759 1.1 mrg NULL, 760 1.1 mrg { 761 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 762 1.1 mrg } 763 1.1 mrg }, 764 1.1.1.2 mrg NULL, 765 1.1 mrg TARGET_ARCH_armv4 766 1.1 mrg }, 767 1.1 mrg { 768 1.1 mrg { 769 1.1 mrg "fa626", 770 1.1 mrg NULL, 771 1.1 mrg { 772 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 773 1.1 mrg } 774 1.1 mrg }, 775 1.1.1.2 mrg NULL, 776 1.1 mrg TARGET_ARCH_armv4 777 1.1 mrg }, 778 1.1 mrg { 779 1.1 mrg { 780 1.1 mrg "arm7tdmi", 781 1.1 mrg NULL, 782 1.1 mrg { 783 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 784 1.1 mrg } 785 1.1 mrg }, 786 1.1.1.2 mrg cpu_aliastab_arm7tdmi, 787 1.1 mrg TARGET_ARCH_armv4t 788 1.1 mrg }, 789 1.1 mrg { 790 1.1 mrg { 791 1.1 mrg "arm710t", 792 1.1 mrg NULL, 793 1.1 mrg { 794 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 795 1.1 mrg } 796 1.1 mrg }, 797 1.1.1.2 mrg cpu_aliastab_arm710t, 798 1.1 mrg TARGET_ARCH_armv4t 799 1.1 mrg }, 800 1.1 mrg { 801 1.1 mrg { 802 1.1 mrg "arm9", 803 1.1 mrg NULL, 804 1.1 mrg { 805 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 806 1.1 mrg } 807 1.1 mrg }, 808 1.1.1.2 mrg NULL, 809 1.1 mrg TARGET_ARCH_armv4t 810 1.1 mrg }, 811 1.1 mrg { 812 1.1 mrg { 813 1.1 mrg "arm9tdmi", 814 1.1 mrg NULL, 815 1.1 mrg { 816 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 817 1.1 mrg } 818 1.1 mrg }, 819 1.1.1.2 mrg NULL, 820 1.1 mrg TARGET_ARCH_armv4t 821 1.1 mrg }, 822 1.1 mrg { 823 1.1 mrg { 824 1.1 mrg "arm920t", 825 1.1 mrg NULL, 826 1.1 mrg { 827 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 828 1.1 mrg } 829 1.1 mrg }, 830 1.1.1.2 mrg cpu_aliastab_arm920t, 831 1.1 mrg TARGET_ARCH_armv4t 832 1.1 mrg }, 833 1.1 mrg { 834 1.1 mrg { 835 1.1 mrg "arm10tdmi", 836 1.1 mrg NULL, 837 1.1 mrg { 838 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 839 1.1.1.2 mrg isa_nobit 840 1.1 mrg } 841 1.1 mrg }, 842 1.1.1.2 mrg cpu_aliastab_arm10tdmi, 843 1.1 mrg TARGET_ARCH_armv5t 844 1.1 mrg }, 845 1.1 mrg { 846 1.1 mrg { 847 1.1 mrg "arm9e", 848 1.1 mrg cpu_opttab_arm9e, 849 1.1 mrg { 850 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 851 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 852 1.1 mrg } 853 1.1 mrg }, 854 1.1.1.2 mrg cpu_aliastab_arm9e, 855 1.1 mrg TARGET_ARCH_armv5te 856 1.1 mrg }, 857 1.1 mrg { 858 1.1 mrg { 859 1.1 mrg "arm10e", 860 1.1 mrg cpu_opttab_arm10e, 861 1.1 mrg { 862 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 863 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 864 1.1 mrg } 865 1.1 mrg }, 866 1.1.1.2 mrg cpu_aliastab_arm10e, 867 1.1 mrg TARGET_ARCH_armv5te 868 1.1 mrg }, 869 1.1 mrg { 870 1.1 mrg { 871 1.1 mrg "xscale", 872 1.1 mrg NULL, 873 1.1 mrg { 874 1.1.1.2 mrg isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, isa_bit_armv5t, 875 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 876 1.1 mrg } 877 1.1 mrg }, 878 1.1.1.2 mrg NULL, 879 1.1 mrg TARGET_ARCH_armv5te 880 1.1 mrg }, 881 1.1 mrg { 882 1.1 mrg { 883 1.1 mrg "iwmmxt", 884 1.1 mrg NULL, 885 1.1 mrg { 886 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 887 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 888 1.1 mrg } 889 1.1 mrg }, 890 1.1.1.2 mrg NULL, 891 1.1 mrg TARGET_ARCH_iwmmxt 892 1.1 mrg }, 893 1.1 mrg { 894 1.1 mrg { 895 1.1 mrg "iwmmxt2", 896 1.1 mrg NULL, 897 1.1 mrg { 898 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 899 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 900 1.1.1.2 mrg isa_nobit 901 1.1 mrg } 902 1.1 mrg }, 903 1.1.1.2 mrg NULL, 904 1.1 mrg TARGET_ARCH_iwmmxt2 905 1.1 mrg }, 906 1.1 mrg { 907 1.1 mrg { 908 1.1 mrg "fa606te", 909 1.1 mrg NULL, 910 1.1 mrg { 911 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 912 1.1.1.2 mrg isa_bit_notm, isa_nobit 913 1.1 mrg } 914 1.1 mrg }, 915 1.1.1.2 mrg NULL, 916 1.1 mrg TARGET_ARCH_armv5te 917 1.1 mrg }, 918 1.1 mrg { 919 1.1 mrg { 920 1.1 mrg "fa626te", 921 1.1 mrg NULL, 922 1.1 mrg { 923 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 924 1.1.1.2 mrg isa_bit_notm, isa_nobit 925 1.1 mrg } 926 1.1 mrg }, 927 1.1.1.2 mrg NULL, 928 1.1 mrg TARGET_ARCH_armv5te 929 1.1 mrg }, 930 1.1 mrg { 931 1.1 mrg { 932 1.1 mrg "fmp626", 933 1.1 mrg NULL, 934 1.1 mrg { 935 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 936 1.1.1.2 mrg isa_bit_notm, isa_nobit 937 1.1 mrg } 938 1.1 mrg }, 939 1.1.1.2 mrg NULL, 940 1.1 mrg TARGET_ARCH_armv5te 941 1.1 mrg }, 942 1.1 mrg { 943 1.1 mrg { 944 1.1 mrg "fa726te", 945 1.1 mrg NULL, 946 1.1 mrg { 947 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 948 1.1.1.2 mrg isa_bit_notm, isa_nobit 949 1.1 mrg } 950 1.1 mrg }, 951 1.1.1.2 mrg NULL, 952 1.1 mrg TARGET_ARCH_armv5te 953 1.1 mrg }, 954 1.1 mrg { 955 1.1 mrg { 956 1.1 mrg "arm926ej-s", 957 1.1 mrg cpu_opttab_arm926ejs, 958 1.1 mrg { 959 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 960 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 961 1.1 mrg } 962 1.1 mrg }, 963 1.1.1.2 mrg NULL, 964 1.1 mrg TARGET_ARCH_armv5tej 965 1.1 mrg }, 966 1.1 mrg { 967 1.1 mrg { 968 1.1 mrg "arm1026ej-s", 969 1.1 mrg cpu_opttab_arm1026ejs, 970 1.1 mrg { 971 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, 972 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_bit_fp_dbl, isa_nobit 973 1.1 mrg } 974 1.1 mrg }, 975 1.1.1.2 mrg NULL, 976 1.1 mrg TARGET_ARCH_armv5tej 977 1.1 mrg }, 978 1.1 mrg { 979 1.1 mrg { 980 1.1 mrg "arm1136j-s", 981 1.1 mrg NULL, 982 1.1 mrg { 983 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 984 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 985 1.1 mrg } 986 1.1 mrg }, 987 1.1.1.2 mrg NULL, 988 1.1 mrg TARGET_ARCH_armv6j 989 1.1 mrg }, 990 1.1 mrg { 991 1.1 mrg { 992 1.1 mrg "arm1136jf-s", 993 1.1 mrg NULL, 994 1.1 mrg { 995 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 996 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 997 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 998 1.1 mrg } 999 1.1 mrg }, 1000 1.1.1.2 mrg NULL, 1001 1.1 mrg TARGET_ARCH_armv6j 1002 1.1 mrg }, 1003 1.1 mrg { 1004 1.1 mrg { 1005 1.1 mrg "arm1176jz-s", 1006 1.1 mrg NULL, 1007 1.1 mrg { 1008 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1009 1.1.1.2 mrg isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 1010 1.1.1.2 mrg isa_bit_armv6k, isa_nobit 1011 1.1 mrg } 1012 1.1 mrg }, 1013 1.1.1.2 mrg NULL, 1014 1.1 mrg TARGET_ARCH_armv6kz 1015 1.1 mrg }, 1016 1.1 mrg { 1017 1.1 mrg { 1018 1.1 mrg "arm1176jzf-s", 1019 1.1 mrg NULL, 1020 1.1 mrg { 1021 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1022 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, 1023 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1024 1.1 mrg } 1025 1.1 mrg }, 1026 1.1.1.2 mrg NULL, 1027 1.1 mrg TARGET_ARCH_armv6kz 1028 1.1 mrg }, 1029 1.1 mrg { 1030 1.1 mrg { 1031 1.1 mrg "mpcorenovfp", 1032 1.1 mrg NULL, 1033 1.1 mrg { 1034 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1035 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 1036 1.1.1.2 mrg isa_nobit 1037 1.1 mrg } 1038 1.1 mrg }, 1039 1.1.1.2 mrg NULL, 1040 1.1 mrg TARGET_ARCH_armv6k 1041 1.1 mrg }, 1042 1.1 mrg { 1043 1.1 mrg { 1044 1.1 mrg "mpcore", 1045 1.1 mrg NULL, 1046 1.1 mrg { 1047 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1048 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_notm, 1049 1.1.1.2 mrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1050 1.1 mrg } 1051 1.1 mrg }, 1052 1.1.1.2 mrg NULL, 1053 1.1 mrg TARGET_ARCH_armv6k 1054 1.1 mrg }, 1055 1.1 mrg { 1056 1.1 mrg { 1057 1.1 mrg "arm1156t2-s", 1058 1.1 mrg NULL, 1059 1.1 mrg { 1060 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1061 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 1062 1.1.1.2 mrg isa_nobit 1063 1.1 mrg } 1064 1.1 mrg }, 1065 1.1.1.2 mrg NULL, 1066 1.1 mrg TARGET_ARCH_armv6t2 1067 1.1 mrg }, 1068 1.1 mrg { 1069 1.1 mrg { 1070 1.1 mrg "arm1156t2f-s", 1071 1.1 mrg NULL, 1072 1.1 mrg { 1073 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 1074 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, 1075 1.1.1.2 mrg isa_bit_notm, isa_bit_fp_dbl, isa_nobit 1076 1.1 mrg } 1077 1.1 mrg }, 1078 1.1.1.2 mrg NULL, 1079 1.1 mrg TARGET_ARCH_armv6t2 1080 1.1 mrg }, 1081 1.1 mrg { 1082 1.1 mrg { 1083 1.1 mrg "cortex-m1", 1084 1.1 mrg NULL, 1085 1.1 mrg { 1086 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1087 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1088 1.1 mrg } 1089 1.1 mrg }, 1090 1.1.1.2 mrg NULL, 1091 1.1 mrg TARGET_ARCH_armv6s_m 1092 1.1 mrg }, 1093 1.1 mrg { 1094 1.1 mrg { 1095 1.1 mrg "cortex-m0", 1096 1.1 mrg NULL, 1097 1.1 mrg { 1098 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1099 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1100 1.1 mrg } 1101 1.1 mrg }, 1102 1.1.1.2 mrg NULL, 1103 1.1 mrg TARGET_ARCH_armv6s_m 1104 1.1 mrg }, 1105 1.1 mrg { 1106 1.1 mrg { 1107 1.1 mrg "cortex-m0plus", 1108 1.1 mrg NULL, 1109 1.1 mrg { 1110 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1111 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1112 1.1 mrg } 1113 1.1 mrg }, 1114 1.1.1.2 mrg NULL, 1115 1.1 mrg TARGET_ARCH_armv6s_m 1116 1.1 mrg }, 1117 1.1 mrg { 1118 1.1 mrg { 1119 1.1 mrg "cortex-m1.small-multiply", 1120 1.1 mrg NULL, 1121 1.1 mrg { 1122 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1123 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1124 1.1 mrg } 1125 1.1 mrg }, 1126 1.1.1.2 mrg NULL, 1127 1.1 mrg TARGET_ARCH_armv6s_m 1128 1.1 mrg }, 1129 1.1 mrg { 1130 1.1 mrg { 1131 1.1 mrg "cortex-m0.small-multiply", 1132 1.1 mrg NULL, 1133 1.1 mrg { 1134 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1135 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1136 1.1 mrg } 1137 1.1 mrg }, 1138 1.1.1.2 mrg NULL, 1139 1.1 mrg TARGET_ARCH_armv6s_m 1140 1.1 mrg }, 1141 1.1 mrg { 1142 1.1 mrg { 1143 1.1 mrg "cortex-m0plus.small-multiply", 1144 1.1 mrg NULL, 1145 1.1 mrg { 1146 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1147 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 1148 1.1 mrg } 1149 1.1 mrg }, 1150 1.1.1.2 mrg NULL, 1151 1.1 mrg TARGET_ARCH_armv6s_m 1152 1.1 mrg }, 1153 1.1 mrg { 1154 1.1 mrg { 1155 1.1 mrg "generic-armv7-a", 1156 1.1 mrg cpu_opttab_genericv7a, 1157 1.1 mrg { 1158 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1159 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1160 1.1.1.2 mrg isa_bit_armv7, isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, 1161 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 1162 1.1 mrg } 1163 1.1 mrg }, 1164 1.1.1.2 mrg NULL, 1165 1.1 mrg TARGET_ARCH_armv7_a 1166 1.1 mrg }, 1167 1.1 mrg { 1168 1.1 mrg { 1169 1.1 mrg "cortex-a5", 1170 1.1 mrg cpu_opttab_cortexa5, 1171 1.1 mrg { 1172 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1173 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1174 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1175 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1176 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1177 1.1 mrg } 1178 1.1 mrg }, 1179 1.1.1.2 mrg NULL, 1180 1.1 mrg TARGET_ARCH_armv7_a 1181 1.1 mrg }, 1182 1.1 mrg { 1183 1.1 mrg { 1184 1.1 mrg "cortex-a7", 1185 1.1 mrg cpu_opttab_cortexa7, 1186 1.1 mrg { 1187 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1188 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1189 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1190 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1191 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1192 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1193 1.1 mrg } 1194 1.1 mrg }, 1195 1.1.1.2 mrg NULL, 1196 1.1 mrg TARGET_ARCH_armv7ve 1197 1.1 mrg }, 1198 1.1 mrg { 1199 1.1 mrg { 1200 1.1 mrg "cortex-a8", 1201 1.1 mrg cpu_opttab_cortexa8, 1202 1.1 mrg { 1203 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1204 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1205 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1206 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_bit_sec, 1207 1.1.1.2 mrg isa_nobit 1208 1.1 mrg } 1209 1.1 mrg }, 1210 1.1.1.2 mrg NULL, 1211 1.1 mrg TARGET_ARCH_armv7_a 1212 1.1 mrg }, 1213 1.1 mrg { 1214 1.1 mrg { 1215 1.1 mrg "cortex-a9", 1216 1.1 mrg cpu_opttab_cortexa9, 1217 1.1 mrg { 1218 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1219 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_neon, 1220 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_fp_d32, isa_bit_thumb2, 1221 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1222 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1223 1.1 mrg } 1224 1.1 mrg }, 1225 1.1.1.2 mrg NULL, 1226 1.1 mrg TARGET_ARCH_armv7_a 1227 1.1 mrg }, 1228 1.1 mrg { 1229 1.1 mrg { 1230 1.1 mrg "cortex-a12", 1231 1.1 mrg cpu_opttab_cortexa12, 1232 1.1 mrg { 1233 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1234 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1235 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1236 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1237 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1238 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1239 1.1 mrg } 1240 1.1 mrg }, 1241 1.1.1.2 mrg NULL, 1242 1.1 mrg TARGET_ARCH_armv7ve 1243 1.1 mrg }, 1244 1.1 mrg { 1245 1.1 mrg { 1246 1.1 mrg "cortex-a15", 1247 1.1 mrg cpu_opttab_cortexa15, 1248 1.1 mrg { 1249 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1250 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1251 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1252 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1253 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1254 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1255 1.1 mrg } 1256 1.1 mrg }, 1257 1.1.1.2 mrg NULL, 1258 1.1 mrg TARGET_ARCH_armv7ve 1259 1.1 mrg }, 1260 1.1 mrg { 1261 1.1 mrg { 1262 1.1 mrg "cortex-a17", 1263 1.1 mrg cpu_opttab_cortexa17, 1264 1.1 mrg { 1265 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1266 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1267 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1268 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1269 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1270 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1271 1.1 mrg } 1272 1.1 mrg }, 1273 1.1.1.2 mrg NULL, 1274 1.1 mrg TARGET_ARCH_armv7ve 1275 1.1 mrg }, 1276 1.1 mrg { 1277 1.1 mrg { 1278 1.1 mrg "cortex-r4", 1279 1.1 mrg NULL, 1280 1.1 mrg { 1281 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1282 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 1283 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 1284 1.1 mrg } 1285 1.1 mrg }, 1286 1.1.1.2 mrg NULL, 1287 1.1 mrg TARGET_ARCH_armv7_r 1288 1.1 mrg }, 1289 1.1 mrg { 1290 1.1 mrg { 1291 1.1 mrg "cortex-r4f", 1292 1.1 mrg NULL, 1293 1.1 mrg { 1294 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_armv5te, isa_bit_thumb, 1295 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, 1296 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 1297 1.1.1.2 mrg isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1298 1.1 mrg } 1299 1.1 mrg }, 1300 1.1.1.2 mrg NULL, 1301 1.1 mrg TARGET_ARCH_armv7_r 1302 1.1 mrg }, 1303 1.1 mrg { 1304 1.1 mrg { 1305 1.1 mrg "cortex-r5", 1306 1.1 mrg cpu_opttab_cortexr5, 1307 1.1 mrg { 1308 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1309 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1310 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1311 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_fp_dbl, isa_nobit 1312 1.1 mrg } 1313 1.1 mrg }, 1314 1.1.1.2 mrg NULL, 1315 1.1 mrg TARGET_ARCH_armv7_r 1316 1.1 mrg }, 1317 1.1 mrg { 1318 1.1 mrg { 1319 1.1 mrg "cortex-r7", 1320 1.1 mrg cpu_opttab_cortexr7, 1321 1.1 mrg { 1322 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1323 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1324 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1325 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1326 1.1.1.2 mrg isa_nobit 1327 1.1 mrg } 1328 1.1 mrg }, 1329 1.1.1.2 mrg NULL, 1330 1.1 mrg TARGET_ARCH_armv7_r 1331 1.1 mrg }, 1332 1.1 mrg { 1333 1.1 mrg { 1334 1.1 mrg "cortex-r8", 1335 1.1 mrg cpu_opttab_cortexr8, 1336 1.1 mrg { 1337 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_armv5te, 1338 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1339 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, 1340 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_fp_dbl, 1341 1.1.1.2 mrg isa_nobit 1342 1.1 mrg } 1343 1.1 mrg }, 1344 1.1.1.2 mrg NULL, 1345 1.1 mrg TARGET_ARCH_armv7_r 1346 1.1 mrg }, 1347 1.1 mrg { 1348 1.1 mrg { 1349 1.1 mrg "cortex-m7", 1350 1.1 mrg cpu_opttab_cortexm7, 1351 1.1 mrg { 1352 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1353 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1354 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_fpv5, 1355 1.1.1.2 mrg isa_bit_tdiv, isa_bit_quirk_no_volatile_ce, isa_bit_thumb2, isa_bit_fp16conv, 1356 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 1357 1.1 mrg } 1358 1.1 mrg }, 1359 1.1.1.2 mrg NULL, 1360 1.1 mrg TARGET_ARCH_armv7e_m 1361 1.1 mrg }, 1362 1.1 mrg { 1363 1.1 mrg { 1364 1.1 mrg "cortex-m4", 1365 1.1 mrg cpu_opttab_cortexm4, 1366 1.1 mrg { 1367 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1368 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1369 1.1 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_tdiv, 1370 1.1.1.2 mrg isa_bit_thumb2, isa_bit_fp16conv, isa_nobit 1371 1.1 mrg } 1372 1.1 mrg }, 1373 1.1.1.2 mrg NULL, 1374 1.1 mrg TARGET_ARCH_armv7e_m 1375 1.1 mrg }, 1376 1.1 mrg { 1377 1.1 mrg { 1378 1.1 mrg "cortex-m3", 1379 1.1 mrg NULL, 1380 1.1 mrg { 1381 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_quirk_cm3_ldrd, isa_bit_be8, 1382 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, 1383 1.1.1.2 mrg isa_bit_tdiv, isa_bit_thumb2, isa_nobit 1384 1.1 mrg } 1385 1.1 mrg }, 1386 1.1.1.2 mrg NULL, 1387 1.1 mrg TARGET_ARCH_armv7_m 1388 1.1 mrg }, 1389 1.1 mrg { 1390 1.1 mrg { 1391 1.1 mrg "marvell-pj4", 1392 1.1 mrg NULL, 1393 1.1 mrg { 1394 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1395 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 1396 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 1397 1.1.1.2 mrg isa_nobit 1398 1.1 mrg } 1399 1.1 mrg }, 1400 1.1.1.2 mrg NULL, 1401 1.1 mrg TARGET_ARCH_armv7_a 1402 1.1 mrg }, 1403 1.1 mrg { 1404 1.1 mrg { 1405 1.1 mrg "cortex-a15.cortex-a7", 1406 1.1 mrg cpu_opttab_cortexa15cortexa7, 1407 1.1 mrg { 1408 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1409 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1410 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1411 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1412 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1413 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1414 1.1 mrg } 1415 1.1 mrg }, 1416 1.1.1.2 mrg NULL, 1417 1.1 mrg TARGET_ARCH_armv7ve 1418 1.1 mrg }, 1419 1.1 mrg { 1420 1.1 mrg { 1421 1.1 mrg "cortex-a17.cortex-a7", 1422 1.1 mrg cpu_opttab_cortexa17cortexa7, 1423 1.1 mrg { 1424 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1425 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1426 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1427 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1428 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, 1429 1.1.1.2 mrg isa_bit_fp_dbl, isa_bit_sec, isa_nobit 1430 1.1 mrg } 1431 1.1 mrg }, 1432 1.1.1.2 mrg NULL, 1433 1.1 mrg TARGET_ARCH_armv7ve 1434 1.1 mrg }, 1435 1.1 mrg { 1436 1.1 mrg { 1437 1.1 mrg "cortex-a32", 1438 1.1 mrg cpu_opttab_cortexa32, 1439 1.1 mrg { 1440 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1441 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1442 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1443 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1444 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1445 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1446 1.1.1.2 mrg isa_bit_sec, isa_nobit 1447 1.1 mrg } 1448 1.1 mrg }, 1449 1.1.1.2 mrg NULL, 1450 1.1 mrg TARGET_ARCH_armv8_a 1451 1.1 mrg }, 1452 1.1 mrg { 1453 1.1 mrg { 1454 1.1 mrg "cortex-a35", 1455 1.1 mrg cpu_opttab_cortexa35, 1456 1.1 mrg { 1457 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1458 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1459 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1460 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1461 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1462 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1463 1.1.1.2 mrg isa_bit_sec, isa_nobit 1464 1.1 mrg } 1465 1.1 mrg }, 1466 1.1.1.2 mrg NULL, 1467 1.1 mrg TARGET_ARCH_armv8_a 1468 1.1 mrg }, 1469 1.1 mrg { 1470 1.1 mrg { 1471 1.1 mrg "cortex-a53", 1472 1.1 mrg cpu_opttab_cortexa53, 1473 1.1 mrg { 1474 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1475 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1476 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1477 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1478 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1479 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1480 1.1.1.2 mrg isa_bit_sec, isa_nobit 1481 1.1 mrg } 1482 1.1 mrg }, 1483 1.1.1.2 mrg NULL, 1484 1.1 mrg TARGET_ARCH_armv8_a 1485 1.1 mrg }, 1486 1.1 mrg { 1487 1.1 mrg { 1488 1.1 mrg "cortex-a57", 1489 1.1 mrg cpu_opttab_cortexa57, 1490 1.1 mrg { 1491 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1492 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1493 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1494 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1495 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1496 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1497 1.1.1.2 mrg isa_bit_sec, isa_nobit 1498 1.1 mrg } 1499 1.1 mrg }, 1500 1.1.1.2 mrg NULL, 1501 1.1 mrg TARGET_ARCH_armv8_a 1502 1.1 mrg }, 1503 1.1 mrg { 1504 1.1 mrg { 1505 1.1 mrg "cortex-a72", 1506 1.1 mrg cpu_opttab_cortexa72, 1507 1.1 mrg { 1508 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1509 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1510 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1511 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1512 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1513 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1514 1.1.1.2 mrg isa_bit_sec, isa_nobit 1515 1.1 mrg } 1516 1.1 mrg }, 1517 1.1.1.2 mrg NULL, 1518 1.1 mrg TARGET_ARCH_armv8_a 1519 1.1 mrg }, 1520 1.1 mrg { 1521 1.1 mrg { 1522 1.1 mrg "cortex-a73", 1523 1.1 mrg cpu_opttab_cortexa73, 1524 1.1 mrg { 1525 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1526 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1527 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1528 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1529 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1530 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1531 1.1.1.2 mrg isa_bit_sec, isa_nobit 1532 1.1 mrg } 1533 1.1 mrg }, 1534 1.1.1.2 mrg NULL, 1535 1.1 mrg TARGET_ARCH_armv8_a 1536 1.1 mrg }, 1537 1.1 mrg { 1538 1.1 mrg { 1539 1.1 mrg "exynos-m1", 1540 1.1 mrg cpu_opttab_exynosm1, 1541 1.1 mrg { 1542 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1543 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1544 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1545 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1546 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1547 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1548 1.1.1.2 mrg isa_bit_sec, isa_nobit 1549 1.1 mrg } 1550 1.1 mrg }, 1551 1.1.1.2 mrg NULL, 1552 1.1 mrg TARGET_ARCH_armv8_a 1553 1.1 mrg }, 1554 1.1 mrg { 1555 1.1 mrg { 1556 1.1 mrg "xgene1", 1557 1.1 mrg cpu_opttab_xgene1, 1558 1.1 mrg { 1559 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1560 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1561 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1562 1.1 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, 1563 1.1.1.2 mrg isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, isa_bit_fp16conv, 1564 1.1.1.2 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, isa_bit_sec, 1565 1.1.1.2 mrg isa_nobit 1566 1.1 mrg } 1567 1.1 mrg }, 1568 1.1.1.2 mrg NULL, 1569 1.1 mrg TARGET_ARCH_armv8_a 1570 1.1 mrg }, 1571 1.1 mrg { 1572 1.1 mrg { 1573 1.1 mrg "cortex-a57.cortex-a53", 1574 1.1 mrg cpu_opttab_cortexa57cortexa53, 1575 1.1 mrg { 1576 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1577 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1578 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1579 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1580 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1581 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1582 1.1.1.2 mrg isa_bit_sec, isa_nobit 1583 1.1 mrg } 1584 1.1 mrg }, 1585 1.1.1.2 mrg NULL, 1586 1.1 mrg TARGET_ARCH_armv8_a 1587 1.1 mrg }, 1588 1.1 mrg { 1589 1.1 mrg { 1590 1.1 mrg "cortex-a72.cortex-a53", 1591 1.1 mrg cpu_opttab_cortexa72cortexa53, 1592 1.1 mrg { 1593 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1594 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1595 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1596 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1597 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1598 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1599 1.1.1.2 mrg isa_bit_sec, isa_nobit 1600 1.1 mrg } 1601 1.1 mrg }, 1602 1.1.1.2 mrg NULL, 1603 1.1 mrg TARGET_ARCH_armv8_a 1604 1.1 mrg }, 1605 1.1 mrg { 1606 1.1 mrg { 1607 1.1 mrg "cortex-a73.cortex-a35", 1608 1.1 mrg cpu_opttab_cortexa73cortexa35, 1609 1.1 mrg { 1610 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1611 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1612 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1613 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1614 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1615 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1616 1.1.1.2 mrg isa_bit_sec, isa_nobit 1617 1.1 mrg } 1618 1.1 mrg }, 1619 1.1.1.2 mrg NULL, 1620 1.1 mrg TARGET_ARCH_armv8_a 1621 1.1 mrg }, 1622 1.1 mrg { 1623 1.1 mrg { 1624 1.1 mrg "cortex-a73.cortex-a53", 1625 1.1 mrg cpu_opttab_cortexa73cortexa53, 1626 1.1 mrg { 1627 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1628 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1629 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1630 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1631 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1632 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1633 1.1.1.2 mrg isa_bit_sec, isa_nobit 1634 1.1 mrg } 1635 1.1 mrg }, 1636 1.1.1.2 mrg NULL, 1637 1.1 mrg TARGET_ARCH_armv8_a 1638 1.1 mrg }, 1639 1.1 mrg { 1640 1.1 mrg { 1641 1.1 mrg "cortex-a55", 1642 1.1 mrg cpu_opttab_cortexa55, 1643 1.1 mrg { 1644 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1645 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1646 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1647 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1648 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1649 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1650 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1651 1.1.1.2 mrg isa_bit_sec, isa_nobit 1652 1.1 mrg } 1653 1.1 mrg }, 1654 1.1.1.2 mrg NULL, 1655 1.1 mrg TARGET_ARCH_armv8_2_a 1656 1.1 mrg }, 1657 1.1 mrg { 1658 1.1 mrg { 1659 1.1 mrg "cortex-a75", 1660 1.1 mrg cpu_opttab_cortexa75, 1661 1.1 mrg { 1662 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1663 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1664 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1665 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1666 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1667 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1668 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1669 1.1.1.2 mrg isa_bit_sec, isa_nobit 1670 1.1.1.2 mrg } 1671 1.1.1.2 mrg }, 1672 1.1.1.2 mrg NULL, 1673 1.1.1.2 mrg TARGET_ARCH_armv8_2_a 1674 1.1.1.2 mrg }, 1675 1.1.1.2 mrg { 1676 1.1.1.2 mrg { 1677 1.1.1.2 mrg "cortex-a76", 1678 1.1.1.2 mrg cpu_opttab_cortexa76, 1679 1.1.1.2 mrg { 1680 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1681 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1682 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1683 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1684 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1685 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1686 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1687 1.1.1.2 mrg isa_bit_sec, isa_nobit 1688 1.1.1.2 mrg } 1689 1.1.1.2 mrg }, 1690 1.1.1.2 mrg NULL, 1691 1.1.1.2 mrg TARGET_ARCH_armv8_2_a 1692 1.1.1.2 mrg }, 1693 1.1.1.2 mrg { 1694 1.1.1.2 mrg { 1695 1.1.1.2 mrg "neoverse-n1", 1696 1.1.1.2 mrg cpu_opttab_neoversen1, 1697 1.1.1.2 mrg { 1698 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1699 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1700 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1701 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1702 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1703 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1704 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1705 1.1.1.2 mrg isa_bit_sec, isa_nobit 1706 1.1 mrg } 1707 1.1 mrg }, 1708 1.1.1.2 mrg cpu_aliastab_neoversen1, 1709 1.1 mrg TARGET_ARCH_armv8_2_a 1710 1.1 mrg }, 1711 1.1 mrg { 1712 1.1 mrg { 1713 1.1 mrg "cortex-a75.cortex-a55", 1714 1.1 mrg cpu_opttab_cortexa75cortexa55, 1715 1.1 mrg { 1716 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1717 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1718 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1719 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1720 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1721 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1722 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1723 1.1.1.2 mrg isa_bit_sec, isa_nobit 1724 1.1.1.2 mrg } 1725 1.1.1.2 mrg }, 1726 1.1.1.2 mrg NULL, 1727 1.1.1.2 mrg TARGET_ARCH_armv8_2_a 1728 1.1.1.2 mrg }, 1729 1.1.1.2 mrg { 1730 1.1.1.2 mrg { 1731 1.1.1.2 mrg "cortex-a76.cortex-a55", 1732 1.1.1.2 mrg cpu_opttab_cortexa76cortexa55, 1733 1.1.1.2 mrg { 1734 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1735 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1736 1.1.1.2 mrg isa_bit_dotprod, isa_bit_lpae, isa_bit_armv4, isa_bit_neon, 1737 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 1738 1.1.1.2 mrg isa_bit_fpv5, isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, 1739 1.1.1.2 mrg isa_bit_notm, isa_bit_fp16, isa_bit_armv8_1, isa_bit_fp16conv, 1740 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1741 1.1.1.2 mrg isa_bit_sec, isa_nobit 1742 1.1 mrg } 1743 1.1 mrg }, 1744 1.1.1.2 mrg NULL, 1745 1.1 mrg TARGET_ARCH_armv8_2_a 1746 1.1 mrg }, 1747 1.1 mrg { 1748 1.1 mrg { 1749 1.1 mrg "cortex-m23", 1750 1.1 mrg NULL, 1751 1.1 mrg { 1752 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1753 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_cmse, isa_bit_armv8, 1754 1.1.1.2 mrg isa_bit_tdiv, isa_nobit 1755 1.1 mrg } 1756 1.1 mrg }, 1757 1.1.1.2 mrg NULL, 1758 1.1 mrg TARGET_ARCH_armv8_m_base 1759 1.1 mrg }, 1760 1.1 mrg { 1761 1.1 mrg { 1762 1.1 mrg "cortex-m33", 1763 1.1 mrg cpu_opttab_cortexm33, 1764 1.1 mrg { 1765 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_armv5te, 1766 1.1.1.2 mrg isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, isa_bit_armv4, 1767 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, isa_bit_cmse, 1768 1.1.1.2 mrg isa_bit_armv8, isa_bit_fpv5, isa_bit_tdiv, isa_bit_thumb2, 1769 1.1.1.2 mrg isa_bit_fp16conv, isa_nobit 1770 1.1 mrg } 1771 1.1 mrg }, 1772 1.1.1.2 mrg NULL, 1773 1.1 mrg TARGET_ARCH_armv8_m_main 1774 1.1 mrg }, 1775 1.1 mrg { 1776 1.1 mrg { 1777 1.1 mrg "cortex-r52", 1778 1.1 mrg cpu_opttab_cortexr52, 1779 1.1 mrg { 1780 1.1 mrg isa_bit_vfpv2, isa_bit_adiv, isa_bit_vfpv3, isa_bit_vfpv4, 1781 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 1782 1.1.1.2 mrg isa_bit_lpae, isa_bit_armv4, isa_bit_neon, isa_bit_armv6, 1783 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_fpv5, 1784 1.1.1.2 mrg isa_bit_tdiv, isa_bit_fp_d32, isa_bit_thumb2, isa_bit_notm, 1785 1.1.1.2 mrg isa_bit_fp16conv, isa_bit_armv6k, isa_bit_mp, isa_bit_fp_dbl, 1786 1.1.1.2 mrg isa_bit_sec, isa_nobit 1787 1.1 mrg } 1788 1.1 mrg }, 1789 1.1.1.2 mrg NULL, 1790 1.1 mrg TARGET_ARCH_armv8_r 1791 1.1 mrg }, 1792 1.1.1.2 mrg {{NULL, NULL, {isa_nobit}}, NULL, TARGET_ARCH_arm_none} 1793 1.1 mrg }; 1794 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5te[] = { 1795 1.1 mrg { 1796 1.1 mrg "fp", false, false, 1797 1.1 mrg { 1798 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1799 1.1 mrg } 1800 1.1 mrg }, 1801 1.1 mrg { 1802 1.1 mrg "nofp", true, false, 1803 1.1 mrg { 1804 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1805 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1806 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1807 1.1 mrg } 1808 1.1 mrg }, 1809 1.1 mrg { 1810 1.1 mrg "vfpv2", false, true, 1811 1.1 mrg { 1812 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1813 1.1 mrg } 1814 1.1 mrg }, 1815 1.1 mrg { NULL, false, false, {isa_nobit}} 1816 1.1 mrg }; 1817 1.1 mrg 1818 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv5tej[] = { 1819 1.1 mrg { 1820 1.1 mrg "fp", false, false, 1821 1.1 mrg { 1822 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1823 1.1 mrg } 1824 1.1 mrg }, 1825 1.1 mrg { 1826 1.1 mrg "nofp", true, false, 1827 1.1 mrg { 1828 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1829 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1830 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1831 1.1 mrg } 1832 1.1 mrg }, 1833 1.1 mrg { 1834 1.1 mrg "vfpv2", false, true, 1835 1.1 mrg { 1836 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1837 1.1 mrg } 1838 1.1 mrg }, 1839 1.1 mrg { NULL, false, false, {isa_nobit}} 1840 1.1 mrg }; 1841 1.1 mrg 1842 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6[] = { 1843 1.1 mrg { 1844 1.1 mrg "fp", false, false, 1845 1.1 mrg { 1846 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1847 1.1 mrg } 1848 1.1 mrg }, 1849 1.1 mrg { 1850 1.1 mrg "nofp", true, false, 1851 1.1 mrg { 1852 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1853 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1854 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1855 1.1 mrg } 1856 1.1 mrg }, 1857 1.1 mrg { 1858 1.1 mrg "vfpv2", false, true, 1859 1.1 mrg { 1860 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1861 1.1 mrg } 1862 1.1 mrg }, 1863 1.1 mrg { NULL, false, false, {isa_nobit}} 1864 1.1 mrg }; 1865 1.1 mrg 1866 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6j[] = { 1867 1.1 mrg { 1868 1.1 mrg "fp", false, false, 1869 1.1 mrg { 1870 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1871 1.1 mrg } 1872 1.1 mrg }, 1873 1.1 mrg { 1874 1.1 mrg "nofp", true, false, 1875 1.1 mrg { 1876 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1877 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1878 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1879 1.1 mrg } 1880 1.1 mrg }, 1881 1.1 mrg { 1882 1.1 mrg "vfpv2", false, true, 1883 1.1 mrg { 1884 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1885 1.1 mrg } 1886 1.1 mrg }, 1887 1.1 mrg { NULL, false, false, {isa_nobit}} 1888 1.1 mrg }; 1889 1.1 mrg 1890 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6k[] = { 1891 1.1 mrg { 1892 1.1 mrg "fp", false, false, 1893 1.1 mrg { 1894 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1895 1.1 mrg } 1896 1.1 mrg }, 1897 1.1 mrg { 1898 1.1 mrg "nofp", true, false, 1899 1.1 mrg { 1900 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1901 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1902 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1903 1.1 mrg } 1904 1.1 mrg }, 1905 1.1 mrg { 1906 1.1 mrg "vfpv2", false, true, 1907 1.1 mrg { 1908 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1909 1.1 mrg } 1910 1.1 mrg }, 1911 1.1 mrg { NULL, false, false, {isa_nobit}} 1912 1.1 mrg }; 1913 1.1 mrg 1914 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6z[] = { 1915 1.1 mrg { 1916 1.1 mrg "fp", false, false, 1917 1.1 mrg { 1918 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1919 1.1 mrg } 1920 1.1 mrg }, 1921 1.1 mrg { 1922 1.1 mrg "nofp", true, false, 1923 1.1 mrg { 1924 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1925 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1926 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1927 1.1 mrg } 1928 1.1 mrg }, 1929 1.1 mrg { 1930 1.1 mrg "vfpv2", false, true, 1931 1.1 mrg { 1932 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1933 1.1 mrg } 1934 1.1 mrg }, 1935 1.1 mrg { NULL, false, false, {isa_nobit}} 1936 1.1 mrg }; 1937 1.1 mrg 1938 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6kz[] = { 1939 1.1 mrg { 1940 1.1 mrg "fp", false, false, 1941 1.1 mrg { 1942 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1943 1.1 mrg } 1944 1.1 mrg }, 1945 1.1 mrg { 1946 1.1 mrg "nofp", true, false, 1947 1.1 mrg { 1948 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1949 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1950 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1951 1.1 mrg } 1952 1.1 mrg }, 1953 1.1 mrg { 1954 1.1 mrg "vfpv2", false, true, 1955 1.1 mrg { 1956 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1957 1.1 mrg } 1958 1.1 mrg }, 1959 1.1 mrg { NULL, false, false, {isa_nobit}} 1960 1.1 mrg }; 1961 1.1 mrg 1962 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6zk[] = { 1963 1.1 mrg { 1964 1.1 mrg "fp", false, false, 1965 1.1 mrg { 1966 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1967 1.1 mrg } 1968 1.1 mrg }, 1969 1.1 mrg { 1970 1.1 mrg "nofp", true, false, 1971 1.1 mrg { 1972 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1973 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1974 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1975 1.1 mrg } 1976 1.1 mrg }, 1977 1.1 mrg { 1978 1.1 mrg "vfpv2", false, true, 1979 1.1 mrg { 1980 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1981 1.1 mrg } 1982 1.1 mrg }, 1983 1.1 mrg { NULL, false, false, {isa_nobit}} 1984 1.1 mrg }; 1985 1.1 mrg 1986 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv6t2[] = { 1987 1.1 mrg { 1988 1.1 mrg "fp", false, false, 1989 1.1 mrg { 1990 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 1991 1.1 mrg } 1992 1.1 mrg }, 1993 1.1 mrg { 1994 1.1 mrg "nofp", true, false, 1995 1.1 mrg { 1996 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 1997 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 1998 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 1999 1.1 mrg } 2000 1.1 mrg }, 2001 1.1 mrg { 2002 1.1 mrg "vfpv2", false, true, 2003 1.1 mrg { 2004 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 2005 1.1 mrg } 2006 1.1 mrg }, 2007 1.1 mrg { NULL, false, false, {isa_nobit}} 2008 1.1 mrg }; 2009 1.1 mrg 2010 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7[] = { 2011 1.1 mrg { 2012 1.1 mrg "fp", false, false, 2013 1.1 mrg { 2014 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2015 1.1 mrg } 2016 1.1 mrg }, 2017 1.1 mrg { 2018 1.1 mrg "nofp", true, false, 2019 1.1 mrg { 2020 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2021 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2022 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2023 1.1 mrg } 2024 1.1 mrg }, 2025 1.1 mrg { 2026 1.1 mrg "vfpv3-d16", false, true, 2027 1.1 mrg { 2028 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2029 1.1 mrg } 2030 1.1 mrg }, 2031 1.1 mrg { NULL, false, false, {isa_nobit}} 2032 1.1 mrg }; 2033 1.1 mrg 2034 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7_a[] = { 2035 1.1 mrg { 2036 1.1 mrg "mp", false, false, 2037 1.1 mrg { 2038 1.1 mrg isa_bit_mp, isa_nobit 2039 1.1 mrg } 2040 1.1 mrg }, 2041 1.1 mrg { 2042 1.1 mrg "sec", false, false, 2043 1.1 mrg { 2044 1.1 mrg isa_bit_sec, isa_nobit 2045 1.1 mrg } 2046 1.1 mrg }, 2047 1.1 mrg { 2048 1.1 mrg "fp", false, false, 2049 1.1 mrg { 2050 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2051 1.1 mrg } 2052 1.1 mrg }, 2053 1.1 mrg { 2054 1.1 mrg "vfpv3", false, false, 2055 1.1 mrg { 2056 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2057 1.1 mrg isa_nobit 2058 1.1 mrg } 2059 1.1 mrg }, 2060 1.1 mrg { 2061 1.1 mrg "vfpv3-d16-fp16", false, false, 2062 1.1 mrg { 2063 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2064 1.1 mrg isa_nobit 2065 1.1 mrg } 2066 1.1 mrg }, 2067 1.1 mrg { 2068 1.1 mrg "vfpv3-fp16", false, false, 2069 1.1 mrg { 2070 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2071 1.1 mrg isa_bit_fp_dbl, isa_nobit 2072 1.1 mrg } 2073 1.1 mrg }, 2074 1.1 mrg { 2075 1.1 mrg "vfpv4-d16", false, false, 2076 1.1 mrg { 2077 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2078 1.1 mrg isa_bit_fp_dbl, isa_nobit 2079 1.1 mrg } 2080 1.1 mrg }, 2081 1.1 mrg { 2082 1.1 mrg "vfpv4", false, false, 2083 1.1 mrg { 2084 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2085 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2086 1.1 mrg } 2087 1.1 mrg }, 2088 1.1 mrg { 2089 1.1 mrg "simd", false, false, 2090 1.1 mrg { 2091 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2092 1.1 mrg isa_bit_fp_dbl, isa_nobit 2093 1.1 mrg } 2094 1.1 mrg }, 2095 1.1 mrg { 2096 1.1 mrg "neon-fp16", false, false, 2097 1.1 mrg { 2098 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2099 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2100 1.1 mrg } 2101 1.1 mrg }, 2102 1.1 mrg { 2103 1.1 mrg "neon-vfpv4", false, false, 2104 1.1 mrg { 2105 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2106 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2107 1.1 mrg } 2108 1.1 mrg }, 2109 1.1 mrg { 2110 1.1 mrg "nosimd", true, false, 2111 1.1 mrg { 2112 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2113 1.1 mrg isa_bit_crypto, isa_nobit 2114 1.1 mrg } 2115 1.1 mrg }, 2116 1.1 mrg { 2117 1.1 mrg "nofp", true, false, 2118 1.1 mrg { 2119 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2120 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2121 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2122 1.1 mrg } 2123 1.1 mrg }, 2124 1.1 mrg { 2125 1.1 mrg "vfpv3-d16", false, true, 2126 1.1 mrg { 2127 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2128 1.1 mrg } 2129 1.1 mrg }, 2130 1.1 mrg { 2131 1.1 mrg "neon", false, true, 2132 1.1 mrg { 2133 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2134 1.1 mrg isa_bit_fp_dbl, isa_nobit 2135 1.1 mrg } 2136 1.1 mrg }, 2137 1.1 mrg { 2138 1.1 mrg "neon-vfpv3", false, true, 2139 1.1 mrg { 2140 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2141 1.1 mrg isa_bit_fp_dbl, isa_nobit 2142 1.1 mrg } 2143 1.1 mrg }, 2144 1.1 mrg { NULL, false, false, {isa_nobit}} 2145 1.1 mrg }; 2146 1.1 mrg 2147 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7ve[] = { 2148 1.1 mrg { 2149 1.1 mrg "vfpv3-d16", false, false, 2150 1.1 mrg { 2151 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2152 1.1 mrg } 2153 1.1 mrg }, 2154 1.1 mrg { 2155 1.1 mrg "vfpv3", false, false, 2156 1.1 mrg { 2157 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 2158 1.1 mrg isa_nobit 2159 1.1 mrg } 2160 1.1 mrg }, 2161 1.1 mrg { 2162 1.1 mrg "vfpv3-d16-fp16", false, false, 2163 1.1 mrg { 2164 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2165 1.1 mrg isa_nobit 2166 1.1 mrg } 2167 1.1 mrg }, 2168 1.1 mrg { 2169 1.1 mrg "vfpv3-fp16", false, false, 2170 1.1 mrg { 2171 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 2172 1.1 mrg isa_bit_fp_dbl, isa_nobit 2173 1.1 mrg } 2174 1.1 mrg }, 2175 1.1 mrg { 2176 1.1 mrg "fp", false, false, 2177 1.1 mrg { 2178 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2179 1.1 mrg isa_bit_fp_dbl, isa_nobit 2180 1.1 mrg } 2181 1.1 mrg }, 2182 1.1 mrg { 2183 1.1 mrg "vfpv4", false, false, 2184 1.1 mrg { 2185 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 2186 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2187 1.1 mrg } 2188 1.1 mrg }, 2189 1.1 mrg { 2190 1.1 mrg "neon", false, false, 2191 1.1 mrg { 2192 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2193 1.1 mrg isa_bit_fp_dbl, isa_nobit 2194 1.1 mrg } 2195 1.1 mrg }, 2196 1.1 mrg { 2197 1.1 mrg "neon-fp16", false, false, 2198 1.1 mrg { 2199 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2200 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2201 1.1 mrg } 2202 1.1 mrg }, 2203 1.1 mrg { 2204 1.1 mrg "simd", false, false, 2205 1.1 mrg { 2206 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2207 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2208 1.1 mrg } 2209 1.1 mrg }, 2210 1.1 mrg { 2211 1.1 mrg "nosimd", true, false, 2212 1.1 mrg { 2213 1.1 mrg isa_bit_fp16fml, isa_bit_dotprod, isa_bit_neon, isa_bit_fp_d32, 2214 1.1 mrg isa_bit_crypto, isa_nobit 2215 1.1 mrg } 2216 1.1 mrg }, 2217 1.1 mrg { 2218 1.1 mrg "nofp", true, false, 2219 1.1 mrg { 2220 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2221 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2222 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2223 1.1 mrg } 2224 1.1 mrg }, 2225 1.1 mrg { 2226 1.1 mrg "vfpv4-d16", false, true, 2227 1.1 mrg { 2228 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2229 1.1 mrg isa_bit_fp_dbl, isa_nobit 2230 1.1 mrg } 2231 1.1 mrg }, 2232 1.1 mrg { 2233 1.1 mrg "neon-vfpv3", false, true, 2234 1.1 mrg { 2235 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 2236 1.1 mrg isa_bit_fp_dbl, isa_nobit 2237 1.1 mrg } 2238 1.1 mrg }, 2239 1.1 mrg { 2240 1.1 mrg "neon-vfpv4", false, true, 2241 1.1 mrg { 2242 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2243 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2244 1.1 mrg } 2245 1.1 mrg }, 2246 1.1 mrg { NULL, false, false, {isa_nobit}} 2247 1.1 mrg }; 2248 1.1 mrg 2249 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7_r[] = { 2250 1.1 mrg { 2251 1.1 mrg "fp.sp", false, false, 2252 1.1 mrg { 2253 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2254 1.1 mrg } 2255 1.1 mrg }, 2256 1.1 mrg { 2257 1.1 mrg "fp", false, false, 2258 1.1 mrg { 2259 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2260 1.1 mrg } 2261 1.1 mrg }, 2262 1.1 mrg { 2263 1.1 mrg "vfpv3xd-fp16", false, false, 2264 1.1 mrg { 2265 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 2266 1.1 mrg } 2267 1.1 mrg }, 2268 1.1 mrg { 2269 1.1 mrg "vfpv3-d16-fp16", false, false, 2270 1.1 mrg { 2271 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 2272 1.1 mrg isa_nobit 2273 1.1 mrg } 2274 1.1 mrg }, 2275 1.1 mrg { 2276 1.1 mrg "idiv", false, false, 2277 1.1 mrg { 2278 1.1 mrg isa_bit_adiv, isa_nobit 2279 1.1 mrg } 2280 1.1 mrg }, 2281 1.1 mrg { 2282 1.1 mrg "nofp", true, false, 2283 1.1 mrg { 2284 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2285 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2286 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2287 1.1 mrg } 2288 1.1 mrg }, 2289 1.1 mrg { 2290 1.1 mrg "noidiv", true, false, 2291 1.1 mrg { 2292 1.1 mrg isa_bit_adiv, isa_nobit 2293 1.1 mrg } 2294 1.1 mrg }, 2295 1.1 mrg { 2296 1.1 mrg "vfpv3xd", false, true, 2297 1.1 mrg { 2298 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 2299 1.1 mrg } 2300 1.1 mrg }, 2301 1.1 mrg { 2302 1.1 mrg "vfpv3-d16", false, true, 2303 1.1 mrg { 2304 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 2305 1.1 mrg } 2306 1.1 mrg }, 2307 1.1 mrg { NULL, false, false, {isa_nobit}} 2308 1.1 mrg }; 2309 1.1 mrg 2310 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv7e_m[] = { 2311 1.1 mrg { 2312 1.1 mrg "fp", false, false, 2313 1.1 mrg { 2314 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2315 1.1 mrg isa_nobit 2316 1.1 mrg } 2317 1.1 mrg }, 2318 1.1 mrg { 2319 1.1 mrg "fpv5", false, false, 2320 1.1 mrg { 2321 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2322 1.1 mrg isa_bit_fp16conv, isa_nobit 2323 1.1 mrg } 2324 1.1 mrg }, 2325 1.1 mrg { 2326 1.1 mrg "fp.dp", false, false, 2327 1.1 mrg { 2328 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2329 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2330 1.1 mrg } 2331 1.1 mrg }, 2332 1.1 mrg { 2333 1.1 mrg "nofp", true, false, 2334 1.1 mrg { 2335 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2336 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2337 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2338 1.1 mrg } 2339 1.1 mrg }, 2340 1.1 mrg { 2341 1.1 mrg "vfpv4-sp-d16", false, true, 2342 1.1 mrg { 2343 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 2344 1.1 mrg isa_nobit 2345 1.1 mrg } 2346 1.1 mrg }, 2347 1.1 mrg { 2348 1.1 mrg "fpv5-d16", false, true, 2349 1.1 mrg { 2350 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2351 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2352 1.1 mrg } 2353 1.1 mrg }, 2354 1.1 mrg { NULL, false, false, {isa_nobit}} 2355 1.1 mrg }; 2356 1.1 mrg 2357 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_a[] = { 2358 1.1 mrg { 2359 1.1 mrg "crc", false, false, 2360 1.1 mrg { 2361 1.1 mrg isa_bit_crc32, isa_nobit 2362 1.1 mrg } 2363 1.1 mrg }, 2364 1.1 mrg { 2365 1.1 mrg "simd", false, false, 2366 1.1 mrg { 2367 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2368 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2369 1.1 mrg isa_nobit 2370 1.1 mrg } 2371 1.1 mrg }, 2372 1.1 mrg { 2373 1.1 mrg "crypto", false, false, 2374 1.1 mrg { 2375 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2376 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2377 1.1 mrg isa_bit_fp_dbl, isa_nobit 2378 1.1 mrg } 2379 1.1 mrg }, 2380 1.1 mrg { 2381 1.1 mrg "nocrypto", true, false, 2382 1.1 mrg { 2383 1.1 mrg isa_bit_crypto, isa_nobit 2384 1.1 mrg } 2385 1.1 mrg }, 2386 1.1 mrg { 2387 1.1 mrg "nofp", true, false, 2388 1.1 mrg { 2389 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2390 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2391 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2392 1.1 mrg } 2393 1.1 mrg }, 2394 1.1.1.2 mrg { 2395 1.1.1.2 mrg "sb", false, false, 2396 1.1.1.2 mrg { 2397 1.1.1.2 mrg isa_bit_sb, isa_nobit 2398 1.1.1.2 mrg } 2399 1.1.1.2 mrg }, 2400 1.1.1.2 mrg { 2401 1.1.1.2 mrg "predres", false, false, 2402 1.1.1.2 mrg { 2403 1.1.1.2 mrg isa_bit_predres, isa_nobit 2404 1.1.1.2 mrg } 2405 1.1.1.2 mrg }, 2406 1.1 mrg { NULL, false, false, {isa_nobit}} 2407 1.1 mrg }; 2408 1.1 mrg 2409 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_1_a[] = { 2410 1.1 mrg { 2411 1.1 mrg "simd", false, false, 2412 1.1 mrg { 2413 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2414 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2415 1.1 mrg isa_nobit 2416 1.1 mrg } 2417 1.1 mrg }, 2418 1.1 mrg { 2419 1.1 mrg "crypto", false, false, 2420 1.1 mrg { 2421 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2422 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2423 1.1 mrg isa_bit_fp_dbl, isa_nobit 2424 1.1 mrg } 2425 1.1 mrg }, 2426 1.1 mrg { 2427 1.1 mrg "nocrypto", true, false, 2428 1.1 mrg { 2429 1.1 mrg isa_bit_crypto, isa_nobit 2430 1.1 mrg } 2431 1.1 mrg }, 2432 1.1 mrg { 2433 1.1 mrg "nofp", true, false, 2434 1.1 mrg { 2435 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2436 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2437 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2438 1.1 mrg } 2439 1.1 mrg }, 2440 1.1.1.2 mrg { 2441 1.1.1.2 mrg "sb", false, false, 2442 1.1.1.2 mrg { 2443 1.1.1.2 mrg isa_bit_sb, isa_nobit 2444 1.1.1.2 mrg } 2445 1.1.1.2 mrg }, 2446 1.1.1.2 mrg { 2447 1.1.1.2 mrg "predres", false, false, 2448 1.1.1.2 mrg { 2449 1.1.1.2 mrg isa_bit_predres, isa_nobit 2450 1.1.1.2 mrg } 2451 1.1.1.2 mrg }, 2452 1.1 mrg { NULL, false, false, {isa_nobit}} 2453 1.1 mrg }; 2454 1.1 mrg 2455 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_2_a[] = { 2456 1.1 mrg { 2457 1.1 mrg "simd", false, false, 2458 1.1 mrg { 2459 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2460 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2461 1.1 mrg isa_nobit 2462 1.1 mrg } 2463 1.1 mrg }, 2464 1.1 mrg { 2465 1.1 mrg "fp16", false, false, 2466 1.1 mrg { 2467 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2468 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2469 1.1 mrg isa_bit_fp_dbl, isa_nobit 2470 1.1 mrg } 2471 1.1 mrg }, 2472 1.1 mrg { 2473 1.1 mrg "fp16fml", false, false, 2474 1.1 mrg { 2475 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2476 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2477 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2478 1.1 mrg } 2479 1.1 mrg }, 2480 1.1 mrg { 2481 1.1 mrg "crypto", false, false, 2482 1.1 mrg { 2483 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2484 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2485 1.1 mrg isa_bit_fp_dbl, isa_nobit 2486 1.1 mrg } 2487 1.1 mrg }, 2488 1.1 mrg { 2489 1.1 mrg "nocrypto", true, false, 2490 1.1 mrg { 2491 1.1 mrg isa_bit_crypto, isa_nobit 2492 1.1 mrg } 2493 1.1 mrg }, 2494 1.1 mrg { 2495 1.1 mrg "nofp", true, false, 2496 1.1 mrg { 2497 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2498 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2499 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2500 1.1 mrg } 2501 1.1 mrg }, 2502 1.1 mrg { 2503 1.1 mrg "dotprod", false, false, 2504 1.1 mrg { 2505 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2506 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2507 1.1 mrg isa_bit_fp_dbl, isa_nobit 2508 1.1 mrg } 2509 1.1 mrg }, 2510 1.1.1.2 mrg { 2511 1.1.1.2 mrg "sb", false, false, 2512 1.1.1.2 mrg { 2513 1.1.1.2 mrg isa_bit_sb, isa_nobit 2514 1.1.1.2 mrg } 2515 1.1.1.2 mrg }, 2516 1.1.1.2 mrg { 2517 1.1.1.2 mrg "predres", false, false, 2518 1.1.1.2 mrg { 2519 1.1.1.2 mrg isa_bit_predres, isa_nobit 2520 1.1.1.2 mrg } 2521 1.1.1.2 mrg }, 2522 1.1 mrg { NULL, false, false, {isa_nobit}} 2523 1.1 mrg }; 2524 1.1 mrg 2525 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_3_a[] = { 2526 1.1 mrg { 2527 1.1 mrg "simd", false, false, 2528 1.1 mrg { 2529 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2530 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2531 1.1 mrg isa_nobit 2532 1.1 mrg } 2533 1.1 mrg }, 2534 1.1 mrg { 2535 1.1 mrg "fp16", false, false, 2536 1.1 mrg { 2537 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2538 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2539 1.1 mrg isa_bit_fp_dbl, isa_nobit 2540 1.1 mrg } 2541 1.1 mrg }, 2542 1.1 mrg { 2543 1.1 mrg "fp16fml", false, false, 2544 1.1 mrg { 2545 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2546 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, 2547 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2548 1.1 mrg } 2549 1.1 mrg }, 2550 1.1 mrg { 2551 1.1 mrg "crypto", false, false, 2552 1.1 mrg { 2553 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2554 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2555 1.1 mrg isa_bit_fp_dbl, isa_nobit 2556 1.1 mrg } 2557 1.1 mrg }, 2558 1.1 mrg { 2559 1.1 mrg "nocrypto", true, false, 2560 1.1 mrg { 2561 1.1 mrg isa_bit_crypto, isa_nobit 2562 1.1 mrg } 2563 1.1 mrg }, 2564 1.1 mrg { 2565 1.1 mrg "nofp", true, false, 2566 1.1 mrg { 2567 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2568 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2569 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2570 1.1 mrg } 2571 1.1 mrg }, 2572 1.1 mrg { 2573 1.1 mrg "dotprod", false, false, 2574 1.1 mrg { 2575 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2576 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2577 1.1 mrg isa_bit_fp_dbl, isa_nobit 2578 1.1 mrg } 2579 1.1 mrg }, 2580 1.1.1.2 mrg { 2581 1.1.1.2 mrg "sb", false, false, 2582 1.1.1.2 mrg { 2583 1.1.1.2 mrg isa_bit_sb, isa_nobit 2584 1.1.1.2 mrg } 2585 1.1.1.2 mrg }, 2586 1.1.1.2 mrg { 2587 1.1.1.2 mrg "predres", false, false, 2588 1.1.1.2 mrg { 2589 1.1.1.2 mrg isa_bit_predres, isa_nobit 2590 1.1.1.2 mrg } 2591 1.1.1.2 mrg }, 2592 1.1 mrg { NULL, false, false, {isa_nobit}} 2593 1.1 mrg }; 2594 1.1 mrg 2595 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_4_a[] = { 2596 1.1 mrg { 2597 1.1 mrg "simd", false, false, 2598 1.1 mrg { 2599 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2600 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2601 1.1 mrg isa_bit_fp_dbl, isa_nobit 2602 1.1 mrg } 2603 1.1 mrg }, 2604 1.1 mrg { 2605 1.1 mrg "fp16", false, false, 2606 1.1 mrg { 2607 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2608 1.1 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2609 1.1 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2610 1.1 mrg } 2611 1.1 mrg }, 2612 1.1 mrg { 2613 1.1 mrg "crypto", false, false, 2614 1.1 mrg { 2615 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2616 1.1 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2617 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2618 1.1 mrg } 2619 1.1 mrg }, 2620 1.1 mrg { 2621 1.1 mrg "nocrypto", true, false, 2622 1.1 mrg { 2623 1.1 mrg isa_bit_crypto, isa_nobit 2624 1.1 mrg } 2625 1.1 mrg }, 2626 1.1 mrg { 2627 1.1 mrg "nofp", true, false, 2628 1.1 mrg { 2629 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2630 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2631 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2632 1.1 mrg } 2633 1.1 mrg }, 2634 1.1.1.2 mrg { 2635 1.1.1.2 mrg "sb", false, false, 2636 1.1.1.2 mrg { 2637 1.1.1.2 mrg isa_bit_sb, isa_nobit 2638 1.1.1.2 mrg } 2639 1.1.1.2 mrg }, 2640 1.1.1.2 mrg { 2641 1.1.1.2 mrg "predres", false, false, 2642 1.1.1.2 mrg { 2643 1.1.1.2 mrg isa_bit_predres, isa_nobit 2644 1.1.1.2 mrg } 2645 1.1.1.2 mrg }, 2646 1.1.1.2 mrg { NULL, false, false, {isa_nobit}} 2647 1.1.1.2 mrg }; 2648 1.1.1.2 mrg 2649 1.1.1.2 mrg static const struct cpu_arch_extension arch_opttab_armv8_5_a[] = { 2650 1.1.1.2 mrg { 2651 1.1.1.2 mrg "simd", false, false, 2652 1.1.1.2 mrg { 2653 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2654 1.1.1.2 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2655 1.1.1.2 mrg isa_bit_fp_dbl, isa_nobit 2656 1.1.1.2 mrg } 2657 1.1.1.2 mrg }, 2658 1.1.1.2 mrg { 2659 1.1.1.2 mrg "fp16", false, false, 2660 1.1.1.2 mrg { 2661 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16fml, 2662 1.1.1.2 mrg isa_bit_dotprod, isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, 2663 1.1.1.2 mrg isa_bit_fp16, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2664 1.1.1.2 mrg } 2665 1.1.1.2 mrg }, 2666 1.1.1.2 mrg { 2667 1.1.1.2 mrg "crypto", false, false, 2668 1.1.1.2 mrg { 2669 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_dotprod, 2670 1.1.1.2 mrg isa_bit_neon, isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, 2671 1.1.1.2 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2672 1.1.1.2 mrg } 2673 1.1.1.2 mrg }, 2674 1.1.1.2 mrg { 2675 1.1.1.2 mrg "nocrypto", true, false, 2676 1.1.1.2 mrg { 2677 1.1.1.2 mrg isa_bit_crypto, isa_nobit 2678 1.1.1.2 mrg } 2679 1.1.1.2 mrg }, 2680 1.1.1.2 mrg { 2681 1.1.1.2 mrg "nofp", true, false, 2682 1.1.1.2 mrg { 2683 1.1.1.2 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2684 1.1.1.2 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2685 1.1.1.2 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2686 1.1.1.2 mrg } 2687 1.1.1.2 mrg }, 2688 1.1 mrg { NULL, false, false, {isa_nobit}} 2689 1.1 mrg }; 2690 1.1 mrg 2691 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_m_main[] = { 2692 1.1 mrg { 2693 1.1 mrg "dsp", false, false, 2694 1.1 mrg { 2695 1.1 mrg isa_bit_armv7em, isa_nobit 2696 1.1 mrg } 2697 1.1 mrg }, 2698 1.1 mrg { 2699 1.1 mrg "fp", false, false, 2700 1.1 mrg { 2701 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2702 1.1 mrg isa_bit_fp16conv, isa_nobit 2703 1.1 mrg } 2704 1.1 mrg }, 2705 1.1 mrg { 2706 1.1 mrg "fp.dp", false, false, 2707 1.1 mrg { 2708 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2709 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 2710 1.1 mrg } 2711 1.1 mrg }, 2712 1.1 mrg { 2713 1.1 mrg "nofp", true, false, 2714 1.1 mrg { 2715 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2716 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2717 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2718 1.1 mrg } 2719 1.1 mrg }, 2720 1.1 mrg { 2721 1.1 mrg "nodsp", true, false, 2722 1.1 mrg { 2723 1.1 mrg isa_bit_armv7em, isa_nobit 2724 1.1 mrg } 2725 1.1 mrg }, 2726 1.1 mrg { NULL, false, false, {isa_nobit}} 2727 1.1 mrg }; 2728 1.1 mrg 2729 1.1 mrg static const struct cpu_arch_extension arch_opttab_armv8_r[] = { 2730 1.1 mrg { 2731 1.1 mrg "crc", false, false, 2732 1.1 mrg { 2733 1.1 mrg isa_bit_crc32, isa_nobit 2734 1.1 mrg } 2735 1.1 mrg }, 2736 1.1 mrg { 2737 1.1 mrg "fp.sp", false, false, 2738 1.1 mrg { 2739 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 2740 1.1 mrg isa_bit_fp16conv, isa_nobit 2741 1.1 mrg } 2742 1.1 mrg }, 2743 1.1 mrg { 2744 1.1 mrg "simd", false, false, 2745 1.1 mrg { 2746 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2747 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 2748 1.1 mrg isa_nobit 2749 1.1 mrg } 2750 1.1 mrg }, 2751 1.1 mrg { 2752 1.1 mrg "crypto", false, false, 2753 1.1 mrg { 2754 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2755 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 2756 1.1 mrg isa_bit_fp_dbl, isa_nobit 2757 1.1 mrg } 2758 1.1 mrg }, 2759 1.1 mrg { 2760 1.1 mrg "nocrypto", true, false, 2761 1.1 mrg { 2762 1.1 mrg isa_bit_crypto, isa_nobit 2763 1.1 mrg } 2764 1.1 mrg }, 2765 1.1 mrg { 2766 1.1 mrg "nofp", true, false, 2767 1.1 mrg { 2768 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 2769 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16, isa_bit_fp16conv, 2770 1.1 mrg isa_bit_crypto, isa_bit_fp_dbl, isa_nobit 2771 1.1 mrg } 2772 1.1 mrg }, 2773 1.1 mrg { NULL, false, false, {isa_nobit}} 2774 1.1 mrg }; 2775 1.1 mrg 2776 1.1 mrg const arch_option all_architectures[] = 2777 1.1 mrg { 2778 1.1 mrg { 2779 1.1 mrg "armv4", 2780 1.1 mrg NULL, 2781 1.1 mrg { 2782 1.1.1.2 mrg isa_bit_armv4, isa_bit_notm, isa_nobit 2783 1.1 mrg }, 2784 1.1 mrg "4", BASE_ARCH_4, 2785 1.1 mrg 0, 2786 1.1 mrg TARGET_CPU_arm7tdmi, 2787 1.1 mrg }, 2788 1.1 mrg { 2789 1.1 mrg "armv4t", 2790 1.1 mrg NULL, 2791 1.1 mrg { 2792 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv4, isa_bit_notm, isa_nobit 2793 1.1 mrg }, 2794 1.1 mrg "4T", BASE_ARCH_4T, 2795 1.1 mrg 0, 2796 1.1 mrg TARGET_CPU_arm7tdmi, 2797 1.1 mrg }, 2798 1.1 mrg { 2799 1.1 mrg "armv5t", 2800 1.1 mrg NULL, 2801 1.1 mrg { 2802 1.1.1.2 mrg isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, 2803 1.1.1.2 mrg isa_nobit 2804 1.1 mrg }, 2805 1.1 mrg "5T", BASE_ARCH_5T, 2806 1.1 mrg 0, 2807 1.1 mrg TARGET_CPU_arm10tdmi, 2808 1.1 mrg }, 2809 1.1 mrg { 2810 1.1 mrg "armv5te", 2811 1.1 mrg arch_opttab_armv5te, 2812 1.1 mrg { 2813 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 2814 1.1.1.2 mrg isa_bit_notm, isa_nobit 2815 1.1 mrg }, 2816 1.1 mrg "5TE", BASE_ARCH_5TE, 2817 1.1 mrg 0, 2818 1.1 mrg TARGET_CPU_arm1026ejs, 2819 1.1 mrg }, 2820 1.1 mrg { 2821 1.1 mrg "armv5tej", 2822 1.1 mrg arch_opttab_armv5tej, 2823 1.1 mrg { 2824 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_armv5t, isa_bit_armv4, 2825 1.1.1.2 mrg isa_bit_notm, isa_nobit 2826 1.1 mrg }, 2827 1.1 mrg "5TEJ", BASE_ARCH_5TEJ, 2828 1.1 mrg 0, 2829 1.1 mrg TARGET_CPU_arm1026ejs, 2830 1.1 mrg }, 2831 1.1 mrg { 2832 1.1 mrg "armv6", 2833 1.1 mrg arch_opttab_armv6, 2834 1.1 mrg { 2835 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2836 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2837 1.1 mrg }, 2838 1.1 mrg "6", BASE_ARCH_6, 2839 1.1 mrg 0, 2840 1.1 mrg TARGET_CPU_arm1136js, 2841 1.1 mrg }, 2842 1.1 mrg { 2843 1.1 mrg "armv6j", 2844 1.1 mrg arch_opttab_armv6j, 2845 1.1 mrg { 2846 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2847 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2848 1.1 mrg }, 2849 1.1 mrg "6J", BASE_ARCH_6J, 2850 1.1 mrg 0, 2851 1.1 mrg TARGET_CPU_arm1136js, 2852 1.1 mrg }, 2853 1.1 mrg { 2854 1.1 mrg "armv6k", 2855 1.1 mrg arch_opttab_armv6k, 2856 1.1 mrg { 2857 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2858 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_bit_armv6k, 2859 1.1.1.2 mrg isa_nobit 2860 1.1 mrg }, 2861 1.1 mrg "6K", BASE_ARCH_6K, 2862 1.1 mrg 0, 2863 1.1 mrg TARGET_CPU_mpcore, 2864 1.1 mrg }, 2865 1.1 mrg { 2866 1.1 mrg "armv6z", 2867 1.1 mrg arch_opttab_armv6z, 2868 1.1 mrg { 2869 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2870 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_notm, isa_nobit 2871 1.1 mrg }, 2872 1.1 mrg "6Z", BASE_ARCH_6Z, 2873 1.1 mrg 0, 2874 1.1 mrg TARGET_CPU_arm1176jzs, 2875 1.1 mrg }, 2876 1.1 mrg { 2877 1.1 mrg "armv6kz", 2878 1.1 mrg arch_opttab_armv6kz, 2879 1.1 mrg { 2880 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2881 1.1.1.2 mrg isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 2882 1.1.1.2 mrg isa_bit_armv6k, isa_nobit 2883 1.1 mrg }, 2884 1.1 mrg "6KZ", BASE_ARCH_6KZ, 2885 1.1 mrg 0, 2886 1.1 mrg TARGET_CPU_arm1176jzs, 2887 1.1 mrg }, 2888 1.1 mrg { 2889 1.1 mrg "armv6zk", 2890 1.1 mrg arch_opttab_armv6zk, 2891 1.1 mrg { 2892 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2893 1.1.1.2 mrg isa_bit_armv4, isa_bit_quirk_armv6kz, isa_bit_armv6, isa_bit_notm, 2894 1.1.1.2 mrg isa_bit_armv6k, isa_nobit 2895 1.1 mrg }, 2896 1.1 mrg "6KZ", BASE_ARCH_6KZ, 2897 1.1 mrg 0, 2898 1.1 mrg TARGET_CPU_arm1176jzs, 2899 1.1 mrg }, 2900 1.1 mrg { 2901 1.1 mrg "armv6t2", 2902 1.1 mrg arch_opttab_armv6t2, 2903 1.1 mrg { 2904 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2905 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_thumb2, isa_bit_notm, 2906 1.1.1.2 mrg isa_nobit 2907 1.1 mrg }, 2908 1.1 mrg "6T2", BASE_ARCH_6T2, 2909 1.1 mrg 0, 2910 1.1 mrg TARGET_CPU_arm1156t2s, 2911 1.1 mrg }, 2912 1.1 mrg { 2913 1.1 mrg "armv6-m", 2914 1.1 mrg NULL, 2915 1.1 mrg { 2916 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2917 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 2918 1.1 mrg }, 2919 1.1 mrg "6M", BASE_ARCH_6M, 2920 1.1 mrg 'M', 2921 1.1 mrg TARGET_CPU_cortexm1, 2922 1.1 mrg }, 2923 1.1 mrg { 2924 1.1 mrg "armv6s-m", 2925 1.1 mrg NULL, 2926 1.1 mrg { 2927 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2928 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_nobit 2929 1.1 mrg }, 2930 1.1 mrg "6M", BASE_ARCH_6M, 2931 1.1 mrg 'M', 2932 1.1 mrg TARGET_CPU_cortexm1, 2933 1.1 mrg }, 2934 1.1 mrg { 2935 1.1 mrg "armv7", 2936 1.1 mrg arch_opttab_armv7, 2937 1.1 mrg { 2938 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2939 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 2940 1.1.1.2 mrg isa_nobit 2941 1.1 mrg }, 2942 1.1 mrg "7", BASE_ARCH_7, 2943 1.1 mrg 0, 2944 1.1 mrg TARGET_CPU_cortexa8, 2945 1.1 mrg }, 2946 1.1 mrg { 2947 1.1 mrg "armv7-a", 2948 1.1 mrg arch_opttab_armv7_a, 2949 1.1 mrg { 2950 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2951 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_thumb2, 2952 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_nobit 2953 1.1 mrg }, 2954 1.1 mrg "7A", BASE_ARCH_7A, 2955 1.1 mrg 'A', 2956 1.1 mrg TARGET_CPU_cortexa8, 2957 1.1 mrg }, 2958 1.1 mrg { 2959 1.1 mrg "armv7ve", 2960 1.1 mrg arch_opttab_armv7ve, 2961 1.1 mrg { 2962 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 2963 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 2964 1.1.1.2 mrg isa_bit_armv7, isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, 2965 1.1.1.2 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 2966 1.1 mrg }, 2967 1.1 mrg "7A", BASE_ARCH_7A, 2968 1.1 mrg 'A', 2969 1.1 mrg TARGET_CPU_cortexa8, 2970 1.1 mrg }, 2971 1.1 mrg { 2972 1.1 mrg "armv7-r", 2973 1.1 mrg arch_opttab_armv7_r, 2974 1.1 mrg { 2975 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2976 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 2977 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv6k, isa_nobit 2978 1.1 mrg }, 2979 1.1 mrg "7R", BASE_ARCH_7R, 2980 1.1 mrg 'R', 2981 1.1 mrg TARGET_CPU_cortexr4, 2982 1.1 mrg }, 2983 1.1 mrg { 2984 1.1 mrg "armv7-m", 2985 1.1 mrg NULL, 2986 1.1 mrg { 2987 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 2988 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_tdiv, 2989 1.1.1.2 mrg isa_bit_thumb2, isa_nobit 2990 1.1 mrg }, 2991 1.1 mrg "7M", BASE_ARCH_7M, 2992 1.1 mrg 'M', 2993 1.1 mrg TARGET_CPU_cortexm3, 2994 1.1 mrg }, 2995 1.1 mrg { 2996 1.1 mrg "armv7e-m", 2997 1.1 mrg arch_opttab_armv7e_m, 2998 1.1 mrg { 2999 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3000 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7em, isa_bit_armv7, 3001 1.1.1.2 mrg isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3002 1.1 mrg }, 3003 1.1 mrg "7EM", BASE_ARCH_7EM, 3004 1.1 mrg 'M', 3005 1.1 mrg TARGET_CPU_cortexm4, 3006 1.1 mrg }, 3007 1.1 mrg { 3008 1.1 mrg "armv8-a", 3009 1.1 mrg arch_opttab_armv8_a, 3010 1.1 mrg { 3011 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3012 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3013 1.1.1.2 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3014 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3015 1.1.1.2 mrg isa_nobit 3016 1.1 mrg }, 3017 1.1 mrg "8A", BASE_ARCH_8A, 3018 1.1 mrg 'A', 3019 1.1 mrg TARGET_CPU_cortexa53, 3020 1.1 mrg }, 3021 1.1 mrg { 3022 1.1 mrg "armv8.1-a", 3023 1.1 mrg arch_opttab_armv8_1_a, 3024 1.1 mrg { 3025 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3026 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3027 1.1 mrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3028 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3029 1.1.1.2 mrg isa_bit_mp, isa_bit_sec, isa_nobit 3030 1.1 mrg }, 3031 1.1 mrg "8A", BASE_ARCH_8A, 3032 1.1 mrg 'A', 3033 1.1 mrg TARGET_CPU_cortexa53, 3034 1.1 mrg }, 3035 1.1 mrg { 3036 1.1 mrg "armv8.2-a", 3037 1.1 mrg arch_opttab_armv8_2_a, 3038 1.1 mrg { 3039 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3040 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3041 1.1.1.2 mrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3042 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3043 1.1.1.2 mrg isa_bit_armv6k, isa_bit_mp, isa_bit_sec, isa_nobit 3044 1.1 mrg }, 3045 1.1 mrg "8A", BASE_ARCH_8A, 3046 1.1 mrg 'A', 3047 1.1 mrg TARGET_CPU_cortexa53, 3048 1.1 mrg }, 3049 1.1 mrg { 3050 1.1 mrg "armv8.3-a", 3051 1.1 mrg arch_opttab_armv8_3_a, 3052 1.1 mrg { 3053 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3054 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3055 1.1 mrg isa_bit_crc32, isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, 3056 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv6k, 3057 1.1.1.2 mrg isa_bit_armv8_2, isa_bit_armv8_3, isa_bit_mp, isa_bit_sec, 3058 1.1.1.2 mrg isa_nobit 3059 1.1 mrg }, 3060 1.1 mrg "8A", BASE_ARCH_8A, 3061 1.1 mrg 'A', 3062 1.1 mrg TARGET_CPU_cortexa53, 3063 1.1 mrg }, 3064 1.1 mrg { 3065 1.1 mrg "armv8.4-a", 3066 1.1 mrg arch_opttab_armv8_4_a, 3067 1.1 mrg { 3068 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3069 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3070 1.1.1.2 mrg isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, isa_bit_tdiv, 3071 1.1.1.2 mrg isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, isa_bit_armv8_2, 3072 1.1.1.2 mrg isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, isa_bit_mp, 3073 1.1.1.2 mrg isa_bit_sec, isa_nobit 3074 1.1.1.2 mrg }, 3075 1.1.1.2 mrg "8A", BASE_ARCH_8A, 3076 1.1.1.2 mrg 'A', 3077 1.1.1.2 mrg TARGET_CPU_cortexa53, 3078 1.1.1.2 mrg }, 3079 1.1.1.2 mrg { 3080 1.1.1.2 mrg "armv8.5-a", 3081 1.1.1.2 mrg arch_opttab_armv8_5_a, 3082 1.1.1.2 mrg { 3083 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_sb, isa_bit_thumb, 3084 1.1.1.2 mrg isa_bit_be8, isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, 3085 1.1.1.2 mrg isa_bit_armv6, isa_bit_armv7, isa_bit_crc32, isa_bit_armv8, 3086 1.1.1.2 mrg isa_bit_tdiv, isa_bit_thumb2, isa_bit_notm, isa_bit_armv8_1, 3087 1.1 mrg isa_bit_armv8_2, isa_bit_armv6k, isa_bit_armv8_3, isa_bit_armv8_4, 3088 1.1.1.2 mrg isa_bit_mp, isa_bit_armv8_5, isa_bit_sec, isa_bit_predres, 3089 1.1.1.2 mrg isa_nobit 3090 1.1 mrg }, 3091 1.1 mrg "8A", BASE_ARCH_8A, 3092 1.1 mrg 'A', 3093 1.1 mrg TARGET_CPU_cortexa53, 3094 1.1 mrg }, 3095 1.1 mrg { 3096 1.1 mrg "armv8-m.base", 3097 1.1 mrg NULL, 3098 1.1 mrg { 3099 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3100 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_cmse, isa_bit_armv8, 3101 1.1.1.2 mrg isa_bit_tdiv, isa_nobit 3102 1.1 mrg }, 3103 1.1 mrg "8M_BASE", BASE_ARCH_8M_BASE, 3104 1.1 mrg 'M', 3105 1.1 mrg TARGET_CPU_cortexm23, 3106 1.1 mrg }, 3107 1.1 mrg { 3108 1.1 mrg "armv8-m.main", 3109 1.1 mrg arch_opttab_armv8_m_main, 3110 1.1 mrg { 3111 1.1.1.2 mrg isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, isa_bit_armv5t, 3112 1.1.1.2 mrg isa_bit_armv4, isa_bit_armv6, isa_bit_armv7, isa_bit_cmse, 3113 1.1.1.2 mrg isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, isa_nobit 3114 1.1 mrg }, 3115 1.1 mrg "8M_MAIN", BASE_ARCH_8M_MAIN, 3116 1.1 mrg 'M', 3117 1.1 mrg TARGET_CPU_cortexm7, 3118 1.1 mrg }, 3119 1.1 mrg { 3120 1.1 mrg "armv8-r", 3121 1.1 mrg arch_opttab_armv8_r, 3122 1.1 mrg { 3123 1.1.1.2 mrg isa_bit_adiv, isa_bit_armv5te, isa_bit_thumb, isa_bit_be8, 3124 1.1.1.2 mrg isa_bit_armv5t, isa_bit_lpae, isa_bit_armv4, isa_bit_armv6, 3125 1.1.1.2 mrg isa_bit_armv7, isa_bit_armv8, isa_bit_tdiv, isa_bit_thumb2, 3126 1.1.1.2 mrg isa_bit_notm, isa_bit_armv6k, isa_bit_mp, isa_bit_sec, 3127 1.1.1.2 mrg isa_nobit 3128 1.1 mrg }, 3129 1.1 mrg "8R", BASE_ARCH_8R, 3130 1.1 mrg 'R', 3131 1.1 mrg TARGET_CPU_cortexr52, 3132 1.1 mrg }, 3133 1.1 mrg { 3134 1.1 mrg "iwmmxt", 3135 1.1 mrg NULL, 3136 1.1 mrg { 3137 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3138 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_notm, isa_nobit 3139 1.1 mrg }, 3140 1.1 mrg "5TE", BASE_ARCH_5TE, 3141 1.1 mrg 0, 3142 1.1 mrg TARGET_CPU_iwmmxt, 3143 1.1 mrg }, 3144 1.1 mrg { 3145 1.1 mrg "iwmmxt2", 3146 1.1 mrg NULL, 3147 1.1 mrg { 3148 1.1.1.2 mrg isa_bit_iwmmxt, isa_bit_armv5te, isa_bit_xscale, isa_bit_thumb, 3149 1.1.1.2 mrg isa_bit_armv5t, isa_bit_armv4, isa_bit_iwmmxt2, isa_bit_notm, 3150 1.1.1.2 mrg isa_nobit 3151 1.1 mrg }, 3152 1.1 mrg "5TE", BASE_ARCH_5TE, 3153 1.1 mrg 0, 3154 1.1 mrg TARGET_CPU_iwmmxt2, 3155 1.1 mrg }, 3156 1.1 mrg {{NULL, NULL, {isa_nobit}}, 3157 1.1 mrg NULL, BASE_ARCH_0, 0, TARGET_CPU_arm_none} 3158 1.1 mrg }; 3159 1.1 mrg 3160 1.1 mrg const arm_fpu_desc all_fpus[] = 3161 1.1 mrg { 3162 1.1 mrg { 3163 1.1 mrg "vfp", 3164 1.1 mrg { 3165 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3166 1.1 mrg } 3167 1.1 mrg }, 3168 1.1 mrg { 3169 1.1 mrg "vfpv2", 3170 1.1 mrg { 3171 1.1 mrg isa_bit_vfpv2, isa_bit_fp_dbl, isa_nobit 3172 1.1 mrg } 3173 1.1 mrg }, 3174 1.1 mrg { 3175 1.1 mrg "vfpv3", 3176 1.1 mrg { 3177 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3178 1.1 mrg isa_nobit 3179 1.1 mrg } 3180 1.1 mrg }, 3181 1.1 mrg { 3182 1.1 mrg "vfpv3-fp16", 3183 1.1 mrg { 3184 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp16conv, 3185 1.1 mrg isa_bit_fp_dbl, isa_nobit 3186 1.1 mrg } 3187 1.1 mrg }, 3188 1.1 mrg { 3189 1.1 mrg "vfpv3-d16", 3190 1.1 mrg { 3191 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_dbl, isa_nobit 3192 1.1 mrg } 3193 1.1 mrg }, 3194 1.1 mrg { 3195 1.1 mrg "vfpv3-d16-fp16", 3196 1.1 mrg { 3197 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_bit_fp_dbl, 3198 1.1 mrg isa_nobit 3199 1.1 mrg } 3200 1.1 mrg }, 3201 1.1 mrg { 3202 1.1 mrg "vfpv3xd", 3203 1.1 mrg { 3204 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_nobit 3205 1.1 mrg } 3206 1.1 mrg }, 3207 1.1 mrg { 3208 1.1 mrg "vfpv3xd-fp16", 3209 1.1 mrg { 3210 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp16conv, isa_nobit 3211 1.1 mrg } 3212 1.1 mrg }, 3213 1.1 mrg { 3214 1.1 mrg "neon", 3215 1.1 mrg { 3216 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3217 1.1 mrg isa_bit_fp_dbl, isa_nobit 3218 1.1 mrg } 3219 1.1 mrg }, 3220 1.1 mrg { 3221 1.1 mrg "neon-vfpv3", 3222 1.1 mrg { 3223 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3224 1.1 mrg isa_bit_fp_dbl, isa_nobit 3225 1.1 mrg } 3226 1.1 mrg }, 3227 1.1 mrg { 3228 1.1 mrg "neon-fp16", 3229 1.1 mrg { 3230 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_neon, isa_bit_fp_d32, 3231 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3232 1.1 mrg } 3233 1.1 mrg }, 3234 1.1 mrg { 3235 1.1 mrg "vfpv4", 3236 1.1 mrg { 3237 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp_d32, 3238 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3239 1.1 mrg } 3240 1.1 mrg }, 3241 1.1 mrg { 3242 1.1 mrg "neon-vfpv4", 3243 1.1 mrg { 3244 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3245 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3246 1.1 mrg } 3247 1.1 mrg }, 3248 1.1 mrg { 3249 1.1 mrg "vfpv4-d16", 3250 1.1 mrg { 3251 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3252 1.1 mrg isa_bit_fp_dbl, isa_nobit 3253 1.1 mrg } 3254 1.1 mrg }, 3255 1.1 mrg { 3256 1.1 mrg "fpv4-sp-d16", 3257 1.1 mrg { 3258 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fp16conv, 3259 1.1 mrg isa_nobit 3260 1.1 mrg } 3261 1.1 mrg }, 3262 1.1 mrg { 3263 1.1 mrg "fpv5-sp-d16", 3264 1.1 mrg { 3265 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3266 1.1 mrg isa_bit_fp16conv, isa_nobit 3267 1.1 mrg } 3268 1.1 mrg }, 3269 1.1 mrg { 3270 1.1 mrg "fpv5-d16", 3271 1.1 mrg { 3272 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3273 1.1 mrg isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3274 1.1 mrg } 3275 1.1 mrg }, 3276 1.1 mrg { 3277 1.1 mrg "fp-armv8", 3278 1.1 mrg { 3279 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_fpv5, 3280 1.1 mrg isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, isa_nobit 3281 1.1 mrg } 3282 1.1 mrg }, 3283 1.1 mrg { 3284 1.1 mrg "neon-fp-armv8", 3285 1.1 mrg { 3286 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3287 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_fp_dbl, 3288 1.1 mrg isa_nobit 3289 1.1 mrg } 3290 1.1 mrg }, 3291 1.1 mrg { 3292 1.1 mrg "crypto-neon-fp-armv8", 3293 1.1 mrg { 3294 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_vfpv4, isa_bit_neon, 3295 1.1 mrg isa_bit_fpv5, isa_bit_fp_d32, isa_bit_fp16conv, isa_bit_crypto, 3296 1.1 mrg isa_bit_fp_dbl, isa_nobit 3297 1.1 mrg } 3298 1.1 mrg }, 3299 1.1 mrg { 3300 1.1 mrg "vfp3", 3301 1.1 mrg { 3302 1.1 mrg isa_bit_vfpv2, isa_bit_vfpv3, isa_bit_fp_d32, isa_bit_fp_dbl, 3303 1.1 mrg isa_nobit 3304 1.1 mrg } 3305 1.1 mrg }, 3306 1.1 mrg }; 3307
Indexes created Sat Apr 11 00:22:22 UTC 2026